Rev Author Line No. Line
1754 kakl 1 #include <18F4550.h>
1744 kakl 2 #device adc=8
3  
4 #FUSES NOWDT //No Watch Dog Timer
5 #FUSES WDT128 //Watch Dog Timer uses 1:128 Postscale
1754 kakl 6 #FUSES HS //High speed Osc (> 4mhz for PCM/PCH) (>10mhz for PCD)
7 #FUSES NOPROTECT //Code not protected from reading
1744 kakl 8 #FUSES NOBROWNOUT //No brownout reset
1754 kakl 9 #FUSES BORV20 //Brownout reset at 2.0V
10 #FUSES NOPUT //No Power Up Timer
11 #FUSES NOCPD //No EE protection
1744 kakl 12 #FUSES STVREN //Stack full/underflow will cause reset
13 #FUSES NODEBUG //No Debug mode for ICD
1754 kakl 14 #FUSES NOLVP //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O
15 #FUSES NOWRT //Program memory not write protected
16 #FUSES NOWRTD //Data EEPROM not write protected
17 #FUSES IESO //Internal External Switch Over mode enabled
18 #FUSES FCMEN //Fail-safe clock monitor enabled
19 #FUSES PBADEN //PORTB pins are configured as analog input channels on RESET
20 #FUSES NOWRTC //configuration not registers write protected
21 #FUSES NOWRTB //Boot block not write protected
1744 kakl 22 #FUSES NOEBTR //Memory not protected from table reads
1754 kakl 23 #FUSES NOEBTRB //Boot block not protected from table reads
24 #FUSES NOCPB //No Boot Block code protection
1744 kakl 25 #FUSES MCLR //Master Clear pin enabled
1754 kakl 26 #FUSES LPT1OSC //Timer1 configured for low-power operation
27 #FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode)
28 #FUSES PLL12 //Divide By 12(48MHz oscillator input)
29 #FUSES CPUDIV1 //System Clock by 1
30 #FUSES USBDIV //USB clock source comes from PLL divide by 2
31 #FUSES VREGEN //USB voltage regulator enabled
32 #FUSES ICPRT //ICPRT enabled
1744 kakl 33  
1754 kakl 34 #use delay(clock=20000000)
35 #use rs232(baud=9600,parity=N,xmit=PIN_B7,rcv=PIN_B6,bits=8)
1744 kakl 36  
1754 kakl 37 #define TDC_ENABLE PIN_B3 //enable pin for SPI communication with TDC
38 #use spi(DI=PIN_B1, DO=PIN_B0, CLK=PIN_B2, stream=TDC_stream, bits=32) // uses software SPI
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41