Rev Author Line No. Line
1095 mija 1 /* mija 2008
2 defines for module RFM12B - RX/TX 868MHz
3 */
4  
5 #define CMD_SETTING 0x8000 // el, ef, b1, b0, x3, x2, x1, x0
6 #define CMD_POWER 0x8200 // er, ebb, et, es, ex, eb, ew, dc
7 #define CMD_FREQUENCY 0xA000 // f11..f0 860+F*0.005 MHz 36..3903
8 #define CMD_RATE 0xC600 // cs, r6..r0 BR=10M/29/(R+1)/1+cs*7)
9 #define CMD_RX 0x9000 // P16, d1, d0, i2..i0, g1, g0, r2..r0
10 #define CMD_FILTER 0xC228 // al, ml, s, f2..f0
11 #define CMD_FIFO 0xCA00 // f3..f0, sp, al, ff, dr
12 #define CMD_SYNCFIFO 0xCE00 // b7..b0
13 #define CMD_READ_FIFO 0xB000 // use for read FIFO
14 #define CMD_AFC 0xC400 // a1, a0, rl1, rl0, st, fi, oe, en
15 #define CMD_TX 0x9800 // mp, m3..m0, p2..p0
16 #define CMD_PLL 0xCC02 // ob1, ob0, lpx, ddy, ddit, bw0
17 #define CMD_TX_DATA 0xB800 // t7..t0
18 #define CMD_WAKE_UP 0xE000 // r4..r0, m7..m0 T=M*2^R [ms]
19 #define CMD_DUTY 0xC800 // d6..d0 D.C.= (D*2+1)/M*100%
20 #define CMD_BATTERY 0xC000 // d2..d0, v3..v0
21 #define CMD_STATUS 0x0000 // for read status
22  
23 // CMD_SETTING
24 #define SETTING_EL 0x80 // enable TX register
25 #define SETTING_EF 0x40 // enable TX FIFO buffer
26 #define SETTING_B1 0x20 // select band
27 #define SETTING_B0 0x10 // select band
28 #define BAND_868 0x20
29 #define SETTING_X3 0x08 // select capacitor
30 #define SETTING_X2 0x04 // select capacitor
31 #define SETTING_X1 0x02 // select capacitor
32 #define SETTING_X0 0x01 // select capacitor
33 #define C_8_5pF 0x0
34 #define C_9pF 0x1
35 #define C_9_5pF 0x2
36 #define C_10pF 0x3
37 #define C_10_5pF 0x4
38 #define C_11pF 0x5
39 #define C_11_5pF 0x6
40 #define C_12pF 0x7
41 #define C_12_5pF 0x8
42 #define C_13pF 0x9
43 #define C_13_5pF 0xA
44 #define C_14pF 0xB
45 #define C_14_5pF 0xC
46 #define C_15pF 0xD
47 #define C_15_5pF 0xE
48 #define C_16pF 0xF
49  
50 // CMD_POWER
51 #define POWER_ER 0x80 // enable receiver
52 #define POWER_EBB 0x40 // enable base band block
53 #define POWER_ET 0x20 // enable transmitter
54 #define POWER_ES 0x10 // enable synthesizer
55 #define POWER_EX 0x08 // enable crystal oscillator
56 #define POWER_EB 0x04 // enable low battery detector
57 #define POWER_EW 0x02 // enable wake up timer
58 #define POWER_DC 0x01 // disable clock output of CLK pin
59  
60 // CMD_FREQUENCY
61 #define FREQUENCY_867 0x578
62 #define FREQUENCY_868 0x640
63 #define FREQUENCY_869 0x708
64  
65 // CMD_RATE
66 #define RATE_1200 0x123
67 #define RATE_2400 0x8F
68 #define RATE_4800 0x47
69 #define RATE_CS_4800 0x108
70 #define RATE_9600 0x23
71 #define RATE_19200 0x11
72 #define RATE_38400 0x8
73 #define RATE_57600 0x5
74 #define RATE_115200 0x2
75  
76 // CMD_RX
77 #define RX_P16 10 // VDI output / interrupt input
78 #define VDI_FAST 0x000 // VDI response time
79 #define VDI_MEDIUM 0x100
80 #define VDI_SLOW 0x200
81 #define VDI_ALWAYS_ON 0x300
82 #define BANDWIDTH_400 0x20 // baseband bandwidth[kHz]
83 #define BANDWIDTH_340 0x40
84 #define BANDWIDTH_270 0x60
85 #define BANDWIDTH_200 0x80
86 #define BANDWIDTH_134 0xA0
87 #define BANDWIDTH_67 0xC0
88 #define LNA_GAIN_0 0x00 // LNA_GAIN
89 #define LNA_GAIN_6 0x08 // -6dBm
90 #define LNA_GAIN_14 0x10 // -14dBm
91 #define LNA_GAIN_20 0x18 // -20dBm
92 #define DRSSI_103 0x0 // RSSI= DRSSI + LNA_GAIN -103dBm
93 #define DRSSI_97 0x1 // -97dBm
94 #define DRSSI_91 0x2 // -91dBm
95 #define DRSSI_85 0x3 // -85dBm
96 #define DRSSI_79 0x4 // -79dBm
97 #define DRSSI_73 0x5 // -73dBm
98 #define DRSSI_67 0x6 // -67dBm
99 #define DRSSI_61 0x7 // -61dBm
100  
101 // CMD_FILTER
102 #define FILTER_AL 0x80 // enable clock recovery atuo-lock
103 #define FILTER_ML 0x40 // enable clock recovery fast mode
104 #define FILTER_S 0x10 // enable analog RC filter
105 #define DQD_7 0x7
106 #define DQD_6 0x6
107 #define DQD_5 0x5
108 #define DQD_4 0x4
109 #define DQD_3 0x3
110 #define DQD_2 0x2
111 #define DQD_1 0x1
112 #define DQD_0 0x0
113  
114 // CMD_FIFO
115 #define FIFO_16 0x00 // FIFO level
116 #define FIFO_15 0xF0
117 #define FIFO_14 0xE0
118 #define FIFO_13 0xD0
119 #define FIFO_12 0xC0
120 #define FIFO_11 0xB0
121 #define FIFO_10 0xA0
122 #define FIFO_9 0x90
123 #define FIFO_8 0x80
124 #define FIFO_7 0x70
125 #define FIFO_6 0x60
126 #define FIFO_5 0x50
127 #define FIFO_4 0x40
128 #define FIFO_3 0x30
129 #define FIFO_2 0x20
130 #define FIFO_1 0x10
131 #define FIFO_SP 0x8 // select 1 byte sync.pattern
132 #define FIFO_AL 0x4 // start FIFO always
133 #define FIFO_FF 0x2 // enable FIFO fill
134 #define FIFO_DR 0x1 // disable hi sensitivity reset
135  
136 // CMD_AFC
137 #define AFC_MCU 0x00 // AFC auto_mode by MCU
138 #define AFC_POWER_ON 0x40 // AFC at poweron
139 #define AFC_OFFSET 0x80 // AFC keep offset when VDI hi
140 #define AFC_VDI 0xC0 // AFC keeps independently from VDI
141 #define AFC_NORESTR 0x00 // range limit no restriction
142 #define AFC_RANG_16 0x10 // range limit +15/-16
143 #define AFC_RANG_8 0x20 // range limit +7/-8
144 #define AFC_RANG_4 0x30 // range limit +3/-4
145 #define AFC_ST 0x08 // store offset into outpur register
146 #define AFC_FI 0x04 // enable AFC hi accuracy mode
147 #define AFC_OE 0x02 // enable AFC output register
148 #define AFC_EN 0x01 // enable AFC function
149  
150 // CMD_TX
151 #define TX_MP 0x100 // modulation polarity
152 #define TX_DEV_15 0x00 // select frequency deviation
153 #define TX_DEV_30 0x10
154 #define TX_DEV_45 0x20
155 #define TX_DEV_60 0x30
156 #define TX_DEV_75 0x40
157 #define TX_DEV_90 0x50
158 #define TX_DEV_105 0x60
159 #define TX_DEV_120 0x70
160 #define TX_DEV_135 0x80
161 #define TX_DEV_150 0x90
162 #define TX_DEV_165 0xA0
163 #define TX_DEV_180 0xB0
164 #define TX_DEV_195 0xC0
165 #define TX_DEV_210 0xD0
166 #define TX_DEV_225 0xE0
167 #define TX_DEV_240 0xF0
168 #define TX_POWER_0 0x00 // 0 select output power
169 #define TX_POWER_3 0x01 // -3dBm
170 #define TX_POWER_6 0x02 // -6dBm
171 #define TX_POWER_9 0x03 // -9Bm
172 #define TX_POWER_12 0x04 // -12dBm
173 #define TX_POWER_15 0x05 // -15dBm
174 #define TX_POWER_18 0x06 // -18dBm
175 #define TX_POWER_21 0x07 // -21dBm
176  
177 // CMD_PLL
178 #define PLL_CLK_5_10 0x00 // microcontroller output clock 5-10Mhz
179 #define PLL_CLK_33 0x20 // 3.3MHz
180 #define PLL_CLK_25 0x40 // 2.5Mhz
181 #define PLL_LPX 0x10 // low power mode
182 #define PLL_DDY 0x08 // phase detector delay enable
183 #define PLL_DDIT 0x04 // disable the dithering in the PLL loop
184 #define PLL_BW0 0x01 // PLL bandwidth (max rate 256)