Rev Author Line No. Line
3165 kakl 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz
3 -- Based on code written by MIHO.
4 --
5 -- HW Design Name: S3AN01A
6 -- Project Name: gtime
7 -- Target Devices: XC3S50AN-4
8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A.
10 --
11 -- Dependencies: CLKGEN01B, GPS01A
12 --
3172 kakl 13 -- Version: $Id: gtime.vhd 3172 2013-07-15 19:19:25Z kakl $
3165 kakl 14 --
15 ----------------------------------------------------------------------------------
16  
17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL;
19 use IEEE.numeric_std.ALL;
20  
21 library UNISIM;
22 use UNISIM.vcomponents.all;
23  
24 entity gtime is
25 generic (
26 -- Top Value for 100MHz Clock Counter
27 --!!!KAKL MAXCOUNT: integer := 30_000_000;
28 MAXCOUNT: integer := 3_000_000;
29 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
30 );
31 port (
32 -- Main Clock
33 CLK100MHz: in std_logic;
34  
35 -- Mode Signals (usualy not used)
36 M: in std_logic_vector(2 downto 0);
37 VS: in std_logic_vector(2 downto 0);
38  
39 -- Dipswitch Inputs
40 DIPSW: in std_logic_vector(7 downto 0);
41  
42 -- Push Buttons
43 PB: in std_logic_vector(3 downto 0);
44  
45 -- LED Bar Outputs
46 LED: out std_logic_vector(7 downto 0);
47  
48 -- LED Display (8 digit with 7 segments and ddecimal point)
49 LD_A_n: out std_logic;
50 LD_B_n: out std_logic;
51 LD_C_n: out std_logic;
52 LD_D_n: out std_logic;
53 LD_E_n: out std_logic;
54 LD_F_n: out std_logic;
55 LD_G_n: out std_logic;
56 LD_DP_n: out std_logic;
57 LD_0_n: out std_logic;
58 LD_1_n: out std_logic;
59 LD_2_n: out std_logic;
60 LD_3_n: out std_logic;
61 LD_4_n: out std_logic;
62 LD_5_n: out std_logic;
63 LD_6_n: out std_logic;
64 LD_7_n: out std_logic;
65  
66 -- VGA Video Out Port
67 VGA_R: out std_logic_vector(1 downto 0);
68 VGA_G: out std_logic_vector(1 downto 0);
69 VGA_B: out std_logic_vector(1 downto 0);
70 VGA_VS: out std_logic;
71 VGA_HS: out std_logic;
72  
73 -- Bank 1 Pins - Inputs for this Test
74 B: inout std_logic_vector(24 downto 0);
75  
76 -- PS/2 Bidirectional Port (open collector, J31 and J32)
77 -- PS2_CLK1: inout std_logic;
78 -- PS2_DATA1: inout std_logic;
79 PS2_CLK2: inout std_logic;
80 PS2_DATA2: inout std_logic;
81  
82 -- Diferencial Signals on 4 pin header (J7)
83 DIF1P: inout std_logic;
84 DIF1N: inout std_logic;
85 DIF2P: inout std_logic;
86 DIF2N: inout std_logic;
87  
88  
89 -- I2C Signals (on connector J30)
90 I2C_SCL: inout std_logic;
91 I2C_SDA: inout std_logic;
92  
93 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
94 SD1AP: inout std_logic;
95 SD1AN: inout std_logic;
96 SD1BP: inout std_logic;
97 SD1BN: inout std_logic;
98 SD2AP: inout std_logic;
99 SD2AN: inout std_logic;
100 SD2BP: inout std_logic;
101 SD2BN: inout std_logic;
102  
103 -- Analog In Out
104 ANA_OUTD: out std_logic;
105 ANA_REFD: out std_logic;
106 ANA_IND: in std_logic;
107  
108 -- SPI Memory Interface
109 SPI_CS_n: inout std_logic;
110 SPI_DO: inout std_logic;
111 SPI_DI: inout std_logic;
112 SPI_CLK: inout std_logic;
113 SPI_WP_n: inout std_logic
114 );
115 end entity gtime;
116  
117  
118 architecture gtime_a of gtime is
119  
120 function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
121 variable i : integer:=0;
122 variable mybcd : std_logic_vector(11 downto 0) := (others => '0');
123 variable bint : std_logic_vector(7 downto 0) := bin;
124 begin
125 for i in 0 to 7 loop -- repeating 8 times.
126 mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits.
127 mybcd(0) := bint(7);
128 bint(7 downto 1) := bint(6 downto 0);
129 bint(0) :='0';
130  
131  
132 if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
133 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
134 end if;
135  
136 if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
137 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
138 end if;
139  
140 if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
141 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
142 end if;
143 end loop;
144  
145 return mybcd;
146 end to_bcd;
147  
148  
149 -- LED Demo Signals
150 -- ----------------
151  
152 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary)
153 signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary)
154  
155 signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz)
156  
157 -- LED Display
158 -- -----------
159  
160 signal Number: std_logic_vector(32 downto 0); -- LED Display Input
161 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
162 signal Enable: std_logic;
163 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
164 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
165 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
166  
167  
3166 kakl 168 signal LO_CLOCK: std_logic;
3165 kakl 169  
3166 kakl 170 signal Decko: std_logic;
171 signal Disp: std_logic := '0';
3172 kakl 172 signal Reset: std_logic := '0';
3165 kakl 173  
174 begin
175  
176 -- Basic LED Blinking Test
177 -- =======================
178  
179 -- LED Bar Counter
180 process (LO_CLOCK)
181 begin
3172 kakl 182 if Reset = '0' then
183 if rising_edge(LO_CLOCK) then
184  
185 if Disp = '1' then
186 Reset <= '1';
187 end if;
188  
189 Decko <= DIPSW(0);
190  
191 if Counter < MAXCOUNT-1 then
192 Counter <= Counter + 1;
193 else
194 Counter <= (others => '0');
195 Bar <= Bar + 1;
196 end if;
3165 kakl 197 end if;
198  
3172 kakl 199 else
200 Bar <= (others => '0');
201 Reset <= '0';
3166 kakl 202 end if;
203  
3172 kakl 204 end process;
3166 kakl 205  
206 process (LO_CLOCK)
207 begin
208 if rising_edge(LO_CLOCK) then
209 if Decko = '1' then
210 if Disp = '0' then
211 Number(3 downto 0) <= std_logic_vector(Bar(3 downto 0));
212 Number(7 downto 4) <= std_logic_vector(Bar(7 downto 4));
213 Number(15 downto 8) <= (others=>'0');
214 Number(19 downto 16) <= (others=>'0');
215 Number(31 downto 20) <= (others=>'0'); --to_bcd(std_logic_vector(T1));
216 Disp <= '1';
217 end if;
218 else
219 Disp <= '0';
220 end if;
221 end if;
222 end process;
223  
3165 kakl 224 LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
225  
3166 kakl 226 -- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
3165 kakl 227  
228 -- LED Display (multiplexed)
229 -- =========================
230  
231 -- Connect LED Display Output Ports (negative outputs)
232 LD_A_n <= not (Segments(0) and Enable);
233 LD_B_n <= not (Segments(1) and Enable);
234 LD_C_n <= not (Segments(2) and Enable);
235 LD_D_n <= not (Segments(3) and Enable);
236 LD_E_n <= not (Segments(4) and Enable);
237 LD_F_n <= not (Segments(5) and Enable);
238 LD_G_n <= not (Segments(6) and Enable);
239 LD_DP_n <= not (Segments(7) and Enable);
240  
241 LD_0_n <= not Digits(0);
242 LD_1_n <= not Digits(1);
243 LD_2_n <= not Digits(2);
244 LD_3_n <= not Digits(3);
245 LD_4_n <= not Digits(4);
246 LD_5_n <= not Digits(5);
247 LD_6_n <= not Digits(6);
248 LD_7_n <= not Digits(7);
249  
250 -- Time Multiplex
251 process (CLK100MHz)
252 begin
253 if rising_edge(CLK100MHz) then
254 if MuxCounter < MUXCOUNT-1 then
255 MuxCounter <= MuxCounter + 1;
256 else
257 MuxCounter <= (others => '0');
258 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
259 Enable <= '0';
260 end if;
261 if MuxCounter > (MUXCOUNT-4) then
262 Enable <= '1';
263 end if;
264 end if;
265 end process;
266  
3166 kakl 267 -- HEX to 7 Segmet Decoder
3165 kakl 268 -- -- A
269 -- | | F B
270 -- -- G
271 -- | | E C
272 -- -- D H
273 -- ABCDEFGH
274 Segments <= "11111100" when Code="0000" else -- Digit 0
275 "01100000" when Code="0001" else -- Digit 1
276 "11011010" when Code="0010" else -- Digit 2
277 "11110010" when Code="0011" else -- Digit 3
278 "01100110" when Code="0100" else -- Digit 4
279 "10110110" when Code="0101" else -- Digit 5
280 "10111110" when Code="0110" else -- Digit 6
281 "11100000" when Code="0111" else -- Digit 7
282 "11111110" when Code="1000" else -- Digit 8
283 "11110110" when Code="1001" else -- Digit 9
284 "11101110" when Code="1010" else -- Digit A
285 "00111110" when Code="1011" else -- Digit b
286 "10011100" when Code="1100" else -- Digit C
287 "01111010" when Code="1101" else -- Digit d
288 "10011110" when Code="1110" else -- Digit E
289 "10001110" when Code="1111" else -- Digit F
290 "00000000";
291  
292 Code <= Number( 3 downto 0) when Digits="00000001" else
293 Number( 7 downto 4) when Digits="00000010" else
294 Number(11 downto 8) when Digits="00000100" else
295 Number(15 downto 12) when Digits="00001000" else
296 Number(19 downto 16) when Digits="00010000" else
297 Number(23 downto 20) when Digits="00100000" else
298 Number(27 downto 24) when Digits="01000000" else
299 Number(31 downto 28) when Digits="10000000" else
300 "0000";
301  
302  
3166 kakl 303 -- Display on 7seg.
304 -- Number(3 downto 0) <= (others=>'0');
305 -- Number(15 downto 4) <= (others=>'1'); --to_bcd(std_logic_vector(T2));
306 -- Number(19 downto 16) <= (others=>'0');
307 -- Number(31 downto 20) <= (others=>'1'); --to_bcd(std_logic_vector(T1));
3165 kakl 308  
309  
3166 kakl 310 -- Diferencial In/Outs
3165 kakl 311 -- ========================
312 DIFbuffer1 : IBUFGDS
313 generic map (
314 DIFF_TERM => TRUE, -- Differential Termination
315 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
316 -- "0"-"16"
317 IOSTANDARD => "DEFAULT")
318 port map (
319 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
320 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
321 O => LO_CLOCK -- Buffer output
322 );
323  
324  
325 -- Output Signal on SATA Connector
3166 kakl 326 -- SD1AP <= 'Z';
327 -- SD1AN <= 'Z';
3165 kakl 328 SD1BP <= 'Z';
329 SD1BN <= 'Z';
330  
331 -- Input Here via SATA Cable
332 SD2AP <= 'Z';
333 SD2AN <= 'Z';
334 SD2BP <= 'Z';
335 SD2BN <= 'Z';
336  
337  
338 -- Unused Signals
339 -- ==============
340  
341 -- I2C Signals (on connector J30)
342 I2C_SCL <= 'Z';
343 I2C_SDA <= 'Z';
344  
345 -- SPI Memory Interface
346 SPI_CS_n <= 'Z';
347 SPI_DO <= 'Z';
348 SPI_DI <= 'Z';
349 SPI_CLK <= 'Z';
350 SPI_WP_n <= 'Z';
351  
352 ANA_OUTD <= 'Z';
353 ANA_REFD <= 'Z';
354  
355 VGA_R <= "ZZ";
356 VGA_G <= "ZZ";
357 VGA_B <= "ZZ";
358 VGA_VS <= 'Z';
359 VGA_HS <= 'Z';
360  
361 end architecture gtime_a;