Rev Author Line No. Line
1757 kakl 1  
2 //struct {
3 unsigned int8 firenum;
4 unsigned int8 div_fire;
5 unsigned int8 calresnum :2;
6 unsigned int8 clkhsdiv ;
7 unsigned int8 start_clkhs:1;
8 unsigned int8 portnum :1;
9 unsigned int8 Tcycle :1;
10 unsigned int8 fakenum :1;
11 unsigned int8 selclkT :1;
12 unsigned int8 calibrate :1;
13 unsigned int8 disautocal :1;
14 unsigned int8 MRange :1;
15 unsigned int8 neg_stop2 :1;
16 unsigned int8 neg_stop1 :1;
17 unsigned int8 neg_start :1;
18 //}reg0;
19  
20 //struct {
21 unsigned int hit2 :4;
22 unsigned int hit1 :4;
23 unsigned int fast_init :1;
24 unsigned int sc :1;
25 unsigned int hitin2 :3;
26 unsigned int hitin1 :3;
27 //}reg1;
28  
29 //struct {
30 unsigned int en_int :3;
31 unsigned int rfedge2 :1;
32 unsigned int rfedge1 :1;
33 unsigned int delval1 :3;
34 //}reg2;
35  
36 //struct {
37 unsigned int en_err_val :1;
38 unsigned int tim0_mr2 :2;
39 unsigned int32 delval :7;
40 //}reg3;
41  
42 //}TDC_registers;
43  
44  
1744 kakl 45 void TDC_init()
46 {
1745 kakl 47 output_low(TDC_ENABLE);
1744 kakl 48 spi_xfer(TDC_stream,0x70);
1745 kakl 49 output_high(TDC_ENABLE);
1744 kakl 50 }
51  
52 void TDC_reset()
53 {
1745 kakl 54 output_low(TDC_ENABLE);
1744 kakl 55 spi_xfer(TDC_stream,0x50);
1745 kakl 56 output_high(TDC_ENABLE);
1744 kakl 57 }
58  
59 void TDC_start_cycle()
60 {
1745 kakl 61 output_low(TDC_ENABLE);
1744 kakl 62 spi_xfer(TDC_stream,0x01);
1745 kakl 63 output_high(TDC_ENABLE);
1744 kakl 64 }
65  
66 void TDC_start_temp()
67 {
1745 kakl 68 output_low(TDC_ENABLE);
1744 kakl 69 spi_xfer(TDC_stream,0x02);
1745 kakl 70 output_high(TDC_ENABLE);
1744 kakl 71 }
72  
73 void TDC_start_cal_resonator()
74 {
1745 kakl 75 output_low(TDC_ENABLE);
1744 kakl 76 spi_xfer(TDC_stream,0x03);
1745 kakl 77 output_high(TDC_ENABLE);
1744 kakl 78 }
79  
80 void TDC_start_cal()
81 {
1745 kakl 82 output_low(TDC_ENABLE);
1744 kakl 83 spi_xfer(TDC_stream,0x04);
1745 kakl 84 output_high(TDC_ENABLE);
1744 kakl 85 }
86  
87 unsigned int32 TDC_get_measurement(int num)
88 {
1745 kakl 89 unsigned int32 ret;
90  
91 output_low(TDC_ENABLE);
1744 kakl 92 spi_xfer(TDC_stream,0xB0 + num - 1);
1745 kakl 93 ret=spi_xfer(TDC_stream,0,32);
94 output_high(TDC_ENABLE);
95 return ret;
1744 kakl 96 }
97  
98 unsigned int16 TDC_get_status()
99 {
1745 kakl 100 unsigned int16 ret;
101  
102 output_low(TDC_ENABLE);
103 spi_xfer(TDC_stream,0xB4,8);
104 ret=spi_xfer(TDC_stream,0,16);
105 output_high(TDC_ENABLE);
106 return ret;
1744 kakl 107 }
108  
109 unsigned int8 TDC_get_reg1()
110 {
1745 kakl 111 unsigned int8 ret;
112  
113 output_low(TDC_ENABLE);
114 spi_xfer(TDC_stream,0xB5,8);
115 ret=spi_xfer(TDC_stream,0,8);
116 output_high(TDC_ENABLE);
117 return ret;
1744 kakl 118 }
119  
1757 kakl 120 void TDC_update_registers()
1744 kakl 121 {
1745 kakl 122 output_low(TDC_ENABLE);
123 spi_xfer(TDC_stream,0x81,8);
1757 kakl 124 spi_xfer(TDC_stream,reg1.*,24);
1745 kakl 125 output_high(TDC_ENABLE);
1744 kakl 126  
1757 kakl 127 /* output_low(TDC_ENABLE);
1744 kakl 128 spi_xfer(TDC_stream,0xB1);
1745 kakl 129 output_high(TDC_ENABLE);
1744 kakl 130  
1745 kakl 131 output_low(TDC_ENABLE);
1744 kakl 132 spi_xfer(TDC_stream,0xB2);
1745 kakl 133 output_high(TDC_ENABLE);
1744 kakl 134  
1745 kakl 135 output_low(TDC_ENABLE);
1744 kakl 136 spi_xfer(TDC_stream,0xB3);
1745 kakl 137 output_high(TDC_ENABLE);
1744 kakl 138  
1745 kakl 139 output_low(TDC_ENABLE);
1744 kakl 140 spi_xfer(TDC_stream,0xB4);
1757 kakl 141 output_high(TDC_ENABLE); */
1744 kakl 142 }
1757 kakl 143  
144 void TDC_set_firenum()
145 {
146 reg0.Tcycle=TDC_TCYCLE_SHORT;
147 }