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0,0 → 1,46 |
Software Defined Radio Revised: Saturday, August 21, 2010 |
SDRX Revision: A |
Bill Of Materials December 8,2010 12:58:14 Page1 |
Quantity Reference Part |
______________________________________________ |
18 C1,C4,C8,C10,C12,C15,C19,C21,C23,C27,C30,C32,C36,C39,C40,C41,C42,C45 100nF |
15 C2,C5,C9,C11,C13,C16,C20,C22,C24,C31,C35,C43,C44,C46,C47 100uF |
6 C3,C6,C7,C14,C17,C18 4,7uF |
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4 C26,C29,C34,C38 22nF |
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1 F1 200mA |
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0,0 → 1,71 |
\documentclass[12pt,a4paper,oneside]{article} |
\usepackage[colorlinks=true]{hyperref} |
\usepackage[utf8]{inputenc} |
\usepackage[czech]{babel} |
\usepackage{graphicx} |
\textwidth 16cm \textheight 25cm |
\topmargin -1.3cm |
\oddsidemargin 0cm |
\pagestyle{empty} |
\begin{document} |
\title{Softwarově definovaný přijímač SDRX01A} |
\author{Jakub Kákona, kaklik@mlab.cz} |
\maketitle |
\begin{abstract} |
\end{abstract} |
\begin{figure} [htbp] |
\begin{center} |
\includegraphics [width=80mm] {SDRX01A_Top_Big.JPG} |
\end{center} |
\end{figure} |
\tableofcontents |
\section{Technické parametry} |
\begin{table}[htbp] |
\begin{center} |
\begin{tabular}{|c|c|c|} |
\hline |
\multicolumn{1}{|c|}{Parametr} & \multicolumn{1}{|c|}{Hodnota} & \multicolumn{1}{|c|}{Poznámka} \\ \hline |
Napájecí napětí analogové části & $\pm$10V & 100mA \\ \hline |
Napájecí napětí digitální části & +5V & 300mA \\ \hline |
Napájecí napětí LNA & do +20V & max 500mA \\ \hline |
Šumové číslo & $<$ 30dB & \\ \hline |
\end{tabular} |
\end{center} |
\end{table} |
\newpage |
\section{Popis konstrukce} |
\subsection{Zapojení} |
Zapojení přijímače vychází z původní konstrukce SDR přijímače DR2G \cite{DR2G} který požívá starší součástky. Nyní má změněný hlavně obvod vstupu pro lokální oscilátor a umožňuje tak používat přijímač na vyšších kmitočtech, neboť nedělí vstupní frekvenci 4mi, jako původní konstrukce ale pouze 2mi. To mimo jiné znamená, že nejvyšší pracovní kmitočet již není limitován vstupní logikou, ale analogovými spínači a v menší míře i převodníky LVPECL-CMOS těsně před spínači. Použitá diferenciální LVPECL logika navíc také umožňuje podstatně snížit vyzařování. Dále byly vyměněny analogové spínače ve směšovači. Ty nyní spínají trochu rychleji, ale hlavně mají lepší izolační parametry, což umožňuje lepší odstup signálu od šumu. |
Další nezbytnou saoučástí přijímače je lokální oscilátor, který se připojuje k přijímači pomocí krátkého SATA kabelu. Jako LO lze použít modul CLKGEN01 osazený 570ABB000107DG. SATA kabel je vhodné volit co nejkratší kvůli minimalizaci zemní smyčky a vyzařování. |
\subsection{Mechanická konstrukce} |
Mechanická konstrukce je řešena na dvouvrstvé desce s rozměry kompatibilními se základovou deskou MLAB. Dvouvrstvá deska je zvolena hlavně kvůli kvalitnímu odstínění okolního rušení horní měděnou vrstvou. To umožňuje přijímače instalovat i velmi blízko sebe případně i nad sebe avšak všechny konektory kromě NF audio výstupu předpokládají přivedení kabelu kolmo na rovinu desky. SMA konektor je možné osadit i úhlový s přivedením kabelu do boku, ale za cenu nepatrně vyššího útlumu úhlového konektoru. Při těsné montáži je potřeba počítat i s určitou teplotní stabilizací, neboť digitální část okolo spínaného směšovače má poměrně velký příkon a způsobuje zahřívání zhruba o 15$^\circ C$ nad okolní teplotu. |
\section{Výroba a testování} |
Výrobu vlastní desky pro přijímač nemohu doporučit. Neboť domácí výroba je dvouvrstvého plošného spoje je náročná sama o sobě a tento motiv plošného spoje navíc obsahuje plošky pro komponenty s poměrně vysokou třídou přesnosti. |
\subsubsection{Osazení} |
Vlastní osazeni přijímače předpokládá zvládnutí SMT technologie. Nejkomplikovanější část je letování analogových spínačů u kterých je nutné dát pozor na přehřátí a je tedy vhodné použít více pastového tavidla. |
\subsubsection{Nastavení} |
Pokud je přijímač osazen bez chyb a zkratů, tak nastavení přijímače spočívá v opatrném připojení na napájecí napětí. (Symetrický napájecí zdroj musí být dostatečně kvalitní a vyhlazený, aby nedocházelo k průniku rušení do analogové části. Je též vhodné aby zdroj měl proudové omezení.) A nastavení shodných amplitud obou výstupních kanálů I a Q na stejnou úroveň pomocí trimru na horní straně desky. To lze udělat buď pomocí zvukové karty a minimalizace zrcadlových kmitočtů nějakého relativně silného AM vysílače a nebo přesněji pomoci dvoukanálového osciloskopu v libovolné části pásma. Lze použít i metodu, kdy pomocí Jumperů, které slouží na výběr zesílení odpojíme jeden kanál (ten ve větvi s trimrem) a v softwaru si označíme aktuální úroveň signálu z antény. Pak analogicky kanál odpojíme připojíme naopak ten původně odpojený. Pomocí trimru pak nastavíme stejnou hodnotu signálu. Tento způsob je velmi jednoduchý a lze ho použít i za chodu. Ale že je potřeba ještě zkontrolovat fázový posun, který by mezi kanály měl být $\pi / 2$. |
\section{Programové vybavení} |
Základním programovým vybavením jsou všechny softwary využívající zvukovou kartu v komplexním režimu pro vstup signálu. Tedy například programy jako Winrad či Spectrum Lab. |
\begin{thebibliography}{99} |
\bibitem{DR2G}{Původní konstrukce přijímače DR2G} |
\href{http://yu1lm.qrpradio.com/SMT SDR RX DR2G-YU1LM.pdf}{http://yu1lm.qrpradio.com/SMT SDR RX DR2G-YU1LM.pdf} |
\end{thebibliography} |
\end{document} |
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0,0 → 1,18 |
- Je treba vyresit jinak spinani analogoveho prepinace. |
D klopne obvody sice budou generovat vhodny LO signal, ale ne s potrebnymi urovnemi pro spinani CMOS hradla. PECL vystup klopneho obvodu dava presne katalogove hodnoty vystupniho napeti i po zatizeni 100ohm odporem a rozkmit je stale pouze 0,8V. Obvody pro translaci z PECL na CMOS asi nebudou vhodne reseni, protoze jsou tezko dostupne a navic za vysokou cenu. |
<- bylo vyzkouseno zapojeni translatoru z patentu US3766406 s vysledkem, ze prestane fungovat na frekvenci okolo 50MHz. Nakonec bylo tedy rozhodnuto o pouziti integrovaneho translatoru. |
Diky pouziti integrovaneho translatoru bude snizeno napajeci napeti digitalni casti na 3.3V. Tim odpada i nutnost stridave vazby na vstupu LVPECL hodin. |
Na zkusebnim prototypu se ukazala vaznost precizniho blokovani napajeni aby nedochazelo k prusaku ruseni z digitalni casti do analogove. Zda se totiz, ze pila generovana na vystupu operaku souvisi s blokovanim. Nebot existence pily je zavisla na frekvenci a vykonu LO. |
- Zkontrolovat, že všechna napájení včetně přívodů do analogové části jsou řádně odrušena. A oznacena |
- Oddelit napajeni LNA od napajeni vystupnich operacnich zesilovacu. |
- Odpojit GND u vystupnich cinch konektoru. |
- Pridat logo UST |
- Zkontrolovat popisky |
- Oznacit trimr. |
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[InfoShortDescription.en] |
SDR Receiver |
[InfoShortDescription.cs] |
SDR přijímač |
[InfoLongDescription.en] |
A improved design of well known DR2G software defined receiver. It is capable to work up to 200-250MHz |
[InfoLongDescription.cs] |
Vylepšená konstrukce softwarově definovaného přijímače DR2G. Nyní použitelná až do 200-250MHz. |
[End] |
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