| /Designs/HAM Constructions/SDRX02A/HDL/modules/comm/spi_master_transmit.vhd |
|---|
| 0,0 → 1,132 |
| -- this module transmit a given constant data when requested |
| -- and then signals done. |
| -- |
| -- G_DATA has to contain also the address and the r/w bit |
| -- |
| -- MSB of G_DATA will go first |
| -- P1DATA_P2DATA_P3DATA |
| -- |
| -- version for multiple devices with different data |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| entity spi_master_transmit is |
| generic ( |
| G_DATA1 : std_logic_vector; |
| G_DATA2 : std_logic_vector; |
| G_NUM_BITS_PACKET : integer; |
| G_NUM_PACKETS : integer; |
| G_NUM_BITS_PAUSE : integer |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| o_done : out std_logic; |
| -- selects which data to transfer. If '0', it transfers G_DATA1 |
| i_data_selector : in std_logic; |
| -- SPI ports: |
| o_n_ce : out std_logic_vector; |
| o_dout : out std_logic; |
| o_clk : out std_logic |
| ); |
| end spi_master_transmit; |
| architecture behavioral of spi_master_transmit is |
| subtype t_pause_counter is integer range 0 to G_NUM_BITS_PAUSE; |
| signal s_pause_counter : t_pause_counter; |
| subtype t_bit_counter is integer range 0 to G_NUM_BITS_PACKET - 1; |
| signal s_bit_counter : t_bit_counter; |
| subtype t_packet_counter is integer range 0 to G_NUM_PACKETS; |
| signal s_packet_counter : t_packet_counter; |
| subtype t_device_counter is integer range 0 to o_n_ce'length - 1; |
| signal s_device_counter : t_device_counter; |
| signal s_clk_inv : std_logic; |
| --signal s_o_dout_d : std_logic; |
| signal s_o_clk_en : std_logic; |
| constant C_DATALEN_PER_DEVICE : integer := G_NUM_BITS_PACKET*G_NUM_PACKETS; |
| signal s_cs_out : std_logic_vector( o_n_ce'range ); |
| begin |
| assert( G_DATA1'length = C_DATALEN_PER_DEVICE*o_n_ce'length ) report "The size of G_DATA1 does not match the number of devices and other generics." severity failure; |
| assert( G_DATA2'length = C_DATALEN_PER_DEVICE*o_n_ce'length ) report "The size of G_DATA2 does not match the number of devices and other generics." severity failure; |
| -- inverted clock: |
| s_clk_inv <= not i_clk; |
| -- output clock: |
| o_clk <= i_clk and s_o_clk_en; |
| -- done: |
| o_done <= '1' when ( (i_rst = '0') and (s_packet_counter = 0) and (s_pause_counter = 0) and (s_bit_counter = 0 ) and (s_device_counter=0) ) else |
| '0'; |
| transmitter_process : process( s_clk_inv ) |
| begin |
| if( rising_edge( s_clk_inv ) ) then |
| if( i_rst = '1' ) then |
| s_bit_counter <= 0; |
| s_pause_counter <= t_pause_counter'high; |
| s_packet_counter <= t_packet_counter'high; |
| s_device_counter <= t_device_counter'high; |
| s_cs_out( s_cs_out'low ) <= '0'; |
| s_cs_out( s_cs_out'high downto s_cs_out'low+1 ) <= ( others => '1' ); |
| o_n_ce <= ( o_n_ce'range => '1' ); |
| o_dout <= '0'; |
| s_o_clk_en <= '0'; |
| elsif( s_bit_counter > 0 ) then |
| o_n_ce <= s_cs_out; |
| if( i_data_selector = '0' ) then |
| o_dout <= G_DATA1( s_bit_counter + s_packet_counter*G_NUM_BITS_PACKET - 1 + s_device_counter*C_DATALEN_PER_DEVICE ); -- here s_packet_counter points to the current packet and s_bit_counter is one bit behind, therefore the -1. |
| else |
| o_dout <= G_DATA2( s_bit_counter + s_packet_counter*G_NUM_BITS_PACKET - 1 + s_device_counter*C_DATALEN_PER_DEVICE ); |
| end if; |
| s_bit_counter <= s_bit_counter - 1; |
| s_o_clk_en <= '1'; |
| elsif( s_pause_counter > 0 ) then |
| o_n_ce <= ( o_n_ce'range => '1' ); |
| s_pause_counter <= s_pause_counter - 1; |
| o_dout <= '0'; |
| s_o_clk_en <= '0'; |
| elsif( s_packet_counter > 0 ) then |
| s_bit_counter <= t_bit_counter'high; |
| s_pause_counter <= t_pause_counter'high; |
| s_packet_counter <= s_packet_counter - 1; |
| o_n_ce <= s_cs_out; |
| if( i_data_selector = '0' ) then |
| o_dout <= G_DATA1( s_bit_counter + s_packet_counter*G_NUM_BITS_PACKET - 1 + s_device_counter*C_DATALEN_PER_DEVICE ); -- here s_bit_counter = 0, s_packet_counter points to previous packet. Therefore -1 to get the msb of current packet. |
| else |
| o_dout <= G_DATA2( s_bit_counter + s_packet_counter*G_NUM_BITS_PACKET - 1 + s_device_counter*C_DATALEN_PER_DEVICE ); |
| end if; |
| s_o_clk_en <= '1'; |
| elsif( s_device_counter > 0 ) then |
| s_cs_out <= s_cs_out( s_cs_out'high-1 downto s_cs_out'low ) & '1'; |
| s_device_counter <= s_device_counter - 1; |
| -- follows pause. |
| s_bit_counter <= 0; |
| s_pause_counter <= t_pause_counter'high; |
| s_packet_counter <= t_packet_counter'high; |
| o_n_ce <= ( o_n_ce'range => '1' ); |
| o_dout <= '0'; |
| s_o_clk_en <= '0'; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/core_generator_ml605/clk_125MHz_to_6MHz.xco |
|---|
| 0,0 → 1,269 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue May 6 10:43:16 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:clk_wiz:3.6 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 |
| # END Select |
| # BEGIN Parameters |
| CSET calc_done=DONE |
| CSET clk_in_sel_port=CLK_IN_SEL |
| CSET clk_out1_port=CLK_OUT_6 |
| CSET clk_out1_use_fine_ps_gui=false |
| CSET clk_out2_port=CLK_OUT2 |
| CSET clk_out2_use_fine_ps_gui=false |
| CSET clk_out3_port=CLK_OUT3 |
| CSET clk_out3_use_fine_ps_gui=false |
| CSET clk_out4_port=CLK_OUT4 |
| CSET clk_out4_use_fine_ps_gui=false |
| CSET clk_out5_port=CLK_OUT5 |
| CSET clk_out5_use_fine_ps_gui=false |
| CSET clk_out6_port=CLK_OUT6 |
| CSET clk_out6_use_fine_ps_gui=false |
| CSET clk_out7_port=CLK_OUT7 |
| CSET clk_out7_use_fine_ps_gui=false |
| CSET clk_valid_port=CLK_VALID |
| CSET clkfb_in_n_port=CLKFB_IN_N |
| CSET clkfb_in_p_port=CLKFB_IN_P |
| CSET clkfb_in_port=CLKFB_IN |
| CSET clkfb_in_signaling=SINGLE |
| CSET clkfb_out_n_port=CLKFB_OUT_N |
| CSET clkfb_out_p_port=CLKFB_OUT_P |
| CSET clkfb_out_port=CLKFB_OUT |
| CSET clkfb_stopped_port=CLKFB_STOPPED |
| CSET clkin1_jitter_ps=80.0 |
| CSET clkin1_ui_jitter=0.010 |
| CSET clkin2_jitter_ps=100.0 |
| CSET clkin2_ui_jitter=0.010 |
| CSET clkout1_drives=BUFG |
| CSET clkout1_requested_duty_cycle=50.000 |
| CSET clkout1_requested_out_freq=100.000 |
| CSET clkout1_requested_phase=0.000 |
| CSET clkout2_drives=BUFG |
| CSET clkout2_requested_duty_cycle=50.000 |
| CSET clkout2_requested_out_freq=100.000 |
| CSET clkout2_requested_phase=0.000 |
| CSET clkout2_used=false |
| CSET clkout3_drives=BUFG |
| CSET clkout3_requested_duty_cycle=50.000 |
| CSET clkout3_requested_out_freq=100.000 |
| CSET clkout3_requested_phase=0.000 |
| CSET clkout3_used=false |
| CSET clkout4_drives=BUFG |
| CSET clkout4_requested_duty_cycle=50.000 |
| CSET clkout4_requested_out_freq=100.000 |
| CSET clkout4_requested_phase=0.000 |
| CSET clkout4_used=false |
| CSET clkout5_drives=BUFG |
| CSET clkout5_requested_duty_cycle=50.000 |
| CSET clkout5_requested_out_freq=100.000 |
| CSET clkout5_requested_phase=0.000 |
| CSET clkout5_used=false |
| CSET clkout6_drives=BUFG |
| CSET clkout6_requested_duty_cycle=50.000 |
| CSET clkout6_requested_out_freq=100.000 |
| CSET clkout6_requested_phase=0.000 |
| CSET clkout6_used=false |
| CSET clkout7_drives=BUFG |
| CSET clkout7_requested_duty_cycle=50.000 |
| CSET clkout7_requested_out_freq=100.000 |
| CSET clkout7_requested_phase=0.000 |
| CSET clkout7_used=false |
| CSET clock_mgr_type=MANUAL |
| CSET component_name=clk_125MHz_to_6MHz |
| CSET daddr_port=DADDR |
| CSET dclk_port=DCLK |
| CSET dcm_clk_feedback=1X |
| CSET dcm_clk_out1_port=CLK0 |
| CSET dcm_clk_out2_port=CLK0 |
| CSET dcm_clk_out3_port=CLK0 |
| CSET dcm_clk_out4_port=CLK0 |
| CSET dcm_clk_out5_port=CLK0 |
| CSET dcm_clk_out6_port=CLK0 |
| CSET dcm_clkdv_divide=2.0 |
| CSET dcm_clkfx_divide=1 |
| CSET dcm_clkfx_multiply=4 |
| CSET dcm_clkgen_clk_out1_port=CLKFX |
| CSET dcm_clkgen_clk_out2_port=CLKFX |
| CSET dcm_clkgen_clk_out3_port=CLKFX |
| CSET dcm_clkgen_clkfx_divide=1 |
| CSET dcm_clkgen_clkfx_md_max=0.000 |
| CSET dcm_clkgen_clkfx_multiply=4 |
| CSET dcm_clkgen_clkfxdv_divide=2 |
| CSET dcm_clkgen_clkin_period=10.000 |
| CSET dcm_clkgen_notes=None |
| CSET dcm_clkgen_spread_spectrum=NONE |
| CSET dcm_clkgen_startup_wait=false |
| CSET dcm_clkin_divide_by_2=false |
| CSET dcm_clkin_period=10.000 |
| CSET dcm_clkout_phase_shift=NONE |
| CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS |
| CSET dcm_notes=None |
| CSET dcm_phase_shift=0 |
| CSET dcm_pll_cascade=NONE |
| CSET dcm_startup_wait=false |
| CSET den_port=DEN |
| CSET din_port=DIN |
| CSET dout_port=DOUT |
| CSET drdy_port=DRDY |
| CSET dwe_port=DWE |
| CSET feedback_source=FDBK_AUTO |
| CSET in_freq_units=Units_MHz |
| CSET in_jitter_units=Units_UI |
| CSET input_clk_stopped_port=INPUT_CLK_STOPPED |
| CSET jitter_options=UI |
| CSET jitter_sel=No_Jitter |
| CSET locked_port=LOCKED |
| CSET mmcm_bandwidth=OPTIMIZED |
| CSET mmcm_clkfbout_mult_f=6.000 |
| CSET mmcm_clkfbout_phase=0.000 |
| CSET mmcm_clkfbout_use_fine_ps=false |
| CSET mmcm_clkin1_period=8.000 |
| CSET mmcm_clkin2_period=10.0 |
| CSET mmcm_clkout0_divide_f=125.000 |
| CSET mmcm_clkout0_duty_cycle=0.500 |
| CSET mmcm_clkout0_phase=0.000 |
| CSET mmcm_clkout0_use_fine_ps=false |
| CSET mmcm_clkout1_divide=1 |
| CSET mmcm_clkout1_duty_cycle=0.500 |
| CSET mmcm_clkout1_phase=0.000 |
| CSET mmcm_clkout1_use_fine_ps=false |
| CSET mmcm_clkout2_divide=1 |
| CSET mmcm_clkout2_duty_cycle=0.500 |
| CSET mmcm_clkout2_phase=0.000 |
| CSET mmcm_clkout2_use_fine_ps=false |
| CSET mmcm_clkout3_divide=1 |
| CSET mmcm_clkout3_duty_cycle=0.500 |
| CSET mmcm_clkout3_phase=0.000 |
| CSET mmcm_clkout3_use_fine_ps=false |
| CSET mmcm_clkout4_cascade=false |
| CSET mmcm_clkout4_divide=1 |
| CSET mmcm_clkout4_duty_cycle=0.500 |
| CSET mmcm_clkout4_phase=0.000 |
| CSET mmcm_clkout4_use_fine_ps=false |
| CSET mmcm_clkout5_divide=1 |
| CSET mmcm_clkout5_duty_cycle=0.500 |
| CSET mmcm_clkout5_phase=0.000 |
| CSET mmcm_clkout5_use_fine_ps=false |
| CSET mmcm_clkout6_divide=1 |
| CSET mmcm_clkout6_duty_cycle=0.500 |
| CSET mmcm_clkout6_phase=0.000 |
| CSET mmcm_clkout6_use_fine_ps=false |
| CSET mmcm_clock_hold=false |
| CSET mmcm_compensation=ZHOLD |
| CSET mmcm_divclk_divide=1 |
| CSET mmcm_notes=None |
| CSET mmcm_ref_jitter1=0.010 |
| CSET mmcm_ref_jitter2=0.010 |
| CSET mmcm_startup_wait=false |
| CSET num_out_clks=1 |
| CSET override_dcm=false |
| CSET override_dcm_clkgen=false |
| CSET override_mmcm=false |
| CSET override_pll=false |
| CSET platform=lin64 |
| CSET pll_bandwidth=OPTIMIZED |
| CSET pll_clk_feedback=CLKFBOUT |
| CSET pll_clkfbout_mult=4 |
| CSET pll_clkfbout_phase=0.000 |
| CSET pll_clkin_period=10.000 |
| CSET pll_clkout0_divide=1 |
| CSET pll_clkout0_duty_cycle=0.500 |
| CSET pll_clkout0_phase=0.000 |
| CSET pll_clkout1_divide=1 |
| CSET pll_clkout1_duty_cycle=0.500 |
| CSET pll_clkout1_phase=0.000 |
| CSET pll_clkout2_divide=1 |
| CSET pll_clkout2_duty_cycle=0.500 |
| CSET pll_clkout2_phase=0.000 |
| CSET pll_clkout3_divide=1 |
| CSET pll_clkout3_duty_cycle=0.500 |
| CSET pll_clkout3_phase=0.000 |
| CSET pll_clkout4_divide=1 |
| CSET pll_clkout4_duty_cycle=0.500 |
| CSET pll_clkout4_phase=0.000 |
| CSET pll_clkout5_divide=1 |
| CSET pll_clkout5_duty_cycle=0.500 |
| CSET pll_clkout5_phase=0.000 |
| CSET pll_compensation=SYSTEM_SYNCHRONOUS |
| CSET pll_divclk_divide=1 |
| CSET pll_notes=None |
| CSET pll_ref_jitter=0.010 |
| CSET power_down_port=POWER_DOWN |
| CSET prim_in_freq=125 |
| CSET prim_in_jitter=0.010 |
| CSET prim_source=Global_buffer |
| CSET primary_port=CLK_IN_125 |
| CSET primitive=MMCM |
| CSET primtype_sel=MMCM_ADV |
| CSET psclk_port=PSCLK |
| CSET psdone_port=PSDONE |
| CSET psen_port=PSEN |
| CSET psincdec_port=PSINCDEC |
| CSET relative_inclk=REL_PRIMARY |
| CSET reset_port=RESET |
| CSET secondary_in_freq=100.000 |
| CSET secondary_in_jitter=0.010 |
| CSET secondary_port=CLK_IN2 |
| CSET secondary_source=Single_ended_clock_capable_pin |
| CSET ss_mod_freq=250 |
| CSET ss_mode=CENTER_HIGH |
| CSET status_port=STATUS |
| CSET summary_strings=empty |
| CSET use_clk_valid=false |
| CSET use_clkfb_stopped=false |
| CSET use_dyn_phase_shift=false |
| CSET use_dyn_reconfig=false |
| CSET use_freeze=false |
| CSET use_freq_synth=true |
| CSET use_inclk_stopped=false |
| CSET use_inclk_switchover=false |
| CSET use_locked=false |
| CSET use_max_i_jitter=false |
| CSET use_min_o_jitter=false |
| CSET use_min_power=false |
| CSET use_phase_alignment=true |
| CSET use_power_down=false |
| CSET use_reset=false |
| CSET use_spread_spectrum=false |
| CSET use_spread_spectrum_1=false |
| CSET use_status=false |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-05-10T12:44:55Z |
| # END Extra information |
| GENERATE |
| # CRC: 255c3699 |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/core_generator_ml605/fifo_32x512.xco |
|---|
| 0,0 → 1,213 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue Apr 29 09:14:51 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:fifo_generator:9.2 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT Fifo_Generator xilinx.com:ip:fifo_generator:9.2 |
| # END Select |
| # BEGIN Parameters |
| CSET add_ngc_constraint_axi=false |
| CSET almost_empty_flag=false |
| CSET almost_full_flag=false |
| CSET aruser_width=1 |
| CSET awuser_width=1 |
| CSET axi_address_width=32 |
| CSET axi_data_width=64 |
| CSET axi_type=AXI4_Stream |
| CSET axis_type=FIFO |
| CSET buser_width=1 |
| CSET clock_enable_type=Slave_Interface_Clock_Enable |
| CSET clock_type_axi=Common_Clock |
| CSET component_name=fifo_32x512 |
| CSET data_count=false |
| CSET data_count_width=9 |
| CSET disable_timing_violations=false |
| CSET disable_timing_violations_axi=false |
| CSET dout_reset_value=0 |
| CSET empty_threshold_assert_value=2 |
| CSET empty_threshold_assert_value_axis=1022 |
| CSET empty_threshold_assert_value_rach=1022 |
| CSET empty_threshold_assert_value_rdch=1022 |
| CSET empty_threshold_assert_value_wach=1022 |
| CSET empty_threshold_assert_value_wdch=1022 |
| CSET empty_threshold_assert_value_wrch=1022 |
| CSET empty_threshold_negate_value=3 |
| CSET enable_aruser=false |
| CSET enable_awuser=false |
| CSET enable_buser=false |
| CSET enable_common_overflow=false |
| CSET enable_common_underflow=false |
| CSET enable_data_counts_axis=false |
| CSET enable_data_counts_rach=false |
| CSET enable_data_counts_rdch=false |
| CSET enable_data_counts_wach=false |
| CSET enable_data_counts_wdch=false |
| CSET enable_data_counts_wrch=false |
| CSET enable_ecc=false |
| CSET enable_ecc_axis=false |
| CSET enable_ecc_rach=false |
| CSET enable_ecc_rdch=false |
| CSET enable_ecc_wach=false |
| CSET enable_ecc_wdch=false |
| CSET enable_ecc_wrch=false |
| CSET enable_read_channel=false |
| CSET enable_read_pointer_increment_by2=false |
| CSET enable_reset_synchronization=true |
| CSET enable_ruser=false |
| CSET enable_tdata=false |
| CSET enable_tdest=false |
| CSET enable_tid=false |
| CSET enable_tkeep=false |
| CSET enable_tlast=false |
| CSET enable_tready=true |
| CSET enable_tstrobe=false |
| CSET enable_tuser=false |
| CSET enable_write_channel=false |
| CSET enable_wuser=false |
| CSET fifo_application_type_axis=Data_FIFO |
| CSET fifo_application_type_rach=Data_FIFO |
| CSET fifo_application_type_rdch=Data_FIFO |
| CSET fifo_application_type_wach=Data_FIFO |
| CSET fifo_application_type_wdch=Data_FIFO |
| CSET fifo_application_type_wrch=Data_FIFO |
| CSET fifo_implementation=Common_Clock_Block_RAM |
| CSET fifo_implementation_axis=Common_Clock_Block_RAM |
| CSET fifo_implementation_rach=Common_Clock_Block_RAM |
| CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wach=Common_Clock_Block_RAM |
| CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
| CSET full_flags_reset_value=0 |
| CSET full_threshold_assert_value=510 |
| CSET full_threshold_assert_value_axis=1023 |
| CSET full_threshold_assert_value_rach=1023 |
| CSET full_threshold_assert_value_rdch=1023 |
| CSET full_threshold_assert_value_wach=1023 |
| CSET full_threshold_assert_value_wdch=1023 |
| CSET full_threshold_assert_value_wrch=1023 |
| CSET full_threshold_negate_value=509 |
| CSET id_width=4 |
| CSET inject_dbit_error=false |
| CSET inject_dbit_error_axis=false |
| CSET inject_dbit_error_rach=false |
| CSET inject_dbit_error_rdch=false |
| CSET inject_dbit_error_wach=false |
| CSET inject_dbit_error_wdch=false |
| CSET inject_dbit_error_wrch=false |
| CSET inject_sbit_error=false |
| CSET inject_sbit_error_axis=false |
| CSET inject_sbit_error_rach=false |
| CSET inject_sbit_error_rdch=false |
| CSET inject_sbit_error_wach=false |
| CSET inject_sbit_error_wdch=false |
| CSET inject_sbit_error_wrch=false |
| CSET input_data_width=32 |
| CSET input_depth=512 |
| CSET input_depth_axis=1024 |
| CSET input_depth_rach=16 |
| CSET input_depth_rdch=1024 |
| CSET input_depth_wach=16 |
| CSET input_depth_wdch=1024 |
| CSET input_depth_wrch=16 |
| CSET interface_type=Native |
| CSET output_data_width=32 |
| CSET output_depth=512 |
| CSET overflow_flag=false |
| CSET overflow_flag_axi=false |
| CSET overflow_sense=Active_High |
| CSET overflow_sense_axi=Active_High |
| CSET performance_options=Standard_FIFO |
| CSET programmable_empty_type=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
| CSET programmable_full_type=No_Programmable_Full_Threshold |
| CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
| CSET rach_type=FIFO |
| CSET rdch_type=FIFO |
| CSET read_clock_frequency=1 |
| CSET read_data_count=false |
| CSET read_data_count_width=9 |
| CSET register_slice_mode_axis=Fully_Registered |
| CSET register_slice_mode_rach=Fully_Registered |
| CSET register_slice_mode_rdch=Fully_Registered |
| CSET register_slice_mode_wach=Fully_Registered |
| CSET register_slice_mode_wdch=Fully_Registered |
| CSET register_slice_mode_wrch=Fully_Registered |
| CSET reset_pin=true |
| CSET reset_type=Synchronous_Reset |
| CSET ruser_width=1 |
| CSET synchronization_stages=2 |
| CSET synchronization_stages_axi=2 |
| CSET tdata_width=64 |
| CSET tdest_width=4 |
| CSET tid_width=8 |
| CSET tkeep_width=4 |
| CSET tstrb_width=4 |
| CSET tuser_width=4 |
| CSET underflow_flag=false |
| CSET underflow_flag_axi=false |
| CSET underflow_sense=Active_High |
| CSET underflow_sense_axi=Active_High |
| CSET use_clock_enable=false |
| CSET use_dout_reset=true |
| CSET use_embedded_registers=false |
| CSET use_extra_logic=false |
| CSET valid_flag=true |
| CSET valid_sense=Active_High |
| CSET wach_type=FIFO |
| CSET wdch_type=FIFO |
| CSET wrch_type=FIFO |
| CSET write_acknowledge_flag=false |
| CSET write_acknowledge_sense=Active_High |
| CSET write_clock_frequency=1 |
| CSET write_data_count=false |
| CSET write_data_count_width=9 |
| CSET wuser_width=1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-06-23T13:35:37Z |
| # END Extra information |
| GENERATE |
| # CRC: e2c6d431 |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/core_generator_ml605/fifo_32x512_dualclk_fwft.xco |
|---|
| 0,0 → 1,213 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue May 6 09:52:07 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:fifo_generator:9.3 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 |
| # END Select |
| # BEGIN Parameters |
| CSET add_ngc_constraint_axi=false |
| CSET almost_empty_flag=false |
| CSET almost_full_flag=false |
| CSET aruser_width=1 |
| CSET awuser_width=1 |
| CSET axi_address_width=32 |
| CSET axi_data_width=64 |
| CSET axi_type=AXI4_Stream |
| CSET axis_type=FIFO |
| CSET buser_width=1 |
| CSET clock_enable_type=Slave_Interface_Clock_Enable |
| CSET clock_type_axi=Common_Clock |
| CSET component_name=fifo_32x512_dualclk_fwft |
| CSET data_count=false |
| CSET data_count_width=9 |
| CSET disable_timing_violations=false |
| CSET disable_timing_violations_axi=false |
| CSET dout_reset_value=0 |
| CSET empty_threshold_assert_value=4 |
| CSET empty_threshold_assert_value_axis=1022 |
| CSET empty_threshold_assert_value_rach=1022 |
| CSET empty_threshold_assert_value_rdch=1022 |
| CSET empty_threshold_assert_value_wach=1022 |
| CSET empty_threshold_assert_value_wdch=1022 |
| CSET empty_threshold_assert_value_wrch=1022 |
| CSET empty_threshold_negate_value=5 |
| CSET enable_aruser=false |
| CSET enable_awuser=false |
| CSET enable_buser=false |
| CSET enable_common_overflow=false |
| CSET enable_common_underflow=false |
| CSET enable_data_counts_axis=false |
| CSET enable_data_counts_rach=false |
| CSET enable_data_counts_rdch=false |
| CSET enable_data_counts_wach=false |
| CSET enable_data_counts_wdch=false |
| CSET enable_data_counts_wrch=false |
| CSET enable_ecc=false |
| CSET enable_ecc_axis=false |
| CSET enable_ecc_rach=false |
| CSET enable_ecc_rdch=false |
| CSET enable_ecc_wach=false |
| CSET enable_ecc_wdch=false |
| CSET enable_ecc_wrch=false |
| CSET enable_read_channel=false |
| CSET enable_read_pointer_increment_by2=false |
| CSET enable_reset_synchronization=true |
| CSET enable_ruser=false |
| CSET enable_tdata=false |
| CSET enable_tdest=false |
| CSET enable_tid=false |
| CSET enable_tkeep=false |
| CSET enable_tlast=false |
| CSET enable_tready=true |
| CSET enable_tstrobe=false |
| CSET enable_tuser=false |
| CSET enable_write_channel=false |
| CSET enable_wuser=false |
| CSET fifo_application_type_axis=Data_FIFO |
| CSET fifo_application_type_rach=Data_FIFO |
| CSET fifo_application_type_rdch=Data_FIFO |
| CSET fifo_application_type_wach=Data_FIFO |
| CSET fifo_application_type_wdch=Data_FIFO |
| CSET fifo_application_type_wrch=Data_FIFO |
| CSET fifo_implementation=Independent_Clocks_Block_RAM |
| CSET fifo_implementation_axis=Common_Clock_Block_RAM |
| CSET fifo_implementation_rach=Common_Clock_Block_RAM |
| CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wach=Common_Clock_Block_RAM |
| CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
| CSET full_flags_reset_value=1 |
| CSET full_threshold_assert_value=511 |
| CSET full_threshold_assert_value_axis=1023 |
| CSET full_threshold_assert_value_rach=1023 |
| CSET full_threshold_assert_value_rdch=1023 |
| CSET full_threshold_assert_value_wach=1023 |
| CSET full_threshold_assert_value_wdch=1023 |
| CSET full_threshold_assert_value_wrch=1023 |
| CSET full_threshold_negate_value=510 |
| CSET id_width=4 |
| CSET inject_dbit_error=false |
| CSET inject_dbit_error_axis=false |
| CSET inject_dbit_error_rach=false |
| CSET inject_dbit_error_rdch=false |
| CSET inject_dbit_error_wach=false |
| CSET inject_dbit_error_wdch=false |
| CSET inject_dbit_error_wrch=false |
| CSET inject_sbit_error=false |
| CSET inject_sbit_error_axis=false |
| CSET inject_sbit_error_rach=false |
| CSET inject_sbit_error_rdch=false |
| CSET inject_sbit_error_wach=false |
| CSET inject_sbit_error_wdch=false |
| CSET inject_sbit_error_wrch=false |
| CSET input_data_width=32 |
| CSET input_depth=512 |
| CSET input_depth_axis=1024 |
| CSET input_depth_rach=16 |
| CSET input_depth_rdch=1024 |
| CSET input_depth_wach=16 |
| CSET input_depth_wdch=1024 |
| CSET input_depth_wrch=16 |
| CSET interface_type=Native |
| CSET output_data_width=32 |
| CSET output_depth=512 |
| CSET overflow_flag=false |
| CSET overflow_flag_axi=false |
| CSET overflow_sense=Active_High |
| CSET overflow_sense_axi=Active_High |
| CSET performance_options=First_Word_Fall_Through |
| CSET programmable_empty_type=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
| CSET programmable_full_type=No_Programmable_Full_Threshold |
| CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
| CSET rach_type=FIFO |
| CSET rdch_type=FIFO |
| CSET read_clock_frequency=1 |
| CSET read_data_count=false |
| CSET read_data_count_width=9 |
| CSET register_slice_mode_axis=Fully_Registered |
| CSET register_slice_mode_rach=Fully_Registered |
| CSET register_slice_mode_rdch=Fully_Registered |
| CSET register_slice_mode_wach=Fully_Registered |
| CSET register_slice_mode_wdch=Fully_Registered |
| CSET register_slice_mode_wrch=Fully_Registered |
| CSET reset_pin=true |
| CSET reset_type=Asynchronous_Reset |
| CSET ruser_width=1 |
| CSET synchronization_stages=2 |
| CSET synchronization_stages_axi=2 |
| CSET tdata_width=64 |
| CSET tdest_width=4 |
| CSET tid_width=8 |
| CSET tkeep_width=4 |
| CSET tstrb_width=4 |
| CSET tuser_width=4 |
| CSET underflow_flag=false |
| CSET underflow_flag_axi=false |
| CSET underflow_sense=Active_High |
| CSET underflow_sense_axi=Active_High |
| CSET use_clock_enable=false |
| CSET use_dout_reset=false |
| CSET use_embedded_registers=false |
| CSET use_extra_logic=false |
| CSET valid_flag=true |
| CSET valid_sense=Active_High |
| CSET wach_type=FIFO |
| CSET wdch_type=FIFO |
| CSET wrch_type=FIFO |
| CSET write_acknowledge_flag=false |
| CSET write_acknowledge_sense=Active_High |
| CSET write_clock_frequency=1 |
| CSET write_data_count=false |
| CSET write_data_count_width=9 |
| CSET wuser_width=1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-07-25T18:11:59Z |
| # END Extra information |
| GENERATE |
| # CRC: 19014e08 |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/core_generator_ml605/fifo_32x512_walmostfull.xco |
|---|
| 0,0 → 1,213 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue May 6 09:54:30 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:fifo_generator:9.3 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 |
| # END Select |
| # BEGIN Parameters |
| CSET add_ngc_constraint_axi=false |
| CSET almost_empty_flag=false |
| CSET almost_full_flag=false |
| CSET aruser_width=1 |
| CSET awuser_width=1 |
| CSET axi_address_width=32 |
| CSET axi_data_width=64 |
| CSET axi_type=AXI4_Stream |
| CSET axis_type=FIFO |
| CSET buser_width=1 |
| CSET clock_enable_type=Slave_Interface_Clock_Enable |
| CSET clock_type_axi=Common_Clock |
| CSET component_name=fifo_32x512_walmostfull |
| CSET data_count=false |
| CSET data_count_width=9 |
| CSET disable_timing_violations=false |
| CSET disable_timing_violations_axi=false |
| CSET dout_reset_value=0 |
| CSET empty_threshold_assert_value=2 |
| CSET empty_threshold_assert_value_axis=1022 |
| CSET empty_threshold_assert_value_rach=1022 |
| CSET empty_threshold_assert_value_rdch=1022 |
| CSET empty_threshold_assert_value_wach=1022 |
| CSET empty_threshold_assert_value_wdch=1022 |
| CSET empty_threshold_assert_value_wrch=1022 |
| CSET empty_threshold_negate_value=3 |
| CSET enable_aruser=false |
| CSET enable_awuser=false |
| CSET enable_buser=false |
| CSET enable_common_overflow=false |
| CSET enable_common_underflow=false |
| CSET enable_data_counts_axis=false |
| CSET enable_data_counts_rach=false |
| CSET enable_data_counts_rdch=false |
| CSET enable_data_counts_wach=false |
| CSET enable_data_counts_wdch=false |
| CSET enable_data_counts_wrch=false |
| CSET enable_ecc=false |
| CSET enable_ecc_axis=false |
| CSET enable_ecc_rach=false |
| CSET enable_ecc_rdch=false |
| CSET enable_ecc_wach=false |
| CSET enable_ecc_wdch=false |
| CSET enable_ecc_wrch=false |
| CSET enable_read_channel=false |
| CSET enable_read_pointer_increment_by2=false |
| CSET enable_reset_synchronization=true |
| CSET enable_ruser=false |
| CSET enable_tdata=false |
| CSET enable_tdest=false |
| CSET enable_tid=false |
| CSET enable_tkeep=false |
| CSET enable_tlast=false |
| CSET enable_tready=true |
| CSET enable_tstrobe=false |
| CSET enable_tuser=false |
| CSET enable_write_channel=false |
| CSET enable_wuser=false |
| CSET fifo_application_type_axis=Data_FIFO |
| CSET fifo_application_type_rach=Data_FIFO |
| CSET fifo_application_type_rdch=Data_FIFO |
| CSET fifo_application_type_wach=Data_FIFO |
| CSET fifo_application_type_wdch=Data_FIFO |
| CSET fifo_application_type_wrch=Data_FIFO |
| CSET fifo_implementation=Common_Clock_Block_RAM |
| CSET fifo_implementation_axis=Common_Clock_Block_RAM |
| CSET fifo_implementation_rach=Common_Clock_Block_RAM |
| CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wach=Common_Clock_Block_RAM |
| CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
| CSET full_flags_reset_value=0 |
| CSET full_threshold_assert_value=400 |
| CSET full_threshold_assert_value_axis=1023 |
| CSET full_threshold_assert_value_rach=1023 |
| CSET full_threshold_assert_value_rdch=1023 |
| CSET full_threshold_assert_value_wach=1023 |
| CSET full_threshold_assert_value_wdch=1023 |
| CSET full_threshold_assert_value_wrch=1023 |
| CSET full_threshold_negate_value=399 |
| CSET id_width=4 |
| CSET inject_dbit_error=false |
| CSET inject_dbit_error_axis=false |
| CSET inject_dbit_error_rach=false |
| CSET inject_dbit_error_rdch=false |
| CSET inject_dbit_error_wach=false |
| CSET inject_dbit_error_wdch=false |
| CSET inject_dbit_error_wrch=false |
| CSET inject_sbit_error=false |
| CSET inject_sbit_error_axis=false |
| CSET inject_sbit_error_rach=false |
| CSET inject_sbit_error_rdch=false |
| CSET inject_sbit_error_wach=false |
| CSET inject_sbit_error_wdch=false |
| CSET inject_sbit_error_wrch=false |
| CSET input_data_width=32 |
| CSET input_depth=512 |
| CSET input_depth_axis=1024 |
| CSET input_depth_rach=16 |
| CSET input_depth_rdch=1024 |
| CSET input_depth_wach=16 |
| CSET input_depth_wdch=1024 |
| CSET input_depth_wrch=16 |
| CSET interface_type=Native |
| CSET output_data_width=32 |
| CSET output_depth=512 |
| CSET overflow_flag=false |
| CSET overflow_flag_axi=false |
| CSET overflow_sense=Active_High |
| CSET overflow_sense_axi=Active_High |
| CSET performance_options=Standard_FIFO |
| CSET programmable_empty_type=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
| CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant |
| CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
| CSET rach_type=FIFO |
| CSET rdch_type=FIFO |
| CSET read_clock_frequency=1 |
| CSET read_data_count=false |
| CSET read_data_count_width=9 |
| CSET register_slice_mode_axis=Fully_Registered |
| CSET register_slice_mode_rach=Fully_Registered |
| CSET register_slice_mode_rdch=Fully_Registered |
| CSET register_slice_mode_wach=Fully_Registered |
| CSET register_slice_mode_wdch=Fully_Registered |
| CSET register_slice_mode_wrch=Fully_Registered |
| CSET reset_pin=true |
| CSET reset_type=Synchronous_Reset |
| CSET ruser_width=1 |
| CSET synchronization_stages=2 |
| CSET synchronization_stages_axi=2 |
| CSET tdata_width=64 |
| CSET tdest_width=4 |
| CSET tid_width=8 |
| CSET tkeep_width=4 |
| CSET tstrb_width=4 |
| CSET tuser_width=4 |
| CSET underflow_flag=false |
| CSET underflow_flag_axi=false |
| CSET underflow_sense=Active_High |
| CSET underflow_sense_axi=Active_High |
| CSET use_clock_enable=false |
| CSET use_dout_reset=false |
| CSET use_embedded_registers=false |
| CSET use_extra_logic=false |
| CSET valid_flag=true |
| CSET valid_sense=Active_High |
| CSET wach_type=FIFO |
| CSET wdch_type=FIFO |
| CSET wrch_type=FIFO |
| CSET write_acknowledge_flag=false |
| CSET write_acknowledge_sense=Active_High |
| CSET write_clock_frequency=1 |
| CSET write_data_count=false |
| CSET write_data_count_width=9 |
| CSET wuser_width=1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-07-25T18:11:59Z |
| # END Extra information |
| GENERATE |
| # CRC: 53dc1af8 |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/fifo_related/fifo_to_enable.vhd |
|---|
| 0,0 → 1,81 |
| -- A bridge between the read side of a native FIFO and the Flexelerator's "enable" signal technique |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| entity fifo_to_enable is |
| port( |
| -- Input from FIFO: |
| din : in std_logic_vector; |
| rden : out std_logic; |
| empty : in std_logic; |
| -- Output with enable: |
| data : out std_logic_vector; |
| valid : out std_logic; |
| enable : in std_logic; |
| clk : in std_logic; |
| reset : in std_logic |
| ); |
| end entity; |
| architecture behavioral of fifo_to_enable is |
| signal s_rden : std_logic := '0'; |
| signal s_rden_d : std_logic := '0'; |
| signal s_valid : std_logic := '0'; |
| subtype t_data is std_logic_vector( din'range ); |
| type t_data_buffer is array( 1 to 2 ) of t_data; |
| signal s_data_buffer : t_data_buffer := ( others => ( others => '0' ) ); |
| signal s_cntr : natural range 0 to 3; |
| begin |
| s_rden <= '1' when empty = '0' and enable = '1' and reset = '0' and s_cntr < 3 else '0'; |
| rden <= s_rden; |
| s_valid <= '1' when s_cntr > 0 and enable = '1' and reset = '0' else '0'; |
| valid <= s_valid; |
| data <= s_data_buffer( 1 ); |
| -- Delayed rden: |
| delayed_rden : process( clk ) is |
| begin |
| if( rising_edge( clk ) ) then |
| s_rden_d <= s_rden; |
| end if; |
| end process; |
| data_manipulation : process( clk ) is |
| begin |
| if( rising_edge( clk ) ) then |
| if( s_valid = '1' ) then |
| s_data_buffer(1) <= s_data_buffer(2); |
| --s_data_buffer(2) <= s_data_buffer(3); |
| end if; |
| if( reset = '1' ) then |
| s_cntr <= 0; |
| elsif( s_rden_d = '1' and s_valid = '0' ) then |
| s_cntr <= s_cntr + 1; |
| s_data_buffer( s_cntr + 1 ) <= din; |
| elsif( s_rden_d = '1' and s_valid = '1' ) then |
| s_data_buffer( s_cntr ) <= din; |
| elsif( s_rden_d = '0' and s_valid = '1' ) then |
| s_cntr <= s_cntr - 1; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/information/information_block.vhd |
|---|
| 0,0 → 1,117 |
| -- Provides information about the firmware. |
| -- This block is written as a generic memory that sends data based on the requested address. |
| -- |
| -- Generally this block is connected to the 'control' interface in the userlogiccmp_forxilly block and the user interacts with it using the 'control' files. |
| -- The information_data package should contain several mandatory constants as well as the contents of the memory. Generally, the first four 32-bit-tuples are occupied by a unique GUID that identifies the firmware. |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| library utilities; |
| use utilities.utilities.all; |
| library information; |
| use information.information_data.all; |
| ---------------------------------------------------------------- |
| -- NOTE: No range check on the i_data requested address. |
| entity information_block is |
| port ( |
| clk : in std_logic; |
| rst : in std_logic; |
| -- Input side: |
| i_data : in std_logic_vector( 31 downto 0 ); |
| i_valid : in std_logic; |
| o_enable : out std_logic; |
| -- Output side: |
| o_data : out std_logic_vector( 31 downto 0 ); |
| o_valid : out std_logic; |
| i_enable : in std_logic |
| ); |
| end entity; |
| architecture rtl of information_block is |
| -- data in buffer |
| signal buffer_valid : std_logic; |
| signal buffer_data : std_logic_vector( o_data'range ); |
| -- data from the memory |
| signal mem_valid : std_logic; |
| signal mem_data : std_logic_vector( o_data'range ); |
| signal oo_valid : std_logic; |
| signal addr : unsigned( log2( C_INFO_NUMDATA ) - 1 downto 0 ); |
| --signal i_valid_d : std_logic; |
| constant C_RESVAL : std_logic_vector( C_INFO_BITWIDTH -1 downto 0 ) := ( others => '0' ); |
| -- Memory content: |
| subtype t_memdata is t_twodim_stdlogic( C_INFO_NUMDATA - 1 downto 0, C_INFO_BITWIDTH - 1 downto 0 ); |
| constant C_MEMDATA : t_memdata := stdlogicvector_to_twodim( C_INFO_DATA, C_INFO_NUMDATA, C_INFO_BITWIDTH ); |
| begin |
| o_enable <= i_enable; |
| o_valid <= oo_valid and i_enable; |
| o_data <= buffer_data when buffer_valid = '1' else |
| mem_data; |
| oo_valid <= buffer_valid when buffer_valid = '1' else |
| mem_valid; |
| valid_handling: process( clk ) |
| begin |
| if( rising_edge(clk) ) then |
| mem_valid <= i_valid; |
| end if; |
| end process; |
| addr <= unsigned( i_data( addr'range ) ); |
| -- inferred bram: |
| inferred_bram_inst : entity utilities.inferred_bram |
| generic map( |
| G_RAM_CONTENT => C_MEMDATA, |
| G_WIDTH => C_INFO_BITWIDTH, |
| G_SIZE => C_INFO_NUMDATA, |
| G_RESVAL_A => C_RESVAL |
| ) |
| port map( |
| i_clka => clk, |
| i_ena => '1', |
| i_wea => '0', |
| i_resa => '0', |
| i_addra => addr, |
| i_dataa => ( C_INFO_BITWIDTH - 1 downto 0 => '0' ), |
| o_dataa => mem_data |
| ); |
| outp_data : process( clk ) |
| begin |
| if( rising_edge(clk) ) then |
| if( rst = '1' ) then |
| buffer_valid <= '0'; |
| else |
| if( i_enable = '1' ) then |
| buffer_valid <= '0'; |
| elsif( buffer_valid = '0' ) then |
| buffer_valid <= mem_valid; |
| buffer_data <= mem_data; |
| end if; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/sychro1/clock_divider.vhd |
|---|
| 0,0 → 1,68 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| library UNISIM; |
| use UNISIM.vcomponents.all; |
| entity clock_divider is |
| generic ( |
| G_DIVISOR : positive := 2 |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| o_clk : out std_logic |
| ); |
| end entity clock_divider; |
| architecture behavioral of clock_divider is |
| subtype t_counter is natural range 0 to ( G_DIVISOR - 1 ); |
| signal s_counter : t_counter := 0; |
| constant C_COUNTER : t_counter := G_DIVISOR / 2 - 1; |
| signal s_clk_divided : std_logic; |
| attribute clock_signal : string; |
| attribute clock_signal of s_clk_divided : signal is "yes"; |
| begin |
| assert ( G_DIVISOR > 1 ) report "The divisor should be greater than 1" severity failure; |
| counting : process( i_clk ) |
| begin |
| if( rising_edge(i_clk) ) then |
| if( i_rst = '1' ) then |
| s_counter <= 0; |
| s_clk_divided <= '0'; |
| else |
| if( s_counter = t_counter'high ) then |
| s_counter <= 0; |
| s_clk_divided <= '0'; |
| else |
| s_counter <= s_counter + 1; |
| if( s_counter = C_COUNTER ) then |
| s_clk_divided <= '1'; |
| end if; |
| end if; |
| end if; |
| end if; |
| end process counting; |
| BUFR_inst : BUFR |
| generic map ( |
| BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" |
| SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6" |
| port map ( |
| O => o_clk, -- Clock buffer output |
| CE => '1', -- Clock enable input |
| CLR => '0', -- Clock buffer reset input |
| I => s_clk_divided -- Clock buffer input |
| ); |
| end architecture; |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/sychro1/up_counter.vhd |
|---|
| 0,0 → 1,57 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| entity up_counter is |
| generic ( |
| G_MIN_NUMBER : natural := 0; |
| G_MAX_NUMBER : natural := 10 |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| -- Count when this input is '1' |
| i_valid : in std_logic; |
| -- Output the actual number |
| o_data : out natural := G_MIN_NUMBER; |
| o_carry : out std_logic := '0' |
| ); |
| end up_counter; |
| architecture rtl of up_counter is |
| signal number : natural range G_MIN_NUMBER to G_MAX_NUMBER := G_MIN_NUMBER; |
| begin |
| o_data <= number; |
| counter : process( i_clk ) |
| begin |
| if( rising_edge( i_clk ) ) then |
| o_carry <= '0'; |
| if( i_rst = '1' ) then |
| number <= G_MIN_NUMBER; |
| elsif( i_valid = '1' ) then |
| -- count up: |
| if( number = G_MAX_NUMBER ) then |
| number <= G_MIN_NUMBER; |
| o_carry <= '1'; |
| else |
| number <= number + 1; |
| end if; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/sychro1/up_counter_stdlv.vhd |
|---|
| 0,0 → 1,57 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| entity up_counter_stdlv is |
| generic ( |
| G_BITS : positive := 8; |
| G_MIN_NUMBER : std_logic_vector; |
| G_MAX_NUMBER : std_logic_vector |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| -- Count when this input is '1' |
| i_valid : in std_logic; |
| -- Output the actual number |
| o_data : out std_logic_vector( G_BITS-1 downto 0 ); |
| o_carry : out std_logic := '0' |
| ); |
| end up_counter_stdlv; |
| architecture rtl of up_counter_stdlv is |
| signal number : std_logic_vector( G_BITS-1 downto 0 ); |
| begin |
| o_data <= number; |
| counter : process( i_clk ) |
| begin |
| if( rising_edge( i_clk ) ) then |
| o_carry <= '0'; |
| if( i_rst = '1' ) then |
| number <= G_MIN_NUMBER; |
| elsif( i_valid = '1' ) then |
| -- count up: |
| if( number = G_MAX_NUMBER ) then |
| number <= G_MIN_NUMBER; |
| o_carry <= '1'; |
| else |
| number <= std_logic_vector( unsigned(number) + to_unsigned(1,G_BITS) ); |
| end if; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02A/HDL/modules/xilly/xilly_userlogiccmp_wrapper.vhd |
|---|
| 0,0 → 1,248 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| library fifo_related; |
| entity xilly_userlogiccmp_wrapper is |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| user_r_control_r_rden : in std_logic; |
| user_r_control_r_empty : out std_logic := '1'; |
| user_r_control_r_data : out std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_w_control_w_wren : in std_logic; |
| user_w_control_w_full : out std_logic := '0'; |
| user_w_control_w_data : in std_logic_vector(31 DOWNTO 0); |
| user_r_data1_r_rden : in std_logic; |
| user_r_data1_r_empty : out std_logic := '1'; |
| user_r_data1_r_data : out std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_w_data1_w_wren : in std_logic; |
| user_w_data1_w_full : out std_logic := '0'; |
| user_w_data1_w_data : in std_logic_vector(31 DOWNTO 0); |
| user_r_data2_r_rden : in std_logic; |
| user_r_data2_r_empty : out std_logic := '1'; |
| user_r_data2_r_data : out std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_w_data2_w_wren : in std_logic; |
| user_w_data2_w_full : out std_logic := '0'; |
| user_w_data2_w_data : in std_logic_vector(31 DOWNTO 0) |
| ); |
| end entity; |
| architecture behavioral of xilly_userlogiccmp_wrapper is |
| component user_logic_cmp |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| -- data1 interface: |
| i_data1in_data : in std_logic_vector( 31 downto 0 ); |
| i_data1in_valid : in std_logic; |
| o_data1in_enable : out std_logic; |
| o_data1out_data : out std_logic_vector( 31 downto 0 ); |
| o_data1out_valid : out std_logic; |
| i_data1out_enable : in std_logic; |
| -- data2 interface: |
| i_data2in_data : in std_logic_vector( 31 downto 0 ); |
| i_data2in_valid : in std_logic; |
| o_data2in_enable : out std_logic := '1'; |
| o_data2out_data : out std_logic_vector( 31 downto 0 ); |
| o_data2out_valid : out std_logic := '0'; |
| i_data2out_enable : in std_logic; |
| -- control interface: |
| i_controlin_data : in std_logic_vector( 31 downto 0 ); |
| i_controlin_valid : in std_logic; |
| o_controlin_enable : out std_logic := '1'; |
| o_controlout_data : out std_logic_vector( 31 downto 0 ); |
| o_controlout_valid : out std_logic := '0'; |
| i_controlout_enable : in std_logic |
| ); |
| end component; |
| component fifo_32x512 |
| port ( |
| clk: IN std_logic; |
| srst: IN std_logic; |
| din: IN std_logic_vector(31 downto 0) := ( others => '0' ); |
| wr_en: IN std_logic := '0'; |
| rd_en: IN std_logic; |
| dout: OUT std_logic_vector(31 downto 0); |
| valid: OUT std_logic; |
| full: OUT std_logic; |
| empty: OUT std_logic |
| ); |
| end component; |
| -- data1 signals |
| signal s_data1_ffin2fte_data : std_logic_vector( 31 downto 0 ); |
| signal s_data1_ffin2fte_rden : std_logic; |
| signal s_data1_ffin2fte_empty : std_logic; |
| signal s_data1_fte2ul_data : std_logic_vector( 31 downto 0 ); |
| signal s_data1_fte2ul_valid : std_logic; |
| signal s_data1_fte2ul_enable : std_logic; |
| signal s_data1_ul2ffout_data : std_logic_vector( 31 downto 0 ); |
| signal s_data1_ul2ffout_valid : std_logic; |
| signal s_data1_ul2ffout_enable : std_logic; |
| signal s_data1_ul2ffout_full : std_logic; |
| -- data2 signals |
| signal s_data2_ffin2fte_data : std_logic_vector( 31 downto 0 ); |
| signal s_data2_ffin2fte_rden : std_logic; |
| signal s_data2_ffin2fte_empty : std_logic; |
| signal s_data2_fte2ul_data : std_logic_vector( 31 downto 0 ); |
| signal s_data2_fte2ul_valid : std_logic; |
| signal s_data2_fte2ul_enable : std_logic; |
| signal s_data2_ul2ffout_data : std_logic_vector( 31 downto 0 ); |
| signal s_data2_ul2ffout_valid : std_logic; |
| signal s_data2_ul2ffout_enable : std_logic; |
| signal s_data2_ul2ffout_full : std_logic; |
| -- control signals |
| signal s_control_ffin2fte_data : std_logic_vector( 31 downto 0 ); |
| signal s_control_ffin2fte_rden : std_logic; |
| signal s_control_ffin2fte_empty : std_logic; |
| signal s_control_fte2ul_data : std_logic_vector( 31 downto 0 ); |
| signal s_control_fte2ul_valid : std_logic; |
| signal s_control_fte2ul_enable : std_logic; |
| signal s_control_ul2ffout_data : std_logic_vector( 31 downto 0 ); |
| signal s_control_ul2ffout_valid : std_logic; |
| signal s_control_ul2ffout_enable : std_logic; |
| signal s_control_ul2ffout_full : std_logic; |
| begin |
| ------------------------------------------------------ |
| --data1_gen : if( C_USES_DATA1_INTERFACE = '1' ) generate |
| -- FIFO_IN instantiation: |
| data1_fifo_in_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => user_w_data1_w_data, wr_en => user_w_data1_w_wren, full => user_w_data1_w_full, |
| dout => s_data1_ffin2fte_data, rd_en => s_data1_ffin2fte_rden, empty => s_data1_ffin2fte_empty, |
| valid => open ); |
| -- FIFO_to_enable instantiation: |
| data1_fifo_to_enable_inst : entity fifo_related.fifo_to_enable |
| port map ( |
| clk => i_clk, reset => i_rst, |
| din => s_data1_ffin2fte_data, rden => s_data1_ffin2fte_rden, empty => s_data1_ffin2fte_empty, |
| data => s_data1_fte2ul_data, valid => s_data1_fte2ul_valid, enable => s_data1_fte2ul_enable ); |
| -- FIFO_OUT instantiation: |
| data1_fifo_out_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => s_data1_ul2ffout_data, wr_en => s_data1_ul2ffout_valid, full => s_data1_ul2ffout_full, |
| dout => user_r_data1_r_data, rd_en => user_r_data1_r_rden, empty => user_r_data1_r_empty, |
| valid => open ); |
| s_data1_ul2ffout_enable <= not s_data1_ul2ffout_full; |
| -- generate; |
| ------------------------------------------------------ |
| --data2_gen : if( C_USES_DATA2_INTERFACE = '1' ) generate |
| -- FIFO_IN instantiation: |
| data2_fifo_in_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => user_w_data2_w_data, wr_en => user_w_data2_w_wren, full => user_w_data2_w_full, |
| dout => s_data2_ffin2fte_data, rd_en => s_data2_ffin2fte_rden, empty => s_data2_ffin2fte_empty, |
| valid => open ); |
| -- FIFO_to_enable instantiation: |
| data2_fifo_to_enable_inst : entity fifo_related.fifo_to_enable |
| port map ( |
| clk => i_clk, reset => i_rst, |
| din => s_data2_ffin2fte_data, rden => s_data2_ffin2fte_rden, empty => s_data2_ffin2fte_empty, |
| data => s_data2_fte2ul_data, valid => s_data2_fte2ul_valid, enable => s_data2_fte2ul_enable ); |
| -- FIFO_OUT instantiation: |
| data2_fifo_out_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => s_data2_ul2ffout_data, wr_en => s_data2_ul2ffout_valid, full => s_data2_ul2ffout_full, |
| dout => user_r_data2_r_data, rd_en => user_r_data2_r_rden, empty => user_r_data2_r_empty, |
| valid => open ); |
| s_data2_ul2ffout_enable <= not s_data2_ul2ffout_full; |
| --end generate; |
| ---------------------------------------------------------- |
| --control_gen : if( C_USES_CONTROL_INTERFACE = '1' ) generate |
| -- FIFO_IN instantiation: |
| control_fifo_in_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => user_w_control_w_data, wr_en => user_w_control_w_wren, full => user_w_control_w_full, |
| dout => s_control_ffin2fte_data, rd_en => s_control_ffin2fte_rden, empty => s_control_ffin2fte_empty, |
| valid => open ); |
| -- FIFO_to_enable instantiation: |
| control_fifo_to_enable_inst : entity fifo_related.fifo_to_enable |
| port map ( |
| clk => i_clk, reset => i_rst, |
| din => s_control_ffin2fte_data, rden => s_control_ffin2fte_rden, empty => s_control_ffin2fte_empty, |
| data => s_control_fte2ul_data, valid => s_control_fte2ul_valid, enable => s_control_fte2ul_enable ); |
| -- FIFO_OUT instantiation: |
| control_fifo_out_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => s_control_ul2ffout_data, wr_en => s_control_ul2ffout_valid, full => s_control_ul2ffout_full, |
| dout => user_r_control_r_data, rd_en => user_r_control_r_rden, empty => user_r_control_r_empty, |
| valid => open ); |
| s_control_ul2ffout_enable <= not s_control_ul2ffout_full; |
| --end generate; |
| -------------------------------------------------------------- |
| -- user logic: |
| user_logic_cmp_inst : user_logic_cmp |
| port map ( |
| i_clk => i_clk, |
| i_rst => i_rst, |
| -- data1 interface: |
| i_data1in_data => s_data1_fte2ul_data, |
| i_data1in_valid => s_data1_fte2ul_valid, |
| o_data1in_enable => s_data1_fte2ul_enable, |
| o_data1out_data => s_data1_ul2ffout_data, |
| o_data1out_valid => s_data1_ul2ffout_valid, |
| i_data1out_enable => s_data1_ul2ffout_enable, |
| -- data2 interface: |
| i_data2in_data => s_data2_fte2ul_data, |
| i_data2in_valid => s_data2_fte2ul_valid, |
| o_data2in_enable => s_data2_fte2ul_enable, |
| o_data2out_data => s_data2_ul2ffout_data, |
| o_data2out_valid => s_data2_ul2ffout_valid, |
| i_data2out_enable => s_data2_ul2ffout_enable, |
| -- control interface: |
| i_controlin_data => s_control_fte2ul_data, |
| i_controlin_valid => s_control_fte2ul_valid, |
| o_controlin_enable => s_control_fte2ul_enable, |
| o_controlout_data => s_control_ul2ffout_data, |
| o_controlout_valid => s_control_ul2ffout_valid, |
| i_controlout_enable => s_control_ul2ffout_enable |
| ); |
| end architecture; |