0,0 → 1,115 |
-- file: selectio_iserdes_8bit_ddr_diffin.vhd |
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------------------------------------------------------------------------------ |
-- User entered comments |
------------------------------------------------------------------------------ |
-- None |
------------------------------------------------------------------------------ |
-- |
-- EDIT: Only the clock generator buffers here |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_misc.all; |
use ieee.numeric_std.all; |
|
library unisim; |
use unisim.vcomponents.all; |
|
entity iserdes_clock_generator is |
port |
( |
-- Clock and reset signals |
CLK_IN_P : in std_logic; -- Differential fast clock from IOB |
CLK_IN_N : in std_logic; |
CLK_OUT : out std_logic; -- Fast clock output (synchronous to data) |
CLK_DIV_OUT : out std_logic; -- Slow clock output |
|
CLK_RESET : in std_logic); -- Reset signal for Clock circuit |
|
end iserdes_clock_generator; |
|
architecture sychro1 of iserdes_clock_generator is |
|
signal clk_in_int : std_logic; |
|
begin |
|
-- Create the clock logic |
ibufds_clk_inst : IBUFGDS |
generic map ( |
DIFF_TERM => TRUE, |
IOSTANDARD => "LVDS_25" ) |
port map ( |
I => CLK_IN_P, |
IB => CLK_IN_N, |
O => clk_in_int); |
|
-- High Speed BUFIO clock buffer |
bufio_inst : BUFIO |
port map ( |
O => CLK_OUT, |
I => clk_in_int); |
|
-- BUFR generates the slow clock |
clkout_buf_inst : BUFR |
generic map ( |
SIM_DEVICE => "VIRTEX6", |
BUFR_DIVIDE => "4") |
port map ( |
O => CLK_DIV_OUT, |
CE => '1', |
CLR => CLK_RESET, |
I => clk_in_int ); |
|
end sychro1; |
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