No changes between revisions
| /Designs/HAM Constructions/SDRX02B/HDL/README.txt |
|---|
| 0,0 → 1,2 |
| Zdrojove kody FPGA rozhrani bez placeneho Xillybus modulu a par utilit, nepsal Ondrej Syrhrovsky. |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/comm/spi_master_transmit.vhd |
|---|
| 0,0 → 1,132 |
| -- this module transmit a given constant data when requested |
| -- and then signals done. |
| -- |
| -- G_DATA has to contain also the address and the r/w bit |
| -- |
| -- MSB of G_DATA will go first |
| -- P1DATA_P2DATA_P3DATA |
| -- |
| -- version for multiple devices with different data |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| entity spi_master_transmit is |
| generic ( |
| G_DATA1 : std_logic_vector; |
| G_DATA2 : std_logic_vector; |
| G_NUM_BITS_PACKET : integer; |
| G_NUM_PACKETS : integer; |
| G_NUM_BITS_PAUSE : integer |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| o_done : out std_logic; |
| -- selects which data to transfer. If '0', it transfers G_DATA1 |
| i_data_selector : in std_logic; |
| -- SPI ports: |
| o_n_ce : out std_logic_vector; |
| o_dout : out std_logic; |
| o_clk : out std_logic |
| ); |
| end spi_master_transmit; |
| architecture behavioral of spi_master_transmit is |
| subtype t_pause_counter is integer range 0 to G_NUM_BITS_PAUSE; |
| signal s_pause_counter : t_pause_counter; |
| subtype t_bit_counter is integer range 0 to G_NUM_BITS_PACKET - 1; |
| signal s_bit_counter : t_bit_counter; |
| subtype t_packet_counter is integer range 0 to G_NUM_PACKETS; |
| signal s_packet_counter : t_packet_counter; |
| subtype t_device_counter is integer range 0 to o_n_ce'length - 1; |
| signal s_device_counter : t_device_counter; |
| signal s_clk_inv : std_logic; |
| --signal s_o_dout_d : std_logic; |
| signal s_o_clk_en : std_logic; |
| constant C_DATALEN_PER_DEVICE : integer := G_NUM_BITS_PACKET*G_NUM_PACKETS; |
| signal s_cs_out : std_logic_vector( o_n_ce'range ); |
| begin |
| assert( G_DATA1'length = C_DATALEN_PER_DEVICE*o_n_ce'length ) report "The size of G_DATA1 does not match the number of devices and other generics." severity failure; |
| assert( G_DATA2'length = C_DATALEN_PER_DEVICE*o_n_ce'length ) report "The size of G_DATA2 does not match the number of devices and other generics." severity failure; |
| -- inverted clock: |
| s_clk_inv <= not i_clk; |
| -- output clock: |
| o_clk <= i_clk and s_o_clk_en; |
| -- done: |
| o_done <= '1' when ( (i_rst = '0') and (s_packet_counter = 0) and (s_pause_counter = 0) and (s_bit_counter = 0 ) and (s_device_counter=0) ) else |
| '0'; |
| transmitter_process : process( s_clk_inv ) |
| begin |
| if( rising_edge( s_clk_inv ) ) then |
| if( i_rst = '1' ) then |
| s_bit_counter <= 0; |
| s_pause_counter <= t_pause_counter'high; |
| s_packet_counter <= t_packet_counter'high; |
| s_device_counter <= t_device_counter'high; |
| s_cs_out( s_cs_out'low ) <= '0'; |
| s_cs_out( s_cs_out'high downto s_cs_out'low+1 ) <= ( others => '1' ); |
| o_n_ce <= ( o_n_ce'range => '1' ); |
| o_dout <= '0'; |
| s_o_clk_en <= '0'; |
| elsif( s_bit_counter > 0 ) then |
| o_n_ce <= s_cs_out; |
| if( i_data_selector = '0' ) then |
| o_dout <= G_DATA1( s_bit_counter + s_packet_counter*G_NUM_BITS_PACKET - 1 + s_device_counter*C_DATALEN_PER_DEVICE ); -- here s_packet_counter points to the current packet and s_bit_counter is one bit behind, therefore the -1. |
| else |
| o_dout <= G_DATA2( s_bit_counter + s_packet_counter*G_NUM_BITS_PACKET - 1 + s_device_counter*C_DATALEN_PER_DEVICE ); |
| end if; |
| s_bit_counter <= s_bit_counter - 1; |
| s_o_clk_en <= '1'; |
| elsif( s_pause_counter > 0 ) then |
| o_n_ce <= ( o_n_ce'range => '1' ); |
| s_pause_counter <= s_pause_counter - 1; |
| o_dout <= '0'; |
| s_o_clk_en <= '0'; |
| elsif( s_packet_counter > 0 ) then |
| s_bit_counter <= t_bit_counter'high; |
| s_pause_counter <= t_pause_counter'high; |
| s_packet_counter <= s_packet_counter - 1; |
| o_n_ce <= s_cs_out; |
| if( i_data_selector = '0' ) then |
| o_dout <= G_DATA1( s_bit_counter + s_packet_counter*G_NUM_BITS_PACKET - 1 + s_device_counter*C_DATALEN_PER_DEVICE ); -- here s_bit_counter = 0, s_packet_counter points to previous packet. Therefore -1 to get the msb of current packet. |
| else |
| o_dout <= G_DATA2( s_bit_counter + s_packet_counter*G_NUM_BITS_PACKET - 1 + s_device_counter*C_DATALEN_PER_DEVICE ); |
| end if; |
| s_o_clk_en <= '1'; |
| elsif( s_device_counter > 0 ) then |
| s_cs_out <= s_cs_out( s_cs_out'high-1 downto s_cs_out'low ) & '1'; |
| s_device_counter <= s_device_counter - 1; |
| -- follows pause. |
| s_bit_counter <= 0; |
| s_pause_counter <= t_pause_counter'high; |
| s_packet_counter <= t_packet_counter'high; |
| o_n_ce <= ( o_n_ce'range => '1' ); |
| o_dout <= '0'; |
| s_o_clk_en <= '0'; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/clk_125MHz_to_6MHz.xco |
|---|
| 0,0 → 1,269 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue May 6 10:43:16 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:clk_wiz:3.6 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 |
| # END Select |
| # BEGIN Parameters |
| CSET calc_done=DONE |
| CSET clk_in_sel_port=CLK_IN_SEL |
| CSET clk_out1_port=CLK_OUT_6 |
| CSET clk_out1_use_fine_ps_gui=false |
| CSET clk_out2_port=CLK_OUT2 |
| CSET clk_out2_use_fine_ps_gui=false |
| CSET clk_out3_port=CLK_OUT3 |
| CSET clk_out3_use_fine_ps_gui=false |
| CSET clk_out4_port=CLK_OUT4 |
| CSET clk_out4_use_fine_ps_gui=false |
| CSET clk_out5_port=CLK_OUT5 |
| CSET clk_out5_use_fine_ps_gui=false |
| CSET clk_out6_port=CLK_OUT6 |
| CSET clk_out6_use_fine_ps_gui=false |
| CSET clk_out7_port=CLK_OUT7 |
| CSET clk_out7_use_fine_ps_gui=false |
| CSET clk_valid_port=CLK_VALID |
| CSET clkfb_in_n_port=CLKFB_IN_N |
| CSET clkfb_in_p_port=CLKFB_IN_P |
| CSET clkfb_in_port=CLKFB_IN |
| CSET clkfb_in_signaling=SINGLE |
| CSET clkfb_out_n_port=CLKFB_OUT_N |
| CSET clkfb_out_p_port=CLKFB_OUT_P |
| CSET clkfb_out_port=CLKFB_OUT |
| CSET clkfb_stopped_port=CLKFB_STOPPED |
| CSET clkin1_jitter_ps=80.0 |
| CSET clkin1_ui_jitter=0.010 |
| CSET clkin2_jitter_ps=100.0 |
| CSET clkin2_ui_jitter=0.010 |
| CSET clkout1_drives=BUFG |
| CSET clkout1_requested_duty_cycle=50.000 |
| CSET clkout1_requested_out_freq=100.000 |
| CSET clkout1_requested_phase=0.000 |
| CSET clkout2_drives=BUFG |
| CSET clkout2_requested_duty_cycle=50.000 |
| CSET clkout2_requested_out_freq=100.000 |
| CSET clkout2_requested_phase=0.000 |
| CSET clkout2_used=false |
| CSET clkout3_drives=BUFG |
| CSET clkout3_requested_duty_cycle=50.000 |
| CSET clkout3_requested_out_freq=100.000 |
| CSET clkout3_requested_phase=0.000 |
| CSET clkout3_used=false |
| CSET clkout4_drives=BUFG |
| CSET clkout4_requested_duty_cycle=50.000 |
| CSET clkout4_requested_out_freq=100.000 |
| CSET clkout4_requested_phase=0.000 |
| CSET clkout4_used=false |
| CSET clkout5_drives=BUFG |
| CSET clkout5_requested_duty_cycle=50.000 |
| CSET clkout5_requested_out_freq=100.000 |
| CSET clkout5_requested_phase=0.000 |
| CSET clkout5_used=false |
| CSET clkout6_drives=BUFG |
| CSET clkout6_requested_duty_cycle=50.000 |
| CSET clkout6_requested_out_freq=100.000 |
| CSET clkout6_requested_phase=0.000 |
| CSET clkout6_used=false |
| CSET clkout7_drives=BUFG |
| CSET clkout7_requested_duty_cycle=50.000 |
| CSET clkout7_requested_out_freq=100.000 |
| CSET clkout7_requested_phase=0.000 |
| CSET clkout7_used=false |
| CSET clock_mgr_type=MANUAL |
| CSET component_name=clk_125MHz_to_6MHz |
| CSET daddr_port=DADDR |
| CSET dclk_port=DCLK |
| CSET dcm_clk_feedback=1X |
| CSET dcm_clk_out1_port=CLK0 |
| CSET dcm_clk_out2_port=CLK0 |
| CSET dcm_clk_out3_port=CLK0 |
| CSET dcm_clk_out4_port=CLK0 |
| CSET dcm_clk_out5_port=CLK0 |
| CSET dcm_clk_out6_port=CLK0 |
| CSET dcm_clkdv_divide=2.0 |
| CSET dcm_clkfx_divide=1 |
| CSET dcm_clkfx_multiply=4 |
| CSET dcm_clkgen_clk_out1_port=CLKFX |
| CSET dcm_clkgen_clk_out2_port=CLKFX |
| CSET dcm_clkgen_clk_out3_port=CLKFX |
| CSET dcm_clkgen_clkfx_divide=1 |
| CSET dcm_clkgen_clkfx_md_max=0.000 |
| CSET dcm_clkgen_clkfx_multiply=4 |
| CSET dcm_clkgen_clkfxdv_divide=2 |
| CSET dcm_clkgen_clkin_period=10.000 |
| CSET dcm_clkgen_notes=None |
| CSET dcm_clkgen_spread_spectrum=NONE |
| CSET dcm_clkgen_startup_wait=false |
| CSET dcm_clkin_divide_by_2=false |
| CSET dcm_clkin_period=10.000 |
| CSET dcm_clkout_phase_shift=NONE |
| CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS |
| CSET dcm_notes=None |
| CSET dcm_phase_shift=0 |
| CSET dcm_pll_cascade=NONE |
| CSET dcm_startup_wait=false |
| CSET den_port=DEN |
| CSET din_port=DIN |
| CSET dout_port=DOUT |
| CSET drdy_port=DRDY |
| CSET dwe_port=DWE |
| CSET feedback_source=FDBK_AUTO |
| CSET in_freq_units=Units_MHz |
| CSET in_jitter_units=Units_UI |
| CSET input_clk_stopped_port=INPUT_CLK_STOPPED |
| CSET jitter_options=UI |
| CSET jitter_sel=No_Jitter |
| CSET locked_port=LOCKED |
| CSET mmcm_bandwidth=OPTIMIZED |
| CSET mmcm_clkfbout_mult_f=6.000 |
| CSET mmcm_clkfbout_phase=0.000 |
| CSET mmcm_clkfbout_use_fine_ps=false |
| CSET mmcm_clkin1_period=8.000 |
| CSET mmcm_clkin2_period=10.0 |
| CSET mmcm_clkout0_divide_f=125.000 |
| CSET mmcm_clkout0_duty_cycle=0.500 |
| CSET mmcm_clkout0_phase=0.000 |
| CSET mmcm_clkout0_use_fine_ps=false |
| CSET mmcm_clkout1_divide=1 |
| CSET mmcm_clkout1_duty_cycle=0.500 |
| CSET mmcm_clkout1_phase=0.000 |
| CSET mmcm_clkout1_use_fine_ps=false |
| CSET mmcm_clkout2_divide=1 |
| CSET mmcm_clkout2_duty_cycle=0.500 |
| CSET mmcm_clkout2_phase=0.000 |
| CSET mmcm_clkout2_use_fine_ps=false |
| CSET mmcm_clkout3_divide=1 |
| CSET mmcm_clkout3_duty_cycle=0.500 |
| CSET mmcm_clkout3_phase=0.000 |
| CSET mmcm_clkout3_use_fine_ps=false |
| CSET mmcm_clkout4_cascade=false |
| CSET mmcm_clkout4_divide=1 |
| CSET mmcm_clkout4_duty_cycle=0.500 |
| CSET mmcm_clkout4_phase=0.000 |
| CSET mmcm_clkout4_use_fine_ps=false |
| CSET mmcm_clkout5_divide=1 |
| CSET mmcm_clkout5_duty_cycle=0.500 |
| CSET mmcm_clkout5_phase=0.000 |
| CSET mmcm_clkout5_use_fine_ps=false |
| CSET mmcm_clkout6_divide=1 |
| CSET mmcm_clkout6_duty_cycle=0.500 |
| CSET mmcm_clkout6_phase=0.000 |
| CSET mmcm_clkout6_use_fine_ps=false |
| CSET mmcm_clock_hold=false |
| CSET mmcm_compensation=ZHOLD |
| CSET mmcm_divclk_divide=1 |
| CSET mmcm_notes=None |
| CSET mmcm_ref_jitter1=0.010 |
| CSET mmcm_ref_jitter2=0.010 |
| CSET mmcm_startup_wait=false |
| CSET num_out_clks=1 |
| CSET override_dcm=false |
| CSET override_dcm_clkgen=false |
| CSET override_mmcm=false |
| CSET override_pll=false |
| CSET platform=lin64 |
| CSET pll_bandwidth=OPTIMIZED |
| CSET pll_clk_feedback=CLKFBOUT |
| CSET pll_clkfbout_mult=4 |
| CSET pll_clkfbout_phase=0.000 |
| CSET pll_clkin_period=10.000 |
| CSET pll_clkout0_divide=1 |
| CSET pll_clkout0_duty_cycle=0.500 |
| CSET pll_clkout0_phase=0.000 |
| CSET pll_clkout1_divide=1 |
| CSET pll_clkout1_duty_cycle=0.500 |
| CSET pll_clkout1_phase=0.000 |
| CSET pll_clkout2_divide=1 |
| CSET pll_clkout2_duty_cycle=0.500 |
| CSET pll_clkout2_phase=0.000 |
| CSET pll_clkout3_divide=1 |
| CSET pll_clkout3_duty_cycle=0.500 |
| CSET pll_clkout3_phase=0.000 |
| CSET pll_clkout4_divide=1 |
| CSET pll_clkout4_duty_cycle=0.500 |
| CSET pll_clkout4_phase=0.000 |
| CSET pll_clkout5_divide=1 |
| CSET pll_clkout5_duty_cycle=0.500 |
| CSET pll_clkout5_phase=0.000 |
| CSET pll_compensation=SYSTEM_SYNCHRONOUS |
| CSET pll_divclk_divide=1 |
| CSET pll_notes=None |
| CSET pll_ref_jitter=0.010 |
| CSET power_down_port=POWER_DOWN |
| CSET prim_in_freq=125 |
| CSET prim_in_jitter=0.010 |
| CSET prim_source=Global_buffer |
| CSET primary_port=CLK_IN_125 |
| CSET primitive=MMCM |
| CSET primtype_sel=MMCM_ADV |
| CSET psclk_port=PSCLK |
| CSET psdone_port=PSDONE |
| CSET psen_port=PSEN |
| CSET psincdec_port=PSINCDEC |
| CSET relative_inclk=REL_PRIMARY |
| CSET reset_port=RESET |
| CSET secondary_in_freq=100.000 |
| CSET secondary_in_jitter=0.010 |
| CSET secondary_port=CLK_IN2 |
| CSET secondary_source=Single_ended_clock_capable_pin |
| CSET ss_mod_freq=250 |
| CSET ss_mode=CENTER_HIGH |
| CSET status_port=STATUS |
| CSET summary_strings=empty |
| CSET use_clk_valid=false |
| CSET use_clkfb_stopped=false |
| CSET use_dyn_phase_shift=false |
| CSET use_dyn_reconfig=false |
| CSET use_freeze=false |
| CSET use_freq_synth=true |
| CSET use_inclk_stopped=false |
| CSET use_inclk_switchover=false |
| CSET use_locked=false |
| CSET use_max_i_jitter=false |
| CSET use_min_o_jitter=false |
| CSET use_min_power=false |
| CSET use_phase_alignment=true |
| CSET use_power_down=false |
| CSET use_reset=false |
| CSET use_spread_spectrum=false |
| CSET use_spread_spectrum_1=false |
| CSET use_status=false |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-05-10T12:44:55Z |
| # END Extra information |
| GENERATE |
| # CRC: 255c3699 |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/fifo_32x512.xco |
|---|
| 0,0 → 1,213 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue Apr 29 09:14:51 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:fifo_generator:9.2 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT Fifo_Generator xilinx.com:ip:fifo_generator:9.2 |
| # END Select |
| # BEGIN Parameters |
| CSET add_ngc_constraint_axi=false |
| CSET almost_empty_flag=false |
| CSET almost_full_flag=false |
| CSET aruser_width=1 |
| CSET awuser_width=1 |
| CSET axi_address_width=32 |
| CSET axi_data_width=64 |
| CSET axi_type=AXI4_Stream |
| CSET axis_type=FIFO |
| CSET buser_width=1 |
| CSET clock_enable_type=Slave_Interface_Clock_Enable |
| CSET clock_type_axi=Common_Clock |
| CSET component_name=fifo_32x512 |
| CSET data_count=false |
| CSET data_count_width=9 |
| CSET disable_timing_violations=false |
| CSET disable_timing_violations_axi=false |
| CSET dout_reset_value=0 |
| CSET empty_threshold_assert_value=2 |
| CSET empty_threshold_assert_value_axis=1022 |
| CSET empty_threshold_assert_value_rach=1022 |
| CSET empty_threshold_assert_value_rdch=1022 |
| CSET empty_threshold_assert_value_wach=1022 |
| CSET empty_threshold_assert_value_wdch=1022 |
| CSET empty_threshold_assert_value_wrch=1022 |
| CSET empty_threshold_negate_value=3 |
| CSET enable_aruser=false |
| CSET enable_awuser=false |
| CSET enable_buser=false |
| CSET enable_common_overflow=false |
| CSET enable_common_underflow=false |
| CSET enable_data_counts_axis=false |
| CSET enable_data_counts_rach=false |
| CSET enable_data_counts_rdch=false |
| CSET enable_data_counts_wach=false |
| CSET enable_data_counts_wdch=false |
| CSET enable_data_counts_wrch=false |
| CSET enable_ecc=false |
| CSET enable_ecc_axis=false |
| CSET enable_ecc_rach=false |
| CSET enable_ecc_rdch=false |
| CSET enable_ecc_wach=false |
| CSET enable_ecc_wdch=false |
| CSET enable_ecc_wrch=false |
| CSET enable_read_channel=false |
| CSET enable_read_pointer_increment_by2=false |
| CSET enable_reset_synchronization=true |
| CSET enable_ruser=false |
| CSET enable_tdata=false |
| CSET enable_tdest=false |
| CSET enable_tid=false |
| CSET enable_tkeep=false |
| CSET enable_tlast=false |
| CSET enable_tready=true |
| CSET enable_tstrobe=false |
| CSET enable_tuser=false |
| CSET enable_write_channel=false |
| CSET enable_wuser=false |
| CSET fifo_application_type_axis=Data_FIFO |
| CSET fifo_application_type_rach=Data_FIFO |
| CSET fifo_application_type_rdch=Data_FIFO |
| CSET fifo_application_type_wach=Data_FIFO |
| CSET fifo_application_type_wdch=Data_FIFO |
| CSET fifo_application_type_wrch=Data_FIFO |
| CSET fifo_implementation=Common_Clock_Block_RAM |
| CSET fifo_implementation_axis=Common_Clock_Block_RAM |
| CSET fifo_implementation_rach=Common_Clock_Block_RAM |
| CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wach=Common_Clock_Block_RAM |
| CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
| CSET full_flags_reset_value=0 |
| CSET full_threshold_assert_value=510 |
| CSET full_threshold_assert_value_axis=1023 |
| CSET full_threshold_assert_value_rach=1023 |
| CSET full_threshold_assert_value_rdch=1023 |
| CSET full_threshold_assert_value_wach=1023 |
| CSET full_threshold_assert_value_wdch=1023 |
| CSET full_threshold_assert_value_wrch=1023 |
| CSET full_threshold_negate_value=509 |
| CSET id_width=4 |
| CSET inject_dbit_error=false |
| CSET inject_dbit_error_axis=false |
| CSET inject_dbit_error_rach=false |
| CSET inject_dbit_error_rdch=false |
| CSET inject_dbit_error_wach=false |
| CSET inject_dbit_error_wdch=false |
| CSET inject_dbit_error_wrch=false |
| CSET inject_sbit_error=false |
| CSET inject_sbit_error_axis=false |
| CSET inject_sbit_error_rach=false |
| CSET inject_sbit_error_rdch=false |
| CSET inject_sbit_error_wach=false |
| CSET inject_sbit_error_wdch=false |
| CSET inject_sbit_error_wrch=false |
| CSET input_data_width=32 |
| CSET input_depth=512 |
| CSET input_depth_axis=1024 |
| CSET input_depth_rach=16 |
| CSET input_depth_rdch=1024 |
| CSET input_depth_wach=16 |
| CSET input_depth_wdch=1024 |
| CSET input_depth_wrch=16 |
| CSET interface_type=Native |
| CSET output_data_width=32 |
| CSET output_depth=512 |
| CSET overflow_flag=false |
| CSET overflow_flag_axi=false |
| CSET overflow_sense=Active_High |
| CSET overflow_sense_axi=Active_High |
| CSET performance_options=Standard_FIFO |
| CSET programmable_empty_type=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
| CSET programmable_full_type=No_Programmable_Full_Threshold |
| CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
| CSET rach_type=FIFO |
| CSET rdch_type=FIFO |
| CSET read_clock_frequency=1 |
| CSET read_data_count=false |
| CSET read_data_count_width=9 |
| CSET register_slice_mode_axis=Fully_Registered |
| CSET register_slice_mode_rach=Fully_Registered |
| CSET register_slice_mode_rdch=Fully_Registered |
| CSET register_slice_mode_wach=Fully_Registered |
| CSET register_slice_mode_wdch=Fully_Registered |
| CSET register_slice_mode_wrch=Fully_Registered |
| CSET reset_pin=true |
| CSET reset_type=Synchronous_Reset |
| CSET ruser_width=1 |
| CSET synchronization_stages=2 |
| CSET synchronization_stages_axi=2 |
| CSET tdata_width=64 |
| CSET tdest_width=4 |
| CSET tid_width=8 |
| CSET tkeep_width=4 |
| CSET tstrb_width=4 |
| CSET tuser_width=4 |
| CSET underflow_flag=false |
| CSET underflow_flag_axi=false |
| CSET underflow_sense=Active_High |
| CSET underflow_sense_axi=Active_High |
| CSET use_clock_enable=false |
| CSET use_dout_reset=true |
| CSET use_embedded_registers=false |
| CSET use_extra_logic=false |
| CSET valid_flag=true |
| CSET valid_sense=Active_High |
| CSET wach_type=FIFO |
| CSET wdch_type=FIFO |
| CSET wrch_type=FIFO |
| CSET write_acknowledge_flag=false |
| CSET write_acknowledge_sense=Active_High |
| CSET write_clock_frequency=1 |
| CSET write_data_count=false |
| CSET write_data_count_width=9 |
| CSET wuser_width=1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-06-23T13:35:37Z |
| # END Extra information |
| GENERATE |
| # CRC: e2c6d431 |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/fifo_32x512_dualclk_fwft.xco |
|---|
| 0,0 → 1,213 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue May 6 09:52:07 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:fifo_generator:9.3 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 |
| # END Select |
| # BEGIN Parameters |
| CSET add_ngc_constraint_axi=false |
| CSET almost_empty_flag=false |
| CSET almost_full_flag=false |
| CSET aruser_width=1 |
| CSET awuser_width=1 |
| CSET axi_address_width=32 |
| CSET axi_data_width=64 |
| CSET axi_type=AXI4_Stream |
| CSET axis_type=FIFO |
| CSET buser_width=1 |
| CSET clock_enable_type=Slave_Interface_Clock_Enable |
| CSET clock_type_axi=Common_Clock |
| CSET component_name=fifo_32x512_dualclk_fwft |
| CSET data_count=false |
| CSET data_count_width=9 |
| CSET disable_timing_violations=false |
| CSET disable_timing_violations_axi=false |
| CSET dout_reset_value=0 |
| CSET empty_threshold_assert_value=4 |
| CSET empty_threshold_assert_value_axis=1022 |
| CSET empty_threshold_assert_value_rach=1022 |
| CSET empty_threshold_assert_value_rdch=1022 |
| CSET empty_threshold_assert_value_wach=1022 |
| CSET empty_threshold_assert_value_wdch=1022 |
| CSET empty_threshold_assert_value_wrch=1022 |
| CSET empty_threshold_negate_value=5 |
| CSET enable_aruser=false |
| CSET enable_awuser=false |
| CSET enable_buser=false |
| CSET enable_common_overflow=false |
| CSET enable_common_underflow=false |
| CSET enable_data_counts_axis=false |
| CSET enable_data_counts_rach=false |
| CSET enable_data_counts_rdch=false |
| CSET enable_data_counts_wach=false |
| CSET enable_data_counts_wdch=false |
| CSET enable_data_counts_wrch=false |
| CSET enable_ecc=false |
| CSET enable_ecc_axis=false |
| CSET enable_ecc_rach=false |
| CSET enable_ecc_rdch=false |
| CSET enable_ecc_wach=false |
| CSET enable_ecc_wdch=false |
| CSET enable_ecc_wrch=false |
| CSET enable_read_channel=false |
| CSET enable_read_pointer_increment_by2=false |
| CSET enable_reset_synchronization=true |
| CSET enable_ruser=false |
| CSET enable_tdata=false |
| CSET enable_tdest=false |
| CSET enable_tid=false |
| CSET enable_tkeep=false |
| CSET enable_tlast=false |
| CSET enable_tready=true |
| CSET enable_tstrobe=false |
| CSET enable_tuser=false |
| CSET enable_write_channel=false |
| CSET enable_wuser=false |
| CSET fifo_application_type_axis=Data_FIFO |
| CSET fifo_application_type_rach=Data_FIFO |
| CSET fifo_application_type_rdch=Data_FIFO |
| CSET fifo_application_type_wach=Data_FIFO |
| CSET fifo_application_type_wdch=Data_FIFO |
| CSET fifo_application_type_wrch=Data_FIFO |
| CSET fifo_implementation=Independent_Clocks_Block_RAM |
| CSET fifo_implementation_axis=Common_Clock_Block_RAM |
| CSET fifo_implementation_rach=Common_Clock_Block_RAM |
| CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wach=Common_Clock_Block_RAM |
| CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
| CSET full_flags_reset_value=1 |
| CSET full_threshold_assert_value=511 |
| CSET full_threshold_assert_value_axis=1023 |
| CSET full_threshold_assert_value_rach=1023 |
| CSET full_threshold_assert_value_rdch=1023 |
| CSET full_threshold_assert_value_wach=1023 |
| CSET full_threshold_assert_value_wdch=1023 |
| CSET full_threshold_assert_value_wrch=1023 |
| CSET full_threshold_negate_value=510 |
| CSET id_width=4 |
| CSET inject_dbit_error=false |
| CSET inject_dbit_error_axis=false |
| CSET inject_dbit_error_rach=false |
| CSET inject_dbit_error_rdch=false |
| CSET inject_dbit_error_wach=false |
| CSET inject_dbit_error_wdch=false |
| CSET inject_dbit_error_wrch=false |
| CSET inject_sbit_error=false |
| CSET inject_sbit_error_axis=false |
| CSET inject_sbit_error_rach=false |
| CSET inject_sbit_error_rdch=false |
| CSET inject_sbit_error_wach=false |
| CSET inject_sbit_error_wdch=false |
| CSET inject_sbit_error_wrch=false |
| CSET input_data_width=32 |
| CSET input_depth=512 |
| CSET input_depth_axis=1024 |
| CSET input_depth_rach=16 |
| CSET input_depth_rdch=1024 |
| CSET input_depth_wach=16 |
| CSET input_depth_wdch=1024 |
| CSET input_depth_wrch=16 |
| CSET interface_type=Native |
| CSET output_data_width=32 |
| CSET output_depth=512 |
| CSET overflow_flag=false |
| CSET overflow_flag_axi=false |
| CSET overflow_sense=Active_High |
| CSET overflow_sense_axi=Active_High |
| CSET performance_options=First_Word_Fall_Through |
| CSET programmable_empty_type=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
| CSET programmable_full_type=No_Programmable_Full_Threshold |
| CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
| CSET rach_type=FIFO |
| CSET rdch_type=FIFO |
| CSET read_clock_frequency=1 |
| CSET read_data_count=false |
| CSET read_data_count_width=9 |
| CSET register_slice_mode_axis=Fully_Registered |
| CSET register_slice_mode_rach=Fully_Registered |
| CSET register_slice_mode_rdch=Fully_Registered |
| CSET register_slice_mode_wach=Fully_Registered |
| CSET register_slice_mode_wdch=Fully_Registered |
| CSET register_slice_mode_wrch=Fully_Registered |
| CSET reset_pin=true |
| CSET reset_type=Asynchronous_Reset |
| CSET ruser_width=1 |
| CSET synchronization_stages=2 |
| CSET synchronization_stages_axi=2 |
| CSET tdata_width=64 |
| CSET tdest_width=4 |
| CSET tid_width=8 |
| CSET tkeep_width=4 |
| CSET tstrb_width=4 |
| CSET tuser_width=4 |
| CSET underflow_flag=false |
| CSET underflow_flag_axi=false |
| CSET underflow_sense=Active_High |
| CSET underflow_sense_axi=Active_High |
| CSET use_clock_enable=false |
| CSET use_dout_reset=false |
| CSET use_embedded_registers=false |
| CSET use_extra_logic=false |
| CSET valid_flag=true |
| CSET valid_sense=Active_High |
| CSET wach_type=FIFO |
| CSET wdch_type=FIFO |
| CSET wrch_type=FIFO |
| CSET write_acknowledge_flag=false |
| CSET write_acknowledge_sense=Active_High |
| CSET write_clock_frequency=1 |
| CSET write_data_count=false |
| CSET write_data_count_width=9 |
| CSET wuser_width=1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-07-25T18:11:59Z |
| # END Extra information |
| GENERATE |
| # CRC: 19014e08 |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/fifo_32x512_walmostfull.xco |
|---|
| 0,0 → 1,213 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue May 6 09:54:30 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:fifo_generator:9.3 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 |
| # END Select |
| # BEGIN Parameters |
| CSET add_ngc_constraint_axi=false |
| CSET almost_empty_flag=false |
| CSET almost_full_flag=false |
| CSET aruser_width=1 |
| CSET awuser_width=1 |
| CSET axi_address_width=32 |
| CSET axi_data_width=64 |
| CSET axi_type=AXI4_Stream |
| CSET axis_type=FIFO |
| CSET buser_width=1 |
| CSET clock_enable_type=Slave_Interface_Clock_Enable |
| CSET clock_type_axi=Common_Clock |
| CSET component_name=fifo_32x512_walmostfull |
| CSET data_count=false |
| CSET data_count_width=9 |
| CSET disable_timing_violations=false |
| CSET disable_timing_violations_axi=false |
| CSET dout_reset_value=0 |
| CSET empty_threshold_assert_value=2 |
| CSET empty_threshold_assert_value_axis=1022 |
| CSET empty_threshold_assert_value_rach=1022 |
| CSET empty_threshold_assert_value_rdch=1022 |
| CSET empty_threshold_assert_value_wach=1022 |
| CSET empty_threshold_assert_value_wdch=1022 |
| CSET empty_threshold_assert_value_wrch=1022 |
| CSET empty_threshold_negate_value=3 |
| CSET enable_aruser=false |
| CSET enable_awuser=false |
| CSET enable_buser=false |
| CSET enable_common_overflow=false |
| CSET enable_common_underflow=false |
| CSET enable_data_counts_axis=false |
| CSET enable_data_counts_rach=false |
| CSET enable_data_counts_rdch=false |
| CSET enable_data_counts_wach=false |
| CSET enable_data_counts_wdch=false |
| CSET enable_data_counts_wrch=false |
| CSET enable_ecc=false |
| CSET enable_ecc_axis=false |
| CSET enable_ecc_rach=false |
| CSET enable_ecc_rdch=false |
| CSET enable_ecc_wach=false |
| CSET enable_ecc_wdch=false |
| CSET enable_ecc_wrch=false |
| CSET enable_read_channel=false |
| CSET enable_read_pointer_increment_by2=false |
| CSET enable_reset_synchronization=true |
| CSET enable_ruser=false |
| CSET enable_tdata=false |
| CSET enable_tdest=false |
| CSET enable_tid=false |
| CSET enable_tkeep=false |
| CSET enable_tlast=false |
| CSET enable_tready=true |
| CSET enable_tstrobe=false |
| CSET enable_tuser=false |
| CSET enable_write_channel=false |
| CSET enable_wuser=false |
| CSET fifo_application_type_axis=Data_FIFO |
| CSET fifo_application_type_rach=Data_FIFO |
| CSET fifo_application_type_rdch=Data_FIFO |
| CSET fifo_application_type_wach=Data_FIFO |
| CSET fifo_application_type_wdch=Data_FIFO |
| CSET fifo_application_type_wrch=Data_FIFO |
| CSET fifo_implementation=Common_Clock_Block_RAM |
| CSET fifo_implementation_axis=Common_Clock_Block_RAM |
| CSET fifo_implementation_rach=Common_Clock_Block_RAM |
| CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wach=Common_Clock_Block_RAM |
| CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
| CSET full_flags_reset_value=0 |
| CSET full_threshold_assert_value=400 |
| CSET full_threshold_assert_value_axis=1023 |
| CSET full_threshold_assert_value_rach=1023 |
| CSET full_threshold_assert_value_rdch=1023 |
| CSET full_threshold_assert_value_wach=1023 |
| CSET full_threshold_assert_value_wdch=1023 |
| CSET full_threshold_assert_value_wrch=1023 |
| CSET full_threshold_negate_value=399 |
| CSET id_width=4 |
| CSET inject_dbit_error=false |
| CSET inject_dbit_error_axis=false |
| CSET inject_dbit_error_rach=false |
| CSET inject_dbit_error_rdch=false |
| CSET inject_dbit_error_wach=false |
| CSET inject_dbit_error_wdch=false |
| CSET inject_dbit_error_wrch=false |
| CSET inject_sbit_error=false |
| CSET inject_sbit_error_axis=false |
| CSET inject_sbit_error_rach=false |
| CSET inject_sbit_error_rdch=false |
| CSET inject_sbit_error_wach=false |
| CSET inject_sbit_error_wdch=false |
| CSET inject_sbit_error_wrch=false |
| CSET input_data_width=32 |
| CSET input_depth=512 |
| CSET input_depth_axis=1024 |
| CSET input_depth_rach=16 |
| CSET input_depth_rdch=1024 |
| CSET input_depth_wach=16 |
| CSET input_depth_wdch=1024 |
| CSET input_depth_wrch=16 |
| CSET interface_type=Native |
| CSET output_data_width=32 |
| CSET output_depth=512 |
| CSET overflow_flag=false |
| CSET overflow_flag_axi=false |
| CSET overflow_sense=Active_High |
| CSET overflow_sense_axi=Active_High |
| CSET performance_options=Standard_FIFO |
| CSET programmable_empty_type=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
| CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant |
| CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
| CSET rach_type=FIFO |
| CSET rdch_type=FIFO |
| CSET read_clock_frequency=1 |
| CSET read_data_count=false |
| CSET read_data_count_width=9 |
| CSET register_slice_mode_axis=Fully_Registered |
| CSET register_slice_mode_rach=Fully_Registered |
| CSET register_slice_mode_rdch=Fully_Registered |
| CSET register_slice_mode_wach=Fully_Registered |
| CSET register_slice_mode_wdch=Fully_Registered |
| CSET register_slice_mode_wrch=Fully_Registered |
| CSET reset_pin=true |
| CSET reset_type=Synchronous_Reset |
| CSET ruser_width=1 |
| CSET synchronization_stages=2 |
| CSET synchronization_stages_axi=2 |
| CSET tdata_width=64 |
| CSET tdest_width=4 |
| CSET tid_width=8 |
| CSET tkeep_width=4 |
| CSET tstrb_width=4 |
| CSET tuser_width=4 |
| CSET underflow_flag=false |
| CSET underflow_flag_axi=false |
| CSET underflow_sense=Active_High |
| CSET underflow_sense_axi=Active_High |
| CSET use_clock_enable=false |
| CSET use_dout_reset=false |
| CSET use_embedded_registers=false |
| CSET use_extra_logic=false |
| CSET valid_flag=true |
| CSET valid_sense=Active_High |
| CSET wach_type=FIFO |
| CSET wdch_type=FIFO |
| CSET wrch_type=FIFO |
| CSET write_acknowledge_flag=false |
| CSET write_acknowledge_sense=Active_High |
| CSET write_clock_frequency=1 |
| CSET write_data_count=false |
| CSET write_data_count_width=9 |
| CSET wuser_width=1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-07-25T18:11:59Z |
| # END Extra information |
| GENERATE |
| # CRC: 53dc1af8 |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/fifo_related/fifo_to_enable.vhd |
|---|
| 0,0 → 1,81 |
| -- A bridge between the read side of a native FIFO and the Flexelerator's "enable" signal technique |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| entity fifo_to_enable is |
| port( |
| -- Input from FIFO: |
| din : in std_logic_vector; |
| rden : out std_logic; |
| empty : in std_logic; |
| -- Output with enable: |
| data : out std_logic_vector; |
| valid : out std_logic; |
| enable : in std_logic; |
| clk : in std_logic; |
| reset : in std_logic |
| ); |
| end entity; |
| architecture behavioral of fifo_to_enable is |
| signal s_rden : std_logic := '0'; |
| signal s_rden_d : std_logic := '0'; |
| signal s_valid : std_logic := '0'; |
| subtype t_data is std_logic_vector( din'range ); |
| type t_data_buffer is array( 1 to 2 ) of t_data; |
| signal s_data_buffer : t_data_buffer := ( others => ( others => '0' ) ); |
| signal s_cntr : natural range 0 to 3; |
| begin |
| s_rden <= '1' when empty = '0' and enable = '1' and reset = '0' and s_cntr < 3 else '0'; |
| rden <= s_rden; |
| s_valid <= '1' when s_cntr > 0 and enable = '1' and reset = '0' else '0'; |
| valid <= s_valid; |
| data <= s_data_buffer( 1 ); |
| -- Delayed rden: |
| delayed_rden : process( clk ) is |
| begin |
| if( rising_edge( clk ) ) then |
| s_rden_d <= s_rden; |
| end if; |
| end process; |
| data_manipulation : process( clk ) is |
| begin |
| if( rising_edge( clk ) ) then |
| if( s_valid = '1' ) then |
| s_data_buffer(1) <= s_data_buffer(2); |
| --s_data_buffer(2) <= s_data_buffer(3); |
| end if; |
| if( reset = '1' ) then |
| s_cntr <= 0; |
| elsif( s_rden_d = '1' and s_valid = '0' ) then |
| s_cntr <= s_cntr + 1; |
| s_data_buffer( s_cntr + 1 ) <= din; |
| elsif( s_rden_d = '1' and s_valid = '1' ) then |
| s_data_buffer( s_cntr ) <= din; |
| elsif( s_rden_d = '0' and s_valid = '1' ) then |
| s_cntr <= s_cntr - 1; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/information/information_block.vhd |
|---|
| 0,0 → 1,117 |
| -- Provides information about the firmware. |
| -- This block is written as a generic memory that sends data based on the requested address. |
| -- |
| -- Generally this block is connected to the 'control' interface in the userlogiccmp_forxilly block and the user interacts with it using the 'control' files. |
| -- The information_data package should contain several mandatory constants as well as the contents of the memory. Generally, the first four 32-bit-tuples are occupied by a unique GUID that identifies the firmware. |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| library utilities; |
| use utilities.utilities.all; |
| library information; |
| use information.information_data.all; |
| ---------------------------------------------------------------- |
| -- NOTE: No range check on the i_data requested address. |
| entity information_block is |
| port ( |
| clk : in std_logic; |
| rst : in std_logic; |
| -- Input side: |
| i_data : in std_logic_vector( 31 downto 0 ); |
| i_valid : in std_logic; |
| o_enable : out std_logic; |
| -- Output side: |
| o_data : out std_logic_vector( 31 downto 0 ); |
| o_valid : out std_logic; |
| i_enable : in std_logic |
| ); |
| end entity; |
| architecture rtl of information_block is |
| -- data in buffer |
| signal buffer_valid : std_logic; |
| signal buffer_data : std_logic_vector( o_data'range ); |
| -- data from the memory |
| signal mem_valid : std_logic; |
| signal mem_data : std_logic_vector( o_data'range ); |
| signal oo_valid : std_logic; |
| signal addr : unsigned( log2( C_INFO_NUMDATA ) - 1 downto 0 ); |
| --signal i_valid_d : std_logic; |
| constant C_RESVAL : std_logic_vector( C_INFO_BITWIDTH -1 downto 0 ) := ( others => '0' ); |
| -- Memory content: |
| subtype t_memdata is t_twodim_stdlogic( C_INFO_NUMDATA - 1 downto 0, C_INFO_BITWIDTH - 1 downto 0 ); |
| constant C_MEMDATA : t_memdata := stdlogicvector_to_twodim( C_INFO_DATA, C_INFO_NUMDATA, C_INFO_BITWIDTH ); |
| begin |
| o_enable <= i_enable; |
| o_valid <= oo_valid and i_enable; |
| o_data <= buffer_data when buffer_valid = '1' else |
| mem_data; |
| oo_valid <= buffer_valid when buffer_valid = '1' else |
| mem_valid; |
| valid_handling: process( clk ) |
| begin |
| if( rising_edge(clk) ) then |
| mem_valid <= i_valid; |
| end if; |
| end process; |
| addr <= unsigned( i_data( addr'range ) ); |
| -- inferred bram: |
| inferred_bram_inst : entity utilities.inferred_bram |
| generic map( |
| G_RAM_CONTENT => C_MEMDATA, |
| G_WIDTH => C_INFO_BITWIDTH, |
| G_SIZE => C_INFO_NUMDATA, |
| G_RESVAL_A => C_RESVAL |
| ) |
| port map( |
| i_clka => clk, |
| i_ena => '1', |
| i_wea => '0', |
| i_resa => '0', |
| i_addra => addr, |
| i_dataa => ( C_INFO_BITWIDTH - 1 downto 0 => '0' ), |
| o_dataa => mem_data |
| ); |
| outp_data : process( clk ) |
| begin |
| if( rising_edge(clk) ) then |
| if( rst = '1' ) then |
| buffer_valid <= '0'; |
| else |
| if( i_enable = '1' ) then |
| buffer_valid <= '0'; |
| elsif( buffer_valid = '0' ) then |
| buffer_valid <= mem_valid; |
| buffer_data <= mem_data; |
| end if; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1/clock_divider.vhd |
|---|
| 0,0 → 1,68 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| library UNISIM; |
| use UNISIM.vcomponents.all; |
| entity clock_divider is |
| generic ( |
| G_DIVISOR : positive := 2 |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| o_clk : out std_logic |
| ); |
| end entity clock_divider; |
| architecture behavioral of clock_divider is |
| subtype t_counter is natural range 0 to ( G_DIVISOR - 1 ); |
| signal s_counter : t_counter := 0; |
| constant C_COUNTER : t_counter := G_DIVISOR / 2 - 1; |
| signal s_clk_divided : std_logic; |
| attribute clock_signal : string; |
| attribute clock_signal of s_clk_divided : signal is "yes"; |
| begin |
| assert ( G_DIVISOR > 1 ) report "The divisor should be greater than 1" severity failure; |
| counting : process( i_clk ) |
| begin |
| if( rising_edge(i_clk) ) then |
| if( i_rst = '1' ) then |
| s_counter <= 0; |
| s_clk_divided <= '0'; |
| else |
| if( s_counter = t_counter'high ) then |
| s_counter <= 0; |
| s_clk_divided <= '0'; |
| else |
| s_counter <= s_counter + 1; |
| if( s_counter = C_COUNTER ) then |
| s_clk_divided <= '1'; |
| end if; |
| end if; |
| end if; |
| end if; |
| end process counting; |
| BUFR_inst : BUFR |
| generic map ( |
| BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" |
| SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6" |
| port map ( |
| O => o_clk, -- Clock buffer output |
| CE => '1', -- Clock enable input |
| CLR => '0', -- Clock buffer reset input |
| I => s_clk_divided -- Clock buffer input |
| ); |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1/up_counter.vhd |
|---|
| 0,0 → 1,57 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| entity up_counter is |
| generic ( |
| G_MIN_NUMBER : natural := 0; |
| G_MAX_NUMBER : natural := 10 |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| -- Count when this input is '1' |
| i_valid : in std_logic; |
| -- Output the actual number |
| o_data : out natural := G_MIN_NUMBER; |
| o_carry : out std_logic := '0' |
| ); |
| end up_counter; |
| architecture rtl of up_counter is |
| signal number : natural range G_MIN_NUMBER to G_MAX_NUMBER := G_MIN_NUMBER; |
| begin |
| o_data <= number; |
| counter : process( i_clk ) |
| begin |
| if( rising_edge( i_clk ) ) then |
| o_carry <= '0'; |
| if( i_rst = '1' ) then |
| number <= G_MIN_NUMBER; |
| elsif( i_valid = '1' ) then |
| -- count up: |
| if( number = G_MAX_NUMBER ) then |
| number <= G_MIN_NUMBER; |
| o_carry <= '1'; |
| else |
| number <= number + 1; |
| end if; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1/up_counter_stdlv.vhd |
|---|
| 0,0 → 1,57 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| entity up_counter_stdlv is |
| generic ( |
| G_BITS : positive := 8; |
| G_MIN_NUMBER : std_logic_vector; |
| G_MAX_NUMBER : std_logic_vector |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| -- Count when this input is '1' |
| i_valid : in std_logic; |
| -- Output the actual number |
| o_data : out std_logic_vector( G_BITS-1 downto 0 ); |
| o_carry : out std_logic := '0' |
| ); |
| end up_counter_stdlv; |
| architecture rtl of up_counter_stdlv is |
| signal number : std_logic_vector( G_BITS-1 downto 0 ); |
| begin |
| o_data <= number; |
| counter : process( i_clk ) |
| begin |
| if( rising_edge( i_clk ) ) then |
| o_carry <= '0'; |
| if( i_rst = '1' ) then |
| number <= G_MIN_NUMBER; |
| elsif( i_valid = '1' ) then |
| -- count up: |
| if( number = G_MAX_NUMBER ) then |
| number <= G_MIN_NUMBER; |
| o_carry <= '1'; |
| else |
| number <= std_logic_vector( unsigned(number) + to_unsigned(1,G_BITS) ); |
| end if; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/modules/xilly/xilly_userlogiccmp_wrapper.vhd |
|---|
| 0,0 → 1,248 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| library fifo_related; |
| entity xilly_userlogiccmp_wrapper is |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| user_r_control_r_rden : in std_logic; |
| user_r_control_r_empty : out std_logic := '1'; |
| user_r_control_r_data : out std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_w_control_w_wren : in std_logic; |
| user_w_control_w_full : out std_logic := '0'; |
| user_w_control_w_data : in std_logic_vector(31 DOWNTO 0); |
| user_r_data1_r_rden : in std_logic; |
| user_r_data1_r_empty : out std_logic := '1'; |
| user_r_data1_r_data : out std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_w_data1_w_wren : in std_logic; |
| user_w_data1_w_full : out std_logic := '0'; |
| user_w_data1_w_data : in std_logic_vector(31 DOWNTO 0); |
| user_r_data2_r_rden : in std_logic; |
| user_r_data2_r_empty : out std_logic := '1'; |
| user_r_data2_r_data : out std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_w_data2_w_wren : in std_logic; |
| user_w_data2_w_full : out std_logic := '0'; |
| user_w_data2_w_data : in std_logic_vector(31 DOWNTO 0) |
| ); |
| end entity; |
| architecture behavioral of xilly_userlogiccmp_wrapper is |
| component user_logic_cmp |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| -- data1 interface: |
| i_data1in_data : in std_logic_vector( 31 downto 0 ); |
| i_data1in_valid : in std_logic; |
| o_data1in_enable : out std_logic; |
| o_data1out_data : out std_logic_vector( 31 downto 0 ); |
| o_data1out_valid : out std_logic; |
| i_data1out_enable : in std_logic; |
| -- data2 interface: |
| i_data2in_data : in std_logic_vector( 31 downto 0 ); |
| i_data2in_valid : in std_logic; |
| o_data2in_enable : out std_logic := '1'; |
| o_data2out_data : out std_logic_vector( 31 downto 0 ); |
| o_data2out_valid : out std_logic := '0'; |
| i_data2out_enable : in std_logic; |
| -- control interface: |
| i_controlin_data : in std_logic_vector( 31 downto 0 ); |
| i_controlin_valid : in std_logic; |
| o_controlin_enable : out std_logic := '1'; |
| o_controlout_data : out std_logic_vector( 31 downto 0 ); |
| o_controlout_valid : out std_logic := '0'; |
| i_controlout_enable : in std_logic |
| ); |
| end component; |
| component fifo_32x512 |
| port ( |
| clk: IN std_logic; |
| srst: IN std_logic; |
| din: IN std_logic_vector(31 downto 0) := ( others => '0' ); |
| wr_en: IN std_logic := '0'; |
| rd_en: IN std_logic; |
| dout: OUT std_logic_vector(31 downto 0); |
| valid: OUT std_logic; |
| full: OUT std_logic; |
| empty: OUT std_logic |
| ); |
| end component; |
| -- data1 signals |
| signal s_data1_ffin2fte_data : std_logic_vector( 31 downto 0 ); |
| signal s_data1_ffin2fte_rden : std_logic; |
| signal s_data1_ffin2fte_empty : std_logic; |
| signal s_data1_fte2ul_data : std_logic_vector( 31 downto 0 ); |
| signal s_data1_fte2ul_valid : std_logic; |
| signal s_data1_fte2ul_enable : std_logic; |
| signal s_data1_ul2ffout_data : std_logic_vector( 31 downto 0 ); |
| signal s_data1_ul2ffout_valid : std_logic; |
| signal s_data1_ul2ffout_enable : std_logic; |
| signal s_data1_ul2ffout_full : std_logic; |
| -- data2 signals |
| signal s_data2_ffin2fte_data : std_logic_vector( 31 downto 0 ); |
| signal s_data2_ffin2fte_rden : std_logic; |
| signal s_data2_ffin2fte_empty : std_logic; |
| signal s_data2_fte2ul_data : std_logic_vector( 31 downto 0 ); |
| signal s_data2_fte2ul_valid : std_logic; |
| signal s_data2_fte2ul_enable : std_logic; |
| signal s_data2_ul2ffout_data : std_logic_vector( 31 downto 0 ); |
| signal s_data2_ul2ffout_valid : std_logic; |
| signal s_data2_ul2ffout_enable : std_logic; |
| signal s_data2_ul2ffout_full : std_logic; |
| -- control signals |
| signal s_control_ffin2fte_data : std_logic_vector( 31 downto 0 ); |
| signal s_control_ffin2fte_rden : std_logic; |
| signal s_control_ffin2fte_empty : std_logic; |
| signal s_control_fte2ul_data : std_logic_vector( 31 downto 0 ); |
| signal s_control_fte2ul_valid : std_logic; |
| signal s_control_fte2ul_enable : std_logic; |
| signal s_control_ul2ffout_data : std_logic_vector( 31 downto 0 ); |
| signal s_control_ul2ffout_valid : std_logic; |
| signal s_control_ul2ffout_enable : std_logic; |
| signal s_control_ul2ffout_full : std_logic; |
| begin |
| ------------------------------------------------------ |
| --data1_gen : if( C_USES_DATA1_INTERFACE = '1' ) generate |
| -- FIFO_IN instantiation: |
| data1_fifo_in_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => user_w_data1_w_data, wr_en => user_w_data1_w_wren, full => user_w_data1_w_full, |
| dout => s_data1_ffin2fte_data, rd_en => s_data1_ffin2fte_rden, empty => s_data1_ffin2fte_empty, |
| valid => open ); |
| -- FIFO_to_enable instantiation: |
| data1_fifo_to_enable_inst : entity fifo_related.fifo_to_enable |
| port map ( |
| clk => i_clk, reset => i_rst, |
| din => s_data1_ffin2fte_data, rden => s_data1_ffin2fte_rden, empty => s_data1_ffin2fte_empty, |
| data => s_data1_fte2ul_data, valid => s_data1_fte2ul_valid, enable => s_data1_fte2ul_enable ); |
| -- FIFO_OUT instantiation: |
| data1_fifo_out_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => s_data1_ul2ffout_data, wr_en => s_data1_ul2ffout_valid, full => s_data1_ul2ffout_full, |
| dout => user_r_data1_r_data, rd_en => user_r_data1_r_rden, empty => user_r_data1_r_empty, |
| valid => open ); |
| s_data1_ul2ffout_enable <= not s_data1_ul2ffout_full; |
| -- generate; |
| ------------------------------------------------------ |
| --data2_gen : if( C_USES_DATA2_INTERFACE = '1' ) generate |
| -- FIFO_IN instantiation: |
| data2_fifo_in_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => user_w_data2_w_data, wr_en => user_w_data2_w_wren, full => user_w_data2_w_full, |
| dout => s_data2_ffin2fte_data, rd_en => s_data2_ffin2fte_rden, empty => s_data2_ffin2fte_empty, |
| valid => open ); |
| -- FIFO_to_enable instantiation: |
| data2_fifo_to_enable_inst : entity fifo_related.fifo_to_enable |
| port map ( |
| clk => i_clk, reset => i_rst, |
| din => s_data2_ffin2fte_data, rden => s_data2_ffin2fte_rden, empty => s_data2_ffin2fte_empty, |
| data => s_data2_fte2ul_data, valid => s_data2_fte2ul_valid, enable => s_data2_fte2ul_enable ); |
| -- FIFO_OUT instantiation: |
| data2_fifo_out_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => s_data2_ul2ffout_data, wr_en => s_data2_ul2ffout_valid, full => s_data2_ul2ffout_full, |
| dout => user_r_data2_r_data, rd_en => user_r_data2_r_rden, empty => user_r_data2_r_empty, |
| valid => open ); |
| s_data2_ul2ffout_enable <= not s_data2_ul2ffout_full; |
| --end generate; |
| ---------------------------------------------------------- |
| --control_gen : if( C_USES_CONTROL_INTERFACE = '1' ) generate |
| -- FIFO_IN instantiation: |
| control_fifo_in_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => user_w_control_w_data, wr_en => user_w_control_w_wren, full => user_w_control_w_full, |
| dout => s_control_ffin2fte_data, rd_en => s_control_ffin2fte_rden, empty => s_control_ffin2fte_empty, |
| valid => open ); |
| -- FIFO_to_enable instantiation: |
| control_fifo_to_enable_inst : entity fifo_related.fifo_to_enable |
| port map ( |
| clk => i_clk, reset => i_rst, |
| din => s_control_ffin2fte_data, rden => s_control_ffin2fte_rden, empty => s_control_ffin2fte_empty, |
| data => s_control_fte2ul_data, valid => s_control_fte2ul_valid, enable => s_control_fte2ul_enable ); |
| -- FIFO_OUT instantiation: |
| control_fifo_out_inst : fifo_32x512 |
| port map ( |
| clk => i_clk, srst => i_rst, |
| din => s_control_ul2ffout_data, wr_en => s_control_ul2ffout_valid, full => s_control_ul2ffout_full, |
| dout => user_r_control_r_data, rd_en => user_r_control_r_rden, empty => user_r_control_r_empty, |
| valid => open ); |
| s_control_ul2ffout_enable <= not s_control_ul2ffout_full; |
| --end generate; |
| -------------------------------------------------------------- |
| -- user logic: |
| user_logic_cmp_inst : user_logic_cmp |
| port map ( |
| i_clk => i_clk, |
| i_rst => i_rst, |
| -- data1 interface: |
| i_data1in_data => s_data1_fte2ul_data, |
| i_data1in_valid => s_data1_fte2ul_valid, |
| o_data1in_enable => s_data1_fte2ul_enable, |
| o_data1out_data => s_data1_ul2ffout_data, |
| o_data1out_valid => s_data1_ul2ffout_valid, |
| i_data1out_enable => s_data1_ul2ffout_enable, |
| -- data2 interface: |
| i_data2in_data => s_data2_fte2ul_data, |
| i_data2in_valid => s_data2_fte2ul_valid, |
| o_data2in_enable => s_data2_fte2ul_enable, |
| o_data2out_data => s_data2_ul2ffout_data, |
| o_data2out_valid => s_data2_ul2ffout_valid, |
| i_data2out_enable => s_data2_ul2ffout_enable, |
| -- control interface: |
| i_controlin_data => s_control_fte2ul_data, |
| i_controlin_valid => s_control_fte2ul_valid, |
| o_controlin_enable => s_control_fte2ul_enable, |
| o_controlout_data => s_control_ul2ffout_data, |
| o_controlout_valid => s_control_ul2ffout_valid, |
| i_controlout_enable => s_control_ul2ffout_enable |
| ); |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/bitslip_compensation.vhd |
|---|
| 0,0 → 1,116 |
| --------------------------------------------- |
| -- internal bitslip in iserdes works only with 8 bits. It may happen that when we make a 16-bit word from them, |
| -- internal bitslip is correct, but we need to swap the whole bytes. -> o_bitslip_swap_bytes |
| -- |
| -- NOTE: swapping bytes is wrong, because that means we're grabbing when frame is "00FF". That suggests, that |
| -- we're using LSbyte from previous sample and MSbyte from current sample. It is correct to drop the byte, to have the frame signal "FF00" |
| -- |
| -- However, the bytes are not swapped, i.e. LSbyte is still LSbyte. They just do not come from the same sample. |
| library ieee; |
| use ieee.std_logic_1164.all; |
| library UNISIM; |
| use UNISIM.vcomponents.all; |
| --library utilities; |
| entity bitslip_compensation is |
| port ( |
| clk : in std_logic; |
| rst : in std_logic; |
| i_data : in std_logic_vector( 15 downto 0 ); |
| i_valid : in std_logic; |
| o_bitslip : out std_logic; |
| o_bitslip_done : out std_logic; |
| o_bitslip_drop_byte : out std_logic; |
| o_bitslip_failed : out std_logic |
| ); |
| end bitslip_compensation; |
| architecture behavioral of bitslip_compensation is |
| component swap_endianness |
| port ( |
| i_data : in std_logic_vector; |
| o_data : out std_logic_vector |
| ); |
| end component; |
| constant C_BITSLIP_FRAME_TRAINING_PATTERN : std_logic_vector( 15 downto 0 ) := X"FF00"; |
| -- wait a while before bitslipping again |
| subtype t_counter_busy is natural range 0 to 5; -- in theory 2 is enough |
| signal s_counter_busy : t_counter_busy := 0; |
| -- count the number of bitslip attempts |
| subtype t_counter_attempts is natural range 0 to 9; |
| signal s_counter_attempts : t_counter_attempts := 0; |
| signal s_i_data_bytes_swapped : std_logic_vector( 15 downto 0 ); |
| signal s_bitslip_done : std_logic; |
| signal s_bitslip_failed : std_logic; |
| begin |
| swap_endianness_inst : swap_endianness |
| port map( i_data => i_data, o_data => s_i_data_bytes_swapped ); |
| o_bitslip_done <= s_bitslip_done; |
| o_bitslip_failed <= s_bitslip_failed; |
| main_process : process( clk ) |
| begin |
| if( rising_edge(clk) ) then |
| o_bitslip <= '0'; |
| o_bitslip_drop_byte <= '0'; |
| if( rst = '1' ) then |
| -- reset |
| s_counter_busy <= t_counter_busy'high; |
| s_counter_attempts <= 0; |
| s_bitslip_done <= '0'; |
| s_bitslip_failed <= '0'; |
| elsif( s_bitslip_done = '1' or s_bitslip_failed = '1' ) then |
| -- do nothing, the bitslip has already been determined. |
| elsif( i_valid = '1' and s_counter_busy > 0 ) then |
| -- we are busy now, do not do anything |
| s_counter_busy <= s_counter_busy - 1; |
| elsif( i_valid = '1' and s_counter_busy = 0 and i_data = C_BITSLIP_FRAME_TRAINING_PATTERN ) then |
| -- we are not busy and the incoming pattern matches the training pattern. |
| s_bitslip_done <= '1'; |
| elsif( i_valid = '1' and s_counter_busy = 0 and s_i_data_bytes_swapped = C_BITSLIP_FRAME_TRAINING_PATTERN ) then |
| -- we are not busy and the incoming pattern matches the training pattern if we swap its bytes: |
| -- drop the byte and start over. |
| o_bitslip_drop_byte <= '1'; |
| s_counter_busy <= t_counter_busy'high; |
| elsif( i_valid = '1' and s_counter_busy = 0 and s_counter_attempts < t_counter_attempts'high ) then |
| -- we are not busy, we may bitslip again and the incoming pattern does not match. |
| s_counter_attempts <= s_counter_attempts + 1; |
| s_counter_busy <= t_counter_busy'high; |
| o_bitslip <= '1'; |
| elsif( i_valid = '1' and s_counter_busy = 0 and s_counter_attempts = t_counter_attempts'high ) then |
| -- we are not busy, but we do not have another attempt and the pattern still does not match. |
| s_bitslip_failed <= '1'; |
| end if; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/glue_data.vhd |
|---|
| 0,0 → 1,60 |
| --------------------------------------------- |
| -- glue incoming data (from MSB position) |
| -- |
| -- in: D1, D2, D3, D4... |
| -- out: D1D2, D3D4... |
| -- |
| -- |
| -- NOTE: hardwired for 8 + 8, beware if changing dimensions. swap_endianness only works on 8-bits |
| library ieee; |
| use ieee.std_logic_1164.all; |
| library utilities; |
| entity glue_data is |
| port ( |
| i_clk : in std_logic; |
| i_reset_n : in std_logic; |
| i_data : in std_logic_vector( 7 downto 0 ); |
| i_valid : in std_logic; |
| o_enable : out std_logic; |
| o_data : out std_logic_vector( 15 downto 0 ); |
| o_valid : out std_logic; |
| i_enable : in std_logic |
| ); |
| end glue_data; |
| architecture behavioral of glue_data is |
| component swap_endianness |
| port ( |
| i_data : in std_logic_vector; |
| o_data : out std_logic_vector |
| ); |
| end component; |
| signal s_rst_n : std_logic; |
| signal s_packed_data : std_logic_vector( 15 downto 0 ); |
| begin |
| -- pack data: |
| pack_data_inst : entity utilities.pack_data |
| generic map ( G_OUTPUT_WIDTH => 16 ) |
| port map ( |
| i_clk => i_clk, i_reset_n => i_reset_n, |
| i_data => i_data, i_valid => i_valid, o_enable => o_enable, |
| o_data => s_packed_data, o_valid => o_valid, i_enable => i_enable ); |
| -- and swap the bytes to have the first to come on MSB: |
| swap_endianness_inst : swap_endianness |
| port map( i_data => s_packed_data, o_data => o_data ); |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/information_data.vhd |
|---|
| 0,0 → 1,18 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| library kakona; |
| use kakona.kakona_package.all; |
| package information_data is |
| -- Size: |
| constant C_INFO_BITWIDTH : natural := C_KAK_INFO_BITWIDTH; -- not to be changed |
| constant C_INFO_NUMDATA : natural := 4; |
| -- Contents: |
| constant C_INFO_DATA : std_logic_vector( C_INFO_BITWIDTH*C_INFO_NUMDATA - 1 downto 0 ) := C_GUID; |
| end package; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/iserdes_clock_generator.vhd |
|---|
| 0,0 → 1,115 |
| -- file: selectio_iserdes_8bit_ddr_diffin.vhd |
| -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. |
| -- |
| -- This file contains confidential and proprietary information |
| -- of Xilinx, Inc. and is protected under U.S. and |
| -- international copyright and other intellectual property |
| -- laws. |
| -- |
| -- DISCLAIMER |
| -- This disclaimer is not a license and does not grant any |
| -- rights to the materials distributed herewith. Except as |
| -- otherwise provided in a valid license issued to you by |
| -- Xilinx, and to the maximum extent permitted by applicable |
| -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
| -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
| -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
| -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
| -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
| -- (2) Xilinx shall not be liable (whether in contract or tort, |
| -- including negligence, or under any other theory of |
| -- liability) for any loss or damage of any kind or nature |
| -- related to, arising under or in connection with these |
| -- materials, including for any direct, or any indirect, |
| -- special, incidental, or consequential loss or damage |
| -- (including loss of data, profits, goodwill, or any type of |
| -- loss or damage suffered as a result of any action brought |
| -- by a third party) even if such damage or loss was |
| -- reasonably foreseeable or Xilinx had been advised of the |
| -- possibility of the same. |
| -- |
| -- CRITICAL APPLICATIONS |
| -- Xilinx products are not designed or intended to be fail- |
| -- safe, or for use in any application requiring fail-safe |
| -- performance, such as life-support or safety devices or |
| -- systems, Class III medical devices, nuclear facilities, |
| -- applications related to the deployment of airbags, or any |
| -- other applications that could lead to death, personal |
| -- injury, or severe property or environmental damage |
| -- (individually and collectively, "Critical |
| -- Applications"). Customer assumes the sole risk and |
| -- liability of any use of Xilinx products in Critical |
| -- Applications, subject only to applicable laws and |
| -- regulations governing limitations on product liability. |
| -- |
| -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
| -- PART OF THIS FILE AT ALL TIMES. |
| ------------------------------------------------------------------------------ |
| -- User entered comments |
| ------------------------------------------------------------------------------ |
| -- None |
| ------------------------------------------------------------------------------ |
| -- |
| -- EDIT: Only the clock generator buffers here |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.std_logic_unsigned.all; |
| use ieee.std_logic_arith.all; |
| use ieee.std_logic_misc.all; |
| use ieee.numeric_std.all; |
| library unisim; |
| use unisim.vcomponents.all; |
| entity iserdes_clock_generator is |
| port |
| ( |
| -- Clock and reset signals |
| CLK_IN_P : in std_logic; -- Differential fast clock from IOB |
| CLK_IN_N : in std_logic; |
| CLK_OUT : out std_logic; -- Fast clock output (synchronous to data) |
| CLK_DIV_OUT : out std_logic; -- Slow clock output |
| CLK_RESET : in std_logic); -- Reset signal for Clock circuit |
| end iserdes_clock_generator; |
| architecture sychro1 of iserdes_clock_generator is |
| signal clk_in_int : std_logic; |
| begin |
| -- Create the clock logic |
| ibufds_clk_inst : IBUFGDS |
| generic map ( |
| DIFF_TERM => TRUE, |
| IOSTANDARD => "LVDS_25" ) |
| port map ( |
| I => CLK_IN_P, |
| IB => CLK_IN_N, |
| O => clk_in_int); |
| -- High Speed BUFIO clock buffer |
| bufio_inst : BUFIO |
| port map ( |
| O => CLK_OUT, |
| I => clk_in_int); |
| -- BUFR generates the slow clock |
| clkout_buf_inst : BUFR |
| generic map ( |
| SIM_DEVICE => "VIRTEX6", |
| BUFR_DIVIDE => "4") |
| port map ( |
| O => CLK_DIV_OUT, |
| CE => '1', |
| CLR => CLK_RESET, |
| I => clk_in_int ); |
| end sychro1; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/kakona_package.vhd |
|---|
| 0,0 → 1,58 |
| library IEEE; |
| use IEEE.STD_LOGIC_1164.all; |
| use IEEE.numeric_std.all; |
| package kakona_package is |
| -- information block constants: |
| -- Size: |
| constant C_KAK_INFO_BITWIDTH : natural := 32; -- not to be changed |
| constant C_GUID : std_logic_vector( 4*C_KAK_INFO_BITWIDTH - 1 downto 0 ) := X"D52900BA62BC431DBB38C1D38551887A"; -- 1-lane |
| constant C_NUM_INPUT_ADC_MODULES : natural := 2; -- for SPI block |
| constant C_NUM_INPUT_ADC_DATA_PORTS : natural := 4; -- for processing block generate |
| -- configuration for the SPI transmitter for ADCs: |
| -- SPI DATA version 1: |
| constant C_SPI_ADC1_DATA1 : std_logic_vector( 79 downto 0 ) := X"00" & "10000000" & -- software reset |
| X"01" & "00100000" & -- two's complement enabled |
| X"02" & "00000010" & -- 3.5mA LVDS driver, test pattern off, 1-lane |
| X"03" & "10010110" & -- test pattern msb '96' |
| X"04" & "11110010"; -- test pattern lsb 'F2' |
| constant C_SPI_ADC2_DATA1 : std_logic_vector( 79 downto 0 ) := X"00" & "10000000" & -- software reset |
| X"01" & "00100000" & -- two's complement enabled |
| X"02" & "00000010" & -- 3.5mA LVDS driver, test pattern off, 1-lane |
| X"03" & "11111111" & -- test pattern msb 'FF' |
| X"04" & "00000000"; -- test pattern lsb '00' |
| constant C_SPI_ADC_DATA1 : std_logic_vector( C_SPI_ADC1_DATA1'length + C_SPI_ADC2_DATA1'length - 1 downto 0 ) := C_SPI_ADC1_DATA1 & C_SPI_ADC2_DATA1; |
| -- SPI DATA version 2: |
| -- difference: test pattern on. |
| constant C_SPI_ADC1_DATA2 : std_logic_vector( 79 downto 0 ) := X"00" & "10000000" & -- software reset |
| X"01" & "00100000" & -- two's complement enabled |
| X"02" & "00000110" & -- 3.5mA LVDS driver, test pattern on, 1-lane |
| X"03" & "10010110" & -- test pattern msb '96' |
| X"04" & "11110010"; -- test pattern lsb 'F2' |
| constant C_SPI_ADC2_DATA2 : std_logic_vector( 79 downto 0 ) := X"00" & "10000000" & -- software reset |
| X"01" & "00100000" & -- two's complement enabled |
| X"02" & "00000110" & -- 3.5mA LVDS driver, test pattern on, 1-lane |
| X"03" & "11111110" & -- test pattern msb 'FE' |
| X"04" & "11111111"; -- test pattern lsb 'FF' |
| constant C_SPI_ADC_DATA2 : std_logic_vector( C_SPI_ADC1_DATA2'length + C_SPI_ADC2_DATA2'length - 1 downto 0 ) := C_SPI_ADC1_DATA2 & C_SPI_ADC2_DATA2; |
| constant C_SPI_ADC_LENGTH : integer := 16; |
| constant C_SPI_ADC_PACKETS : integer := 5; |
| constant C_SPI_ADC_PAUSE : integer := 300; |
| -- definition of swapped P&N wires: |
| constant C_FRAME_WIRES_SWAPPED_PN : std_logic := '1'; |
| -- definition of swapped P&N wires in data lines. Direction conforms to .ucf file array. |
| constant C_DATA_WIRES_SWAPPED_PN : std_logic_vector( 0 to 3 ) := "0101"; |
| end package; |
| package body kakona_package is |
| end package body; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/lo_divider_wrapper.vhd |
|---|
| 0,0 → 1,86 |
| -------------------------------------------- |
| -- wrapper for the local oscillator division logic |
| -- |
| library ieee; |
| use ieee.std_logic_1164.all; |
| library UNISIM; |
| use UNISIM.vcomponents.all; |
| library sychro1; |
| entity lo_divider_wrapper is |
| generic ( |
| G_DIVISOR : integer |
| ); |
| port ( |
| -- input clock: |
| IN_CLK_LO_N : IN std_logic; |
| IN_CLK_LO_P : IN std_logic; |
| in_clk_enable : in std_logic; |
| -- divided clock |
| OUT_CLK_LO_DIVIDED_N : OUT std_logic; |
| OUT_CLK_LO_DIVIDED_P : OUT std_logic |
| ); |
| end lo_divider_wrapper; |
| architecture behavioral of lo_divider_wrapper is |
| -- clock signals for in->divide->out clock: |
| signal s_in_clk_lo : std_logic; |
| signal s_in_clk_lo_bufred : std_logic; |
| signal s_divided_lo : std_logic; |
| attribute clock_signal : string; |
| attribute clock_signal of s_divided_lo : signal is "yes"; |
| begin |
| IBUFGDS_inst : IBUFGDS |
| generic map ( |
| DIFF_TERM => TRUE |
| --IBUF_LOW_PWR => TRUE -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards |
| ) |
| port map ( |
| O => s_in_clk_lo, -- Clock buffer output |
| I => IN_CLK_LO_P, -- Diff_p clock buffer input (connect directly to top-level port) |
| IB => IN_CLK_LO_N -- Diff_n clock buffer input (connect directly to top-level port) |
| ); |
| -- TEST2: misto counteru pouziju deleni v BUFR |
| BUFR_inst : BUFR |
| generic map ( |
| BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" |
| SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6" |
| port map ( |
| O => s_in_clk_lo_bufred, -- Clock buffer output |
| CE => in_clk_enable, -- Clock enable input |
| CLR => '0', -- Clock buffer reset input |
| I => s_in_clk_lo -- Clock buffer input |
| ); |
| -- TEST3: opravil jsem clock_divider, zkusim ho sem dat zpatky |
| -- -> BUFR -> BYPASS |
| -- zpatky clock_divider |
| -- TEMP1: vyhozeni counteru |
| divider_inst : entity sychro1.clock_divider |
| generic map( G_DIVISOR => G_DIVISOR ) |
| port map( i_clk => s_in_clk_lo_bufred, i_rst => '0', o_clk => s_divided_lo ); |
| --s_divided_lo <= s_in_clk_lo_bufred; |
| OBUFDS_inst : OBUFDS |
| generic map ( |
| IOSTANDARD => "DEFAULT" ) |
| port map ( |
| O => OUT_CLK_LO_DIVIDED_P, -- Diff_p output (connect directly to top-level port) |
| OB => OUT_CLK_LO_DIVIDED_N, -- Diff_n output (connect directly to top-level port) |
| I => s_divided_lo -- Buffer input |
| ); |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/multiplexer_from_fifos.vhd |
|---|
| 0,0 → 1,92 |
| -------------------------------------------- |
| -- Multiplexer from FIFOs |
| -- |
| -- Waits until all i_valid signals are asserted. Then, if i_full == '0', cycles through all inputs and puts them to output. |
| -- If at that time i_full == '1', all the inputs are discarded. |
| library ieee; |
| use ieee.std_logic_1164.all; |
| entity multiplexer_from_fifos is |
| generic |
| ( G_NUM_CHANNELS : natural := 2; -- number of channels |
| G_DATA_WIDTH : natural := 32 -- data width of individual packets |
| ); |
| port ( |
| clk : in std_logic; |
| rst : in std_logic; |
| -- input side |
| i_data : in std_logic_vector( G_DATA_WIDTH*G_NUM_CHANNELS - 1 downto 0 ); |
| i_valid : in std_logic_vector( G_NUM_CHANNELS - 1 downto 0 ); |
| o_rden : out std_logic_vector( G_NUM_CHANNELS - 1 downto 0 ); |
| -- output side |
| o_data : out std_logic_vector( G_DATA_WIDTH - 1 downto 0 ); |
| o_valid : out std_logic; |
| i_full : in std_logic |
| ); |
| end multiplexer_from_fifos; |
| architecture behavioral of multiplexer_from_fifos is |
| subtype t_counter is natural range 0 to G_NUM_CHANNELS; |
| signal s_counter : t_counter := 0; |
| signal s_all_i_valid : std_logic; |
| signal s_drop_data : std_logic; |
| begin |
| assert( G_NUM_CHANNELS > 1 ) report "The number of channels must be higher than 1." severity failure; |
| s_all_i_valid <= '1' when i_valid = ( i_valid'range => '1' ) else |
| '0'; |
| counter_process : process( clk ) |
| begin |
| if( rising_edge( clk ) ) then |
| s_drop_data <= '0'; |
| if( rst = '1' ) then |
| -- reset |
| s_counter <= 0; |
| elsif( s_counter = 0 and s_all_i_valid = '1' and i_full = '0' and s_drop_data = '0' ) then |
| -- counter is stopped, i_data have new data and the following FIFO is ready to receive. |
| -- start the counter. |
| s_counter <= 1; |
| elsif( s_counter = 0 and s_all_i_valid = '1' and i_full = '1' ) then |
| -- discard the complete set of data because the following FIFO is full. |
| s_drop_data <= '1'; |
| elsif( s_counter > 0 and s_counter < t_counter'high ) then |
| -- the counter is running and is somewhere in between, just increase the value. |
| s_counter <= s_counter + 1; |
| elsif( s_counter = t_counter'high and s_all_i_valid = '1' and i_full = '0' ) then |
| -- the counter has reached maximum value and there are new data waiting |
| -- start the counter right away |
| s_counter <= 1; |
| else |
| -- stop the counter |
| s_counter <= 0; |
| end if; |
| end if; |
| end process; |
| ---------------------------------------------- |
| -- OUTPUT SIGNALS: |
| o_data <= i_data( G_DATA_WIDTH*s_counter - 1 downto G_DATA_WIDTH*s_counter - G_DATA_WIDTH ) when s_counter > 0 and rst = '0' else |
| ( others => '0' ); |
| o_valid <= i_valid( s_counter - 1 ) when s_counter > 0 and rst = '0' else |
| '0'; |
| o_rden_gen : for i in 0 to G_NUM_CHANNELS - 1 generate |
| o_rden(i) <= '1' when ( s_counter = i + 1 or s_drop_data = '1' ) and i_valid(i) = '1' else |
| '0'; |
| end generate; |
| ---------------------------------------------- |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/myserdes_ddr.vhd |
|---|
| 0,0 → 1,247 |
| -- file: selectio_iserdes_8bit_ddr_diffin.vhd |
| -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. |
| -- |
| -- This file contains confidential and proprietary information |
| -- of Xilinx, Inc. and is protected under U.S. and |
| -- international copyright and other intellectual property |
| -- laws. |
| -- |
| -- DISCLAIMER |
| -- This disclaimer is not a license and does not grant any |
| -- rights to the materials distributed herewith. Except as |
| -- otherwise provided in a valid license issued to you by |
| -- Xilinx, and to the maximum extent permitted by applicable |
| -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
| -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
| -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
| -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
| -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
| -- (2) Xilinx shall not be liable (whether in contract or tort, |
| -- including negligence, or under any other theory of |
| -- liability) for any loss or damage of any kind or nature |
| -- related to, arising under or in connection with these |
| -- materials, including for any direct, or any indirect, |
| -- special, incidental, or consequential loss or damage |
| -- (including loss of data, profits, goodwill, or any type of |
| -- loss or damage suffered as a result of any action brought |
| -- by a third party) even if such damage or loss was |
| -- reasonably foreseeable or Xilinx had been advised of the |
| -- possibility of the same. |
| -- |
| -- CRITICAL APPLICATIONS |
| -- Xilinx products are not designed or intended to be fail- |
| -- safe, or for use in any application requiring fail-safe |
| -- performance, such as life-support or safety devices or |
| -- systems, Class III medical devices, nuclear facilities, |
| -- applications related to the deployment of airbags, or any |
| -- other applications that could lead to death, personal |
| -- injury, or severe property or environmental damage |
| -- (individually and collectively, "Critical |
| -- Applications"). Customer assumes the sole risk and |
| -- liability of any use of Xilinx products in Critical |
| -- Applications, subject only to applicable laws and |
| -- regulations governing limitations on product liability. |
| -- |
| -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
| -- PART OF THIS FILE AT ALL TIMES. |
| ------------------------------------------------------------------------------ |
| -- User entered comments |
| ------------------------------------------------------------------------------ |
| -- None |
| ------------------------------------------------------------------------------ |
| -- |
| -- EDIT: the clocking logic has been moved outside |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.std_logic_unsigned.all; |
| use ieee.std_logic_arith.all; |
| use ieee.std_logic_misc.all; |
| use ieee.numeric_std.all; |
| library unisim; |
| use unisim.vcomponents.all; |
| entity myserdes_ddr is |
| generic |
| (-- width of the data for the system |
| sys_w : integer := 1; |
| -- width of the data for the device |
| dev_w : integer := 8); |
| port |
| ( |
| -- From the system into the device |
| DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0); |
| DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0); |
| DATA_IN_TO_DEVICE : out std_logic_vector(dev_w-1 downto 0); |
| BITSLIP : in std_logic; -- Bitslip module is enabled in NETWORKING mode |
| -- User should tie it to '0' if not needed |
| -- Clock and reset signals |
| CLK_IN : in std_logic; -- Fast clock from IOB, after IBUFGDS and BUFIO |
| CLK_DIV_IN : in std_logic; -- Divided fast clock from IBUFGDS and BUFR |
| IO_RESET : in std_logic); -- Reset signal for IO circuit |
| end myserdes_ddr; |
| architecture xilinx of myserdes_ddr is |
| attribute CORE_GENERATION_INFO : string; |
| attribute CORE_GENERATION_INFO of xilinx : architecture is "selectio_iserdes_8bit_ddr_diffin,selectio_wiz_v4_1,{component_name=selectio_iserdes_8bit_ddr_diffin,bus_dir=INPUTS,bus_sig_type=DIFF,bus_io_std=LVDS_25,use_serialization=true,use_phase_detector=false,serialization_factor=8,enable_bitslip=false,enable_train=false,system_data_width=1,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=DIFF,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,v6_bus_in_delay=NONE,v6_bus_out_delay=NONE,v6_clk_buf=BUFIO,v6_active_edge=DDR,v6_ddr_alignment=SAME_EDGE_PIPELINED,v6_oddr_alignment=SAME_EDGE,ddr_alignment=C0,v6_interface_type=NETWORKING,interface_type=NETWORKING,v6_bus_in_tap=0,v6_bus_out_tap=0,v6_clk_io_std=LVDS_25,v6_clk_sig_type=DIFF}"; |
| constant clock_enable : std_logic := '1'; |
| signal unused : std_logic; |
| -- After the buffer |
| signal data_in_from_pins_int : std_logic_vector(sys_w-1 downto 0); |
| -- Between the delay and serdes |
| signal data_in_from_pins_delay : std_logic_vector(sys_w-1 downto 0); |
| constant num_serial_bits : integer := dev_w/sys_w; |
| type serdarr is array (0 to 9) of std_logic_vector(sys_w-1 downto 0); |
| -- Array to use intermediately from the serdes to the internal |
| -- devices. bus "0" is the leftmost bus |
| -- * fills in starting with 0 |
| signal iserdes_q : serdarr := (( others => (others => '0'))); |
| signal serdesstrobe : std_logic; |
| signal icascade1 : std_logic_vector(sys_w-1 downto 0); |
| signal icascade2 : std_logic_vector(sys_w-1 downto 0); |
| signal clk_in_inv : std_logic; |
| begin |
| -- We have multiple bits- step over every bit, instantiating the required elements |
| pins: for pin_count in 0 to sys_w-1 generate |
| begin |
| -- Instantiate the buffers |
| ---------------------------------- |
| -- Instantiate a buffer for every bit of the data bus |
| ibufds_inst : IBUFDS |
| generic map ( |
| DIFF_TERM => TRUE, -- Differential termination |
| IOSTANDARD => "LVDS_25") |
| port map ( |
| I => DATA_IN_FROM_PINS_P (pin_count), |
| IB => DATA_IN_FROM_PINS_N (pin_count), |
| O => data_in_from_pins_int(pin_count)); |
| -- Pass through the delay |
| ----------------------------------- |
| data_in_from_pins_delay(pin_count) <= data_in_from_pins_int(pin_count); |
| -- Instantiate the serdes primitive |
| ---------------------------------- |
| clk_in_inv <= not (CLK_IN); |
| -- declare the iserdes |
| iserdese1_master : ISERDESE1 |
| generic map ( |
| DATA_RATE => "DDR", |
| DATA_WIDTH => 8, |
| INTERFACE_TYPE => "NETWORKING", |
| DYN_CLKDIV_INV_EN => FALSE, |
| DYN_CLK_INV_EN => FALSE, |
| NUM_CE => 2, |
| OFB_USED => FALSE, |
| IOBDELAY => "NONE", -- Use input at D to output the data on Q1-Q6 |
| SERDES_MODE => "MASTER") |
| port map ( |
| Q1 => iserdes_q(0)(pin_count), |
| Q2 => iserdes_q(1)(pin_count), |
| Q3 => iserdes_q(2)(pin_count), |
| Q4 => iserdes_q(3)(pin_count), |
| Q5 => iserdes_q(4)(pin_count), |
| Q6 => iserdes_q(5)(pin_count), |
| SHIFTOUT1 => icascade1(pin_count), -- Cascade connection to Slave ISERDES |
| SHIFTOUT2 => icascade2(pin_count), -- Cascade connection to Slave ISERDES |
| BITSLIP => BITSLIP, -- 1-bit Invoke Bitslip. This can be used with any |
| -- DATA_WIDTH, cascaded or not. |
| CE1 => clock_enable, -- 1-bit Clock enable input |
| CE2 => clock_enable, -- 1-bit Clock enable input |
| CLK => CLK_IN, -- Fast Source Synchronous SERDES clock from BUFIO |
| CLKB => clk_in_inv, -- Locally inverted clock |
| CLKDIV => CLK_DIV_IN, -- Slow clock driven by BUFR |
| D => data_in_from_pins_delay(pin_count), -- 1-bit Input signal from IOB. |
| DDLY => '0', |
| RST => IO_RESET, -- 1-bit Asynchronous reset only. |
| SHIFTIN1 => '0', |
| SHIFTIN2 => '0', |
| -- unused connections |
| DYNCLKDIVSEL => '0', |
| DYNCLKSEL => '0', |
| OFB => '0', |
| OCLK => '0', |
| O => open); -- unregistered output of ISERDESE1 |
| iserdese1_slave : ISERDESE1 |
| generic map ( |
| DATA_RATE => "DDR", |
| DATA_WIDTH => 8, |
| INTERFACE_TYPE => "NETWORKING", |
| DYN_CLKDIV_INV_EN => FALSE, |
| DYN_CLK_INV_EN => FALSE, |
| NUM_CE => 2, |
| OFB_USED => FALSE, |
| IOBDELAY => "NONE", -- Use input at D to output the data on Q1-Q6 |
| SERDES_MODE => "SLAVE") |
| port map ( |
| Q1 => open, |
| Q2 => open, |
| Q3 => iserdes_q(6)(pin_count), |
| Q4 => iserdes_q(7)(pin_count), |
| Q5 => iserdes_q(8)(pin_count), |
| Q6 => iserdes_q(9)(pin_count), |
| SHIFTOUT1 => open, |
| SHIFTOUT2 => open, |
| SHIFTIN1 => icascade1(pin_count), -- Cascade connections from Master ISERDES |
| SHIFTIN2 => icascade2(pin_count), -- Cascade connections from Master ISERDES |
| BITSLIP => BITSLIP, -- 1-bit Invoke Bitslip. This can be used with any |
| -- DATA_WIDTH, cascaded or not. |
| CE1 => clock_enable, -- 1-bit Clock enable input |
| CE2 => clock_enable, -- 1-bit Clock enable input |
| CLK => CLK_IN, -- Fast source synchronous serdes clock |
| CLKB => clk_in_inv, -- locally inverted clock |
| CLKDIV => CLK_DIV_IN, -- Slow clock sriven by BUFR. |
| D => '0', -- Slave ISERDES module. No need to connect D, DDLY |
| DDLY => '0', |
| RST => IO_RESET, -- 1-bit Asynchronous reset only. |
| -- unused connections |
| DYNCLKDIVSEL => '0', |
| DYNCLKSEL => '0', |
| OFB => '0', |
| OCLK => '0', |
| O => open); -- unregistered output of ISERDESE1 |
| -- Concatenate the serdes outputs together. Keep the timesliced |
| -- bits together, and placing the earliest bits on the right |
| -- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ... |
| -- the output will be 3210, 7654, ... |
| ------------------------------------------------------------- |
| in_slices: for slice_count in 0 to num_serial_bits-1 generate begin |
| -- This places the first data in time on the right |
| -- DATA_IN_TO_DEVICE(slice_count) <= |
| -- iserdes_q(num_serial_bits-slice_count-1)(0); |
| -- To place the first data in time on the left, use the |
| -- following code, instead |
| DATA_IN_TO_DEVICE(slice_count) <= |
| iserdes_q(slice_count)(0); |
| end generate in_slices; |
| end generate pins; |
| end xilinx; |
| Property changes: |
| Added: svn:executable |
| +* |
| \ No newline at end of property |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/myserdes_ddr_wrapper.vhd |
|---|
| 0,0 → 1,78 |
| -------------------------------------------- |
| -- wrapper for the iserdes_ddr and pack_data |
| -- |
| library ieee; |
| use ieee.std_logic_1164.all; |
| library UNISIM; |
| use UNISIM.vcomponents.all; |
| entity myserdes_ddr_wrapper is |
| generic |
| (-- width of the data for the system |
| sys_w : integer := 1; |
| -- width of the data for the device |
| dev_w : integer := 8); |
| port ( |
| -- CLOCK: |
| clk_in : in std_logic; |
| clk_in_div : in std_logic; |
| -- PADS IN: |
| data_in_from_pins_p : in std_logic; |
| data_in_from_pins_n : in std_logic; |
| data_in_to_device : out std_logic_vector( dev_w - 1 downto 0 ); |
| bitslip : in std_logic; |
| rst_in : in std_logic ); |
| end myserdes_ddr_wrapper; |
| architecture behavioral of myserdes_ddr_wrapper is |
| component myserdes_ddr is |
| generic |
| (-- width of the data for the system |
| sys_w : integer := 1; |
| -- width of the data for the device |
| dev_w : integer := 8); |
| port |
| ( |
| -- From the system into the device |
| DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0); |
| DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0); |
| DATA_IN_TO_DEVICE : out std_logic_vector(dev_w-1 downto 0); |
| BITSLIP : in std_logic; -- Bitslip module is enabled in NETWORKING mode |
| -- User should tie it to '0' if not needed |
| -- Clock and reset signals |
| CLK_IN : in std_logic; -- Fast clock from IOB, after IBUFGDS and BUFIO |
| CLK_DIV_IN : in std_logic; -- Divided fast clock from IBUFGDS and BUFR |
| IO_RESET : in std_logic); -- Reset signal for IO circuit |
| end component; |
| -- data in signal: |
| signal s_data_in_from_pins_p : std_logic_vector( sys_w-1 downto 0 ); |
| signal s_data_in_from_pins_n : std_logic_vector( sys_w-1 downto 0 ); |
| begin |
| -- convert std_logic to std_logic_vector |
| s_data_in_from_pins_n(0) <= data_in_from_pins_n; |
| s_data_in_from_pins_p(0) <= data_in_from_pins_p; |
| -- instantiate the myserdes_ddr |
| myserdes_ddr_inst : myserdes_ddr |
| port map ( |
| DATA_IN_FROM_PINS_P => s_data_in_from_pins_p, DATA_IN_FROM_PINS_N => s_data_in_from_pins_n, |
| DATA_IN_TO_DEVICE => data_in_to_device, |
| BITSLIP => bitslip, CLK_IN => clk_in, CLK_DIV_IN => clk_in_div, IO_RESET => rst_in ); |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/processing_block.vhd |
|---|
| 0,0 → 1,185 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| library UNISIM; |
| use UNISIM.vcomponents.all; |
| library utilities; |
| entity processing_block is |
| port ( |
| -- clock: |
| clk_iserdes_in : in std_logic; |
| clk_iserdes_in_div : in std_logic; |
| clk_global : in std_logic; |
| -- reset: |
| rst : in std_logic; |
| -- bitslip: |
| bitslip : in std_logic; |
| bitslip_done : in std_logic; -- todo: use this |
| bitslip_drop_byte : in std_logic; |
| -- input signal: |
| in_data_p : in std_logic; |
| in_data_n : in std_logic; |
| in_data_swap_pn : in std_logic; |
| -- input switch for counter output: |
| in_output_counting : in std_logic; |
| -- output after iserdes and pack16 for bitslip: |
| o_iserdes_output : out std_logic_vector( 15 downto 0 ); |
| o_iserdes_output_valid : out std_logic; |
| -- output fwft FIFO: |
| o_data : out std_logic_vector( 31 downto 0 ); |
| o_valid : out std_logic; |
| i_rden : in std_logic |
| ); |
| end processing_block; |
| architecture behavioral of processing_block is |
| component swap_endianness |
| port ( |
| i_data : in std_logic_vector; |
| o_data : out std_logic_vector |
| ); |
| end component; |
| component fifo_32x512_dualclk_fwft |
| port ( |
| rst : in std_logic; |
| wr_clk : in std_logic; |
| rd_clk : in std_logic; |
| din : in std_logic_vector(31 downto 0); |
| wr_en : in std_logic; |
| rd_en : in std_logic; |
| dout : out std_logic_vector(31 downto 0); |
| full : out std_logic; |
| empty : out std_logic; |
| valid : out std_logic |
| ); |
| end component; |
| component myserdes_ddr_wrapper |
| generic |
| ( sys_w : integer := 1; |
| dev_w : integer := 8); |
| port ( |
| -- CLOCK: |
| clk_in : in std_logic; |
| clk_in_div : in std_logic; |
| -- PADS IN: |
| data_in_from_pins_p : in std_logic; |
| data_in_from_pins_n : in std_logic; |
| -- DATA OUT: |
| data_in_to_device : out std_logic_vector( dev_w - 1 downto 0 ); |
| bitslip : in std_logic; |
| rst_in : in std_logic ); |
| end component; |
| component saw_generator_wrapper |
| generic ( |
| G_INCREASE_EVERY_NTH : positive := 4 |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| o_valid : out std_logic; |
| o_data : out std_logic_vector |
| ); |
| end component; |
| -- Frame signal |
| signal s_in_frame_for_data : std_logic_vector( 7 downto 0 ); |
| signal s_in_frame_for_data_precorrect : std_logic_vector( 7 downto 0 ); |
| signal s_in_frame_for_data_packed16 : std_logic_vector( 15 downto 0 ); |
| signal s_in_frame_for_data_packed16_le : std_logic_vector( 15 downto 0 ); |
| signal s_in_frame_for_data_packed16_swapped : std_logic_vector( 15 downto 0 ); |
| signal s_in_frame_for_data_packed16_valid : std_logic; |
| signal s_in_frame_for_data_packed16_valid_wbitslip_done : std_logic; |
| signal s_in_frame_for_data_packed32 : std_logic_vector( 31 downto 0 ); |
| signal s_in_frame_for_data_packed32_valid : std_logic; |
| signal s_rst_n : std_logic; |
| -- counter: |
| signal s_counter_valid : std_logic; |
| signal s_counter_data : std_logic_vector( 31 downto 0 ); |
| -- selection signals for the final FIFO: |
| signal s_selected_source_valid : std_logic; |
| signal s_selected_source_data : std_logic_vector( 31 downto 0 ); |
| -- byte drop request |
| signal s_bitslip_drop_byte_n : std_logic; |
| begin |
| s_rst_n <= not rst; |
| s_bitslip_drop_byte_n <= not bitslip_drop_byte; |
| -- iserdes wrapper: |
| myserdes_ddr_wrapper_inst : myserdes_ddr_wrapper |
| port map ( |
| clk_in => clk_iserdes_in, clk_in_div => clk_iserdes_in_div, |
| data_in_from_pins_p => in_data_p, data_in_from_pins_n => in_data_n, data_in_to_device => s_in_frame_for_data_precorrect, |
| bitslip => bitslip, rst_in => rst ); |
| -- correct hardware swapping of P&N wires: |
| s_in_frame_for_data <= s_in_frame_for_data_precorrect when in_data_swap_pn = '0' else |
| not s_in_frame_for_data_precorrect; |
| -- glue two parts to 16-bit full data: |
| glue_data_inst : entity work.glue_data |
| port map ( |
| i_clk => clk_iserdes_in_div, i_reset_n => s_rst_n, |
| i_data => s_in_frame_for_data, i_valid => s_bitslip_drop_byte_n, o_enable => open, |
| o_data => s_in_frame_for_data_packed16, o_valid => s_in_frame_for_data_packed16_valid, i_enable => '1' ); |
| -- output the 16-bit to manage bitslip: |
| o_iserdes_output <= s_in_frame_for_data_packed16; |
| o_iserdes_output_valid <= s_in_frame_for_data_packed16_valid; |
| -- these data go further after bitslip has been set: |
| s_in_frame_for_data_packed16_le <= s_in_frame_for_data_packed16; |
| s_in_frame_for_data_packed16_valid_wbitslip_done <= bitslip_done and s_in_frame_for_data_packed16_valid; |
| -- insert the pack block to 32 bits: |
| pack_data32_inst : entity utilities.pack_data |
| generic map ( |
| G_OUTPUT_WIDTH => 32 ) |
| port map ( |
| i_clk => clk_iserdes_in_div, i_reset_n => s_rst_n, |
| i_data => s_in_frame_for_data_packed16_le, i_valid => s_in_frame_for_data_packed16_valid_wbitslip_done, o_enable => open, |
| o_data => s_in_frame_for_data_packed32, o_valid => s_in_frame_for_data_packed32_valid, i_enable => '1' ); |
| -- counter: |
| counter_inst : saw_generator_wrapper |
| generic map( G_INCREASE_EVERY_NTH => 4 ) |
| port map( |
| i_clk => clk_iserdes_in_div, i_rst => rst, o_valid => s_counter_valid, o_data => s_counter_data ); |
| -- output either the grabbed data or the counter, based on request: |
| s_selected_source_valid <= s_counter_valid when in_output_counting = '1' else s_in_frame_for_data_packed32_valid; |
| s_selected_source_data <= s_counter_data when in_output_counting = '1' else s_in_frame_for_data_packed32; |
| -- insert the cross-domain FIFO: |
| cross_domain_fifo_inst : fifo_32x512_dualclk_fwft |
| port map ( |
| rst => rst, wr_clk => clk_iserdes_in_div, rd_clk => clk_global, |
| din => s_selected_source_data, wr_en => s_selected_source_valid, full => open, |
| dout => o_data, valid => o_valid, rd_en => i_rden, empty => open ); |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/saw_generator_wrapper.vhd |
|---|
| 0,0 → 1,47 |
| --------------------------------------------- |
| -- increase output every fourth clock cycle |
| -- |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| library sychro1; |
| entity saw_generator_wrapper is |
| generic ( |
| G_INCREASE_EVERY_NTH : positive := 4 |
| ); |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| o_valid : out std_logic; |
| o_data : out std_logic_vector |
| ); |
| end saw_generator_wrapper; |
| architecture behavioral of saw_generator_wrapper is |
| signal s_modulo_counter_carry : std_logic; |
| begin |
| -- first counter that counts modulo G_INCREASE_EVERY_NTH to generate a valid signal for the second counter |
| -- and the output: |
| modulo_up_counter : entity sychro1.up_counter |
| generic map ( G_MIN_NUMBER => 0, G_MAX_NUMBER => G_INCREASE_EVERY_NTH - 1 ) |
| port map ( i_clk => i_clk, i_rst => i_rst, i_valid => '1', o_data => open, o_carry => s_modulo_counter_carry ); |
| -- the second counter: |
| main_up_counter : entity sychro1.up_counter_stdlv |
| generic map ( G_BITS => o_data'length, G_MIN_NUMBER => ( o_data'range => '0' ), G_MAX_NUMBER => ( o_data'range => '1' ) ) |
| port map( i_clk => i_clk, i_rst => i_rst, i_valid => s_modulo_counter_carry, o_data => o_data, o_carry => open ); |
| -- signal connection: |
| o_valid <= s_modulo_counter_carry; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/spi_transmitter_wrapper2.vhd |
|---|
| 0,0 → 1,123 |
| ----------------------------------------------- |
| -- wrapper for the SPI master transmitter logic |
| -- |
| library ieee; |
| use ieee.std_logic_1164.all; |
| library UNISIM; |
| use UNISIM.vcomponents.all; |
| library comm; |
| entity spi_transmitter_wrapper is |
| generic ( |
| G_DATA1 : std_logic_vector; |
| G_DATA2 : std_logic_vector; |
| G_NUM_BITS_PACKET : integer; |
| G_NUM_PACKETS : integer; |
| G_NUM_BITS_PAUSE : integer |
| ); |
| port ( |
| -- input clock: |
| i_clk125 : in std_logic; |
| i_reset : in std_logic; |
| i_data_selector : in std_logic; |
| o_done : out std_logic; |
| -- SPI output: |
| OUT_SPI_N_CE : OUT std_logic_vector; |
| OUT_SPI_DOUT : OUT std_logic; |
| OUT_SPI_CLK : OUT std_logic |
| ); |
| end spi_transmitter_wrapper; |
| architecture behavioral of spi_transmitter_wrapper is |
| component clk_125MHz_to_6MHz |
| port |
| (-- Clock in ports |
| CLK_IN_125 : in std_logic; |
| -- Clock out ports |
| CLK_OUT_6 : out std_logic |
| ); |
| end component; |
| -- divided clock: |
| signal s_spi_input_clk : std_logic; |
| signal s_clk_6MHz : std_logic; |
| signal s_clk_125kHz_tmp : std_logic; |
| attribute clock_signal : string; |
| attribute clock_signal of s_spi_input_clk : signal is "yes"; |
| -- SPI output pins registers: |
| signal s_out_spi_n_ce_d : std_logic_vector( OUT_SPI_N_CE'range ); |
| signal s_out_spi_dout_d : std_logic; |
| signal s_out_spi_clk_d : std_logic; |
| -- pack the OUT registers to IOB so that the timing is better: |
| attribute iob : string; |
| attribute iob of OUT_SPI_N_CE : signal is "FORCE"; |
| attribute iob of OUT_SPI_DOUT : signal is "FORCE"; |
| attribute iob of OUT_SPI_CLK : signal is "FORCE"; |
| begin |
| -- IP Core clock wizard: |
| clk_125MHz_to_6MHz_inst : clk_125MHz_to_6MHz |
| port map ( CLK_IN_125 => i_clk125, CLK_OUT_6 => s_clk_6MHz ); |
| -- ~1MHz clock: |
| BUFR_inst : BUFR |
| generic map ( |
| BUFR_DIVIDE => "6", SIM_DEVICE => "VIRTEX6" ) |
| port map ( |
| O => s_clk_125kHz_tmp, -- s_spi_input_clk |
| CE => '1', |
| CLR => '0', |
| I => s_clk_6MHz |
| ); |
| BUFR2_inst : BUFR |
| generic map ( |
| BUFR_DIVIDE => "8", SIM_DEVICE => "VIRTEX6" ) |
| port map ( |
| O => s_spi_input_clk, |
| CE => '1', |
| CLR => '0', |
| I => s_clk_125kHz_tmp |
| ); |
| -- SPI master transmitter: |
| spi_transmit_inst : entity comm.spi_master_transmit |
| generic map( |
| G_DATA1 => G_DATA1, |
| G_DATA2 => G_DATA2, |
| G_NUM_BITS_PACKET => G_NUM_BITS_PACKET, |
| G_NUM_PACKETS => G_NUM_PACKETS, |
| G_NUM_BITS_PAUSE => G_NUM_BITS_PAUSE ) |
| port map( |
| i_clk => s_spi_input_clk, i_rst => i_reset, i_data_selector => i_data_selector, |
| o_done => o_done, |
| o_n_ce => s_out_spi_n_ce_d, |
| o_dout => s_out_spi_dout_d, |
| o_clk => s_out_spi_clk_d |
| ); |
| -- registers: |
| registered_spi_output : process( s_clk_6MHz ) |
| begin |
| if( rising_edge( s_clk_6MHz ) ) then |
| OUT_SPI_N_CE <= s_out_spi_n_ce_d; |
| OUT_SPI_DOUT <= s_out_spi_dout_d; |
| OUT_SPI_CLK <= s_out_spi_clk_d; |
| end if; |
| end process; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/swap_endianness.vhd |
|---|
| 0,0 → 1,24 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| entity swap_endianness is |
| port ( |
| i_data : in std_logic_vector; |
| o_data : out std_logic_vector |
| ); |
| end swap_endianness; |
| architecture behavioral of swap_endianness is |
| begin |
| assert ( i_data'length = o_data'length ) report "The input and output data lengths have to match." severity failure; |
| assert ( i_data'length mod 8 = 0 ) report "The data length has to be divisible by 8. (Whole bytes)." severity failure; |
| swap_gen : for i in 0 to ((i_data'length / 8) - 1) generate |
| o_data( 8*(i+1) - 1 downto 8*i ) <= i_data( i_data'length - 8*i - 1 downto i_data'length - 8*(i+1) ); |
| end generate; |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/userlogiccmp_template.vhd |
|---|
| 0,0 → 1,82 |
| -- Dummy user_logic_cmp_winfo |
| -- |
| -- |
| -- Uses only data1 stream and simply adds to each byte a given number |
| -- |
| -- uses the information_block entity for version/type control |
| library ieee; |
| use ieee.std_logic_1164.all; |
| use ieee.numeric_std.all; |
| entity user_logic_cmp is |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| -- data1 interface: |
| i_data1in_data : in std_logic_vector( 31 downto 0 ); |
| i_data1in_valid : in std_logic; |
| o_data1in_enable : out std_logic; |
| o_data1out_data : out std_logic_vector( 31 downto 0 ); |
| o_data1out_valid : out std_logic; |
| i_data1out_enable : in std_logic; |
| -- data2 interface: |
| i_data2in_data : in std_logic_vector( 31 downto 0 ); |
| i_data2in_valid : in std_logic; |
| o_data2in_enable : out std_logic; |
| o_data2out_data : out std_logic_vector( 31 downto 0 ); |
| o_data2out_valid : out std_logic; |
| i_data2out_enable : in std_logic; |
| -- control interface: |
| i_controlin_data : in std_logic_vector( 31 downto 0 ); |
| i_controlin_valid : in std_logic; |
| o_controlin_enable : out std_logic; |
| o_controlout_data : out std_logic_vector( 31 downto 0 ); |
| o_controlout_valid : out std_logic; |
| i_controlout_enable : in std_logic |
| ); |
| end entity; |
| architecture behavioral of user_logic_cmp is |
| component information_block is |
| port ( |
| clk : in std_logic; rst : in std_logic; |
| -- Input side: |
| i_data : in std_logic_vector( 31 downto 0 ); i_valid : in std_logic; o_enable : out std_logic; |
| -- Output side: |
| o_data : out std_logic_vector( 31 downto 0 ); o_valid : out std_logic; i_enable : in std_logic ); |
| end component; |
| begin |
| -- Example how to read and transmit data: |
| sum_process : process( i_clk ) |
| begin |
| if( rising_edge( i_clk ) ) then |
| if( i_rst = '1' ) then |
| o_data1out_data <= ( others => '0' ); |
| o_data1out_valid <= '0'; |
| else |
| o_data1out_data( 31 downto 24 ) <= std_logic_vector( unsigned(i_data1in_data( 31 downto 24 )) + to_unsigned(1,8) ); |
| o_data1out_data( 23 downto 16 ) <= std_logic_vector( unsigned(i_data1in_data( 23 downto 16 )) + to_unsigned(2,8) ); |
| o_data1out_data( 15 downto 8 ) <= std_logic_vector( unsigned(i_data1in_data( 15 downto 8 )) + to_unsigned(3,8) ); |
| o_data1out_data( 7 downto 0 ) <= std_logic_vector( unsigned(i_data1in_data( 7 downto 0 )) + to_unsigned(4,8) ); |
| o_data1out_valid <= i_data1in_valid; |
| end if; |
| end if; |
| end process; |
| o_data1in_enable <= i_data1out_enable; |
| -- information_block: |
| info_block_inst : information_block |
| port map ( |
| clk => i_clk, rst => i_rst, |
| i_data => i_controlin_data, i_valid => i_controlin_valid, o_enable => o_controlin_enable, |
| o_data => o_controlout_data, o_valid => o_controlout_valid, i_enable => i_controlout_enable ); |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/xilly/xilly_toplevel.userlogiccmp_kakona.vhd |
|---|
| 0,0 → 1,543 |
| library ieee; |
| use ieee.std_logic_1164.all; |
| library UNISIM; |
| use UNISIM.vcomponents.all; |
| library sychro1; |
| library utilities; |
| library comm; |
| library kakona; |
| use kakona.kakona_package.all; |
| entity xilly_toplevel is |
| port ( |
| -- FMC & other ports: |
| -- local oscillator to be divided |
| IN_CLK_LO_N : IN std_logic; |
| IN_CLK_LO_P : IN std_logic; |
| -- divided clock |
| OUT_CLK_LO_DIVIDED_N : OUT std_logic; |
| OUT_CLK_LO_DIVIDED_P : OUT std_logic; |
| -- input data: |
| -- clock: |
| IN_CLK_FOR_DATA_P : IN std_logic; |
| IN_CLK_FOR_DATA_N : IN std_logic; |
| -- frame signal: |
| IN_FRAME_FOR_DATA_N : IN std_logic; |
| IN_FRAME_FOR_DATA_P : IN std_logic; |
| -- data from ADCs: |
| IN_DATA_ADC_P : IN std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS - 1 downto 0 ); |
| IN_DATA_ADC_N : IN std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS - 1 downto 0 ); |
| -- our LEDs: |
| GPIO_LED2 : OUT std_logic_vector(3 DOWNTO 0); |
| -- SPI communication block: |
| OUT_SPI_N_CE : OUT std_logic_vector( C_NUM_INPUT_ADC_MODULES-1 downto 0 ); |
| OUT_SPI_DOUT : OUT std_logic; |
| OUT_SPI_CLK : OUT std_logic; |
| -- test: |
| --OUT_TEST1 : OUT std_logic; |
| -- dummy inputs due to incorrect soldering -- pins are hardconnected to ground. |
| IN_DUMMY : IN std_logic_vector( 1 downto 0 ); |
| -- GPIO_DIP_SWITCH: |
| GPIO_DIP_SW : IN std_logic_vector( 7 downto 0 ); |
| -- original xillybus-only ports: |
| PCIE_PERST_B_LS : IN std_logic; |
| PCIE_REFCLK_N : IN std_logic; |
| PCIE_REFCLK_P : IN std_logic; |
| PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0); |
| PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0); |
| GPIO_LED : OUT std_logic_vector(3 DOWNTO 0); |
| PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0); |
| PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0)); |
| end xilly_toplevel; |
| architecture behavioral of xilly_toplevel is |
| component multiplexer_from_fifos |
| generic |
| ( G_NUM_CHANNELS : natural := 2; -- number of channels |
| G_DATA_WIDTH : natural := 32 -- data width of individual packets |
| ); |
| port ( |
| clk : in std_logic; |
| rst : in std_logic; |
| -- input side |
| i_data : in std_logic_vector( G_DATA_WIDTH*G_NUM_CHANNELS - 1 downto 0 ); |
| i_valid : in std_logic_vector( G_NUM_CHANNELS - 1 downto 0 ); |
| o_rden : out std_logic_vector( G_NUM_CHANNELS - 1 downto 0 ); |
| -- output side |
| o_data : out std_logic_vector( G_DATA_WIDTH - 1 downto 0 ); |
| o_valid : out std_logic; |
| i_full : in std_logic |
| ); |
| end component; |
| COMPONENT fifo_32x512_walmostfull |
| PORT ( |
| clk : IN STD_LOGIC; |
| srst : IN STD_LOGIC; |
| din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
| wr_en : IN STD_LOGIC; |
| rd_en : IN STD_LOGIC; |
| dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
| full : OUT STD_LOGIC; |
| empty : OUT STD_LOGIC; |
| valid : OUT STD_LOGIC; |
| prog_full : OUT STD_LOGIC |
| ); |
| END COMPONENT; |
| component bitslip_compensation |
| port ( |
| clk : in std_logic; |
| rst : in std_logic; |
| i_data : in std_logic_vector( 15 downto 0 ); |
| i_valid : in std_logic; |
| o_bitslip : out std_logic; |
| o_bitslip_done : out std_logic; |
| o_bitslip_drop_byte : out std_logic; |
| o_bitslip_failed : out std_logic |
| ); |
| end component; |
| component iserdes_clock_generator |
| port |
| ( |
| -- Clock and reset signals |
| CLK_IN_P : in std_logic; -- Differential fast clock from IOB |
| CLK_IN_N : in std_logic; |
| CLK_OUT : out std_logic; -- Fast clock output (synchronous to data) |
| CLK_DIV_OUT : out std_logic; -- Slow clock output |
| CLK_RESET : in std_logic); -- Reset signal for Clock circuit |
| end component; |
| component xillybus |
| port ( |
| PCIE_PERST_B_LS : IN std_logic; |
| PCIE_REFCLK_N : IN std_logic; |
| PCIE_REFCLK_P : IN std_logic; |
| PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0); |
| PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0); |
| GPIO_LED : OUT std_logic_vector(3 DOWNTO 0); |
| PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0); |
| PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0); |
| bus_clk : OUT std_logic; |
| quiesce : OUT std_logic; |
| user_r_control_r_rden : OUT std_logic; |
| user_r_control_r_empty : IN std_logic := '0'; |
| user_r_control_r_data : IN std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_r_control_r_eof : IN std_logic := '0'; |
| user_r_control_r_open : OUT std_logic; |
| user_w_control_w_wren : OUT std_logic; |
| user_w_control_w_full : IN std_logic := '0'; |
| user_w_control_w_data : OUT std_logic_vector(31 DOWNTO 0); |
| user_w_control_w_open : OUT std_logic; |
| user_r_data1_r_rden : OUT std_logic; |
| user_r_data1_r_empty : IN std_logic; |
| user_r_data1_r_data : IN std_logic_vector(31 DOWNTO 0); |
| user_r_data1_r_eof : IN std_logic; |
| user_r_data1_r_open : OUT std_logic; |
| user_w_data1_w_wren : OUT std_logic; |
| user_w_data1_w_full : IN std_logic; |
| user_w_data1_w_data : OUT std_logic_vector(31 DOWNTO 0); |
| user_w_data1_w_open : OUT std_logic; |
| user_r_data2_r_rden : OUT std_logic; |
| user_r_data2_r_empty : IN std_logic := '0'; |
| user_r_data2_r_data : IN std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_r_data2_r_eof : IN std_logic := '0'; |
| user_r_data2_r_open : OUT std_logic; |
| user_w_data2_w_wren : OUT std_logic; |
| user_w_data2_w_full : IN std_logic := '0'; |
| user_w_data2_w_data : OUT std_logic_vector(31 DOWNTO 0); |
| user_w_data2_w_open : OUT std_logic); |
| end component; |
| component xilly_userlogiccmp_wrapper |
| port ( |
| i_clk : in std_logic; |
| i_rst : in std_logic; |
| user_r_control_r_rden : in std_logic := '0'; |
| user_r_control_r_empty : out std_logic := '1'; |
| user_r_control_r_data : out std_logic_vector(31 DOWNTO 0); |
| user_w_control_w_wren : in std_logic := '0'; |
| user_w_control_w_full : out std_logic := '0'; |
| user_w_control_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_r_data1_r_rden : in std_logic := '0'; |
| user_r_data1_r_empty : out std_logic := '1'; |
| user_r_data1_r_data : out std_logic_vector(31 DOWNTO 0); |
| user_w_data1_w_wren : in std_logic := '0'; |
| user_w_data1_w_full : out std_logic := '0'; |
| user_w_data1_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
| user_r_data2_r_rden : in std_logic := '0'; |
| user_r_data2_r_empty : out std_logic := '1'; |
| user_r_data2_r_data : out std_logic_vector(31 DOWNTO 0); |
| user_w_data2_w_wren : in std_logic := '0'; |
| user_w_data2_w_full : out std_logic := '0'; |
| user_w_data2_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' ) |
| ); |
| end component; |
| signal bus_clk : std_logic; |
| signal quiesce : std_logic; |
| signal user_r_control_r_rden : std_logic; |
| signal user_r_control_r_empty : std_logic; |
| signal user_r_control_r_data : std_logic_vector(31 DOWNTO 0); |
| --signal user_r_control_r_eof : std_logic; |
| signal user_r_control_r_open : std_logic; |
| signal user_w_control_w_wren : std_logic; |
| signal user_w_control_w_full : std_logic; |
| signal user_w_control_w_data : std_logic_vector(31 DOWNTO 0); |
| signal user_w_control_w_open : std_logic; |
| signal user_r_data1_r_rden : std_logic; |
| signal user_r_data1_r_empty : std_logic; |
| signal user_r_data1_r_data : std_logic_vector(31 DOWNTO 0); |
| --signal user_r_data1_r_eof : std_logic; |
| signal user_r_data1_r_open : std_logic; |
| signal user_w_data1_w_wren : std_logic; |
| signal user_w_data1_w_full : std_logic; |
| signal user_w_data1_w_data : std_logic_vector(31 DOWNTO 0); |
| signal user_w_data1_w_open : std_logic; |
| signal user_r_data2_r_rden : std_logic; |
| signal user_r_data2_r_empty : std_logic; |
| signal user_r_data2_r_data : std_logic_vector(31 DOWNTO 0); |
| --signal user_r_data2_r_eof : std_logic; |
| signal user_r_data2_r_open : std_logic; |
| signal user_w_data2_w_wren : std_logic; |
| signal user_w_data2_w_full : std_logic; |
| signal user_w_data2_w_data : std_logic_vector(31 DOWNTO 0); |
| signal user_w_data2_w_open : std_logic; |
| -- reset signal from xillybus. '1' when no device is open |
| signal s_reset : std_logic; |
| -- generated clock from ADC by iserdes_clock_generator: |
| signal s_iserdes_clk : std_logic; |
| signal s_iserdes_clk_div : std_logic; |
| -- Frame signal |
| signal s_data16_to_bitslip : std_logic_vector( 15 downto 0 ); |
| signal s_data16_to_bitslip_valid : std_logic; |
| signal s_bitslip : std_logic; |
| signal s_bitslip_done : std_logic; |
| signal s_bitslip_drop_byte : std_logic; |
| signal s_bitslip_failed : std_logic; |
| signal s_bitslip_regged : std_logic; |
| signal s_bitslip_drop_byte_regged : std_logic; |
| -- from all ADC processing blocks: |
| signal s_from_processing_blocks_data : std_logic_vector( (C_NUM_INPUT_ADC_DATA_PORTS+1)*32 - 1 downto 0 ); -- +1 is space for output from frame |
| signal s_from_processing_blocks_valid : std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS+1 - 1 downto 0 ); |
| signal s_from_processing_blocks_rden : std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS+1 - 1 downto 0 ); |
| -- from multiplexer: |
| signal s_from_multiplexer_data : std_logic_vector( 31 downto 0 ); |
| signal s_from_multiplexer_valid : std_logic; |
| signal s_from_multiplexer_full : std_logic; |
| -- SPI communication module: |
| signal s_spi_done : std_logic; |
| -- GPIO_DIP_SW register |
| signal s_gpio_dip_sw : std_logic_vector( 7 downto 0 ); |
| signal s_valid_for_bitslip_processing : std_logic; |
| begin |
| -- Xillybus instantiation: |
| xillybus_ins : xillybus |
| port map ( |
| -- Ports related to /dev/xillybus_control_r |
| -- FPGA to CPU signals: |
| user_r_control_r_rden => user_r_control_r_rden, |
| user_r_control_r_empty => user_r_control_r_empty, |
| user_r_control_r_data => user_r_control_r_data, |
| user_r_control_r_eof => '0', |
| user_r_control_r_open => user_r_control_r_open, |
| -- Ports related to /dev/xillybus_control_w |
| -- CPU to FPGA signals: |
| user_w_control_w_wren => user_w_control_w_wren, |
| user_w_control_w_full => user_w_control_w_full, |
| user_w_control_w_data => user_w_control_w_data, |
| user_w_control_w_open => user_w_control_w_open, |
| -- Ports related to /dev/xillybus_data1_r |
| -- FPGA to CPU signals: |
| user_r_data1_r_rden => user_r_data1_r_rden, |
| user_r_data1_r_empty => user_r_data1_r_empty, |
| user_r_data1_r_data => user_r_data1_r_data, |
| user_r_data1_r_eof => '0', |
| user_r_data1_r_open => user_r_data1_r_open, |
| -- Ports related to /dev/xillybus_data1_w |
| -- CPU to FPGA signals: |
| user_w_data1_w_wren => user_w_data1_w_wren, |
| user_w_data1_w_full => user_w_data1_w_full, |
| user_w_data1_w_data => user_w_data1_w_data, |
| user_w_data1_w_open => user_w_data1_w_open, |
| -- Ports related to /dev/xillybus_data2_r |
| -- FPGA to CPU signals: |
| user_r_data2_r_rden => user_r_data2_r_rden, |
| user_r_data2_r_empty => user_r_data2_r_empty, |
| user_r_data2_r_data => user_r_data2_r_data, |
| user_r_data2_r_eof => '0', |
| user_r_data2_r_open => user_r_data2_r_open, |
| -- Ports related to /dev/xillybus_data2_w |
| -- CPU to FPGA signals: |
| user_w_data2_w_wren => user_w_data2_w_wren, |
| user_w_data2_w_full => user_w_data2_w_full, |
| user_w_data2_w_data => user_w_data2_w_data, |
| user_w_data2_w_open => user_w_data2_w_open, |
| -- General signals |
| PCIE_PERST_B_LS => PCIE_PERST_B_LS, |
| PCIE_REFCLK_N => PCIE_REFCLK_N, |
| PCIE_REFCLK_P => PCIE_REFCLK_P, |
| PCIE_RX_N => PCIE_RX_N, |
| PCIE_RX_P => PCIE_RX_P, |
| GPIO_LED => GPIO_LED, |
| PCIE_TX_N => PCIE_TX_N, |
| PCIE_TX_P => PCIE_TX_P, |
| bus_clk => bus_clk, |
| quiesce => quiesce |
| ); |
| s_reset <= '0' when user_r_control_r_open = '1' or |
| user_w_control_w_open = '1' or |
| user_r_data1_r_open = '1' or |
| user_w_data1_w_open = '1' or |
| user_r_data2_r_open = '1' or |
| user_w_data2_w_open = '1' or |
| s_gpio_dip_sw(0) = '0' else |
| '1'; |
| -- register the gpio_dip_sw(0) with the 125MHz clock: |
| registers_for_gpio0 : process( bus_clk ) |
| begin |
| if( rising_edge( bus_clk ) ) then |
| s_gpio_dip_sw(0) <= gpio_dip_sw(0); |
| s_gpio_dip_sw(2) <= gpio_dip_sw(2); -- used for SPI confifuration block that is clocked with bus_clk |
| end if; |
| end process; |
| -- register the gpio_dip_sw(1) with the clk_div clock: |
| registers_for_gpio1 : process( s_iserdes_clk_div ) |
| begin |
| if( rising_edge( s_iserdes_clk_div ) ) then |
| s_gpio_dip_sw(1) <= gpio_dip_sw(1); |
| end if; |
| end process; |
| -- xilly_userlogiccmp_wrapper instantiation: |
| xilly_userlogiccmp_wrapper_inst : xilly_userlogiccmp_wrapper |
| port map ( |
| i_clk => bus_clk, |
| i_rst => s_reset, |
| user_r_control_r_rden => user_r_control_r_rden, |
| user_r_control_r_empty => user_r_control_r_empty, |
| user_r_control_r_data => user_r_control_r_data, |
| user_w_control_w_wren => user_w_control_w_wren, |
| user_w_control_w_full => user_w_control_w_full, |
| user_w_control_w_data => user_w_control_w_data, |
| user_r_data1_r_rden => user_r_data1_r_rden, |
| user_r_data1_r_empty => user_r_data1_r_empty, |
| user_r_data1_r_data => user_r_data1_r_data, |
| user_w_data1_w_wren => user_w_data1_w_wren, |
| user_w_data1_w_full => user_w_data1_w_full, |
| user_w_data1_w_data => user_w_data1_w_data, |
| -- user_r_data2_r_rden => user_r_data2_r_rden, |
| -- user_r_data2_r_empty => user_r_data2_r_empty, |
| -- user_r_data2_r_data => user_r_data2_r_data, |
| -- user_w_data2_w_wren => user_w_data2_w_wren, |
| -- user_w_data2_w_full => user_w_data2_w_full, |
| -- user_w_data2_w_data => user_w_data2_w_data |
| user_r_data2_r_rden => open, |
| user_r_data2_r_empty => open, |
| user_r_data2_r_data => open, |
| user_w_data2_w_wren => open, |
| user_w_data2_w_full => open, |
| user_w_data2_w_data => open |
| ); |
| -- tie outputs: |
| --OUT_TEST1 <= '0'; |
| GPIO_LED2(0) <= s_bitslip_done; |
| GPIO_LED2(1) <= s_bitslip_failed; |
| GPIO_LED2(2) <= s_bitslip_drop_byte_regged; |
| GPIO_LED2(3) <= s_bitslip_regged; |
| ddd : process( s_iserdes_clk_div ) |
| begin |
| if( rising_edge( s_iserdes_clk_div ) ) then |
| if( s_reset = '1' ) then |
| s_bitslip_regged <= '0'; |
| s_bitslip_drop_byte_regged <= '0'; |
| else |
| s_bitslip_regged <= s_bitslip_regged or s_bitslip; |
| s_bitslip_drop_byte_regged <= s_bitslip_drop_byte_regged or s_bitslip_drop_byte; |
| end if; |
| end if; |
| end process; |
| ----------------------------------------------------------------------------------------------- |
| -- DATA PROCESSING: |
| -- Clock generator: |
| iserdes_clock_generator_inst : iserdes_clock_generator |
| port map ( |
| CLK_IN_P => IN_CLK_FOR_DATA_P, CLK_IN_N => IN_CLK_FOR_DATA_N, |
| CLK_OUT => s_iserdes_clk, CLK_DIV_OUT => s_iserdes_clk_div, CLK_RESET => '0' ); |
| -- FRAME signal processing block: |
| frame_processing_block_inst : entity work.processing_block |
| port map ( |
| clk_iserdes_in => s_iserdes_clk, clk_iserdes_in_div => s_iserdes_clk_div, clk_global => bus_clk, |
| rst => s_reset, |
| bitslip => s_bitslip, bitslip_done => s_bitslip_done, bitslip_drop_byte => s_bitslip_drop_byte, |
| in_data_p => IN_FRAME_FOR_DATA_P, in_data_n => IN_FRAME_FOR_DATA_N, |
| in_data_swap_pn => C_FRAME_WIRES_SWAPPED_PN, |
| in_output_counting => s_gpio_dip_sw(1), |
| o_iserdes_output => s_data16_to_bitslip, |
| o_iserdes_output_valid => s_data16_to_bitslip_valid, |
| o_data => s_from_processing_blocks_data( 31 downto 0 ), |
| o_valid => s_from_processing_blocks_valid( 0 ), |
| i_rden => s_from_processing_blocks_rden( 0 ) |
| ); |
| -- bitslip processing: |
| s_valid_for_bitslip_processing <= s_data16_to_bitslip_valid and s_spi_done; |
| bitslip_compensation_inst : bitslip_compensation |
| port map ( |
| clk => s_iserdes_clk_div, rst => s_reset, |
| i_data => s_data16_to_bitslip, i_valid => s_valid_for_bitslip_processing, |
| o_bitslip => s_bitslip, o_bitslip_done => s_bitslip_done, o_bitslip_drop_byte => s_bitslip_drop_byte, o_bitslip_failed => s_bitslip_failed ); |
| -- ADCs signal processing blocks: |
| adc_proc_block_gen : for i in 0 to C_NUM_INPUT_ADC_DATA_PORTS - 1 generate |
| adc_processing_block_inst : entity work.processing_block |
| port map ( |
| clk_iserdes_in => s_iserdes_clk, clk_iserdes_in_div => s_iserdes_clk_div, clk_global => bus_clk, |
| rst => s_reset, |
| bitslip => s_bitslip, bitslip_done => s_bitslip_done, bitslip_drop_byte => s_bitslip_drop_byte, |
| in_data_p => IN_DATA_ADC_P(i), in_data_n => IN_DATA_ADC_N(i), |
| in_data_swap_pn => C_DATA_WIRES_SWAPPED_PN(i), |
| in_output_counting => '0', |
| o_iserdes_output => open, o_iserdes_output_valid => open, |
| o_data => s_from_processing_blocks_data( 32*(i+1+1) - 1 downto 32*(i+1) ), -- i+1, because 31 downto 0 is used by the FRAME result |
| o_valid => s_from_processing_blocks_valid( i + 1 ), |
| i_rden => s_from_processing_blocks_rden( i + 1 ) |
| ); |
| end generate; |
| -- multiplexer: |
| multiplexer_from_fifos_inst : multiplexer_from_fifos |
| generic map ( |
| G_NUM_CHANNELS => C_NUM_INPUT_ADC_DATA_PORTS + 1, |
| G_DATA_WIDTH => 32 ) |
| port map ( |
| clk => bus_clk, rst => s_reset, |
| i_data => s_from_processing_blocks_data, i_valid => s_from_processing_blocks_valid, |
| o_rden => s_from_processing_blocks_rden, |
| o_data => s_from_multiplexer_data, o_valid => s_from_multiplexer_valid, i_full => s_from_multiplexer_full |
| ); |
| -- interface to xillybus: |
| -- FIFO_OUT instantiation: |
| data2_frame_fifo_out_inst : fifo_32x512_walmostfull |
| port map ( |
| clk => bus_clk, srst => s_reset, |
| din => s_from_multiplexer_data, wr_en => s_from_multiplexer_valid, full => open, prog_full => s_from_multiplexer_full, |
| dout => user_r_data2_r_data, rd_en => user_r_data2_r_rden, empty => user_r_data2_r_empty, valid => open ); |
| ----------------------------------------------------------------------------------------------- |
| -- LO - Local Oscillator division module: |
| -- TODO: not tested: addition of the CE input. Will the ADCs configure themselves without CLOCK? |
| lo_divider_wrapper_inst : entity work.lo_divider_wrapper |
| generic map ( G_DIVISOR => 30 ) |
| port map ( |
| IN_CLK_LO_N => IN_CLK_LO_N, IN_CLK_LO_P => IN_CLK_LO_P, in_clk_enable => '1', |
| OUT_CLK_LO_DIVIDED_N => OUT_CLK_LO_DIVIDED_N, OUT_CLK_LO_DIVIDED_P => OUT_CLK_LO_DIVIDED_P ); |
| ----------------------------------------------------------------------------------------------- |
| -- SPI MASTER COMMUNICATION MODULE |
| spi_transmitter_wrapper_inst : entity work.spi_transmitter_wrapper |
| generic map( |
| G_DATA1 => C_SPI_ADC_DATA1, |
| G_DATA2 => C_SPI_ADC_DATA2, |
| G_NUM_BITS_PACKET => C_SPI_ADC_LENGTH, |
| G_NUM_PACKETS => C_SPI_ADC_PACKETS, |
| G_NUM_BITS_PAUSE => C_SPI_ADC_PAUSE ) |
| port map( |
| i_clk125 => bus_clk, i_reset => s_reset, i_data_selector => s_gpio_dip_sw(2), |
| o_done => s_spi_done, |
| OUT_SPI_N_CE => OUT_SPI_N_CE, OUT_SPI_DOUT => OUT_SPI_DOUT, OUT_SPI_CLK => OUT_SPI_CLK ); |
| end architecture; |
| /Designs/HAM Constructions/SDRX02B/HDL/project_src/xillybus_ml605_kakona.ucf |
|---|
| 0,0 → 1,197 |
| CONFIG PART = xc6vlx240t-ff1156-1; |
| # The location constraints for REFCLK are implicitly given by the choice |
| # of the input buffer. |
| #NET "PCIE_REFCLK_P" LOC = V6; |
| #NET "PCIE_REFCLK_N" LOC = V5; |
| INST "*/pcieclk_ibuf" LOC = IBUFDS_GTXE1_X0Y4; |
| INST "*/pcie/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15; |
| INST "*/pcie/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX" LOC = GTXE1_X0Y14; |
| INST "*/pcie/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX" LOC = GTXE1_X0Y13; |
| INST "*/pcie/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX" LOC = GTXE1_X0Y12; |
| INST "*/pcie/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1; |
| INST "*/pcie/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7; |
| NET "PCIE_REFCLK_P" TNM_NET = "SYSCLK" ; |
| NET "*/pcie/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ; |
| NET "*/pcie/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG"; |
| TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 250 MHz HIGH 50 % PRIORITY 100 ; |
| TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK/2 HIGH 50 % PRIORITY 1 ; |
| TIMESPEC "TS_TXOUTCLKBUFG" = PERIOD "TXOUTCLKBUFG" 250 MHz HIGH 50 % PRIORITY 100 ; |
| PIN "*/pcie/trn_reset_n_int_i.CLR" TIG ; |
| PIN "*/pcie/trn_reset_n_i.CLR" TIG ; |
| PIN "*/pcie/pcie_clocking_i/mmcm_adv_i.RST" TIG ; |
| NET "PCIE_PERST_B_LS" TIG; |
| NET "PCIE_PERST_B_LS" LOC = AE13 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ; |
| NET "GPIO_LED[0]" LOC = "AC22"; # DS12 |
| NET "GPIO_LED[1]" LOC = "AC24"; # DS11 |
| NET "GPIO_LED[2]" LOC = "AE22"; # DS9 |
| NET "GPIO_LED[3]" LOC = "AE23"; # DS10 |
| ################################################################# |
| ############## SYCHRO1 |
| # Incoming clock to be divided: |
| NET "IN_CLK_LO_N" LOC = "B10"; ## H5 on J63 FMC_LPC_CLK0_M2C_N |
| NET "IN_CLK_LO_P" LOC = "A10"; ## H4 on J63 FMC_LPC_CLK0_M2C_P |
| # Timing for that: |
| NET "IN_CLK_LO_P" TNM_NET = "LOCLK"; |
| TIMESPEC "TS_LOCLK" = PERIOD "LOCLK" 300 MHz HIGH 50% PRIORITY 50; |
| # Divided clock: |
| NET "OUT_CLK_LO_DIVIDED_N" LOC = "E31"; ## D9 on J63 FMC_LPC_LA01_CC_N |
| NET "OUT_CLK_LO_DIVIDED_P" LOC = "F31"; ## D8 on J63 FMC_LPC_LA01_CC_P |
| #nejde NET "OUT_CLK_LO_DIVIDED_N" LOC = "M5"; ## D5 on J63 "FMC_LPC_GBTCLK0_M2C_N" |
| #nejde NET "OUT_CLK_LO_DIVIDED_P" LOC = "M6"; ## D4 on J63 "FMC_LPC_GBTCLK0_M2C_P" |
| ################################## |
| # INCOMING DATA FROM ADCs |
| # Incoming clock synchronous to incoming data: |
| NET "IN_CLK_FOR_DATA_N" LOC = "G33"; ## G3 on J63 FMC_LPC_CLK1_M2C_N |
| NET "IN_CLK_FOR_DATA_P" LOC = "F33"; ## G2 on J63 FMC_LPC_CLK1_M2C_P |
| # Timing for that: |
| NET "IN_CLK_FOR_DATA_P" TNM_NET = "ADCDATACLK"; |
| #TIMESPEC "TS_ADCDATACLK" = PERIOD "ADCDATACLK" 40 MHz HIGH 50% PRIORITY 50; |
| TIMESPEC "TS_ADCDATACLK" = PERIOD "ADCDATACLK" 80 MHz HIGH 50% PRIORITY 50; # freq to ADC is 10MHz |
| # Incoming frame signal: |
| NET "IN_FRAME_FOR_DATA_N" LOC = "L30"; ## C23 on J63 FMC_LPC_LA18_CC_N |
| NET "IN_FRAME_FOR_DATA_P" LOC = "L29"; ## C22 on J63 FMC_LPC_LA18_CC_P |
| # Incoming data signal: |
| NET "IN_DATA_ADC_N[0]" LOC = "B33"; ## G19 on J63 FMC_LPC_LA16_N SAS-P2_0_N |
| NET "IN_DATA_ADC_P[0]" LOC = "A33"; ## G18 on J63 FMC_LPC_LA16_P SAS-P2_0_P |
| NET "IN_DATA_ADC_N[1]" LOC = "D32"; ## H17 on J63 FMC_LPC_LA11_N SAS-P2_1_N |
| NET "IN_DATA_ADC_P[1]" LOC = "D31"; ## H16 on J63 FMC_LPC_LA11_P SAS-P2_1_P |
| NET "IN_DATA_ADC_N[2]" LOC = "N29"; ## D21 on J63 FMC_LPC_LA17_CC_N SAS-P3_0_N |
| NET "IN_DATA_ADC_P[2]" LOC = "N28"; ## D20 on J63 FMC_LPC_LA17_CC_P SAS-P3_0_P |
| NET "IN_DATA_ADC_N[3]" LOC = "B32"; ## H20 on J63 FMC_LPC_LA15_N SAS-P3_1_N |
| NET "IN_DATA_ADC_P[3]" LOC = "C32"; ## H19 on J63 FMC_LPC_LA15_P SAS-P3_1_P |
| # MiniSAS channels P0 and P1 |
| #NET "IN_DATA_ADC_N[0]" LOC = "J32"; ## G10 on J63 FMC_LPC_LA03_N SAS-P0_0_N |
| #NET "IN_DATA_ADC_P[0]" LOC = "J31"; ## G9 on J63 FMC_LPC_LA03_P SAS-P0_0_P |
| #NET "IN_DATA_ADC_N[1]" LOC = "J29"; ## H11 on J63 FMC_LPC_LA04_N SAS-P0_1_N |
| #NET "IN_DATA_ADC_P[1]" LOC = "K28"; ## H10 on J63 FMC_LPC_LA04_P SAS-P0_1_P |
| #NET "IN_DATA_ADC_N[2]" LOC = "K29"; ## G13 on J63 FMC_LPC_LA08_N SAS-P1_0_N |
| #NET "IN_DATA_ADC_P[2]" LOC = "J30"; ## G12 on J63 FMC_LPC_LA08_P SAS-P1_0_P |
| #NET "IN_DATA_ADC_N[3]" LOC = "H32"; ## H14 on J63 FMC_LPC_LA07_N SAS-P1_1_N |
| #NET "IN_DATA_ADC_P[3]" LOC = "G32"; ## H13 on J63 FMC_LPC_LA07_P SAS-P1_1_P |
| #NET "IN_DATA_ADC_N[0]" LOC = "R27"; ## D24 on J63 FMC_LPC_LA23_N |
| #NET "IN_DATA_ADC_P[0]" LOC = "R28"; ## D23 on J63 FMC_LPC_LA23_P |
| #NET "IN_DATA_ADC_N[1]" LOC = "M32"; ## D27 on J63 FMC_LPC_LA26_N |
| #NET "IN_DATA_ADC_P[1]" LOC = "L33"; ## D26 on J63 FMC_LPC_LA26_P |
| #NET "IN_DATA_ADC_N[2]" LOC = "J29"; ## H11 on J63 "FMC_LPC_LA04_N" |
| #NET "IN_DATA_ADC_P[2]" LOC = "K28"; ## H10 on J63 "FMC_LPC_LA04_P" |
| #NET "IN_DATA_ADC_N[3]" LOC = "H33"; ## D12 on J63 "FMC_LPC_LA05_N" |
| #NET "IN_DATA_ADC_P[3]" LOC = "H34"; ## D11 on J63 "FMC_LPC_LA05_P" |
| #NET "IN_DATA_ADC_N[4]" LOC = "J34"; ## C11 on J63 "FMC_LPC_LA06_N" |
| #NET "IN_DATA_ADC_P[4]" LOC = "K33"; ## C10 on J63 "FMC_LPC_LA06_P" |
| #NET "IN_DATA_ADC_N[5]" LOC = "H32"; ## H14 on J63 "FMC_LPC_LA07_N" |
| #NET "IN_DATA_ADC_P[5]" LOC = "G32"; ## H13 on J63 "FMC_LPC_LA07_P" |
| #NET "IN_DATA_ADC_N[6]" LOC = "K29"; ## G13 on J63 "FMC_LPC_LA08_N" |
| #NET "IN_DATA_ADC_P[6]" LOC = "J30"; ## G12 on J63 "FMC_LPC_LA08_P" |
| #NET "IN_DATA_ADC_N[7]" LOC = "L26"; ## D15 on J63 "FMC_LPC_LA09_N" |
| #NET "IN_DATA_ADC_P[7]" LOC = "L25"; ## D14 on J63 "FMC_LPC_LA09_P" |
| #NET "IN_DATA_ADC_N[8]" LOC = "G30"; ## C15 on J63 "FMC_LPC_LA10_N" |
| #NET "IN_DATA_ADC_P[8]" LOC = "F30"; ## C14 on J63 "FMC_LPC_LA10_P" |
| #NET "IN_DATA_ADC_N[9]" LOC = "D32"; ## H17 on J63 "FMC_LPC_LA11_N" |
| #NET "IN_DATA_ADC_P[9]" LOC = "D31"; ## H16 on J63 "FMC_LPC_LA11_P" |
| #NET "IN_DATA_ADC_N[10]" LOC = "E33"; ## G16 on J63 "FMC_LPC_LA12_N" |
| #NET "IN_DATA_ADC_P[10]" LOC = "E32"; ## G15 on J63 "FMC_LPC_LA12_P" |
| #NET "IN_DATA_ADC_N[11]" LOC = "C34"; ## D18 on J63 "FMC_LPC_LA13_N" |
| #NET "IN_DATA_ADC_P[11]" LOC = "D34"; ## D17 on J63 "FMC_LPC_LA13_P" |
| #NET "IN_DATA_ADC_N[12]" LOC = "B34"; ## C19 on J63 "FMC_LPC_LA14_N" |
| #NET "IN_DATA_ADC_P[12]" LOC = "C33"; ## C18 on J63 "FMC_LPC_LA14_P" |
| #NET "IN_DATA_ADC_N[13]" LOC = "B32"; ## H20 on J63 "FMC_LPC_LA15_N" |
| #NET "IN_DATA_ADC_P[13]" LOC = "C32"; ## H19 on J63 "FMC_LPC_LA15_P" |
| #NET "IN_DATA_ADC_N[14]" LOC = "B33"; ## G19 on J63 "FMC_LPC_LA16_N" |
| #NET "IN_DATA_ADC_P[14]" LOC = "A33"; ## G18 on J63 "FMC_LPC_LA16_P" |
| #NET "IN_DATA_ADC_N[15]" LOC = "N29"; ## D21 on J63 "FMC_LPC_LA17_CC_N" |
| #NET "IN_DATA_ADC_P[15]" LOC = "N28"; ## D20 on J63 "FMC_LPC_LA17_CC_P" |
| ########################################################## |
| # four other LEDs: |
| NET "GPIO_LED2[0]" LOC = "AB23"; ## 2 on LED DS15, 5 on J62 |
| NET "GPIO_LED2[1]" LOC = "AG23"; ## 2 on LED DS14, 6 on J62 |
| NET "GPIO_LED2[2]" LOC = "AE24"; ## 2 on LED DS22, 7 on J62 |
| NET "GPIO_LED2[3]" LOC = "AD24"; ## 2 on LED DS21, 8 on J62 |
| ########################################################## |
| ## SAS-interface AUX 1 ~ 8 |
| #NET "SAS-AUX[1]" LOC = "B34"; ## C19 on J63 FMC_LPC_LA14_N |
| #NET "SAS-AUX[2]" LOC = "C33"; ## C18 on J63 FMC_LPC_LA14_P |
| #NET "SAS-AUX[3]" LOC = "E33"; ## G16 on J63 FMC_LPC_LA12_N |
| #NET "SAS-AUX[4]" LOC = "E32"; ## G15 on J63 FMC_LPC_LA12_P |
| #NET "SAS-AUX[5]" LOC = "C34"; ## D18 on J63 FMC_LPC_LA13_N ## SOLDERED TO GND |
| #NET "SAS-AUX[6]" LOC = "D34"; ## D17 on J63 FMC_LPC_LA13_P |
| #NET "SAS-AUX[7]" LOC = "L26"; ## D15 on J63 FMC_LPC_LA09_N |
| #NET "SAS-AUX[8]" LOC = "L25"; ## D14 on J63 FMC_LPC_LA09_P ## SOLDERED TO GND |
| ## SAS-interface LVDS lines: |
| #NET "SAS-P0_0_N" LOC = "J32"; ## G10 on J63 FMC_LPC_LA03_N SAS-P0_0_N |
| #NET "SAS-P0_0_P" LOC = "J31"; ## G9 on J63 FMC_LPC_LA03_P SAS-P0_0_P |
| #NET "SAS-P0_1_N" LOC = "J29"; ## H11 on J63 FMC_LPC_LA04_N SAS-P0_1_N |
| #NET "SAS-P0_1_P" LOC = "K28"; ## H10 on J63 FMC_LPC_LA04_P SAS-P0_1_P |
| #NET "SAS-P1_0_N" LOC = "K29"; ## G13 on J63 FMC_LPC_LA08_N SAS-P1_0_N |
| #NET "SAS-P1_0_P" LOC = "J30"; ## G12 on J63 FMC_LPC_LA08_P SAS-P1_0_P |
| #NET "SAS-P1_1_N" LOC = "H32"; ## H14 on J63 FMC_LPC_LA07_N SAS-P1_1_N |
| #NET "SAS-P1_1_P" LOC = "G32"; ## H13 on J63 FMC_LPC_LA07_P SAS-P1_1_P |
| #NET "SAS-P2_0_N" LOC = "B33"; ## G19 on J63 FMC_LPC_LA16_N SAS-P2_0_N |
| #NET "SAS-P2_0_P" LOC = "A33"; ## G18 on J63 FMC_LPC_LA16_P SAS-P2_0_P |
| #NET "SAS-P2_1_N" LOC = "D32"; ## H17 on J63 FMC_LPC_LA11_N SAS-P2_1_N |
| #NET "SAS-P2_1_P" LOC = "D31"; ## H16 on J63 FMC_LPC_LA11_P SAS-P2_1_P |
| #NET "SAS-P3_0_N" LOC = "N29"; ## D21 on J63 FMC_LPC_LA17_CC_N SAS-P3_0_N |
| #NET "SAS-P3_0_P" LOC = "N28"; ## D20 on J63 FMC_LPC_LA17_CC_P SAS-P3_0_P |
| #NET "SAS-P3_1_N" LOC = "B32"; ## H20 on J63 FMC_LPC_LA15_N SAS-P3_1_N |
| #NET "SAS-P3_1_P" LOC = "C32"; ## H19 on J63 FMC_LPC_LA15_P SAS-P3_1_P |
| ########################################################## |
| # SPI interface: |
| NET "OUT_SPI_DOUT" LOC = "B34" | SLEW = SLOW | DRIVE = 2; ## C19 on J63 FMC_LPC_LA14_N SAS-AUX[1] |
| NET "OUT_SPI_CLK" LOC = "C33" | SLEW = SLOW | DRIVE = 2; ## C18 on J63 FMC_LPC_LA14_P SAS-AUX[2] |
| NET "OUT_SPI_N_CE[0]" LOC = "E33" | SLEW = SLOW | DRIVE = 2; ## G16 on J63 FMC_LPC_LA12_N SAS-AUX[3] |
| NET "OUT_SPI_N_CE[1]" LOC = "E32" | SLEW = SLOW | DRIVE = 2; ## G15 on J63 FMC_LPC_LA12_P SAS-AUX[4] |
| # Locate the BUFR near the output pins so that the timing can be reached. |
| INST "spi_transmitter_wrapper_inst/BUFR_inst" LOC = BUFR_X0Y8; |
| # test: |
| #NET "OUT_TEST1" LOC = "E32" | SLEW = FAST; ## G15 on J63 FMC_LPC_LA12_P |
| # DUMMY hard-connected to ground. |
| NET "IN_DUMMY[0]" LOC = "C34"; ## D18 on J63 FMC_LPC_LA13_N ## SOLDERED TO GND |
| NET "IN_DUMMY[1]" LOC = "L25"; ## D14 on J63 FMC_LPC_LA09_P ## SOLDERED TO GND |
| ############################################### |
| # DIP switch |
| NET "GPIO_DIP_SW<0>" LOC = "D22"; ## 1 on SW1 DIP switch (active-high) |
| NET "GPIO_DIP_SW<1>" LOC = "C22"; ## 2 on SW1 DIP switch (active-high) |
| NET "GPIO_DIP_SW<2>" LOC = "L21"; ## 3 on SW1 DIP switch (active-high) |
| NET "GPIO_DIP_SW<3>" LOC = "L20"; ## 4 on SW1 DIP switch (active-high) |
| NET "GPIO_DIP_SW<4>" LOC = "C18"; ## 5 on SW1 DIP switch (active-high) |
| NET "GPIO_DIP_SW<5>" LOC = "B18"; ## 6 on SW1 DIP switch (active-high) |
| NET "GPIO_DIP_SW<6>" LOC = "K22"; ## 7 on SW1 DIP switch (active-high) |
| NET "GPIO_DIP_SW<7>" LOC = "K21"; ## 8 on SW1 DIP switch (active-high) |