| /Designs/HAM_Constructions/SDRX02A/HDL/modules/core_generator_ml605/clk_125MHz_to_6MHz.xco |
|---|
| 0,0 → 1,269 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue May 6 10:43:16 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:clk_wiz:3.6 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 |
| # END Select |
| # BEGIN Parameters |
| CSET calc_done=DONE |
| CSET clk_in_sel_port=CLK_IN_SEL |
| CSET clk_out1_port=CLK_OUT_6 |
| CSET clk_out1_use_fine_ps_gui=false |
| CSET clk_out2_port=CLK_OUT2 |
| CSET clk_out2_use_fine_ps_gui=false |
| CSET clk_out3_port=CLK_OUT3 |
| CSET clk_out3_use_fine_ps_gui=false |
| CSET clk_out4_port=CLK_OUT4 |
| CSET clk_out4_use_fine_ps_gui=false |
| CSET clk_out5_port=CLK_OUT5 |
| CSET clk_out5_use_fine_ps_gui=false |
| CSET clk_out6_port=CLK_OUT6 |
| CSET clk_out6_use_fine_ps_gui=false |
| CSET clk_out7_port=CLK_OUT7 |
| CSET clk_out7_use_fine_ps_gui=false |
| CSET clk_valid_port=CLK_VALID |
| CSET clkfb_in_n_port=CLKFB_IN_N |
| CSET clkfb_in_p_port=CLKFB_IN_P |
| CSET clkfb_in_port=CLKFB_IN |
| CSET clkfb_in_signaling=SINGLE |
| CSET clkfb_out_n_port=CLKFB_OUT_N |
| CSET clkfb_out_p_port=CLKFB_OUT_P |
| CSET clkfb_out_port=CLKFB_OUT |
| CSET clkfb_stopped_port=CLKFB_STOPPED |
| CSET clkin1_jitter_ps=80.0 |
| CSET clkin1_ui_jitter=0.010 |
| CSET clkin2_jitter_ps=100.0 |
| CSET clkin2_ui_jitter=0.010 |
| CSET clkout1_drives=BUFG |
| CSET clkout1_requested_duty_cycle=50.000 |
| CSET clkout1_requested_out_freq=100.000 |
| CSET clkout1_requested_phase=0.000 |
| CSET clkout2_drives=BUFG |
| CSET clkout2_requested_duty_cycle=50.000 |
| CSET clkout2_requested_out_freq=100.000 |
| CSET clkout2_requested_phase=0.000 |
| CSET clkout2_used=false |
| CSET clkout3_drives=BUFG |
| CSET clkout3_requested_duty_cycle=50.000 |
| CSET clkout3_requested_out_freq=100.000 |
| CSET clkout3_requested_phase=0.000 |
| CSET clkout3_used=false |
| CSET clkout4_drives=BUFG |
| CSET clkout4_requested_duty_cycle=50.000 |
| CSET clkout4_requested_out_freq=100.000 |
| CSET clkout4_requested_phase=0.000 |
| CSET clkout4_used=false |
| CSET clkout5_drives=BUFG |
| CSET clkout5_requested_duty_cycle=50.000 |
| CSET clkout5_requested_out_freq=100.000 |
| CSET clkout5_requested_phase=0.000 |
| CSET clkout5_used=false |
| CSET clkout6_drives=BUFG |
| CSET clkout6_requested_duty_cycle=50.000 |
| CSET clkout6_requested_out_freq=100.000 |
| CSET clkout6_requested_phase=0.000 |
| CSET clkout6_used=false |
| CSET clkout7_drives=BUFG |
| CSET clkout7_requested_duty_cycle=50.000 |
| CSET clkout7_requested_out_freq=100.000 |
| CSET clkout7_requested_phase=0.000 |
| CSET clkout7_used=false |
| CSET clock_mgr_type=MANUAL |
| CSET component_name=clk_125MHz_to_6MHz |
| CSET daddr_port=DADDR |
| CSET dclk_port=DCLK |
| CSET dcm_clk_feedback=1X |
| CSET dcm_clk_out1_port=CLK0 |
| CSET dcm_clk_out2_port=CLK0 |
| CSET dcm_clk_out3_port=CLK0 |
| CSET dcm_clk_out4_port=CLK0 |
| CSET dcm_clk_out5_port=CLK0 |
| CSET dcm_clk_out6_port=CLK0 |
| CSET dcm_clkdv_divide=2.0 |
| CSET dcm_clkfx_divide=1 |
| CSET dcm_clkfx_multiply=4 |
| CSET dcm_clkgen_clk_out1_port=CLKFX |
| CSET dcm_clkgen_clk_out2_port=CLKFX |
| CSET dcm_clkgen_clk_out3_port=CLKFX |
| CSET dcm_clkgen_clkfx_divide=1 |
| CSET dcm_clkgen_clkfx_md_max=0.000 |
| CSET dcm_clkgen_clkfx_multiply=4 |
| CSET dcm_clkgen_clkfxdv_divide=2 |
| CSET dcm_clkgen_clkin_period=10.000 |
| CSET dcm_clkgen_notes=None |
| CSET dcm_clkgen_spread_spectrum=NONE |
| CSET dcm_clkgen_startup_wait=false |
| CSET dcm_clkin_divide_by_2=false |
| CSET dcm_clkin_period=10.000 |
| CSET dcm_clkout_phase_shift=NONE |
| CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS |
| CSET dcm_notes=None |
| CSET dcm_phase_shift=0 |
| CSET dcm_pll_cascade=NONE |
| CSET dcm_startup_wait=false |
| CSET den_port=DEN |
| CSET din_port=DIN |
| CSET dout_port=DOUT |
| CSET drdy_port=DRDY |
| CSET dwe_port=DWE |
| CSET feedback_source=FDBK_AUTO |
| CSET in_freq_units=Units_MHz |
| CSET in_jitter_units=Units_UI |
| CSET input_clk_stopped_port=INPUT_CLK_STOPPED |
| CSET jitter_options=UI |
| CSET jitter_sel=No_Jitter |
| CSET locked_port=LOCKED |
| CSET mmcm_bandwidth=OPTIMIZED |
| CSET mmcm_clkfbout_mult_f=6.000 |
| CSET mmcm_clkfbout_phase=0.000 |
| CSET mmcm_clkfbout_use_fine_ps=false |
| CSET mmcm_clkin1_period=8.000 |
| CSET mmcm_clkin2_period=10.0 |
| CSET mmcm_clkout0_divide_f=125.000 |
| CSET mmcm_clkout0_duty_cycle=0.500 |
| CSET mmcm_clkout0_phase=0.000 |
| CSET mmcm_clkout0_use_fine_ps=false |
| CSET mmcm_clkout1_divide=1 |
| CSET mmcm_clkout1_duty_cycle=0.500 |
| CSET mmcm_clkout1_phase=0.000 |
| CSET mmcm_clkout1_use_fine_ps=false |
| CSET mmcm_clkout2_divide=1 |
| CSET mmcm_clkout2_duty_cycle=0.500 |
| CSET mmcm_clkout2_phase=0.000 |
| CSET mmcm_clkout2_use_fine_ps=false |
| CSET mmcm_clkout3_divide=1 |
| CSET mmcm_clkout3_duty_cycle=0.500 |
| CSET mmcm_clkout3_phase=0.000 |
| CSET mmcm_clkout3_use_fine_ps=false |
| CSET mmcm_clkout4_cascade=false |
| CSET mmcm_clkout4_divide=1 |
| CSET mmcm_clkout4_duty_cycle=0.500 |
| CSET mmcm_clkout4_phase=0.000 |
| CSET mmcm_clkout4_use_fine_ps=false |
| CSET mmcm_clkout5_divide=1 |
| CSET mmcm_clkout5_duty_cycle=0.500 |
| CSET mmcm_clkout5_phase=0.000 |
| CSET mmcm_clkout5_use_fine_ps=false |
| CSET mmcm_clkout6_divide=1 |
| CSET mmcm_clkout6_duty_cycle=0.500 |
| CSET mmcm_clkout6_phase=0.000 |
| CSET mmcm_clkout6_use_fine_ps=false |
| CSET mmcm_clock_hold=false |
| CSET mmcm_compensation=ZHOLD |
| CSET mmcm_divclk_divide=1 |
| CSET mmcm_notes=None |
| CSET mmcm_ref_jitter1=0.010 |
| CSET mmcm_ref_jitter2=0.010 |
| CSET mmcm_startup_wait=false |
| CSET num_out_clks=1 |
| CSET override_dcm=false |
| CSET override_dcm_clkgen=false |
| CSET override_mmcm=false |
| CSET override_pll=false |
| CSET platform=lin64 |
| CSET pll_bandwidth=OPTIMIZED |
| CSET pll_clk_feedback=CLKFBOUT |
| CSET pll_clkfbout_mult=4 |
| CSET pll_clkfbout_phase=0.000 |
| CSET pll_clkin_period=10.000 |
| CSET pll_clkout0_divide=1 |
| CSET pll_clkout0_duty_cycle=0.500 |
| CSET pll_clkout0_phase=0.000 |
| CSET pll_clkout1_divide=1 |
| CSET pll_clkout1_duty_cycle=0.500 |
| CSET pll_clkout1_phase=0.000 |
| CSET pll_clkout2_divide=1 |
| CSET pll_clkout2_duty_cycle=0.500 |
| CSET pll_clkout2_phase=0.000 |
| CSET pll_clkout3_divide=1 |
| CSET pll_clkout3_duty_cycle=0.500 |
| CSET pll_clkout3_phase=0.000 |
| CSET pll_clkout4_divide=1 |
| CSET pll_clkout4_duty_cycle=0.500 |
| CSET pll_clkout4_phase=0.000 |
| CSET pll_clkout5_divide=1 |
| CSET pll_clkout5_duty_cycle=0.500 |
| CSET pll_clkout5_phase=0.000 |
| CSET pll_compensation=SYSTEM_SYNCHRONOUS |
| CSET pll_divclk_divide=1 |
| CSET pll_notes=None |
| CSET pll_ref_jitter=0.010 |
| CSET power_down_port=POWER_DOWN |
| CSET prim_in_freq=125 |
| CSET prim_in_jitter=0.010 |
| CSET prim_source=Global_buffer |
| CSET primary_port=CLK_IN_125 |
| CSET primitive=MMCM |
| CSET primtype_sel=MMCM_ADV |
| CSET psclk_port=PSCLK |
| CSET psdone_port=PSDONE |
| CSET psen_port=PSEN |
| CSET psincdec_port=PSINCDEC |
| CSET relative_inclk=REL_PRIMARY |
| CSET reset_port=RESET |
| CSET secondary_in_freq=100.000 |
| CSET secondary_in_jitter=0.010 |
| CSET secondary_port=CLK_IN2 |
| CSET secondary_source=Single_ended_clock_capable_pin |
| CSET ss_mod_freq=250 |
| CSET ss_mode=CENTER_HIGH |
| CSET status_port=STATUS |
| CSET summary_strings=empty |
| CSET use_clk_valid=false |
| CSET use_clkfb_stopped=false |
| CSET use_dyn_phase_shift=false |
| CSET use_dyn_reconfig=false |
| CSET use_freeze=false |
| CSET use_freq_synth=true |
| CSET use_inclk_stopped=false |
| CSET use_inclk_switchover=false |
| CSET use_locked=false |
| CSET use_max_i_jitter=false |
| CSET use_min_o_jitter=false |
| CSET use_min_power=false |
| CSET use_phase_alignment=true |
| CSET use_power_down=false |
| CSET use_reset=false |
| CSET use_spread_spectrum=false |
| CSET use_spread_spectrum_1=false |
| CSET use_status=false |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-05-10T12:44:55Z |
| # END Extra information |
| GENERATE |
| # CRC: 255c3699 |
| /Designs/HAM_Constructions/SDRX02A/HDL/modules/core_generator_ml605/fifo_32x512.xco |
|---|
| 0,0 → 1,213 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue Apr 29 09:14:51 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:fifo_generator:9.2 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT Fifo_Generator xilinx.com:ip:fifo_generator:9.2 |
| # END Select |
| # BEGIN Parameters |
| CSET add_ngc_constraint_axi=false |
| CSET almost_empty_flag=false |
| CSET almost_full_flag=false |
| CSET aruser_width=1 |
| CSET awuser_width=1 |
| CSET axi_address_width=32 |
| CSET axi_data_width=64 |
| CSET axi_type=AXI4_Stream |
| CSET axis_type=FIFO |
| CSET buser_width=1 |
| CSET clock_enable_type=Slave_Interface_Clock_Enable |
| CSET clock_type_axi=Common_Clock |
| CSET component_name=fifo_32x512 |
| CSET data_count=false |
| CSET data_count_width=9 |
| CSET disable_timing_violations=false |
| CSET disable_timing_violations_axi=false |
| CSET dout_reset_value=0 |
| CSET empty_threshold_assert_value=2 |
| CSET empty_threshold_assert_value_axis=1022 |
| CSET empty_threshold_assert_value_rach=1022 |
| CSET empty_threshold_assert_value_rdch=1022 |
| CSET empty_threshold_assert_value_wach=1022 |
| CSET empty_threshold_assert_value_wdch=1022 |
| CSET empty_threshold_assert_value_wrch=1022 |
| CSET empty_threshold_negate_value=3 |
| CSET enable_aruser=false |
| CSET enable_awuser=false |
| CSET enable_buser=false |
| CSET enable_common_overflow=false |
| CSET enable_common_underflow=false |
| CSET enable_data_counts_axis=false |
| CSET enable_data_counts_rach=false |
| CSET enable_data_counts_rdch=false |
| CSET enable_data_counts_wach=false |
| CSET enable_data_counts_wdch=false |
| CSET enable_data_counts_wrch=false |
| CSET enable_ecc=false |
| CSET enable_ecc_axis=false |
| CSET enable_ecc_rach=false |
| CSET enable_ecc_rdch=false |
| CSET enable_ecc_wach=false |
| CSET enable_ecc_wdch=false |
| CSET enable_ecc_wrch=false |
| CSET enable_read_channel=false |
| CSET enable_read_pointer_increment_by2=false |
| CSET enable_reset_synchronization=true |
| CSET enable_ruser=false |
| CSET enable_tdata=false |
| CSET enable_tdest=false |
| CSET enable_tid=false |
| CSET enable_tkeep=false |
| CSET enable_tlast=false |
| CSET enable_tready=true |
| CSET enable_tstrobe=false |
| CSET enable_tuser=false |
| CSET enable_write_channel=false |
| CSET enable_wuser=false |
| CSET fifo_application_type_axis=Data_FIFO |
| CSET fifo_application_type_rach=Data_FIFO |
| CSET fifo_application_type_rdch=Data_FIFO |
| CSET fifo_application_type_wach=Data_FIFO |
| CSET fifo_application_type_wdch=Data_FIFO |
| CSET fifo_application_type_wrch=Data_FIFO |
| CSET fifo_implementation=Common_Clock_Block_RAM |
| CSET fifo_implementation_axis=Common_Clock_Block_RAM |
| CSET fifo_implementation_rach=Common_Clock_Block_RAM |
| CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wach=Common_Clock_Block_RAM |
| CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
| CSET full_flags_reset_value=0 |
| CSET full_threshold_assert_value=510 |
| CSET full_threshold_assert_value_axis=1023 |
| CSET full_threshold_assert_value_rach=1023 |
| CSET full_threshold_assert_value_rdch=1023 |
| CSET full_threshold_assert_value_wach=1023 |
| CSET full_threshold_assert_value_wdch=1023 |
| CSET full_threshold_assert_value_wrch=1023 |
| CSET full_threshold_negate_value=509 |
| CSET id_width=4 |
| CSET inject_dbit_error=false |
| CSET inject_dbit_error_axis=false |
| CSET inject_dbit_error_rach=false |
| CSET inject_dbit_error_rdch=false |
| CSET inject_dbit_error_wach=false |
| CSET inject_dbit_error_wdch=false |
| CSET inject_dbit_error_wrch=false |
| CSET inject_sbit_error=false |
| CSET inject_sbit_error_axis=false |
| CSET inject_sbit_error_rach=false |
| CSET inject_sbit_error_rdch=false |
| CSET inject_sbit_error_wach=false |
| CSET inject_sbit_error_wdch=false |
| CSET inject_sbit_error_wrch=false |
| CSET input_data_width=32 |
| CSET input_depth=512 |
| CSET input_depth_axis=1024 |
| CSET input_depth_rach=16 |
| CSET input_depth_rdch=1024 |
| CSET input_depth_wach=16 |
| CSET input_depth_wdch=1024 |
| CSET input_depth_wrch=16 |
| CSET interface_type=Native |
| CSET output_data_width=32 |
| CSET output_depth=512 |
| CSET overflow_flag=false |
| CSET overflow_flag_axi=false |
| CSET overflow_sense=Active_High |
| CSET overflow_sense_axi=Active_High |
| CSET performance_options=Standard_FIFO |
| CSET programmable_empty_type=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
| CSET programmable_full_type=No_Programmable_Full_Threshold |
| CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
| CSET rach_type=FIFO |
| CSET rdch_type=FIFO |
| CSET read_clock_frequency=1 |
| CSET read_data_count=false |
| CSET read_data_count_width=9 |
| CSET register_slice_mode_axis=Fully_Registered |
| CSET register_slice_mode_rach=Fully_Registered |
| CSET register_slice_mode_rdch=Fully_Registered |
| CSET register_slice_mode_wach=Fully_Registered |
| CSET register_slice_mode_wdch=Fully_Registered |
| CSET register_slice_mode_wrch=Fully_Registered |
| CSET reset_pin=true |
| CSET reset_type=Synchronous_Reset |
| CSET ruser_width=1 |
| CSET synchronization_stages=2 |
| CSET synchronization_stages_axi=2 |
| CSET tdata_width=64 |
| CSET tdest_width=4 |
| CSET tid_width=8 |
| CSET tkeep_width=4 |
| CSET tstrb_width=4 |
| CSET tuser_width=4 |
| CSET underflow_flag=false |
| CSET underflow_flag_axi=false |
| CSET underflow_sense=Active_High |
| CSET underflow_sense_axi=Active_High |
| CSET use_clock_enable=false |
| CSET use_dout_reset=true |
| CSET use_embedded_registers=false |
| CSET use_extra_logic=false |
| CSET valid_flag=true |
| CSET valid_sense=Active_High |
| CSET wach_type=FIFO |
| CSET wdch_type=FIFO |
| CSET wrch_type=FIFO |
| CSET write_acknowledge_flag=false |
| CSET write_acknowledge_sense=Active_High |
| CSET write_clock_frequency=1 |
| CSET write_data_count=false |
| CSET write_data_count_width=9 |
| CSET wuser_width=1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-06-23T13:35:37Z |
| # END Extra information |
| GENERATE |
| # CRC: e2c6d431 |
| /Designs/HAM_Constructions/SDRX02A/HDL/modules/core_generator_ml605/fifo_32x512_dualclk_fwft.xco |
|---|
| 0,0 → 1,213 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue May 6 09:52:07 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:fifo_generator:9.3 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 |
| # END Select |
| # BEGIN Parameters |
| CSET add_ngc_constraint_axi=false |
| CSET almost_empty_flag=false |
| CSET almost_full_flag=false |
| CSET aruser_width=1 |
| CSET awuser_width=1 |
| CSET axi_address_width=32 |
| CSET axi_data_width=64 |
| CSET axi_type=AXI4_Stream |
| CSET axis_type=FIFO |
| CSET buser_width=1 |
| CSET clock_enable_type=Slave_Interface_Clock_Enable |
| CSET clock_type_axi=Common_Clock |
| CSET component_name=fifo_32x512_dualclk_fwft |
| CSET data_count=false |
| CSET data_count_width=9 |
| CSET disable_timing_violations=false |
| CSET disable_timing_violations_axi=false |
| CSET dout_reset_value=0 |
| CSET empty_threshold_assert_value=4 |
| CSET empty_threshold_assert_value_axis=1022 |
| CSET empty_threshold_assert_value_rach=1022 |
| CSET empty_threshold_assert_value_rdch=1022 |
| CSET empty_threshold_assert_value_wach=1022 |
| CSET empty_threshold_assert_value_wdch=1022 |
| CSET empty_threshold_assert_value_wrch=1022 |
| CSET empty_threshold_negate_value=5 |
| CSET enable_aruser=false |
| CSET enable_awuser=false |
| CSET enable_buser=false |
| CSET enable_common_overflow=false |
| CSET enable_common_underflow=false |
| CSET enable_data_counts_axis=false |
| CSET enable_data_counts_rach=false |
| CSET enable_data_counts_rdch=false |
| CSET enable_data_counts_wach=false |
| CSET enable_data_counts_wdch=false |
| CSET enable_data_counts_wrch=false |
| CSET enable_ecc=false |
| CSET enable_ecc_axis=false |
| CSET enable_ecc_rach=false |
| CSET enable_ecc_rdch=false |
| CSET enable_ecc_wach=false |
| CSET enable_ecc_wdch=false |
| CSET enable_ecc_wrch=false |
| CSET enable_read_channel=false |
| CSET enable_read_pointer_increment_by2=false |
| CSET enable_reset_synchronization=true |
| CSET enable_ruser=false |
| CSET enable_tdata=false |
| CSET enable_tdest=false |
| CSET enable_tid=false |
| CSET enable_tkeep=false |
| CSET enable_tlast=false |
| CSET enable_tready=true |
| CSET enable_tstrobe=false |
| CSET enable_tuser=false |
| CSET enable_write_channel=false |
| CSET enable_wuser=false |
| CSET fifo_application_type_axis=Data_FIFO |
| CSET fifo_application_type_rach=Data_FIFO |
| CSET fifo_application_type_rdch=Data_FIFO |
| CSET fifo_application_type_wach=Data_FIFO |
| CSET fifo_application_type_wdch=Data_FIFO |
| CSET fifo_application_type_wrch=Data_FIFO |
| CSET fifo_implementation=Independent_Clocks_Block_RAM |
| CSET fifo_implementation_axis=Common_Clock_Block_RAM |
| CSET fifo_implementation_rach=Common_Clock_Block_RAM |
| CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wach=Common_Clock_Block_RAM |
| CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
| CSET full_flags_reset_value=1 |
| CSET full_threshold_assert_value=511 |
| CSET full_threshold_assert_value_axis=1023 |
| CSET full_threshold_assert_value_rach=1023 |
| CSET full_threshold_assert_value_rdch=1023 |
| CSET full_threshold_assert_value_wach=1023 |
| CSET full_threshold_assert_value_wdch=1023 |
| CSET full_threshold_assert_value_wrch=1023 |
| CSET full_threshold_negate_value=510 |
| CSET id_width=4 |
| CSET inject_dbit_error=false |
| CSET inject_dbit_error_axis=false |
| CSET inject_dbit_error_rach=false |
| CSET inject_dbit_error_rdch=false |
| CSET inject_dbit_error_wach=false |
| CSET inject_dbit_error_wdch=false |
| CSET inject_dbit_error_wrch=false |
| CSET inject_sbit_error=false |
| CSET inject_sbit_error_axis=false |
| CSET inject_sbit_error_rach=false |
| CSET inject_sbit_error_rdch=false |
| CSET inject_sbit_error_wach=false |
| CSET inject_sbit_error_wdch=false |
| CSET inject_sbit_error_wrch=false |
| CSET input_data_width=32 |
| CSET input_depth=512 |
| CSET input_depth_axis=1024 |
| CSET input_depth_rach=16 |
| CSET input_depth_rdch=1024 |
| CSET input_depth_wach=16 |
| CSET input_depth_wdch=1024 |
| CSET input_depth_wrch=16 |
| CSET interface_type=Native |
| CSET output_data_width=32 |
| CSET output_depth=512 |
| CSET overflow_flag=false |
| CSET overflow_flag_axi=false |
| CSET overflow_sense=Active_High |
| CSET overflow_sense_axi=Active_High |
| CSET performance_options=First_Word_Fall_Through |
| CSET programmable_empty_type=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
| CSET programmable_full_type=No_Programmable_Full_Threshold |
| CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
| CSET rach_type=FIFO |
| CSET rdch_type=FIFO |
| CSET read_clock_frequency=1 |
| CSET read_data_count=false |
| CSET read_data_count_width=9 |
| CSET register_slice_mode_axis=Fully_Registered |
| CSET register_slice_mode_rach=Fully_Registered |
| CSET register_slice_mode_rdch=Fully_Registered |
| CSET register_slice_mode_wach=Fully_Registered |
| CSET register_slice_mode_wdch=Fully_Registered |
| CSET register_slice_mode_wrch=Fully_Registered |
| CSET reset_pin=true |
| CSET reset_type=Asynchronous_Reset |
| CSET ruser_width=1 |
| CSET synchronization_stages=2 |
| CSET synchronization_stages_axi=2 |
| CSET tdata_width=64 |
| CSET tdest_width=4 |
| CSET tid_width=8 |
| CSET tkeep_width=4 |
| CSET tstrb_width=4 |
| CSET tuser_width=4 |
| CSET underflow_flag=false |
| CSET underflow_flag_axi=false |
| CSET underflow_sense=Active_High |
| CSET underflow_sense_axi=Active_High |
| CSET use_clock_enable=false |
| CSET use_dout_reset=false |
| CSET use_embedded_registers=false |
| CSET use_extra_logic=false |
| CSET valid_flag=true |
| CSET valid_sense=Active_High |
| CSET wach_type=FIFO |
| CSET wdch_type=FIFO |
| CSET wrch_type=FIFO |
| CSET write_acknowledge_flag=false |
| CSET write_acknowledge_sense=Active_High |
| CSET write_clock_frequency=1 |
| CSET write_data_count=false |
| CSET write_data_count_width=9 |
| CSET wuser_width=1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-07-25T18:11:59Z |
| # END Extra information |
| GENERATE |
| # CRC: 19014e08 |
| /Designs/HAM_Constructions/SDRX02A/HDL/modules/core_generator_ml605/fifo_32x512_walmostfull.xco |
|---|
| 0,0 → 1,213 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.3 |
| # Date: Tue May 6 09:54:30 2014 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:fifo_generator:9.3 |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc6vlx240t |
| SET devicefamily = virtex6 |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = ff1156 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -1 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 |
| # END Select |
| # BEGIN Parameters |
| CSET add_ngc_constraint_axi=false |
| CSET almost_empty_flag=false |
| CSET almost_full_flag=false |
| CSET aruser_width=1 |
| CSET awuser_width=1 |
| CSET axi_address_width=32 |
| CSET axi_data_width=64 |
| CSET axi_type=AXI4_Stream |
| CSET axis_type=FIFO |
| CSET buser_width=1 |
| CSET clock_enable_type=Slave_Interface_Clock_Enable |
| CSET clock_type_axi=Common_Clock |
| CSET component_name=fifo_32x512_walmostfull |
| CSET data_count=false |
| CSET data_count_width=9 |
| CSET disable_timing_violations=false |
| CSET disable_timing_violations_axi=false |
| CSET dout_reset_value=0 |
| CSET empty_threshold_assert_value=2 |
| CSET empty_threshold_assert_value_axis=1022 |
| CSET empty_threshold_assert_value_rach=1022 |
| CSET empty_threshold_assert_value_rdch=1022 |
| CSET empty_threshold_assert_value_wach=1022 |
| CSET empty_threshold_assert_value_wdch=1022 |
| CSET empty_threshold_assert_value_wrch=1022 |
| CSET empty_threshold_negate_value=3 |
| CSET enable_aruser=false |
| CSET enable_awuser=false |
| CSET enable_buser=false |
| CSET enable_common_overflow=false |
| CSET enable_common_underflow=false |
| CSET enable_data_counts_axis=false |
| CSET enable_data_counts_rach=false |
| CSET enable_data_counts_rdch=false |
| CSET enable_data_counts_wach=false |
| CSET enable_data_counts_wdch=false |
| CSET enable_data_counts_wrch=false |
| CSET enable_ecc=false |
| CSET enable_ecc_axis=false |
| CSET enable_ecc_rach=false |
| CSET enable_ecc_rdch=false |
| CSET enable_ecc_wach=false |
| CSET enable_ecc_wdch=false |
| CSET enable_ecc_wrch=false |
| CSET enable_read_channel=false |
| CSET enable_read_pointer_increment_by2=false |
| CSET enable_reset_synchronization=true |
| CSET enable_ruser=false |
| CSET enable_tdata=false |
| CSET enable_tdest=false |
| CSET enable_tid=false |
| CSET enable_tkeep=false |
| CSET enable_tlast=false |
| CSET enable_tready=true |
| CSET enable_tstrobe=false |
| CSET enable_tuser=false |
| CSET enable_write_channel=false |
| CSET enable_wuser=false |
| CSET fifo_application_type_axis=Data_FIFO |
| CSET fifo_application_type_rach=Data_FIFO |
| CSET fifo_application_type_rdch=Data_FIFO |
| CSET fifo_application_type_wach=Data_FIFO |
| CSET fifo_application_type_wdch=Data_FIFO |
| CSET fifo_application_type_wrch=Data_FIFO |
| CSET fifo_implementation=Common_Clock_Block_RAM |
| CSET fifo_implementation_axis=Common_Clock_Block_RAM |
| CSET fifo_implementation_rach=Common_Clock_Block_RAM |
| CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wach=Common_Clock_Block_RAM |
| CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
| CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
| CSET full_flags_reset_value=0 |
| CSET full_threshold_assert_value=400 |
| CSET full_threshold_assert_value_axis=1023 |
| CSET full_threshold_assert_value_rach=1023 |
| CSET full_threshold_assert_value_rdch=1023 |
| CSET full_threshold_assert_value_wach=1023 |
| CSET full_threshold_assert_value_wdch=1023 |
| CSET full_threshold_assert_value_wrch=1023 |
| CSET full_threshold_negate_value=399 |
| CSET id_width=4 |
| CSET inject_dbit_error=false |
| CSET inject_dbit_error_axis=false |
| CSET inject_dbit_error_rach=false |
| CSET inject_dbit_error_rdch=false |
| CSET inject_dbit_error_wach=false |
| CSET inject_dbit_error_wdch=false |
| CSET inject_dbit_error_wrch=false |
| CSET inject_sbit_error=false |
| CSET inject_sbit_error_axis=false |
| CSET inject_sbit_error_rach=false |
| CSET inject_sbit_error_rdch=false |
| CSET inject_sbit_error_wach=false |
| CSET inject_sbit_error_wdch=false |
| CSET inject_sbit_error_wrch=false |
| CSET input_data_width=32 |
| CSET input_depth=512 |
| CSET input_depth_axis=1024 |
| CSET input_depth_rach=16 |
| CSET input_depth_rdch=1024 |
| CSET input_depth_wach=16 |
| CSET input_depth_wdch=1024 |
| CSET input_depth_wrch=16 |
| CSET interface_type=Native |
| CSET output_data_width=32 |
| CSET output_depth=512 |
| CSET overflow_flag=false |
| CSET overflow_flag_axi=false |
| CSET overflow_sense=Active_High |
| CSET overflow_sense_axi=Active_High |
| CSET performance_options=Standard_FIFO |
| CSET programmable_empty_type=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
| CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
| CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant |
| CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
| CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
| CSET rach_type=FIFO |
| CSET rdch_type=FIFO |
| CSET read_clock_frequency=1 |
| CSET read_data_count=false |
| CSET read_data_count_width=9 |
| CSET register_slice_mode_axis=Fully_Registered |
| CSET register_slice_mode_rach=Fully_Registered |
| CSET register_slice_mode_rdch=Fully_Registered |
| CSET register_slice_mode_wach=Fully_Registered |
| CSET register_slice_mode_wdch=Fully_Registered |
| CSET register_slice_mode_wrch=Fully_Registered |
| CSET reset_pin=true |
| CSET reset_type=Synchronous_Reset |
| CSET ruser_width=1 |
| CSET synchronization_stages=2 |
| CSET synchronization_stages_axi=2 |
| CSET tdata_width=64 |
| CSET tdest_width=4 |
| CSET tid_width=8 |
| CSET tkeep_width=4 |
| CSET tstrb_width=4 |
| CSET tuser_width=4 |
| CSET underflow_flag=false |
| CSET underflow_flag_axi=false |
| CSET underflow_sense=Active_High |
| CSET underflow_sense_axi=Active_High |
| CSET use_clock_enable=false |
| CSET use_dout_reset=false |
| CSET use_embedded_registers=false |
| CSET use_extra_logic=false |
| CSET valid_flag=true |
| CSET valid_sense=Active_High |
| CSET wach_type=FIFO |
| CSET wdch_type=FIFO |
| CSET wrch_type=FIFO |
| CSET write_acknowledge_flag=false |
| CSET write_acknowledge_sense=Active_High |
| CSET write_clock_frequency=1 |
| CSET write_data_count=false |
| CSET write_data_count_width=9 |
| CSET wuser_width=1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2012-07-25T18:11:59Z |
| # END Extra information |
| GENERATE |
| # CRC: 53dc1af8 |