/Designs/HAM_Constructions/SDRX02A/HDL/modules/sychro1/clock_divider.vhd
0,0 → 1,68
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library UNISIM;
use UNISIM.vcomponents.all;
 
entity clock_divider is
generic (
G_DIVISOR : positive := 2
);
port (
i_clk : in std_logic;
i_rst : in std_logic;
o_clk : out std_logic
);
end entity clock_divider;
 
architecture behavioral of clock_divider is
 
subtype t_counter is natural range 0 to ( G_DIVISOR - 1 );
signal s_counter : t_counter := 0;
 
constant C_COUNTER : t_counter := G_DIVISOR / 2 - 1;
 
signal s_clk_divided : std_logic;
attribute clock_signal : string;
attribute clock_signal of s_clk_divided : signal is "yes";
 
begin
 
assert ( G_DIVISOR > 1 ) report "The divisor should be greater than 1" severity failure;
counting : process( i_clk )
begin
if( rising_edge(i_clk) ) then
if( i_rst = '1' ) then
s_counter <= 0;
s_clk_divided <= '0';
else
if( s_counter = t_counter'high ) then
s_counter <= 0;
s_clk_divided <= '0';
else
s_counter <= s_counter + 1;
if( s_counter = C_COUNTER ) then
s_clk_divided <= '1';
end if;
end if;
end if;
end if;
end process counting;
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6"
port map (
O => o_clk, -- Clock buffer output
CE => '1', -- Clock enable input
CLR => '0', -- Clock buffer reset input
I => s_clk_divided -- Clock buffer input
);
end architecture;
/Designs/HAM_Constructions/SDRX02A/HDL/modules/sychro1/up_counter.vhd
0,0 → 1,57
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity up_counter is
generic (
G_MIN_NUMBER : natural := 0;
G_MAX_NUMBER : natural := 10
);
port (
 
i_clk : in std_logic;
i_rst : in std_logic;
-- Count when this input is '1'
i_valid : in std_logic;
-- Output the actual number
o_data : out natural := G_MIN_NUMBER;
o_carry : out std_logic := '0'
);
end up_counter;
 
architecture rtl of up_counter is
 
signal number : natural range G_MIN_NUMBER to G_MAX_NUMBER := G_MIN_NUMBER;
 
begin
 
o_data <= number;
counter : process( i_clk )
begin
if( rising_edge( i_clk ) ) then
o_carry <= '0';
if( i_rst = '1' ) then
number <= G_MIN_NUMBER;
elsif( i_valid = '1' ) then
-- count up:
if( number = G_MAX_NUMBER ) then
number <= G_MIN_NUMBER;
o_carry <= '1';
else
number <= number + 1;
end if;
end if;
end if;
end process;
end architecture;
/Designs/HAM_Constructions/SDRX02A/HDL/modules/sychro1/up_counter_stdlv.vhd
0,0 → 1,57
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity up_counter_stdlv is
generic (
G_BITS : positive := 8;
G_MIN_NUMBER : std_logic_vector;
G_MAX_NUMBER : std_logic_vector
);
port (
 
i_clk : in std_logic;
i_rst : in std_logic;
-- Count when this input is '1'
i_valid : in std_logic;
-- Output the actual number
o_data : out std_logic_vector( G_BITS-1 downto 0 );
o_carry : out std_logic := '0'
);
end up_counter_stdlv;
 
architecture rtl of up_counter_stdlv is
 
signal number : std_logic_vector( G_BITS-1 downto 0 );
 
begin
 
o_data <= number;
counter : process( i_clk )
begin
if( rising_edge( i_clk ) ) then
o_carry <= '0';
if( i_rst = '1' ) then
number <= G_MIN_NUMBER;
elsif( i_valid = '1' ) then
-- count up:
if( number = G_MAX_NUMBER ) then
number <= G_MIN_NUMBER;
o_carry <= '1';
else
number <= std_logic_vector( unsigned(number) + to_unsigned(1,G_BITS) );
end if;
end if;
end if;
end process;
end architecture;