/Designs/HAM_Constructions/SDRX02A/HDL/modules/sychro1/up_counter_stdlv.vhd
0,0 → 1,57
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity up_counter_stdlv is
generic (
G_BITS : positive := 8;
G_MIN_NUMBER : std_logic_vector;
G_MAX_NUMBER : std_logic_vector
);
port (
 
i_clk : in std_logic;
i_rst : in std_logic;
-- Count when this input is '1'
i_valid : in std_logic;
-- Output the actual number
o_data : out std_logic_vector( G_BITS-1 downto 0 );
o_carry : out std_logic := '0'
);
end up_counter_stdlv;
 
architecture rtl of up_counter_stdlv is
 
signal number : std_logic_vector( G_BITS-1 downto 0 );
 
begin
 
o_data <= number;
counter : process( i_clk )
begin
if( rising_edge( i_clk ) ) then
o_carry <= '0';
if( i_rst = '1' ) then
number <= G_MIN_NUMBER;
elsif( i_valid = '1' ) then
-- count up:
if( number = G_MAX_NUMBER ) then
number <= G_MIN_NUMBER;
o_carry <= '1';
else
number <= std_logic_vector( unsigned(number) + to_unsigned(1,G_BITS) );
end if;
end if;
end if;
end process;
end architecture;