/Designs/Laboratory_instruments/AtomicCounter/VHDL/src/S3AN01B.ucf |
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9,7 → 9,7 |
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%; |
NET "LO_CLOCK" TNM_NET = LO_CLOCK; |
TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.0 ns HIGH 50%; |
TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.2 ns HIGH 50%; |
# For DCM connection across the whole chip |
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE; |