| 6,7 → 6,7 |
|---|
| #define RAM_Tamb 0x06 // Ta address in the RAM |
| |
| |
| //*High and Low level of clock |
| // High and Low level of clock |
| #define HIGHLEV 40 // max. 50us |
| #define LOWLEV 100 // max. 30ms |
| #define TBUF 20 |
| 17,7 → 17,7 |
|---|
| |
| #define mSDA_HIGH() output_float(SDA); // SDA float |
| #define mSDA_LOW() output_low(SDA); // SDA low |
| #define mSCL_HIGH() output_float(SCL); //output_high(SCL); // SCL high |
| #define mSCL_HIGH() output_float(SCL); // SCL float |
| #define mSCL_LOW() output_low(SCL); // SCL low |
| |
| #define ACK 0 |
| 42,13 → 42,14 |
|---|
| delay_us( TBUF ); // Generate bus free time between Stop |
| // and Start condition (Tbuf=4.7us min) |
| mSDA_LOW(); // Clear SDA line |
| delay_us( TBUF ); // Hold time after (Repeated) Start |
| // Condition. After this period, the first clock is generated. |
| delay_us( TBUF ); // Hold time after (Repeated) Start Condition. |
| // After this period, the first clock is generated. |
| //(Thd:sta=4.0us min) |
| mSCL_LOW(); // Clear SCL line |
| // enable_interrupts(GLOBAL); |
| delay_us( TBUF ); // Wait a few microseconds |
| } |
| |
| //********************************************************************************************* |
| // STOP CONDITION ON SMBus |
| //********************************************************************************************* |