/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/gtime.ipf
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/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/gtime.xise
9,10 → 9,10
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL">
47,7 → 47,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/gtime.vhd
166,7 → 166,6
-- LED Display
-- -----------
 
signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
signal HalfFreq: std_logic_vector(31 downto 0);
178,7 → 177,6
 
signal LO_CLOCK: std_logic;
signal EXT_CLOCK: std_logic;
 
signal Decko: std_logic;
signal State: unsigned(2 downto 0) := (others => '0');
185,15 → 183,6
begin
 
process (EXT_CLOCK)
begin
if rising_edge(EXT_CLOCK) then
LO_CLOCK <= not LO_CLOCK;
end if;
end process;
 
 
-- Counter
process (LO_CLOCK)
begin
245,16 → 234,15
 
-- Coding to BCD for LED Display
 
process (Decko)
begin
if falling_edge(Decko) then
NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0);
NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0);
end if;
end process;
-- HalfFreq(14 downto 0) <= Freq(15 downto 1);
-- HalfFreq(15) <= '0';
-- HalfFreq(30 downto 16) <= Freq(31 downto 17);
-- HalfFreq(31) <= '0';
-- Number(15 downto 0) <= to_bcd(HalfFreq(15 downto 0))(15 downto 0);
-- Number(35 downto 16) <= to_bcd(HalfFreq(31 downto 16))(19 downto 0);
Number(15 downto 0) <= Freq(15 downto 0);
Number(31 downto 16) <= Freq(31 downto 16);
 
Number(35 downto 0) <= NumberPom(35 downto 0);
LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
LED(6 downto 4) <= (others => '0');
LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
334,7 → 322,13
"0000";
 
 
-- Display on 7seg.
-- Number(3 downto 0) <= (others=>'0');
-- Number(15 downto 4) <= (others=>'1'); --to_bcd(std_logic_vector(T2));
-- Number(19 downto 16) <= (others=>'0');
-- Number(31 downto 20) <= (others=>'1'); --to_bcd(std_logic_vector(T1));
 
 
-- Diferencial In/Outs
-- ========================
DIFbuffer1 : IBUFGDS
346,7 → 340,7
port map (
I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
O => EXT_CLOCK -- Buffer output
O => LO_CLOCK -- Buffer output
);
 
OBUFDS_inst : OBUFDS
355,7 → 349,7
port map (
O => SD2AP, -- Diff_p output (connect directly to top-level port)
OB => SD2AN, -- Diff_n output (connect directly to top-level port)
I => EXT_CLOCK -- Buffer input
I => LO_CLOCK -- Buffer input
);
-- Output Signal on SATA Connector