/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/gtime.vhd
25,7 → 25,7
generic (
-- Top Value for 100MHz Clock Counter
--!!!KAKL MAXCOUNT: integer := 30_000_000;
MAXCOUNT: integer := 3_000_000;
MAXCOUNT: integer := 10_000;
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
);
port (
149,7 → 149,8
-- LED Demo Signals
-- ----------------
 
signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary)
signal Counter: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary)
signal CounterMaxcount: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary)
signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary)
 
signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz)
157,7 → 158,7
-- LED Display
-- -----------
 
signal Number: std_logic_vector(32 downto 0); -- LED Display Input
signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
signal Enable: std_logic;
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
168,8 → 169,7
signal LO_CLOCK: std_logic;
 
signal Decko: std_logic;
signal Disp: std_logic := '0';
signal Reset: std_logic := '0';
signal State: unsigned(2 downto 0) := (others => '0');
begin
 
179,48 → 179,52
-- LED Bar Counter
process (LO_CLOCK)
begin
if Reset = '0' then
if rising_edge(LO_CLOCK) then
if Disp = '1' then
Reset <= '1';
end if;
 
Decko <= DIPSW(0);
 
if (State = 3) or (State = 0) then
if Counter < MAXCOUNT-1 then
Counter <= Counter + 1;
else
Counter <= (others => '0');
Bar <= Bar + 1;
CounterMaxcount <= CounterMaxcount + 1;
end if;
end if;
 
else
Bar <= (others => '0');
Reset <= '0';
if (State = 1) then
Number(15 downto 0) <= std_logic_vector(Counter(15 downto 0));
Number(31 downto 16) <= std_logic_vector(CounterMaxcount(15 downto 0));
end if;
if (State = 2) then
CounterMaxcount <= (others => '0');
Counter <= (others => '0');
end if;
end if;
end process;
 
 
process (LO_CLOCK)
begin
if rising_edge(LO_CLOCK) then
if Decko = '1' then
if Disp = '0' then
Number(3 downto 0) <= std_logic_vector(Bar(3 downto 0));
Number(7 downto 4) <= std_logic_vector(Bar(7 downto 4));
Number(15 downto 8) <= (others=>'0');
Number(19 downto 16) <= (others=>'0');
Number(31 downto 20) <= (others=>'0'); --to_bcd(std_logic_vector(T1));
Disp <= '1';
Decko <= DIPSW(0);
end if;
end process;
 
process (LO_CLOCK)
begin
if rising_edge(LO_CLOCK) then
if (Decko = '1') then
if (State < 3) then
State <= State + 1;
end if;
else
Disp <= '0';
State <= (others => '0');
end if;
end if;
end process;
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
 
-- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
311,7 → 315,7
-- ========================
DIFbuffer1 : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
DIFF_TERM => FALSE, -- Differential Termination
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
-- "0"-"16"
IOSTANDARD => "DEFAULT")