/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/S3AN01B.ucf
4,13 → 4,18
# Main Clock (Embedded 100MHz board oscillator)
NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33;
#NET "CLK100MHz" LOC = P125 | IOSTANDARD = LVCMOS33;
#NET "SCLK" LOC = P1 |IOSTANDARD = LVCMOS33;
 
NET "CLK100MHz" TNM_NET = CLK100MHz;
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;
 
NET "LO_CLOCK" TNM_NET = LO_CLOCK;
TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 4.5 ns HIGH 50%;
NET "EXT_CLOCK" TNM_NET = EXT_CLOCK;
TIMESPEC TS_EXT_CLOCK = PERIOD "EXT_CLOCK" 4.5 ns HIGH 50%;
 
#NET "SCLK" TNM_NET = SCLK;
#TIMESPEC TS_SCLK = PERIOD "SCLK" 50 MHz HIGH 10%;
NET "B<0>" CLOCK_DEDICATED_ROUTE = FALSE;
 
# For DCM connection across the whole chip
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;
NET "PS2_CLK2" CLOCK_DEDICATED_ROUTE = FALSE;