Problem with comparison.
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.6/S3AN01_ChipScope_18x1024.bit |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.6/S3AN01_ChipScope_9x2048.bit |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.6/Version |
|---|
| 0,0 → 1,4 |
| TimeStamp: 2013_06_28__12_18 |
| ComputerName: MIHO-W7 |
| ISE Version: 14.6 |
| ReleaseInfo: None |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/S3AN01_ChipScope_18x1024.bit |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/S3AN01_ChipScope_9x2048.bit |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/Version |
|---|
| 0,0 → 1,4 |
| TimeStamp: 2013_06_25__09_41 |
| ComputerName: MIHOMSI |
| ISE Version: 13.3 |
| ReleaseInfo: None |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/S3AN01_ChipScope_18x1024.bit |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/S3AN01_ChipScope_9x2048.bit |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/Version |
|---|
| 0,0 → 1,4 |
| TimeStamp: 2013_06_25__17_31 |
| ComputerName: MIHO-W7 |
| ISE Version: 14.5 |
| ReleaseInfo: None |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser.ini |
|---|
| 0,0 → 1,24 |
| #ChipScope Pro Analyzer Configuration File |
| #Tue Jun 25 16:04:01 CEST 2013 |
| OPEN_TARGET.host=localhost\:2542 |
| xilinx_parallel.PORT=LPT1 |
| previous_cable_name=xilinx_xvc |
| OPEN_TARGET.disableversioncheck=true |
| guiLocationY=14 |
| guiLocationX=90 |
| guiWidth=1448 |
| guiHeight=907 |
| previous_cable_cmd=open_target |
| lastParallelCable=xilinx_parallel3 |
| projectDir=..\\ANALYSER |
| OPEN_TARGET.keylist=disableversioncheck host |
| xilinx_parallel.FREQUENCY=5000000 |
| previous_cable_key=OPEN_TARGET |
| xilinx_parallel.keylist=FREQUENCY PORT |
| previous.defaultDirectory=..\\ANALYSER |
| openTarget.2=xilinx_parallel PORT\=LPT1 FREQUENCY\=2500000 |
| openTarget.1=xilinx_platformusb PORT\=USB21 FREQUENCY\=6000000 |
| debugOn=0 |
| openTarget.0=xilinx_xvc host\=localhost\:2542 disableversioncheck\=true |
| project1=..\\ANALYSER\\Analyser_9_2048.cpj |
| project0=..\\ANALYSER\\Analyser_18_1024.cpj |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser_18_1024.cpj |
|---|
| 0,0 → 1,1076 |
| #ChipScope Pro Analyzer Project File, Version 3.0 |
| #Tue Jun 25 09:46:51 CEST 2013 |
| device.0.configFileDir=..\\BIN |
| device.0.configFilename=S3AN01_ChipScope_18x1024.bit |
| device.0.inserterCDCFileDir= |
| device.0.inserterCDCFilename= |
| deviceChain.deviceName0=XC3S50AN |
| deviceChain.iRLength0=6 |
| deviceChain.name0=Trigger Setup |
| deviceIds=02610093 |
| mdiAreaHeight=0.6990077177508269 |
| mdiAreaHeightLast=0.6990077177508269 |
| mdiCount=4 |
| mdiDevice0=0 |
| mdiDevice1=0 |
| mdiDevice2=0 |
| mdiDevice3=0 |
| mdiType0=1 |
| mdiType1=6 |
| mdiType2=0 |
| mdiType3=6 |
| mdiUnit0=2 |
| mdiUnit1=1 |
| mdiUnit2=2 |
| mdiUnit3=0 |
| navigatorHeight=0.24807056229327454 |
| navigatorHeightLast=0.2866593164277839 |
| navigatorWidth=0.17472375690607736 |
| navigatorWidthLast=0.14433701657458564 |
| signalDisplayPath=0 |
| unit.-1.-1.username= |
| unit.0.-1.username= |
| unit.0.0.0.HEIGHT0=0.3660856 |
| unit.0.0.0.TriggerRow0=1 |
| unit.0.0.0.TriggerRow1=1 |
| unit.0.0.0.TriggerRow2=1 |
| unit.0.0.0.WIDTH0=0.9940426 |
| unit.0.0.0.X0=0.0 |
| unit.0.0.0.Y0=0.0 |
| unit.0.0.1.HEIGHT1=0.58161646 |
| unit.0.0.1.WIDTH1=0.9940426 |
| unit.0.0.1.X1=0.0 |
| unit.0.0.1.Y1=0.3660856 |
| unit.0.0.6.HEIGHT6=0.75594294 |
| unit.0.0.6.WIDTH6=0.17021276 |
| unit.0.0.6.X6=0.0025531915 |
| unit.0.0.6.Y6=0.014263075 |
| unit.0.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXX |
| unit.0.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXX |
| unit.0.0.MFBitsB0=000000000000000000000000 |
| unit.0.0.MFBitsB1=000000000000000000000000 |
| unit.0.0.MFCompareA0=0 |
| unit.0.0.MFCompareA1=0 |
| unit.0.0.MFCompareB0=999 |
| unit.0.0.MFCompareB1=999 |
| unit.0.0.MFCount=2 |
| unit.0.0.MFDisplay0=0 |
| unit.0.0.MFDisplay1=0 |
| unit.0.0.MFEventType0=3 |
| unit.0.0.MFEventType1=3 |
| unit.0.0.RunMode=SINGLE RUN |
| unit.0.0.SQCondition=All Data |
| unit.0.0.SQContiguous0=0 |
| unit.0.0.SequencerOn=0 |
| unit.0.0.TCActive=0 |
| unit.0.0.TCAdvanced0=0 |
| unit.0.0.TCCondition0_0=M0 |
| unit.0.0.TCCondition0_1= |
| unit.0.0.TCConditionType0=0 |
| unit.0.0.TCCount=1 |
| unit.0.0.TCEventCount0=1 |
| unit.0.0.TCEventType0=3 |
| unit.0.0.TCName0=TriggerCondition0 |
| unit.0.0.TCOutputEnable0=0 |
| unit.0.0.TCOutputHigh0=1 |
| unit.0.0.TCOutputMode0=0 |
| unit.0.0.coretype=VIO |
| unit.0.0.eventCount0=1 |
| unit.0.0.eventCount1=1 |
| unit.0.0.port.-1.buscount=0 |
| unit.0.0.port.-1.channelcount=0 |
| unit.0.0.port.-1.s.0.alias= |
| unit.0.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.0.name=DataPort[0] |
| unit.0.0.port.-1.s.0.orderindex=-1 |
| unit.0.0.port.-1.s.0.visible=1 |
| unit.0.0.port.-1.s.1.alias= |
| unit.0.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.1.name=DataPort[1] |
| unit.0.0.port.-1.s.1.orderindex=-1 |
| unit.0.0.port.-1.s.1.visible=1 |
| unit.0.0.port.-1.s.10.alias= |
| unit.0.0.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.10.name=DataPort[10] |
| unit.0.0.port.-1.s.10.orderindex=-1 |
| unit.0.0.port.-1.s.10.visible=1 |
| unit.0.0.port.-1.s.11.alias= |
| unit.0.0.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.11.name=DataPort[11] |
| unit.0.0.port.-1.s.11.orderindex=-1 |
| unit.0.0.port.-1.s.11.visible=1 |
| unit.0.0.port.-1.s.12.alias= |
| unit.0.0.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.12.name=DataPort[12] |
| unit.0.0.port.-1.s.12.orderindex=-1 |
| unit.0.0.port.-1.s.12.visible=1 |
| unit.0.0.port.-1.s.13.alias= |
| unit.0.0.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.13.name=DataPort[13] |
| unit.0.0.port.-1.s.13.orderindex=-1 |
| unit.0.0.port.-1.s.13.visible=1 |
| unit.0.0.port.-1.s.14.alias= |
| unit.0.0.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.14.name=DataPort[14] |
| unit.0.0.port.-1.s.14.orderindex=-1 |
| unit.0.0.port.-1.s.14.visible=1 |
| unit.0.0.port.-1.s.15.alias= |
| unit.0.0.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.15.name=DataPort[15] |
| unit.0.0.port.-1.s.15.orderindex=-1 |
| unit.0.0.port.-1.s.15.visible=1 |
| unit.0.0.port.-1.s.16.alias= |
| unit.0.0.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.16.name=DataPort[16] |
| unit.0.0.port.-1.s.16.orderindex=-1 |
| unit.0.0.port.-1.s.16.visible=1 |
| unit.0.0.port.-1.s.17.alias= |
| unit.0.0.port.-1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.17.name=DataPort[17] |
| unit.0.0.port.-1.s.17.orderindex=-1 |
| unit.0.0.port.-1.s.17.visible=1 |
| unit.0.0.port.-1.s.18.alias= |
| unit.0.0.port.-1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.18.name=DataPort[18] |
| unit.0.0.port.-1.s.18.orderindex=-1 |
| unit.0.0.port.-1.s.18.visible=1 |
| unit.0.0.port.-1.s.19.alias= |
| unit.0.0.port.-1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.19.name=DataPort[19] |
| unit.0.0.port.-1.s.19.orderindex=-1 |
| unit.0.0.port.-1.s.19.visible=1 |
| unit.0.0.port.-1.s.2.alias= |
| unit.0.0.port.-1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.2.name=DataPort[2] |
| unit.0.0.port.-1.s.2.orderindex=-1 |
| unit.0.0.port.-1.s.2.visible=1 |
| unit.0.0.port.-1.s.20.alias= |
| unit.0.0.port.-1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.20.name=DataPort[20] |
| unit.0.0.port.-1.s.20.orderindex=-1 |
| unit.0.0.port.-1.s.20.visible=1 |
| unit.0.0.port.-1.s.21.alias= |
| unit.0.0.port.-1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.21.name=DataPort[21] |
| unit.0.0.port.-1.s.21.orderindex=-1 |
| unit.0.0.port.-1.s.21.visible=1 |
| unit.0.0.port.-1.s.22.alias= |
| unit.0.0.port.-1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.22.name=DataPort[22] |
| unit.0.0.port.-1.s.22.orderindex=-1 |
| unit.0.0.port.-1.s.22.visible=1 |
| unit.0.0.port.-1.s.23.alias= |
| unit.0.0.port.-1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.23.name=DataPort[23] |
| unit.0.0.port.-1.s.23.orderindex=-1 |
| unit.0.0.port.-1.s.23.visible=1 |
| unit.0.0.port.-1.s.3.alias= |
| unit.0.0.port.-1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.3.name=DataPort[3] |
| unit.0.0.port.-1.s.3.orderindex=-1 |
| unit.0.0.port.-1.s.3.visible=1 |
| unit.0.0.port.-1.s.4.alias= |
| unit.0.0.port.-1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.4.name=DataPort[4] |
| unit.0.0.port.-1.s.4.orderindex=-1 |
| unit.0.0.port.-1.s.4.visible=1 |
| unit.0.0.port.-1.s.5.alias= |
| unit.0.0.port.-1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.5.name=DataPort[5] |
| unit.0.0.port.-1.s.5.orderindex=-1 |
| unit.0.0.port.-1.s.5.visible=1 |
| unit.0.0.port.-1.s.6.alias= |
| unit.0.0.port.-1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.6.name=DataPort[6] |
| unit.0.0.port.-1.s.6.orderindex=-1 |
| unit.0.0.port.-1.s.6.visible=1 |
| unit.0.0.port.-1.s.7.alias= |
| unit.0.0.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.7.name=DataPort[7] |
| unit.0.0.port.-1.s.7.orderindex=-1 |
| unit.0.0.port.-1.s.7.visible=1 |
| unit.0.0.port.-1.s.8.alias= |
| unit.0.0.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.8.name=DataPort[8] |
| unit.0.0.port.-1.s.8.orderindex=-1 |
| unit.0.0.port.-1.s.8.visible=1 |
| unit.0.0.port.-1.s.9.alias= |
| unit.0.0.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.9.name=DataPort[9] |
| unit.0.0.port.-1.s.9.orderindex=-1 |
| unit.0.0.port.-1.s.9.visible=1 |
| unit.0.0.port.0.b.0.alias= |
| unit.0.0.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 |
| unit.0.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.b.0.name=TriggerPort0 |
| unit.0.0.port.0.b.0.orderindex=-1 |
| unit.0.0.port.0.b.0.radix=Hex |
| unit.0.0.port.0.b.0.signedOffset=0.0 |
| unit.0.0.port.0.b.0.signedPrecision=0 |
| unit.0.0.port.0.b.0.signedScaleFactor=1.0 |
| unit.0.0.port.0.b.0.unsignedOffset=0.0 |
| unit.0.0.port.0.b.0.unsignedPrecision=0 |
| unit.0.0.port.0.b.0.unsignedScaleFactor=1.0 |
| unit.0.0.port.0.b.0.visible=1 |
| unit.0.0.port.0.buscount=0 |
| unit.0.0.port.0.channelcount=8 |
| unit.0.0.port.0.s.0.alias=1 MHz |
| unit.0.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.0.display=14 |
| unit.0.0.port.0.s.0.name=SyncIn[0] |
| unit.0.0.port.0.s.0.orderindex=-1 |
| unit.0.0.port.0.s.0.persistence=0 |
| unit.0.0.port.0.s.0.value=0 |
| unit.0.0.port.0.s.0.visible=1 |
| unit.0.0.port.0.s.1.alias=2 MHz |
| unit.0.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.1.display=14 |
| unit.0.0.port.0.s.1.name=SyncIn[1] |
| unit.0.0.port.0.s.1.orderindex=-1 |
| unit.0.0.port.0.s.1.persistence=0 |
| unit.0.0.port.0.s.1.value=0 |
| unit.0.0.port.0.s.1.visible=1 |
| unit.0.0.port.0.s.10.alias= |
| unit.0.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.10.name=TriggerPort0[10] |
| unit.0.0.port.0.s.10.orderindex=-1 |
| unit.0.0.port.0.s.10.visible=1 |
| unit.0.0.port.0.s.11.alias= |
| unit.0.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.11.name=TriggerPort0[11] |
| unit.0.0.port.0.s.11.orderindex=-1 |
| unit.0.0.port.0.s.11.visible=1 |
| unit.0.0.port.0.s.12.alias= |
| unit.0.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.12.name=TriggerPort0[12] |
| unit.0.0.port.0.s.12.orderindex=-1 |
| unit.0.0.port.0.s.12.visible=1 |
| unit.0.0.port.0.s.13.alias= |
| unit.0.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.13.name=TriggerPort0[13] |
| unit.0.0.port.0.s.13.orderindex=-1 |
| unit.0.0.port.0.s.13.visible=1 |
| unit.0.0.port.0.s.14.alias= |
| unit.0.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.14.name=TriggerPort0[14] |
| unit.0.0.port.0.s.14.orderindex=-1 |
| unit.0.0.port.0.s.14.visible=1 |
| unit.0.0.port.0.s.15.alias= |
| unit.0.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.15.name=TriggerPort0[15] |
| unit.0.0.port.0.s.15.orderindex=-1 |
| unit.0.0.port.0.s.15.visible=1 |
| unit.0.0.port.0.s.16.alias= |
| unit.0.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.16.name=TriggerPort0[16] |
| unit.0.0.port.0.s.16.orderindex=-1 |
| unit.0.0.port.0.s.16.visible=1 |
| unit.0.0.port.0.s.17.alias= |
| unit.0.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.17.name=TriggerPort0[17] |
| unit.0.0.port.0.s.17.orderindex=-1 |
| unit.0.0.port.0.s.17.visible=1 |
| unit.0.0.port.0.s.18.alias= |
| unit.0.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.18.name=TriggerPort0[18] |
| unit.0.0.port.0.s.18.orderindex=-1 |
| unit.0.0.port.0.s.18.visible=1 |
| unit.0.0.port.0.s.19.alias= |
| unit.0.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.19.name=TriggerPort0[19] |
| unit.0.0.port.0.s.19.orderindex=-1 |
| unit.0.0.port.0.s.19.visible=1 |
| unit.0.0.port.0.s.2.alias=5 MHz |
| unit.0.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.2.display=14 |
| unit.0.0.port.0.s.2.name=SyncIn[2] |
| unit.0.0.port.0.s.2.orderindex=-1 |
| unit.0.0.port.0.s.2.persistence=0 |
| unit.0.0.port.0.s.2.value=0 |
| unit.0.0.port.0.s.2.visible=1 |
| unit.0.0.port.0.s.20.alias= |
| unit.0.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.20.name=TriggerPort0[20] |
| unit.0.0.port.0.s.20.orderindex=-1 |
| unit.0.0.port.0.s.20.visible=1 |
| unit.0.0.port.0.s.21.alias= |
| unit.0.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.21.name=TriggerPort0[21] |
| unit.0.0.port.0.s.21.orderindex=-1 |
| unit.0.0.port.0.s.21.visible=1 |
| unit.0.0.port.0.s.22.alias= |
| unit.0.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.22.name=TriggerPort0[22] |
| unit.0.0.port.0.s.22.orderindex=-1 |
| unit.0.0.port.0.s.22.visible=1 |
| unit.0.0.port.0.s.23.alias= |
| unit.0.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.23.name=TriggerPort0[23] |
| unit.0.0.port.0.s.23.orderindex=-1 |
| unit.0.0.port.0.s.23.visible=1 |
| unit.0.0.port.0.s.3.alias=10 MHz |
| unit.0.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.3.display=14 |
| unit.0.0.port.0.s.3.name=SyncIn[3] |
| unit.0.0.port.0.s.3.orderindex=-1 |
| unit.0.0.port.0.s.3.persistence=0 |
| unit.0.0.port.0.s.3.value=0 |
| unit.0.0.port.0.s.3.visible=1 |
| unit.0.0.port.0.s.4.alias=20 MHz |
| unit.0.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.4.display=14 |
| unit.0.0.port.0.s.4.name=SyncIn[4] |
| unit.0.0.port.0.s.4.orderindex=-1 |
| unit.0.0.port.0.s.4.persistence=0 |
| unit.0.0.port.0.s.4.value=0 |
| unit.0.0.port.0.s.4.visible=1 |
| unit.0.0.port.0.s.5.alias=50 MHz |
| unit.0.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.5.display=14 |
| unit.0.0.port.0.s.5.name=SyncIn[5] |
| unit.0.0.port.0.s.5.orderindex=-1 |
| unit.0.0.port.0.s.5.persistence=0 |
| unit.0.0.port.0.s.5.value=0 |
| unit.0.0.port.0.s.5.visible=1 |
| unit.0.0.port.0.s.6.alias=100 MHz |
| unit.0.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.6.display=14 |
| unit.0.0.port.0.s.6.name=SyncIn[6] |
| unit.0.0.port.0.s.6.orderindex=-1 |
| unit.0.0.port.0.s.6.persistence=0 |
| unit.0.0.port.0.s.6.value=0 |
| unit.0.0.port.0.s.6.visible=1 |
| unit.0.0.port.0.s.7.alias=170 MHz |
| unit.0.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.7.display=14 |
| unit.0.0.port.0.s.7.name=SyncIn[7] |
| unit.0.0.port.0.s.7.orderindex=-1 |
| unit.0.0.port.0.s.7.persistence=0 |
| unit.0.0.port.0.s.7.value=0 |
| unit.0.0.port.0.s.7.visible=1 |
| unit.0.0.port.0.s.8.alias= |
| unit.0.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.8.name=TriggerPort0[8] |
| unit.0.0.port.0.s.8.orderindex=-1 |
| unit.0.0.port.0.s.8.visible=1 |
| unit.0.0.port.0.s.9.alias= |
| unit.0.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.9.name=TriggerPort0[9] |
| unit.0.0.port.0.s.9.orderindex=-1 |
| unit.0.0.port.0.s.9.visible=1 |
| unit.0.0.port.1.buscount=0 |
| unit.0.0.port.1.channelcount=0 |
| unit.0.0.port.2.buscount=0 |
| unit.0.0.port.2.channelcount=8 |
| unit.0.0.port.2.s.0.alias=Set 1 MHz |
| unit.0.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.0.display=5 |
| unit.0.0.port.2.s.0.name=SyncOut[0] |
| unit.0.0.port.2.s.0.orderindex=-1 |
| unit.0.0.port.2.s.0.persistence=0 |
| unit.0.0.port.2.s.0.value=0100000000000000 |
| unit.0.0.port.2.s.0.visible=1 |
| unit.0.0.port.2.s.1.alias=Set 2 MHz |
| unit.0.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.1.display=5 |
| unit.0.0.port.2.s.1.name=SyncOut[1] |
| unit.0.0.port.2.s.1.orderindex=-1 |
| unit.0.0.port.2.s.1.persistence=0 |
| unit.0.0.port.2.s.1.value=0100000000000000 |
| unit.0.0.port.2.s.1.visible=1 |
| unit.0.0.port.2.s.2.alias=Set 5 MHz |
| unit.0.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.2.display=5 |
| unit.0.0.port.2.s.2.name=SyncOut[2] |
| unit.0.0.port.2.s.2.orderindex=-1 |
| unit.0.0.port.2.s.2.persistence=0 |
| unit.0.0.port.2.s.2.value=0100000000000000 |
| unit.0.0.port.2.s.2.visible=1 |
| unit.0.0.port.2.s.3.alias=Set 10 MHz |
| unit.0.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.3.display=5 |
| unit.0.0.port.2.s.3.name=SyncOut[3] |
| unit.0.0.port.2.s.3.orderindex=-1 |
| unit.0.0.port.2.s.3.persistence=0 |
| unit.0.0.port.2.s.3.value=0000000000000000 |
| unit.0.0.port.2.s.3.visible=1 |
| unit.0.0.port.2.s.4.alias=Set 20 MHz |
| unit.0.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.4.display=5 |
| unit.0.0.port.2.s.4.name=SyncOut[4] |
| unit.0.0.port.2.s.4.orderindex=-1 |
| unit.0.0.port.2.s.4.persistence=0 |
| unit.0.0.port.2.s.4.value=0100000000000000 |
| unit.0.0.port.2.s.4.visible=1 |
| unit.0.0.port.2.s.5.alias=Set 50 MHz |
| unit.0.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.5.display=5 |
| unit.0.0.port.2.s.5.name=SyncOut[5] |
| unit.0.0.port.2.s.5.orderindex=-1 |
| unit.0.0.port.2.s.5.persistence=0 |
| unit.0.0.port.2.s.5.value=0000000000000000 |
| unit.0.0.port.2.s.5.visible=1 |
| unit.0.0.port.2.s.6.alias=Set 100 MHz |
| unit.0.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.6.display=5 |
| unit.0.0.port.2.s.6.name=SyncOut[6] |
| unit.0.0.port.2.s.6.orderindex=-1 |
| unit.0.0.port.2.s.6.persistence=0 |
| unit.0.0.port.2.s.6.value=0100000000000000 |
| unit.0.0.port.2.s.6.visible=1 |
| unit.0.0.port.2.s.7.alias=Set 170 MHz |
| unit.0.0.port.2.s.7.color=java.awt.Color[r\=100,g\=0,b\=124] |
| unit.0.0.port.2.s.7.display=5 |
| unit.0.0.port.2.s.7.name=SyncOut[7] |
| unit.0.0.port.2.s.7.orderindex=-1 |
| unit.0.0.port.2.s.7.persistence=0 |
| unit.0.0.port.2.s.7.value=0100000000000000 |
| unit.0.0.port.2.s.7.visible=1 |
| unit.0.0.portcount=3 |
| unit.0.0.rep_trigger.clobber=1 |
| unit.0.0.rep_trigger.dir=C\:\\Users\\miho |
| unit.0.0.rep_trigger.filename=waveform |
| unit.0.0.rep_trigger.format=ASCII |
| unit.0.0.rep_trigger.loggingEnabled=0 |
| unit.0.0.rep_trigger.signals=All Signals/Buses |
| unit.0.0.samplesPerTrigger=1 |
| unit.0.0.triggerCapture=1 |
| unit.0.0.triggerNSamplesTS=0 |
| unit.0.0.triggerPosition=0 |
| unit.0.0.triggerWindowCount=1 |
| unit.0.0.triggerWindowDepth=1024 |
| unit.0.0.triggerWindowTS=0 |
| unit.0.0.username=Set Frequency |
| unit.0.0.vio.count=16 |
| unit.0.0.vio.posn.0.channel=0 |
| unit.0.0.vio.posn.0.name=1 MHz |
| unit.0.0.vio.posn.0.port=0 |
| unit.0.0.vio.posn.0.type=signal |
| unit.0.0.vio.posn.1.channel=1 |
| unit.0.0.vio.posn.1.name=2 MHz |
| unit.0.0.vio.posn.1.port=0 |
| unit.0.0.vio.posn.1.type=signal |
| unit.0.0.vio.posn.10.channel=2 |
| unit.0.0.vio.posn.10.name=Set 5 MHz |
| unit.0.0.vio.posn.10.port=2 |
| unit.0.0.vio.posn.10.type=signal |
| unit.0.0.vio.posn.11.channel=3 |
| unit.0.0.vio.posn.11.name=Set 10 MHz |
| unit.0.0.vio.posn.11.port=2 |
| unit.0.0.vio.posn.11.type=signal |
| unit.0.0.vio.posn.12.channel=4 |
| unit.0.0.vio.posn.12.name=Set 20 MHz |
| unit.0.0.vio.posn.12.port=2 |
| unit.0.0.vio.posn.12.type=signal |
| unit.0.0.vio.posn.13.channel=5 |
| unit.0.0.vio.posn.13.name=Set 50 MHz |
| unit.0.0.vio.posn.13.port=2 |
| unit.0.0.vio.posn.13.type=signal |
| unit.0.0.vio.posn.14.channel=6 |
| unit.0.0.vio.posn.14.name=Set 100 MHz |
| unit.0.0.vio.posn.14.port=2 |
| unit.0.0.vio.posn.14.type=signal |
| unit.0.0.vio.posn.15.channel=7 |
| unit.0.0.vio.posn.15.name=Set 170 MHz |
| unit.0.0.vio.posn.15.port=2 |
| unit.0.0.vio.posn.15.type=signal |
| unit.0.0.vio.posn.2.channel=2 |
| unit.0.0.vio.posn.2.name=5 MHz |
| unit.0.0.vio.posn.2.port=0 |
| unit.0.0.vio.posn.2.type=signal |
| unit.0.0.vio.posn.3.channel=3 |
| unit.0.0.vio.posn.3.name=10 MHz |
| unit.0.0.vio.posn.3.port=0 |
| unit.0.0.vio.posn.3.type=signal |
| unit.0.0.vio.posn.4.channel=4 |
| unit.0.0.vio.posn.4.name=20 MHz |
| unit.0.0.vio.posn.4.port=0 |
| unit.0.0.vio.posn.4.type=signal |
| unit.0.0.vio.posn.5.channel=5 |
| unit.0.0.vio.posn.5.name=50 MHz |
| unit.0.0.vio.posn.5.port=0 |
| unit.0.0.vio.posn.5.type=signal |
| unit.0.0.vio.posn.6.channel=6 |
| unit.0.0.vio.posn.6.name=100 MHz |
| unit.0.0.vio.posn.6.port=0 |
| unit.0.0.vio.posn.6.type=signal |
| unit.0.0.vio.posn.7.channel=7 |
| unit.0.0.vio.posn.7.name=170 MHz |
| unit.0.0.vio.posn.7.port=0 |
| unit.0.0.vio.posn.7.type=signal |
| unit.0.0.vio.posn.8.channel=0 |
| unit.0.0.vio.posn.8.name=Set 1 MHz |
| unit.0.0.vio.posn.8.port=2 |
| unit.0.0.vio.posn.8.type=signal |
| unit.0.0.vio.posn.9.channel=1 |
| unit.0.0.vio.posn.9.name=Set 2 MHz |
| unit.0.0.vio.posn.9.port=2 |
| unit.0.0.vio.posn.9.type=signal |
| unit.0.0.vio.readperiod=0 |
| unit.0.0.waveform.count=24 |
| unit.0.0.waveform.posn.0.channel=0 |
| unit.0.0.waveform.posn.0.name=DataPort[0] |
| unit.0.0.waveform.posn.0.type=signal |
| unit.0.0.waveform.posn.1.channel=1 |
| unit.0.0.waveform.posn.1.name=DataPort[1] |
| unit.0.0.waveform.posn.1.type=signal |
| unit.0.0.waveform.posn.10.channel=10 |
| unit.0.0.waveform.posn.10.name=DataPort[10] |
| unit.0.0.waveform.posn.10.type=signal |
| unit.0.0.waveform.posn.11.channel=11 |
| unit.0.0.waveform.posn.11.name=DataPort[11] |
| unit.0.0.waveform.posn.11.type=signal |
| unit.0.0.waveform.posn.12.channel=12 |
| unit.0.0.waveform.posn.12.name=DataPort[12] |
| unit.0.0.waveform.posn.12.type=signal |
| unit.0.0.waveform.posn.13.channel=13 |
| unit.0.0.waveform.posn.13.name=DataPort[13] |
| unit.0.0.waveform.posn.13.type=signal |
| unit.0.0.waveform.posn.14.channel=14 |
| unit.0.0.waveform.posn.14.name=DataPort[14] |
| unit.0.0.waveform.posn.14.type=signal |
| unit.0.0.waveform.posn.15.channel=15 |
| unit.0.0.waveform.posn.15.name=DataPort[15] |
| unit.0.0.waveform.posn.15.type=signal |
| unit.0.0.waveform.posn.16.channel=16 |
| unit.0.0.waveform.posn.16.name=DataPort[16] |
| unit.0.0.waveform.posn.16.type=signal |
| unit.0.0.waveform.posn.17.channel=17 |
| unit.0.0.waveform.posn.17.name=DataPort[17] |
| unit.0.0.waveform.posn.17.type=signal |
| unit.0.0.waveform.posn.18.channel=18 |
| unit.0.0.waveform.posn.18.name=DataPort[18] |
| unit.0.0.waveform.posn.18.type=signal |
| unit.0.0.waveform.posn.19.channel=19 |
| unit.0.0.waveform.posn.19.name=DataPort[19] |
| unit.0.0.waveform.posn.19.type=signal |
| unit.0.0.waveform.posn.2.channel=2 |
| unit.0.0.waveform.posn.2.name=DataPort[2] |
| unit.0.0.waveform.posn.2.type=signal |
| unit.0.0.waveform.posn.20.channel=20 |
| unit.0.0.waveform.posn.20.name=DataPort[20] |
| unit.0.0.waveform.posn.20.type=signal |
| unit.0.0.waveform.posn.21.channel=21 |
| unit.0.0.waveform.posn.21.name=DataPort[21] |
| unit.0.0.waveform.posn.21.type=signal |
| unit.0.0.waveform.posn.22.channel=22 |
| unit.0.0.waveform.posn.22.name=DataPort[22] |
| unit.0.0.waveform.posn.22.type=signal |
| unit.0.0.waveform.posn.23.channel=23 |
| unit.0.0.waveform.posn.23.name=DataPort[23] |
| unit.0.0.waveform.posn.23.type=signal |
| unit.0.0.waveform.posn.3.channel=3 |
| unit.0.0.waveform.posn.3.name=DataPort[3] |
| unit.0.0.waveform.posn.3.type=signal |
| unit.0.0.waveform.posn.4.channel=4 |
| unit.0.0.waveform.posn.4.name=DataPort[4] |
| unit.0.0.waveform.posn.4.type=signal |
| unit.0.0.waveform.posn.5.channel=5 |
| unit.0.0.waveform.posn.5.name=DataPort[5] |
| unit.0.0.waveform.posn.5.type=signal |
| unit.0.0.waveform.posn.6.channel=6 |
| unit.0.0.waveform.posn.6.name=DataPort[6] |
| unit.0.0.waveform.posn.6.type=signal |
| unit.0.0.waveform.posn.7.channel=7 |
| unit.0.0.waveform.posn.7.name=DataPort[7] |
| unit.0.0.waveform.posn.7.type=signal |
| unit.0.0.waveform.posn.8.channel=8 |
| unit.0.0.waveform.posn.8.name=DataPort[8] |
| unit.0.0.waveform.posn.8.type=signal |
| unit.0.0.waveform.posn.9.channel=9 |
| unit.0.0.waveform.posn.9.name=DataPort[9] |
| unit.0.0.waveform.posn.9.type=signal |
| unit.0.1.6.HEIGHT6=0.23296355 |
| unit.0.1.6.WIDTH6=0.17021276 |
| unit.0.1.6.X6=8.510638E-4 |
| unit.0.1.6.Y6=0.7717908 |
| unit.0.1.coretype=VIO |
| unit.0.1.port.-1.buscount=0 |
| unit.0.1.port.-1.channelcount=0 |
| unit.0.1.port.0.buscount=0 |
| unit.0.1.port.0.channelcount=0 |
| unit.0.1.port.1.buscount=0 |
| unit.0.1.port.1.channelcount=0 |
| unit.0.1.port.2.buscount=0 |
| unit.0.1.port.2.channelcount=3 |
| unit.0.1.port.2.s.0.alias=VS[0] |
| unit.0.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.1.port.2.s.0.display=3 |
| unit.0.1.port.2.s.0.name=SyncOut[0] |
| unit.0.1.port.2.s.0.orderindex=-1 |
| unit.0.1.port.2.s.0.persistence=0 |
| unit.0.1.port.2.s.0.value=0 |
| unit.0.1.port.2.s.0.visible=1 |
| unit.0.1.port.2.s.1.alias=VS[1] |
| unit.0.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.1.port.2.s.1.display=3 |
| unit.0.1.port.2.s.1.name=SyncOut[1] |
| unit.0.1.port.2.s.1.orderindex=-1 |
| unit.0.1.port.2.s.1.persistence=0 |
| unit.0.1.port.2.s.1.value=0 |
| unit.0.1.port.2.s.1.visible=1 |
| unit.0.1.port.2.s.2.alias=VS[2] |
| unit.0.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.1.port.2.s.2.display=3 |
| unit.0.1.port.2.s.2.name=SyncOut[2] |
| unit.0.1.port.2.s.2.orderindex=-1 |
| unit.0.1.port.2.s.2.persistence=0 |
| unit.0.1.port.2.s.2.value=0 |
| unit.0.1.port.2.s.2.visible=1 |
| unit.0.1.portcount=3 |
| unit.0.1.username=Set User Output |
| unit.0.1.vio.count=3 |
| unit.0.1.vio.posn.0.channel=0 |
| unit.0.1.vio.posn.0.name=VS[0] |
| unit.0.1.vio.posn.0.port=2 |
| unit.0.1.vio.posn.0.type=signal |
| unit.0.1.vio.posn.1.channel=1 |
| unit.0.1.vio.posn.1.name=VS[1] |
| unit.0.1.vio.posn.1.port=2 |
| unit.0.1.vio.posn.1.type=signal |
| unit.0.1.vio.posn.2.channel=2 |
| unit.0.1.vio.posn.2.name=VS[2] |
| unit.0.1.vio.posn.2.port=2 |
| unit.0.1.vio.posn.2.type=signal |
| unit.0.1.vio.readperiod=0 |
| unit.0.2.0.HEIGHT0=0.79873216 |
| unit.0.2.0.TriggerRow0=1 |
| unit.0.2.0.TriggerRow1=1 |
| unit.0.2.0.TriggerRow2=1 |
| unit.0.2.0.WIDTH0=0.99659574 |
| unit.0.2.0.X0=0.0 |
| unit.0.2.0.Y0=0.0 |
| unit.0.2.1.HEIGHT1=0.9191759 |
| unit.0.2.1.WIDTH1=0.9361702 |
| unit.0.2.1.X1=0.015319149 |
| unit.0.2.1.Y1=0.08082409 |
| unit.0.2.2.HEIGHT2=0.42472267 |
| unit.0.2.2.WIDTH2=0.91574466 |
| unit.0.2.2.X2=0.08425532 |
| unit.0.2.2.Y2=0.5229794 |
| unit.0.2.5.HEIGHT5=0.42472267 |
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| unit.0.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.2.port.0.s.8.name=TriggerPort0[8] |
| unit.0.2.port.0.s.8.orderindex=-1 |
| unit.0.2.port.0.s.8.visible=1 |
| unit.0.2.port.0.s.9.alias= |
| unit.0.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] |
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| unit.0.2.port.0.s.9.visible=1 |
| unit.0.2.portcount=1 |
| unit.0.2.rep_trigger.clobber=1 |
| unit.0.2.rep_trigger.dir=D\:\\MLAB\\Modules\\CPLD_FPGA\\XILINX_ChipScope\\MAKE\\BIN\\13.3 |
| unit.0.2.rep_trigger.filename=waveform |
| unit.0.2.rep_trigger.format=ASCII |
| unit.0.2.rep_trigger.loggingEnabled=0 |
| unit.0.2.rep_trigger.signals=All Signals/Buses |
| unit.0.2.samplesPerTrigger=1 |
| unit.0.2.triggerCapture=1 |
| unit.0.2.triggerNSamplesTS=0 |
| unit.0.2.triggerPosition=0 |
| unit.0.2.triggerWindowCount=1 |
| unit.0.2.triggerWindowDepth=1024 |
| unit.0.2.triggerWindowTS=0 |
| unit.0.2.username=Logic Analyser |
| unit.0.2.waveform.count=18 |
| unit.0.2.waveform.posn.0.channel=0 |
| unit.0.2.waveform.posn.0.name=P[0] |
| unit.0.2.waveform.posn.0.type=signal |
| unit.0.2.waveform.posn.1.channel=1 |
| unit.0.2.waveform.posn.1.name=P[1] |
| unit.0.2.waveform.posn.1.type=signal |
| unit.0.2.waveform.posn.10.channel=10 |
| unit.0.2.waveform.posn.10.name=P[10] |
| unit.0.2.waveform.posn.10.type=signal |
| unit.0.2.waveform.posn.11.channel=11 |
| unit.0.2.waveform.posn.11.name=P[11] |
| unit.0.2.waveform.posn.11.type=signal |
| unit.0.2.waveform.posn.12.channel=12 |
| unit.0.2.waveform.posn.12.name=P[12] |
| unit.0.2.waveform.posn.12.type=signal |
| unit.0.2.waveform.posn.13.channel=13 |
| unit.0.2.waveform.posn.13.name=P[13] |
| unit.0.2.waveform.posn.13.type=signal |
| unit.0.2.waveform.posn.14.channel=14 |
| unit.0.2.waveform.posn.14.name=P[14] |
| unit.0.2.waveform.posn.14.type=signal |
| unit.0.2.waveform.posn.15.channel=15 |
| unit.0.2.waveform.posn.15.name=P[15] |
| unit.0.2.waveform.posn.15.type=signal |
| unit.0.2.waveform.posn.16.channel=16 |
| unit.0.2.waveform.posn.16.name=P[16] |
| unit.0.2.waveform.posn.16.type=signal |
| unit.0.2.waveform.posn.17.channel=17 |
| unit.0.2.waveform.posn.17.name=P[17] |
| unit.0.2.waveform.posn.17.type=signal |
| unit.0.2.waveform.posn.2.channel=2 |
| unit.0.2.waveform.posn.2.name=P[2] |
| unit.0.2.waveform.posn.2.type=signal |
| unit.0.2.waveform.posn.3.channel=3 |
| unit.0.2.waveform.posn.3.name=P[3] |
| unit.0.2.waveform.posn.3.type=signal |
| unit.0.2.waveform.posn.4.channel=4 |
| unit.0.2.waveform.posn.4.name=P[4] |
| unit.0.2.waveform.posn.4.type=signal |
| unit.0.2.waveform.posn.5.channel=5 |
| unit.0.2.waveform.posn.5.name=P[5] |
| unit.0.2.waveform.posn.5.type=signal |
| unit.0.2.waveform.posn.6.channel=6 |
| unit.0.2.waveform.posn.6.name=P[6] |
| unit.0.2.waveform.posn.6.type=signal |
| unit.0.2.waveform.posn.7.channel=7 |
| unit.0.2.waveform.posn.7.name=P[7] |
| unit.0.2.waveform.posn.7.type=signal |
| unit.0.2.waveform.posn.8.channel=8 |
| unit.0.2.waveform.posn.8.name=P[8] |
| unit.0.2.waveform.posn.8.type=signal |
| unit.0.2.waveform.posn.9.channel=9 |
| unit.0.2.waveform.posn.9.name=P[9] |
| unit.0.2.waveform.posn.9.type=signal |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser_9_2048.cpj |
|---|
| 0,0 → 1,1076 |
| #ChipScope Pro Analyzer Project File, Version 3.0 |
| #Tue Jun 25 09:45:10 CEST 2013 |
| device.0.configFileDir=..\\BIN |
| device.0.configFilename=S3AN01_ChipScope_9x2048.bit |
| device.0.inserterCDCFileDir= |
| device.0.inserterCDCFilename= |
| deviceChain.deviceName0=XC3S50AN |
| deviceChain.iRLength0=6 |
| deviceChain.name0=Trigger Setup |
| deviceIds=02610093 |
| mdiAreaHeight=0.6990077177508269 |
| mdiAreaHeightLast=0.6990077177508269 |
| mdiCount=4 |
| mdiDevice0=0 |
| mdiDevice1=0 |
| mdiDevice2=0 |
| mdiDevice3=0 |
| mdiType0=1 |
| mdiType1=6 |
| mdiType2=0 |
| mdiType3=6 |
| mdiUnit0=2 |
| mdiUnit1=1 |
| mdiUnit2=2 |
| mdiUnit3=0 |
| navigatorHeight=0.24696802646085997 |
| navigatorHeightLast=0.2866593164277839 |
| navigatorWidth=0.17472375690607736 |
| navigatorWidthLast=0.14433701657458564 |
| signalDisplayPath=0 |
| unit.-1.-1.username= |
| unit.0.-1.username= |
| unit.0.0.0.HEIGHT0=0.3660856 |
| unit.0.0.0.TriggerRow0=1 |
| unit.0.0.0.TriggerRow1=1 |
| unit.0.0.0.TriggerRow2=1 |
| unit.0.0.0.WIDTH0=0.9940426 |
| unit.0.0.0.X0=0.0 |
| unit.0.0.0.Y0=0.0 |
| unit.0.0.1.HEIGHT1=0.58161646 |
| unit.0.0.1.WIDTH1=0.9940426 |
| unit.0.0.1.X1=0.0 |
| unit.0.0.1.Y1=0.3660856 |
| unit.0.0.6.HEIGHT6=0.75594294 |
| unit.0.0.6.WIDTH6=0.17021276 |
| unit.0.0.6.X6=0.0025531915 |
| unit.0.0.6.Y6=0.014263075 |
| unit.0.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXX |
| unit.0.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXX |
| unit.0.0.MFBitsB0=000000000000000000000000 |
| unit.0.0.MFBitsB1=000000000000000000000000 |
| unit.0.0.MFCompareA0=0 |
| unit.0.0.MFCompareA1=0 |
| unit.0.0.MFCompareB0=999 |
| unit.0.0.MFCompareB1=999 |
| unit.0.0.MFCount=2 |
| unit.0.0.MFDisplay0=0 |
| unit.0.0.MFDisplay1=0 |
| unit.0.0.MFEventType0=3 |
| unit.0.0.MFEventType1=3 |
| unit.0.0.RunMode=SINGLE RUN |
| unit.0.0.SQCondition=All Data |
| unit.0.0.SQContiguous0=0 |
| unit.0.0.SequencerOn=0 |
| unit.0.0.TCActive=0 |
| unit.0.0.TCAdvanced0=0 |
| unit.0.0.TCCondition0_0=M0 |
| unit.0.0.TCCondition0_1= |
| unit.0.0.TCConditionType0=0 |
| unit.0.0.TCCount=1 |
| unit.0.0.TCEventCount0=1 |
| unit.0.0.TCEventType0=3 |
| unit.0.0.TCName0=TriggerCondition0 |
| unit.0.0.TCOutputEnable0=0 |
| unit.0.0.TCOutputHigh0=1 |
| unit.0.0.TCOutputMode0=0 |
| unit.0.0.coretype=VIO |
| unit.0.0.eventCount0=1 |
| unit.0.0.eventCount1=1 |
| unit.0.0.port.-1.buscount=0 |
| unit.0.0.port.-1.channelcount=0 |
| unit.0.0.port.-1.s.0.alias= |
| unit.0.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.0.name=DataPort[0] |
| unit.0.0.port.-1.s.0.orderindex=-1 |
| unit.0.0.port.-1.s.0.visible=1 |
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| unit.0.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.-1.s.1.name=DataPort[1] |
| unit.0.0.port.-1.s.1.orderindex=-1 |
| unit.0.0.port.-1.s.1.visible=1 |
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| unit.0.0.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] |
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| unit.0.0.port.0.s.18.visible=1 |
| unit.0.0.port.0.s.19.alias= |
| unit.0.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.19.name=TriggerPort0[19] |
| unit.0.0.port.0.s.19.orderindex=-1 |
| unit.0.0.port.0.s.19.visible=1 |
| unit.0.0.port.0.s.2.alias=5 MHz |
| unit.0.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.2.display=14 |
| unit.0.0.port.0.s.2.name=SyncIn[2] |
| unit.0.0.port.0.s.2.orderindex=-1 |
| unit.0.0.port.0.s.2.persistence=0 |
| unit.0.0.port.0.s.2.value=0 |
| unit.0.0.port.0.s.2.visible=1 |
| unit.0.0.port.0.s.20.alias= |
| unit.0.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.20.name=TriggerPort0[20] |
| unit.0.0.port.0.s.20.orderindex=-1 |
| unit.0.0.port.0.s.20.visible=1 |
| unit.0.0.port.0.s.21.alias= |
| unit.0.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.21.name=TriggerPort0[21] |
| unit.0.0.port.0.s.21.orderindex=-1 |
| unit.0.0.port.0.s.21.visible=1 |
| unit.0.0.port.0.s.22.alias= |
| unit.0.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.22.name=TriggerPort0[22] |
| unit.0.0.port.0.s.22.orderindex=-1 |
| unit.0.0.port.0.s.22.visible=1 |
| unit.0.0.port.0.s.23.alias= |
| unit.0.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.23.name=TriggerPort0[23] |
| unit.0.0.port.0.s.23.orderindex=-1 |
| unit.0.0.port.0.s.23.visible=1 |
| unit.0.0.port.0.s.3.alias=10 MHz |
| unit.0.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.3.display=14 |
| unit.0.0.port.0.s.3.name=SyncIn[3] |
| unit.0.0.port.0.s.3.orderindex=-1 |
| unit.0.0.port.0.s.3.persistence=0 |
| unit.0.0.port.0.s.3.value=0 |
| unit.0.0.port.0.s.3.visible=1 |
| unit.0.0.port.0.s.4.alias=20 MHz |
| unit.0.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.4.display=14 |
| unit.0.0.port.0.s.4.name=SyncIn[4] |
| unit.0.0.port.0.s.4.orderindex=-1 |
| unit.0.0.port.0.s.4.persistence=0 |
| unit.0.0.port.0.s.4.value=0 |
| unit.0.0.port.0.s.4.visible=1 |
| unit.0.0.port.0.s.5.alias=50 MHz |
| unit.0.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.5.display=14 |
| unit.0.0.port.0.s.5.name=SyncIn[5] |
| unit.0.0.port.0.s.5.orderindex=-1 |
| unit.0.0.port.0.s.5.persistence=0 |
| unit.0.0.port.0.s.5.value=0 |
| unit.0.0.port.0.s.5.visible=1 |
| unit.0.0.port.0.s.6.alias=100 MHz |
| unit.0.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.6.display=14 |
| unit.0.0.port.0.s.6.name=SyncIn[6] |
| unit.0.0.port.0.s.6.orderindex=-1 |
| unit.0.0.port.0.s.6.persistence=0 |
| unit.0.0.port.0.s.6.value=0 |
| unit.0.0.port.0.s.6.visible=1 |
| unit.0.0.port.0.s.7.alias=170 MHz |
| unit.0.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.7.display=14 |
| unit.0.0.port.0.s.7.name=SyncIn[7] |
| unit.0.0.port.0.s.7.orderindex=-1 |
| unit.0.0.port.0.s.7.persistence=0 |
| unit.0.0.port.0.s.7.value=0 |
| unit.0.0.port.0.s.7.visible=1 |
| unit.0.0.port.0.s.8.alias= |
| unit.0.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.8.name=TriggerPort0[8] |
| unit.0.0.port.0.s.8.orderindex=-1 |
| unit.0.0.port.0.s.8.visible=1 |
| unit.0.0.port.0.s.9.alias= |
| unit.0.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.0.s.9.name=TriggerPort0[9] |
| unit.0.0.port.0.s.9.orderindex=-1 |
| unit.0.0.port.0.s.9.visible=1 |
| unit.0.0.port.1.buscount=0 |
| unit.0.0.port.1.channelcount=0 |
| unit.0.0.port.2.buscount=0 |
| unit.0.0.port.2.channelcount=8 |
| unit.0.0.port.2.s.0.alias=Set 1 MHz |
| unit.0.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.0.display=5 |
| unit.0.0.port.2.s.0.name=SyncOut[0] |
| unit.0.0.port.2.s.0.orderindex=-1 |
| unit.0.0.port.2.s.0.persistence=0 |
| unit.0.0.port.2.s.0.value=0100000000000000 |
| unit.0.0.port.2.s.0.visible=1 |
| unit.0.0.port.2.s.1.alias=Set 2 MHz |
| unit.0.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.1.display=5 |
| unit.0.0.port.2.s.1.name=SyncOut[1] |
| unit.0.0.port.2.s.1.orderindex=-1 |
| unit.0.0.port.2.s.1.persistence=0 |
| unit.0.0.port.2.s.1.value=0100000000000000 |
| unit.0.0.port.2.s.1.visible=1 |
| unit.0.0.port.2.s.2.alias=Set 5 MHz |
| unit.0.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.2.display=5 |
| unit.0.0.port.2.s.2.name=SyncOut[2] |
| unit.0.0.port.2.s.2.orderindex=-1 |
| unit.0.0.port.2.s.2.persistence=0 |
| unit.0.0.port.2.s.2.value=0100000000000000 |
| unit.0.0.port.2.s.2.visible=1 |
| unit.0.0.port.2.s.3.alias=Set 10 MHz |
| unit.0.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.3.display=5 |
| unit.0.0.port.2.s.3.name=SyncOut[3] |
| unit.0.0.port.2.s.3.orderindex=-1 |
| unit.0.0.port.2.s.3.persistence=0 |
| unit.0.0.port.2.s.3.value=0100000000000000 |
| unit.0.0.port.2.s.3.visible=1 |
| unit.0.0.port.2.s.4.alias=Set 20 MHz |
| unit.0.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.4.display=5 |
| unit.0.0.port.2.s.4.name=SyncOut[4] |
| unit.0.0.port.2.s.4.orderindex=-1 |
| unit.0.0.port.2.s.4.persistence=0 |
| unit.0.0.port.2.s.4.value=0100000000000000 |
| unit.0.0.port.2.s.4.visible=1 |
| unit.0.0.port.2.s.5.alias=Set 50 MHz |
| unit.0.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.5.display=5 |
| unit.0.0.port.2.s.5.name=SyncOut[5] |
| unit.0.0.port.2.s.5.orderindex=-1 |
| unit.0.0.port.2.s.5.persistence=0 |
| unit.0.0.port.2.s.5.value=0100000000000000 |
| unit.0.0.port.2.s.5.visible=1 |
| unit.0.0.port.2.s.6.alias=Set 100 MHz |
| unit.0.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.6.display=5 |
| unit.0.0.port.2.s.6.name=SyncOut[6] |
| unit.0.0.port.2.s.6.orderindex=-1 |
| unit.0.0.port.2.s.6.persistence=0 |
| unit.0.0.port.2.s.6.value=0100000000000000 |
| unit.0.0.port.2.s.6.visible=1 |
| unit.0.0.port.2.s.7.alias=Set 170 MHz |
| unit.0.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.0.port.2.s.7.display=5 |
| unit.0.0.port.2.s.7.name=SyncOut[7] |
| unit.0.0.port.2.s.7.orderindex=-1 |
| unit.0.0.port.2.s.7.persistence=0 |
| unit.0.0.port.2.s.7.value=0100000000000000 |
| unit.0.0.port.2.s.7.visible=1 |
| unit.0.0.portcount=3 |
| unit.0.0.rep_trigger.clobber=1 |
| unit.0.0.rep_trigger.dir=C\:\\Users\\miho |
| unit.0.0.rep_trigger.filename=waveform |
| unit.0.0.rep_trigger.format=ASCII |
| unit.0.0.rep_trigger.loggingEnabled=0 |
| unit.0.0.rep_trigger.signals=All Signals/Buses |
| unit.0.0.samplesPerTrigger=1 |
| unit.0.0.triggerCapture=1 |
| unit.0.0.triggerNSamplesTS=0 |
| unit.0.0.triggerPosition=0 |
| unit.0.0.triggerWindowCount=1 |
| unit.0.0.triggerWindowDepth=1024 |
| unit.0.0.triggerWindowTS=0 |
| unit.0.0.username=Set Frequency |
| unit.0.0.vio.count=16 |
| unit.0.0.vio.posn.0.channel=0 |
| unit.0.0.vio.posn.0.name=1 MHz |
| unit.0.0.vio.posn.0.port=0 |
| unit.0.0.vio.posn.0.type=signal |
| unit.0.0.vio.posn.1.channel=1 |
| unit.0.0.vio.posn.1.name=2 MHz |
| unit.0.0.vio.posn.1.port=0 |
| unit.0.0.vio.posn.1.type=signal |
| unit.0.0.vio.posn.10.channel=2 |
| unit.0.0.vio.posn.10.name=Set 5 MHz |
| unit.0.0.vio.posn.10.port=2 |
| unit.0.0.vio.posn.10.type=signal |
| unit.0.0.vio.posn.11.channel=3 |
| unit.0.0.vio.posn.11.name=Set 10 MHz |
| unit.0.0.vio.posn.11.port=2 |
| unit.0.0.vio.posn.11.type=signal |
| unit.0.0.vio.posn.12.channel=4 |
| unit.0.0.vio.posn.12.name=Set 20 MHz |
| unit.0.0.vio.posn.12.port=2 |
| unit.0.0.vio.posn.12.type=signal |
| unit.0.0.vio.posn.13.channel=5 |
| unit.0.0.vio.posn.13.name=Set 50 MHz |
| unit.0.0.vio.posn.13.port=2 |
| unit.0.0.vio.posn.13.type=signal |
| unit.0.0.vio.posn.14.channel=6 |
| unit.0.0.vio.posn.14.name=Set 100 MHz |
| unit.0.0.vio.posn.14.port=2 |
| unit.0.0.vio.posn.14.type=signal |
| unit.0.0.vio.posn.15.channel=7 |
| unit.0.0.vio.posn.15.name=Set 170 MHz |
| unit.0.0.vio.posn.15.port=2 |
| unit.0.0.vio.posn.15.type=signal |
| unit.0.0.vio.posn.2.channel=2 |
| unit.0.0.vio.posn.2.name=5 MHz |
| unit.0.0.vio.posn.2.port=0 |
| unit.0.0.vio.posn.2.type=signal |
| unit.0.0.vio.posn.3.channel=3 |
| unit.0.0.vio.posn.3.name=10 MHz |
| unit.0.0.vio.posn.3.port=0 |
| unit.0.0.vio.posn.3.type=signal |
| unit.0.0.vio.posn.4.channel=4 |
| unit.0.0.vio.posn.4.name=20 MHz |
| unit.0.0.vio.posn.4.port=0 |
| unit.0.0.vio.posn.4.type=signal |
| unit.0.0.vio.posn.5.channel=5 |
| unit.0.0.vio.posn.5.name=50 MHz |
| unit.0.0.vio.posn.5.port=0 |
| unit.0.0.vio.posn.5.type=signal |
| unit.0.0.vio.posn.6.channel=6 |
| unit.0.0.vio.posn.6.name=100 MHz |
| unit.0.0.vio.posn.6.port=0 |
| unit.0.0.vio.posn.6.type=signal |
| unit.0.0.vio.posn.7.channel=7 |
| unit.0.0.vio.posn.7.name=170 MHz |
| unit.0.0.vio.posn.7.port=0 |
| unit.0.0.vio.posn.7.type=signal |
| unit.0.0.vio.posn.8.channel=0 |
| unit.0.0.vio.posn.8.name=Set 1 MHz |
| unit.0.0.vio.posn.8.port=2 |
| unit.0.0.vio.posn.8.type=signal |
| unit.0.0.vio.posn.9.channel=1 |
| unit.0.0.vio.posn.9.name=Set 2 MHz |
| unit.0.0.vio.posn.9.port=2 |
| unit.0.0.vio.posn.9.type=signal |
| unit.0.0.vio.readperiod=0 |
| unit.0.0.waveform.count=24 |
| unit.0.0.waveform.posn.0.channel=0 |
| unit.0.0.waveform.posn.0.name=DataPort[0] |
| unit.0.0.waveform.posn.0.type=signal |
| unit.0.0.waveform.posn.1.channel=1 |
| unit.0.0.waveform.posn.1.name=DataPort[1] |
| unit.0.0.waveform.posn.1.type=signal |
| unit.0.0.waveform.posn.10.channel=10 |
| unit.0.0.waveform.posn.10.name=DataPort[10] |
| unit.0.0.waveform.posn.10.type=signal |
| unit.0.0.waveform.posn.11.channel=11 |
| unit.0.0.waveform.posn.11.name=DataPort[11] |
| unit.0.0.waveform.posn.11.type=signal |
| unit.0.0.waveform.posn.12.channel=12 |
| unit.0.0.waveform.posn.12.name=DataPort[12] |
| unit.0.0.waveform.posn.12.type=signal |
| unit.0.0.waveform.posn.13.channel=13 |
| unit.0.0.waveform.posn.13.name=DataPort[13] |
| unit.0.0.waveform.posn.13.type=signal |
| unit.0.0.waveform.posn.14.channel=14 |
| unit.0.0.waveform.posn.14.name=DataPort[14] |
| unit.0.0.waveform.posn.14.type=signal |
| unit.0.0.waveform.posn.15.channel=15 |
| unit.0.0.waveform.posn.15.name=DataPort[15] |
| unit.0.0.waveform.posn.15.type=signal |
| unit.0.0.waveform.posn.16.channel=16 |
| unit.0.0.waveform.posn.16.name=DataPort[16] |
| unit.0.0.waveform.posn.16.type=signal |
| unit.0.0.waveform.posn.17.channel=17 |
| unit.0.0.waveform.posn.17.name=DataPort[17] |
| unit.0.0.waveform.posn.17.type=signal |
| unit.0.0.waveform.posn.18.channel=18 |
| unit.0.0.waveform.posn.18.name=DataPort[18] |
| unit.0.0.waveform.posn.18.type=signal |
| unit.0.0.waveform.posn.19.channel=19 |
| unit.0.0.waveform.posn.19.name=DataPort[19] |
| unit.0.0.waveform.posn.19.type=signal |
| unit.0.0.waveform.posn.2.channel=2 |
| unit.0.0.waveform.posn.2.name=DataPort[2] |
| unit.0.0.waveform.posn.2.type=signal |
| unit.0.0.waveform.posn.20.channel=20 |
| unit.0.0.waveform.posn.20.name=DataPort[20] |
| unit.0.0.waveform.posn.20.type=signal |
| unit.0.0.waveform.posn.21.channel=21 |
| unit.0.0.waveform.posn.21.name=DataPort[21] |
| unit.0.0.waveform.posn.21.type=signal |
| unit.0.0.waveform.posn.22.channel=22 |
| unit.0.0.waveform.posn.22.name=DataPort[22] |
| unit.0.0.waveform.posn.22.type=signal |
| unit.0.0.waveform.posn.23.channel=23 |
| unit.0.0.waveform.posn.23.name=DataPort[23] |
| unit.0.0.waveform.posn.23.type=signal |
| unit.0.0.waveform.posn.3.channel=3 |
| unit.0.0.waveform.posn.3.name=DataPort[3] |
| unit.0.0.waveform.posn.3.type=signal |
| unit.0.0.waveform.posn.4.channel=4 |
| unit.0.0.waveform.posn.4.name=DataPort[4] |
| unit.0.0.waveform.posn.4.type=signal |
| unit.0.0.waveform.posn.5.channel=5 |
| unit.0.0.waveform.posn.5.name=DataPort[5] |
| unit.0.0.waveform.posn.5.type=signal |
| unit.0.0.waveform.posn.6.channel=6 |
| unit.0.0.waveform.posn.6.name=DataPort[6] |
| unit.0.0.waveform.posn.6.type=signal |
| unit.0.0.waveform.posn.7.channel=7 |
| unit.0.0.waveform.posn.7.name=DataPort[7] |
| unit.0.0.waveform.posn.7.type=signal |
| unit.0.0.waveform.posn.8.channel=8 |
| unit.0.0.waveform.posn.8.name=DataPort[8] |
| unit.0.0.waveform.posn.8.type=signal |
| unit.0.0.waveform.posn.9.channel=9 |
| unit.0.0.waveform.posn.9.name=DataPort[9] |
| unit.0.0.waveform.posn.9.type=signal |
| unit.0.1.6.HEIGHT6=0.23296355 |
| unit.0.1.6.WIDTH6=0.17021276 |
| unit.0.1.6.X6=8.510638E-4 |
| unit.0.1.6.Y6=0.7717908 |
| unit.0.1.coretype=VIO |
| unit.0.1.port.-1.buscount=0 |
| unit.0.1.port.-1.channelcount=0 |
| unit.0.1.port.0.buscount=0 |
| unit.0.1.port.0.channelcount=0 |
| unit.0.1.port.1.buscount=0 |
| unit.0.1.port.1.channelcount=0 |
| unit.0.1.port.2.buscount=0 |
| unit.0.1.port.2.channelcount=3 |
| unit.0.1.port.2.s.0.alias=VS[0] |
| unit.0.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.1.port.2.s.0.display=3 |
| unit.0.1.port.2.s.0.name=SyncOut[0] |
| unit.0.1.port.2.s.0.orderindex=-1 |
| unit.0.1.port.2.s.0.persistence=0 |
| unit.0.1.port.2.s.0.value=0 |
| unit.0.1.port.2.s.0.visible=1 |
| unit.0.1.port.2.s.1.alias=VS[1] |
| unit.0.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.1.port.2.s.1.display=3 |
| unit.0.1.port.2.s.1.name=SyncOut[1] |
| unit.0.1.port.2.s.1.orderindex=-1 |
| unit.0.1.port.2.s.1.persistence=0 |
| unit.0.1.port.2.s.1.value=0 |
| unit.0.1.port.2.s.1.visible=1 |
| unit.0.1.port.2.s.2.alias=VS[2] |
| unit.0.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.1.port.2.s.2.display=3 |
| unit.0.1.port.2.s.2.name=SyncOut[2] |
| unit.0.1.port.2.s.2.orderindex=-1 |
| unit.0.1.port.2.s.2.persistence=0 |
| unit.0.1.port.2.s.2.value=0 |
| unit.0.1.port.2.s.2.visible=1 |
| unit.0.1.portcount=3 |
| unit.0.1.username=Set User Output |
| unit.0.1.vio.count=3 |
| unit.0.1.vio.posn.0.channel=0 |
| unit.0.1.vio.posn.0.name=VS[0] |
| unit.0.1.vio.posn.0.port=2 |
| unit.0.1.vio.posn.0.type=signal |
| unit.0.1.vio.posn.1.channel=1 |
| unit.0.1.vio.posn.1.name=VS[1] |
| unit.0.1.vio.posn.1.port=2 |
| unit.0.1.vio.posn.1.type=signal |
| unit.0.1.vio.posn.2.channel=2 |
| unit.0.1.vio.posn.2.name=VS[2] |
| unit.0.1.vio.posn.2.port=2 |
| unit.0.1.vio.posn.2.type=signal |
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| unit.0.2.port.0.s.4.orderindex=-1 |
| unit.0.2.port.0.s.4.visible=1 |
| unit.0.2.port.0.s.5.alias=P[5] |
| unit.0.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.2.port.0.s.5.name=TriggerPort0[5] |
| unit.0.2.port.0.s.5.orderindex=-1 |
| unit.0.2.port.0.s.5.visible=1 |
| unit.0.2.port.0.s.6.alias=P[6] |
| unit.0.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.2.port.0.s.6.name=TriggerPort0[6] |
| unit.0.2.port.0.s.6.orderindex=-1 |
| unit.0.2.port.0.s.6.visible=1 |
| unit.0.2.port.0.s.7.alias=P[7] |
| unit.0.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.2.port.0.s.7.name=TriggerPort0[7] |
| unit.0.2.port.0.s.7.orderindex=-1 |
| unit.0.2.port.0.s.7.visible=1 |
| unit.0.2.port.0.s.8.alias=P[8] |
| unit.0.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.2.port.0.s.8.name=TriggerPort0[8] |
| unit.0.2.port.0.s.8.orderindex=-1 |
| unit.0.2.port.0.s.8.visible=1 |
| unit.0.2.port.0.s.9.alias=P[9] |
| unit.0.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] |
| unit.0.2.port.0.s.9.name=TriggerPort0[9] |
| unit.0.2.port.0.s.9.orderindex=-1 |
| unit.0.2.port.0.s.9.visible=1 |
| unit.0.2.portcount=1 |
| unit.0.2.rep_trigger.clobber=1 |
| unit.0.2.rep_trigger.dir=D\:\\MLAB\\Modules\\CPLD_FPGA\\XILINX_ChipScope\\MAKE\\BIN\\13.3 |
| unit.0.2.rep_trigger.filename=waveform |
| unit.0.2.rep_trigger.format=ASCII |
| unit.0.2.rep_trigger.loggingEnabled=0 |
| unit.0.2.rep_trigger.signals=All Signals/Buses |
| unit.0.2.samplesPerTrigger=1 |
| unit.0.2.triggerCapture=1 |
| unit.0.2.triggerNSamplesTS=0 |
| unit.0.2.triggerPosition=0 |
| unit.0.2.triggerWindowCount=1 |
| unit.0.2.triggerWindowDepth=1024 |
| unit.0.2.triggerWindowTS=0 |
| unit.0.2.username=Analyser |
| unit.0.2.waveform.count=9 |
| unit.0.2.waveform.posn.0.channel=0 |
| unit.0.2.waveform.posn.0.name=P[0] |
| unit.0.2.waveform.posn.0.type=signal |
| unit.0.2.waveform.posn.1.channel=1 |
| unit.0.2.waveform.posn.1.name=P[1] |
| unit.0.2.waveform.posn.1.type=signal |
| unit.0.2.waveform.posn.10.channel=10 |
| unit.0.2.waveform.posn.10.name=P[10] |
| unit.0.2.waveform.posn.10.type=signal |
| unit.0.2.waveform.posn.11.channel=11 |
| unit.0.2.waveform.posn.11.name=P[11] |
| unit.0.2.waveform.posn.11.type=signal |
| unit.0.2.waveform.posn.12.channel=12 |
| unit.0.2.waveform.posn.12.name=P[12] |
| unit.0.2.waveform.posn.12.type=signal |
| unit.0.2.waveform.posn.13.channel=13 |
| unit.0.2.waveform.posn.13.name=P[13] |
| unit.0.2.waveform.posn.13.type=signal |
| unit.0.2.waveform.posn.14.channel=14 |
| unit.0.2.waveform.posn.14.name=P[14] |
| unit.0.2.waveform.posn.14.type=signal |
| unit.0.2.waveform.posn.15.channel=15 |
| unit.0.2.waveform.posn.15.name=P[15] |
| unit.0.2.waveform.posn.15.type=signal |
| unit.0.2.waveform.posn.16.channel=16 |
| unit.0.2.waveform.posn.16.name=P[16] |
| unit.0.2.waveform.posn.16.type=signal |
| unit.0.2.waveform.posn.17.channel=17 |
| unit.0.2.waveform.posn.17.name=P[17] |
| unit.0.2.waveform.posn.17.type=signal |
| unit.0.2.waveform.posn.2.channel=2 |
| unit.0.2.waveform.posn.2.name=P[2] |
| unit.0.2.waveform.posn.2.type=signal |
| unit.0.2.waveform.posn.3.channel=3 |
| unit.0.2.waveform.posn.3.name=P[3] |
| unit.0.2.waveform.posn.3.type=signal |
| unit.0.2.waveform.posn.4.channel=4 |
| unit.0.2.waveform.posn.4.name=P[4] |
| unit.0.2.waveform.posn.4.type=signal |
| unit.0.2.waveform.posn.5.channel=5 |
| unit.0.2.waveform.posn.5.name=P[5] |
| unit.0.2.waveform.posn.5.type=signal |
| unit.0.2.waveform.posn.6.channel=6 |
| unit.0.2.waveform.posn.6.name=P[6] |
| unit.0.2.waveform.posn.6.type=signal |
| unit.0.2.waveform.posn.7.channel=7 |
| unit.0.2.waveform.posn.7.name=P[7] |
| unit.0.2.waveform.posn.7.type=signal |
| unit.0.2.waveform.posn.8.channel=8 |
| unit.0.2.waveform.posn.8.name=P[8] |
| unit.0.2.waveform.posn.8.type=signal |
| unit.0.2.waveform.posn.9.channel=9 |
| unit.0.2.waveform.posn.9.name=P[9] |
| unit.0.2.waveform.posn.9.type=signal |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/!____!.txt |
|---|
| 0,0 → 1,20 |
| CoreGenerator Project Files |
| --------------------------- |
| Software: ISE 14.5 (WebPack) |
| Device: Spartan3AN XC3S50AN-4TQG144C |
| Input (source) Files |
| -------------------- |
| S3AN01_ChipScopeILA.cgp - Core Generator Project File (used by GUI CoreGen) |
| ChipScope_ICON.xco - ChipScope Config Block Configuration File |
| ChipScope_ILA_18_1024.xco - ChipScope Integrated Logic Analyser Configuration File 18 bits 1024 smaples |
| ChipScope_ILA_9_2048.xco - ChipScope Integrated Logic Analyser Configuration File 9 bits 2048 smaples |
| ChipScope_VIO_FreqSel.xco - ChipScope Virtul IO Configuration File (used for Frequency Selection) |
| ChipScope_VIO_UserOut.xco - ChipScope Virtul IO Configuration File (used for User Output) |
| All other files may be deleted. Open .cgp file in CoreGenerator and let it regenerate |
| all cores. |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ICON.xco |
|---|
| 0,0 → 1,56 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.5 |
| # Date: Thu Jun 20 12:54:35 2013 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:chipscope_icon:1.06.a |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc3s50an |
| SET devicefamily = spartan3a |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = tqg144 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -4 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a |
| # END Select |
| # BEGIN Parameters |
| CSET component_name=ChipScope_ICON |
| CSET constraint_type=external |
| CSET enable_jtag_bufg=true |
| CSET example_design=false |
| CSET number_control_ports=3 |
| CSET use_ext_bscan=false |
| CSET use_softbscan=false |
| CSET use_unused_bscan=false |
| CSET user_scan_chain=USER1 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2013-03-26T22:44:10Z |
| # END Extra information |
| GENERATE |
| # CRC: 1a9afcd1 |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_18_1024.xco |
|---|
| 0,0 → 1,141 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.5 |
| # Date: Thu Jun 20 12:43:44 2013 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:chipscope_ila:1.05.a |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc3s50an |
| SET devicefamily = spartan3a |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = tqg144 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -4 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a |
| # END Select |
| # BEGIN Parameters |
| CSET check_bramcount=false |
| CSET component_name=ChipScope_ILA_18_1024 |
| CSET constraint_type=external |
| CSET counter_width_1=4 |
| CSET counter_width_10=Disabled |
| CSET counter_width_11=Disabled |
| CSET counter_width_12=Disabled |
| CSET counter_width_13=Disabled |
| CSET counter_width_14=Disabled |
| CSET counter_width_15=Disabled |
| CSET counter_width_16=Disabled |
| CSET counter_width_2=Disabled |
| CSET counter_width_3=Disabled |
| CSET counter_width_4=Disabled |
| CSET counter_width_5=Disabled |
| CSET counter_width_6=Disabled |
| CSET counter_width_7=Disabled |
| CSET counter_width_8=Disabled |
| CSET counter_width_9=Disabled |
| CSET data_port_width=18 |
| CSET data_same_as_trigger=false |
| CSET disable_save_keep=false |
| CSET enable_storage_qualification=true |
| CSET enable_trigger_output_port=true |
| CSET example_design=false |
| CSET exclude_from_data_storage_1=true |
| CSET exclude_from_data_storage_10=true |
| CSET exclude_from_data_storage_11=true |
| CSET exclude_from_data_storage_12=true |
| CSET exclude_from_data_storage_13=true |
| CSET exclude_from_data_storage_14=true |
| CSET exclude_from_data_storage_15=true |
| CSET exclude_from_data_storage_16=true |
| CSET exclude_from_data_storage_2=true |
| CSET exclude_from_data_storage_3=true |
| CSET exclude_from_data_storage_4=true |
| CSET exclude_from_data_storage_5=true |
| CSET exclude_from_data_storage_6=true |
| CSET exclude_from_data_storage_7=true |
| CSET exclude_from_data_storage_8=true |
| CSET exclude_from_data_storage_9=true |
| CSET match_type_1=basic_with_edges |
| CSET match_type_10=basic_with_edges |
| CSET match_type_11=basic_with_edges |
| CSET match_type_12=basic_with_edges |
| CSET match_type_13=basic_with_edges |
| CSET match_type_14=basic_with_edges |
| CSET match_type_15=basic_with_edges |
| CSET match_type_16=basic_with_edges |
| CSET match_type_2=basic_with_edges |
| CSET match_type_3=basic_with_edges |
| CSET match_type_4=basic_with_edges |
| CSET match_type_5=basic_with_edges |
| CSET match_type_6=basic_with_edges |
| CSET match_type_7=basic_with_edges |
| CSET match_type_8=basic_with_edges |
| CSET match_type_9=basic_with_edges |
| CSET match_units_1=3 |
| CSET match_units_10=1 |
| CSET match_units_11=1 |
| CSET match_units_12=1 |
| CSET match_units_13=1 |
| CSET match_units_14=1 |
| CSET match_units_15=1 |
| CSET match_units_16=1 |
| CSET match_units_2=1 |
| CSET match_units_3=1 |
| CSET match_units_4=1 |
| CSET match_units_5=1 |
| CSET match_units_6=1 |
| CSET match_units_7=1 |
| CSET match_units_8=1 |
| CSET match_units_9=1 |
| CSET max_sequence_levels=16 |
| CSET number_of_trigger_ports=1 |
| CSET sample_data_depth=1024 |
| CSET sample_on=Rising |
| CSET trigger_port_width_1=24 |
| CSET trigger_port_width_10=8 |
| CSET trigger_port_width_11=8 |
| CSET trigger_port_width_12=8 |
| CSET trigger_port_width_13=8 |
| CSET trigger_port_width_14=8 |
| CSET trigger_port_width_15=8 |
| CSET trigger_port_width_16=8 |
| CSET trigger_port_width_2=8 |
| CSET trigger_port_width_3=8 |
| CSET trigger_port_width_4=8 |
| CSET trigger_port_width_5=8 |
| CSET trigger_port_width_6=8 |
| CSET trigger_port_width_7=8 |
| CSET trigger_port_width_8=8 |
| CSET trigger_port_width_9=8 |
| CSET use_rpms=true |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2013-03-26T22:44:34Z |
| # END Extra information |
| GENERATE |
| # CRC: ab76e1ca |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_9_2048.xco |
|---|
| 0,0 → 1,141 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.5 |
| # Date: Thu Jun 20 13:35:12 2013 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:chipscope_ila:1.05.a |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc3s50an |
| SET devicefamily = spartan3a |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = tqg144 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -4 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a |
| # END Select |
| # BEGIN Parameters |
| CSET check_bramcount=false |
| CSET component_name=ChipScope_ILA_9_2048 |
| CSET constraint_type=external |
| CSET counter_width_1=4 |
| CSET counter_width_10=Disabled |
| CSET counter_width_11=Disabled |
| CSET counter_width_12=Disabled |
| CSET counter_width_13=Disabled |
| CSET counter_width_14=Disabled |
| CSET counter_width_15=Disabled |
| CSET counter_width_16=Disabled |
| CSET counter_width_2=Disabled |
| CSET counter_width_3=Disabled |
| CSET counter_width_4=Disabled |
| CSET counter_width_5=Disabled |
| CSET counter_width_6=Disabled |
| CSET counter_width_7=Disabled |
| CSET counter_width_8=Disabled |
| CSET counter_width_9=Disabled |
| CSET data_port_width=9 |
| CSET data_same_as_trigger=false |
| CSET disable_save_keep=false |
| CSET enable_storage_qualification=true |
| CSET enable_trigger_output_port=true |
| CSET example_design=false |
| CSET exclude_from_data_storage_1=true |
| CSET exclude_from_data_storage_10=true |
| CSET exclude_from_data_storage_11=true |
| CSET exclude_from_data_storage_12=true |
| CSET exclude_from_data_storage_13=true |
| CSET exclude_from_data_storage_14=true |
| CSET exclude_from_data_storage_15=true |
| CSET exclude_from_data_storage_16=true |
| CSET exclude_from_data_storage_2=true |
| CSET exclude_from_data_storage_3=true |
| CSET exclude_from_data_storage_4=true |
| CSET exclude_from_data_storage_5=true |
| CSET exclude_from_data_storage_6=true |
| CSET exclude_from_data_storage_7=true |
| CSET exclude_from_data_storage_8=true |
| CSET exclude_from_data_storage_9=true |
| CSET match_type_1=basic_with_edges |
| CSET match_type_10=basic_with_edges |
| CSET match_type_11=basic_with_edges |
| CSET match_type_12=basic_with_edges |
| CSET match_type_13=basic_with_edges |
| CSET match_type_14=basic_with_edges |
| CSET match_type_15=basic_with_edges |
| CSET match_type_16=basic_with_edges |
| CSET match_type_2=basic_with_edges |
| CSET match_type_3=basic_with_edges |
| CSET match_type_4=basic_with_edges |
| CSET match_type_5=basic_with_edges |
| CSET match_type_6=basic_with_edges |
| CSET match_type_7=basic_with_edges |
| CSET match_type_8=basic_with_edges |
| CSET match_type_9=basic_with_edges |
| CSET match_units_1=3 |
| CSET match_units_10=1 |
| CSET match_units_11=1 |
| CSET match_units_12=1 |
| CSET match_units_13=1 |
| CSET match_units_14=1 |
| CSET match_units_15=1 |
| CSET match_units_16=1 |
| CSET match_units_2=1 |
| CSET match_units_3=1 |
| CSET match_units_4=1 |
| CSET match_units_5=1 |
| CSET match_units_6=1 |
| CSET match_units_7=1 |
| CSET match_units_8=1 |
| CSET match_units_9=1 |
| CSET max_sequence_levels=16 |
| CSET number_of_trigger_ports=1 |
| CSET sample_data_depth=2048 |
| CSET sample_on=Rising |
| CSET trigger_port_width_1=24 |
| CSET trigger_port_width_10=8 |
| CSET trigger_port_width_11=8 |
| CSET trigger_port_width_12=8 |
| CSET trigger_port_width_13=8 |
| CSET trigger_port_width_14=8 |
| CSET trigger_port_width_15=8 |
| CSET trigger_port_width_16=8 |
| CSET trigger_port_width_2=8 |
| CSET trigger_port_width_3=8 |
| CSET trigger_port_width_4=8 |
| CSET trigger_port_width_5=8 |
| CSET trigger_port_width_6=8 |
| CSET trigger_port_width_7=8 |
| CSET trigger_port_width_8=8 |
| CSET trigger_port_width_9=8 |
| CSET use_rpms=true |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2013-03-26T22:44:34Z |
| # END Extra information |
| GENERATE |
| # CRC: 100acb04 |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_FreqSel.xco |
|---|
| 0,0 → 1,59 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.5 |
| # Date: Thu Jun 20 12:56:15 2013 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:chipscope_vio:1.05.a |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc3s50an |
| SET devicefamily = spartan3a |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = tqg144 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -4 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a |
| # END Select |
| # BEGIN Parameters |
| CSET asynchronous_input_port_width=8 |
| CSET asynchronous_output_port_width=8 |
| CSET component_name=ChipScope_VIO_FreqSel |
| CSET constraint_type=external |
| CSET enable_asynchronous_input_port=false |
| CSET enable_asynchronous_output_port=false |
| CSET enable_synchronous_input_port=true |
| CSET enable_synchronous_output_port=true |
| CSET example_design=false |
| CSET invert_clock_input=false |
| CSET synchronous_input_port_width=8 |
| CSET synchronous_output_port_width=8 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2013-03-26T22:44:59Z |
| # END Extra information |
| GENERATE |
| # CRC: c6d481e1 |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_UserOut.xco |
|---|
| 0,0 → 1,59 |
| ############################################################## |
| # |
| # Xilinx Core Generator version 14.5 |
| # Date: Thu Jun 20 12:55:33 2013 |
| # |
| ############################################################## |
| # |
| # This file contains the customisation parameters for a |
| # Xilinx CORE Generator IP GUI. It is strongly recommended |
| # that you do not manually alter this file as it may cause |
| # unexpected and unsupported behavior. |
| # |
| ############################################################## |
| # |
| # Generated from component: xilinx.com:ip:chipscope_vio:1.05.a |
| # |
| ############################################################## |
| # |
| # BEGIN Project Options |
| SET addpads = false |
| SET asysymbol = true |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET createndf = false |
| SET designentry = VHDL |
| SET device = xc3s50an |
| SET devicefamily = spartan3a |
| SET flowvendor = Other |
| SET formalverification = false |
| SET foundationsym = false |
| SET implementationfiletype = Ngc |
| SET package = tqg144 |
| SET removerpms = false |
| SET simulationfiles = Behavioral |
| SET speedgrade = -4 |
| SET verilogsim = false |
| SET vhdlsim = true |
| # END Project Options |
| # BEGIN Select |
| SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a |
| # END Select |
| # BEGIN Parameters |
| CSET asynchronous_input_port_width=8 |
| CSET asynchronous_output_port_width=8 |
| CSET component_name=ChipScope_VIO_UserOut |
| CSET constraint_type=external |
| CSET enable_asynchronous_input_port=false |
| CSET enable_asynchronous_output_port=false |
| CSET enable_synchronous_input_port=false |
| CSET enable_synchronous_output_port=true |
| CSET example_design=false |
| CSET invert_clock_input=false |
| CSET synchronous_input_port_width=8 |
| CSET synchronous_output_port_width=3 |
| # END Parameters |
| # BEGIN Extra information |
| MISC pkg_timestamp=2013-03-26T22:44:59Z |
| # END Extra information |
| GENERATE |
| # CRC: 738ddf25 |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/coregen.cgp |
|---|
| 0,0 → 1,9 |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET designentry = VHDL |
| SET device = xc3s50an |
| SET devicefamily = spartan3a |
| SET flowvendor = Other |
| SET package = tqg144 |
| SET speedgrade = -4 |
| SET verilogsim = false |
| SET vhdlsim = true |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/DirInfo.txt |
|---|
| 0,0 → 1,33 |
| // |
| // Toto je popisný soubor pro popis obsahu adresáře |
| // |
| [InfoShortDescription.en] |
| Xilinx ChipScope Demo |
| [InfoShortDescription.cs] |
| Xilinx ChipScope Demo |
| [InfoLongDescription.en] |
| ChipScope IP Core from Xilinx company enable us to add pretty |
| powerful logic analyser into our own FPGA design. It is necessary |
| to have a valid license for generation of bitfile but not for |
| usage and debugging. The text here shows a realisation of |
| an universal logic analyser in Spartan device on MLAB |
| board S3AN01. It shows the use of Xilinx Virtual Cable technology |
| as well. |
| The maximum achieved sampling rate is 170 MS/s with 9 or 18 input channels. |
| [InfoLongDescription.cs] |
| IP jádro ChipScope firmy Xilinx umožňuje vložit do vlastního návrhu |
| FPGA obvodu docela výkonný logický analyzátor. K překladu takového |
| obvodu potřebujeme příslušnou licenci, ale pro použití (ladění) |
| už ne. Uvedený článek ukazuje realizaci univerzálního logického |
| analyzátoru v obvodu Spartan na desce S3AN01 ze stavebnice MLAB |
| a to současně s použitím technologie Xilinx Virtual Cable |
| s přenosem JTAG příkazů po síti. |
| Maximální dosažená rychlost vzorkování je 170 MS/s na 9 nebo 18 kanálech. |
| [SortPreferences] |
| [End] |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/FindXilinxTools.cmd |
|---|
| 0,0 → 1,40 |
| @echo off |
| rem Finds installation of Xilinx tools and makes necessary env settings |
| rem ----- Set 32/64 bit |
| if Defined PROCESSOR_ARCHITEW6432 ( |
| Set ProcArch=%PROCESSOR_ARCHITEW6432% |
| ) else ( |
| Set ProcArch=%PROCESSOR_ARCHITECTURE% |
| ) |
| if "%ProcArch%" == "AMD64" Set ProcArch=x64 |
| rem echo %ProcArch% |
| if "%ProcArch%" == "x64" ( |
| set fileXilinxSet=settings64.bat |
| ) else ( |
| set fileXilinxSet=settings32.bat |
| ) |
| rem ----- Find Xilinx directory |
| echo Find Xilinx Tools |
| for %%i in (C:\SW32\Xilinx C:\Xilinx) do ( |
| rem Take the last directory |
| for /F %%j in ('dir %%i\*.* /AD /B /O-N') do ( |
| for %%k in (%%i\%%j\ISE_DS) do ( |
| rem echo %%j\%fileXilinxSet% |
| if exist %%k\%fileXilinxSet% ( |
| echo Found at %%k\%fileXilinxSet% |
| call %%k\%fileXilinxSet% |
| set XILINX_VERSION=%%j |
| if not "%1"=="" ( |
| rem Call script |
| call %1 |
| ) else ( |
| rem Just set env |
| goto Label1 |
| ) |
| ) |
| ) |
| ) |
| ) |
| :Label1 |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_CoreGen.cmd |
|---|
| 0,0 → 1,81 |
| @echo off |
| rem Batch to (re)generate IP cores (ChipScope components) |
| rem Run once, takes several minutes to finish. |
| rem |
| rem Do not modify source files directory structure |
| rem |
| rem Tested with Xilinx ISE WebPack 13.3 and 14.5 |
| rem This step does not require ChipScope License |
| rem |
| rem ----- Find and Set Xilinx Tools |
| call FindXilinxTools.cmd |
| rem ----- Run Coregen in paralel (we all have multicore cpu don't we?) |
| rem Unfortunately CoreGen can't be run in parallel. |
| rem There is some conflict (You cenrtainly know what all that cores are good for...) |
| rem start "CoreGen ICON" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r |
| rem start "CoreGen ILA 18x1024" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r |
| rem start "CoreGen ILA 9x2048" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r |
| rem start "CoreGen VIO FreqSel" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r |
| rem start "CoreGen VIO UserOut" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r |
| rem ----- Run CoreGen one after one for all components |
| coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in coregen ChipScope_ICON |
| echo =============================== |
| pause |
| exit 1 |
| ) |
| coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in coregen ChipScope_ILA_18_1024 |
| echo ====================================== |
| pause |
| exit 1 |
| ) |
| coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in coregen ChipScope_ILA_9_2048 |
| echo ===================================== |
| pause |
| exit 1 |
| ) |
| coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in coregen ChipScope_VIO_FreqSel |
| echo ====================================== |
| pause |
| exit 1 |
| ) |
| coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in coregen ChipScope_VIO_UserOut |
| echo ====================================== |
| pause |
| exit 1 |
| ) |
| rem ----- Finished |
| rm coregen.log |
| echo. |
| echo CoreGen Finished with no Errors |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_S3AN01_ChipScope.cmd |
|---|
| 0,0 → 1,179 |
| @echo off |
| rem Batch generates bitfile for Logic Analyser Demo |
| rem |
| rem Parameters: |
| rem |
| rem 18x1024|9x2048 ... select analyser size (width and depth) |
| rem |
| rem Do not modify srouce files directory structure |
| rem |
| rem Tested with Xilinx ISE WebPack 14.5 with ChipScope License |
| rem |
| rem ----- first parameter |
| set product=%1% |
| if "%product%"=="18x1024" ( |
| echo 18x1024 |
| ) else if "%product%" == "9x2048" ( |
| echo 9x2048 |
| ) else ( |
| echo Missing parameter %product% |
| echo usage: %0% 18x1024^|9x2048 |
| pause |
| exit 1 |
| ) |
| echo. |
| echo Product: %product% |
| echo. |
| rem ----- Set core (top VHDL entity) name |
| set core=S3AN01_ChipScope |
| rem ----- Set FPGA part |
| set fpgaPart=xc3s50an-tqg144-4 |
| rem ----- Find and Set Xilinx Tools |
| call FindXilinxTools.cmd |
| rem ----- Set WORK dir |
| if exist WORK_%core%_%product% rmdir /S /Q WORK_%core%_%product% |
| mkdir WORK_%core%_%product% |
| cd WORK_%core%_%product% |
| rem ----- Set TEMP dir (relative to WORK dir) |
| mkdir TMP |
| set TMP=TMP |
| rem ----- INPUT UCF and VHDL files (linux format c:/.../... ) |
| set srcPath=../.. |
| set ucfFile=VHDL/S3AN01_ChipScope.ucf |
| echo vhdl work "%srcPath%/COREGEN/ChipScope_ICON.vhd" > srcFiles.prj |
| echo vhdl work "%srcPath%/COREGEN/ChipScope_VIO_FreqSel.vhd" >>srcFiles.prj |
| echo vhdl work "%srcPath%/COREGEN/ChipScope_ILA_9_2048.vhd" >>srcFiles.prj |
| echo vhdl work "%srcPath%/VHDL/S3AN01_ChipScope.vhd" >>srcFiles.prj |
| rem ----- SET XST setting |
| echo set -xsthdpdir "xst" > setXst.xst |
| echo run >>setXst.xst |
| echo -ifn "srcFiles.prj" >>setXst.xst |
| echo -ofn %core% >>setXst.xst |
| echo -ofmt NGC >>setXst.xst |
| echo -top %core% >>setXst.xst |
| echo -iob True >>setXst.xst |
| echo -p %fpgaPart% >>setXst.xst |
| if "%product%"=="18x1024" ( |
| echo -generics { ILA_WIDE=TRUE } >>setXst.xst |
| ) else ( |
| echo -generics { ILA_WIDE=FALSE } >>setXst.xst |
| ) |
| rem ----- SET BITGEN setting |
| echo -w > setBitGen.ut |
| echo -g ConfigRate:25 >>setBitGen.ut |
| echo -g UnusedPin:PullUp >>setBitGen.ut |
| echo -g DriveDone:Yes >>setBitGen.ut |
| call xst -ifn "setXst.xst" -ofn "%core%.log" |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in xst |
| echo ============ |
| pause |
| exit 1 |
| ) |
| call ngdbuild -intstyle ise -dd _ngo -sd ../../COREGEN -nt timestamp -uc "%srcPath%/%ucfFile%" -p %fpgaPart% %core%.ngc %core%.ngd |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in ngdbuild |
| echo ================= |
| pause |
| exit 1 |
| ) |
| call map -intstyle ise -p %fpgaPart% -cm area -ir off -pr off -c 100 -o %core%.ncd %core%.ngd %core%.pcf |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in map |
| echo ============ |
| pause |
| exit 1 |
| ) |
| call par -w -intstyle ise -ol high -t 1 %core%.ncd %core%.ncd %core%.pcf |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in par |
| echo ============ |
| pause |
| exit 1 |
| ) |
| call trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml %core%.twx %core%.ncd -o %core%.twr %core%.pcf |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in trace |
| echo ============== |
| pause |
| exit 1 |
| ) |
| call bitgen -f "setBitGen.ut" %core%.ncd |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in bidgen |
| echo =============== |
| pause |
| exit 1 |
| ) |
| rem ----- Verify Timing |
| findstr /B /C:"All constraints were met." %core%.par |
| if %errorlevel% NEQ 0 ( |
| echo. |
| echo. |
| echo ERROR in Timing |
| echo =============== |
| pause |
| exit 1 |
| ) |
| if exist ..\BIN\%XILINX_VERSION% ( |
| rem ----- Copy result to BIN\{ISE_VER} directory |
| copy /Y %core%.bit ..\BIN\%XILINX_VERSION%\%core%_%product%.bit |
| rem copy /Y %core%.par ..\BIN\%XILINX_VERSION%\%core%_%product%.par |
| rem ----- Remove WORK dir |
| rem (bitgen starts wbtc.exe as a secondary process) |
| cd .. |
| rem Wait for xwebtalk has finished its work (sending stat data to Xilinx) |
| echo | set /p=Waiting for WebTalk... |
| :StartLoop |
| tasklist | findstr /i /c:"wbtc.exe" > nul |
| if %errorlevel% NEQ 0 ( |
| goto ExitLoop |
| ) |
| sleep 1 |
| echo | set /p=* |
| goto StartLoop |
| ) |
| :ExitLoop |
| rem Tohle nefunguje, protoe výstup wmic je UTF-16 a to finstr neumí |
| rem wmic process | findstr /c:"%core%_%product%" |
| rem wmic process > ..\"%core%_%product%".wmic |
| rmdir /S /Q WORK_%core%_%product% |
| exit 0 |
| ) |
| exit 1 |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_all.cmd |
|---|
| 0,0 → 1,53 |
| @echo off |
| rem Batch to generate bitstream |
| rem |
| rem S3AN01_ChipScope_18x1024.bit |
| rem S3AN01_ChipScope_9x2048.bit |
| rem |
| rem Do not modify srouce files directory structure |
| rem |
| rem Tested with Xilinx ISE WebPack 14.5 with ChipScope License |
| rem |
| rem ----- Check if ChipScope IP Cores are ready |
| if not exist ..\COREGEN\ChipScope_ICON.vhd goto coregen |
| if not exist ..\COREGEN\ChipScope_ILA_18_1024.vhd goto coregen |
| if not exist ..\COREGEN\ChipScope_ILA_9_2048.vhd goto coregen |
| if not exist ..\COREGEN\ChipScope_VIO_FreqSel.vhd goto coregen |
| if not exist ..\COREGEN\ChipScope_VIO_UserOut.vhd goto coregen |
| goto next |
| :coregen |
| rem ----- Regenerate ChipScope IP Cores |
| echo. |
| echo Missing ChipScope IP Core output files |
| echo Regenerating will take a long time (5 minutes on i5-3770) |
| echo. |
| pause |
| call make_CoreGen.cmd |
| :next |
| rem ----- Clear target directory |
| rmdir /S /Q BIN 2> nul |
| mkdir BIN |
| rem ----- Get Current date and time |
| for /F "Tokens=2-4 Delims=. " %%A in ("%DATE%") do ( |
| set CurDate=%%C_%%B_%%A |
| ) |
| for /F "Tokens=1-2 Delims=:,. " %%D in ("%TIME: =0%") do ( |
| set CurTime=%%D_%%E |
| ) |
| rem ----- Find and Set Xilinx Tools |
| call FindXilinxTools.cmd |
| mkdir BIN\%XILINX_VERSION% |
| rem ----- Create Version metafile |
| echo TimeStamp: %CurDate%__%CurTime%> BIN\%XILINX_VERSION%\Version |
| echo ComputerName: %COMPUTERNAME%>> BIN\%XILINX_VERSION%\Version |
| echo ISE Version: %XILINX_VERSION%>> BIN\%XILINX_VERSION%\Version |
| echo ReleaseInfo: None>> BIN\%XILINX_VERSION%\Version |
| rem ----- Compile variants (paralel run) |
| start "compile S3AN01_ChipScope_18x1024" make_S3AN01_ChipScope.cmd 18x1024 |
| start "compile S3AN01_ChipScope_9x2048" make_S3AN01_ChipScope.cmd 9x2048 |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_18_1024.cmd |
|---|
| 0,0 → 1,24 |
| @echo off |
| rem |
| rem Script for starting Analyser.exe with predefined settings. |
| rem The script starts mlab_xvcd.exe deamon for users who use |
| rem Xilinx Virtual Cable and FTDI JTAG cable. Those users |
| rem should select in ChipScope Analyser setting |
| rem JTAG Chain / Open Plug-in. |
| rem |
| rem ----- Run Xilinx Virtual Cable Daemon (as separate process) |
| rem Run it if you use XVC cable connected to the local computer |
| rem To start the daemon if already runnig does no harm |
| if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe ( |
| start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe |
| ) |
| rem ----- Find and Set Xilinx Tools |
| call FindXilinxTools.cmd |
| rem ----- Run ChipScope Analyser |
| analyzer.exe -project ..\ANALYSER\Analyser_18_1024.cpj -init ..\ANALYSER\Analyser.ini |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_9_2048.cmd |
|---|
| 0,0 → 1,24 |
| @echo off |
| rem |
| rem Script for starting Analyser.exe with predefined settings. |
| rem The script starts mlab_xvcd.exe deamon for users who use |
| rem Xilinx Virtual Cable and FTDI JTAG cable. Those users |
| rem should select in ChipScope Analyser setting |
| rem JTAG Chain / Open Plug-in. |
| rem |
| rem ----- Run Xilinx Virtual Cable Daemon (as separate process) |
| rem Run it if you use XVC cable connected to the local computer |
| rem To start the daemon if already runnig does no harm |
| if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe ( |
| start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe |
| ) |
| rem ----- Find and Set Xilinx Tools |
| call FindXilinxTools.cmd |
| rem ----- Run ChipScope Analyser |
| analyzer.exe -project ..\ANALYSER\Analyser_9_2048.cpj -init ..\ANALYSER\Analyser.ini |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL/S3AN01_ChipScope.ucf |
|---|
| 0,0 → 1,112 |
| # Board: www.mlab.cz S3AN01A |
| # Device: XC3S50AN-4TQG144C |
| # Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes |
| # Main Clock (Embedded 100MHz board oscillator) |
| NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33; |
| NET "CLK100MHz" TNM_NET = CLK100MHz; |
| TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%; |
| # Enable suboptimal routing of CLK100MHz to DCM input |
| # (the CLK100MHz pin is across the whole chip realtive to DCM) |
| # PIN "DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; |
| # Place BUFGMUX at the appropriate position |
| NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE; |
| # SPI Flash Vendor Mode Select (for external SPI boot Flash) |
| NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| # DIP Switches (positive signals with pull-down) |
| NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
| NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
| NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
| NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
| NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
| NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
| NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
| NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
| # LED String (positive output signals) |
| NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33; |
| NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33; |
| NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33; |
| NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33; |
| NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33; |
| NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33; |
| NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33; |
| NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33; |
| # LED Display Output Signals (negative, multiplexed) - Segments |
| NET "LD_SEG_n[0]" LOC = P15 |IOSTANDARD = LVCMOS33; # Segment A A |
| NET "LD_SEG_n[1]" LOC = P30 |IOSTANDARD = LVCMOS33; # Segment B ----- |
| NET "LD_SEG_n[2]" LOC = P21 |IOSTANDARD = LVCMOS33; # Segment C F | | B |
| NET "LD_SEG_n[3]" LOC = P19 |IOSTANDARD = LVCMOS33; # Segment D | G | |
| NET "LD_SEG_n[4]" LOC = P18 |IOSTANDARD = LVCMOS33; # Segment E ----- |
| NET "LD_SEG_n[5]" LOC = P16 |IOSTANDARD = LVCMOS33; # Segment F E | | C |
| NET "LD_SEG_n[6]" LOC = P24 |IOSTANDARD = LVCMOS33; # Segment G | D | |
| NET "LD_SEG_n[7]" LOC = P20 |IOSTANDARD = LVCMOS33; # Segment DP ----- DP |
| # LED Display Output Signals (negative, multiplexed) - Common Anodas |
| NET "LD_CA_n[0]" LOC = P25 |IOSTANDARD = LVCMOS33; |
| NET "LD_CA_n[1]" LOC = P31 |IOSTANDARD = LVCMOS33; |
| NET "LD_CA_n[2]" LOC = P32 |IOSTANDARD = LVCMOS33; |
| NET "LD_CA_n[3]" LOC = P13 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.13 with U1.33 |
| NET "LD_CA_n[4]" LOC = P27 |IOSTANDARD = LVCMOS33; |
| NET "LD_CA_n[5]" LOC = P29 |IOSTANDARD = LVCMOS33; |
| NET "LD_CA_n[6]" LOC = P28 |IOSTANDARD = LVCMOS33; |
| NET "LD_CA_n[7]" LOC = P12 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.12 with U1.35 |
| # Bank 1 Port (input for tests, pull-up) |
| NET "P[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| NET "P[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
| # Diferencial Signals on 4 pin header (J7) |
| NET "DIF1P" LOC = P110 |IOSTANDARD = LVDS_33; |
| NET "DIF1N" LOC = P111 |IOSTANDARD = LVDS_33; |
| NET "DIF2P" LOC = P112 |IOSTANDARD = LVDS_33; |
| NET "DIF2N" LOC = P113 |IOSTANDARD = LVDS_33; |
| # Timing Constraint for Crossing Time Domain |
| # Source is ChipScope_VIO_FreqSel output in CLK_FAST time domain |
| # Destination is SW_SYNC register in CLK100MHz time domain |
| INST "SW_SYNC_?" TNM = "TNM_SW_SYNC"; |
| TIMESPEC "TS_SW_SYNC" = TO "TNM_SW_SYNC" TIG; |
| # Timing Constraint for Crossing Time Domain |
| # Source is SET_CLK_xxx register (FSM) in CLK100MHz time domain |
| # Destination is ChipScope_VIO_FreqSel inputs in CLK_FAST time domain |
| INST "SYNC_IN_?" TNM = "TNM_SET_CLK"; |
| TIMESPEC "TS_SET_CLK" = TO "TNM_SET_CLK" TIG; |
| # Timing Constraint for Clock Switch |
| # Block BUFGMUX is used as Assynchronous switcher |
| PIN "BUFGMUX_CLK_FAST.S" TIG; |
| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL/S3AN01_ChipScope.vhd |
|---|
| 0,0 → 1,612 |
| -- ======================================================================== |
| -- |
| -- S3AN01_ChipScope |
| -- |
| -- Logic Analyser based on Xilinx ChipScope IP Core for S3AN01 Board |
| -- |
| -- (c) miho 2013 / http://www.mlab.cz/PermaLink/XILINX_ChipScope |
| -- |
| -- Demo application contains some Clock Logic (DCM block and |
| -- clock switch to be able to set different sample clocks). |
| -- The main function is ChipScope Logic Analyser with 16 data inputs |
| -- (with 24 bit trigger) and storage for 1024 Data Samples. |
| -- |
| -- Sampling clock is selectable to 170/100/50/20/10/5/2/1MHz |
| -- |
| -- To implement the design the ChipScope license is required. |
| -- |
| -- To use (the logic analyser) no speceial license is needed, |
| -- WebPack ISE or Lab Tools is enough). Requires some compatible |
| -- JTAG cable. Compatible with MLAB Xilinx Virtual Cable as well |
| -- http://www.mlab.cz/PermaLink/XILINX_XVC |
| -- |
| -- Device: Spartan3AN XC3S50AN-4TQG144C |
| -- |
| -- Software: ISE WebPack 14.5 |
| -- |
| -- ======================================================================== |
| -- Standard Library |
| library IEEE; |
| use IEEE.STD_LOGIC_1164.ALL; |
| use IEEE.numeric_std.ALL; |
| -- Xilinx Library (necessary for DMC and other Xilinx blocks) |
| library UNISIM; |
| use UNISIM.VComponents.all; |
| -- Interface |
| entity S3AN01_ChipScope is |
| generic( |
| ILA_WIDE: boolean := TRUE; -- TRUE/FALSE -> 18bit x 1024 / 9bit x 2048 logic analyser |
| MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
| ); |
| port( |
| -- Main Clock |
| CLK100MHz: in std_logic; -- 100MHz external xtal clock source |
| -- Mode Signals (usualy not used) |
| VS: out std_logic_vector(2 downto 0); -- SPI Flash Vendor Mode Select |
| -- Dipswitch Inputs |
| DIPSW: in std_logic_vector(7 downto 0); |
| -- LED Bar Outputs |
| LED: out std_logic_vector(7 downto 0); |
| -- LED Display (8 digits with 7 segments and decimal point) |
| LD_CA_n: out std_logic_vector(7 downto 0); |
| LD_SEG_n: out std_logic_vector(7 downto 0); |
| -- Bank 1 Pins Inputs |
| P: in std_logic_vector(24 downto 0); |
| -- Diferencial Signals on 4 pin header (J7) |
| DIF1P: inout std_logic; |
| DIF1N: inout std_logic; |
| DIF2P: inout std_logic; |
| DIF2N: inout std_logic |
| ); |
| end S3AN01_ChipScope; |
| -- Implementation |
| architecture S3AN01_ChipScope_a of S3AN01_ChipScope is |
| -- Clock Signals |
| -- ============= |
| -- DCM Signals |
| signal DCM_CLK0: std_logic; -- DCM output for feedback |
| signal DCM_CLKFX: std_logic; -- DCM output of the fastest clock |
| signal CLK_FAST: std_logic; -- Main clock for ILA |
| signal CLK_FAST_Q: std_logic; -- Auxiliary signal (for CLK_FAST sent to pin) |
| -- 100MHz Clock Switch |
| -- CLK100MHz Clock Domain |
| signal CLK100MHz_CE: std_logic; -- Gate Signal for slow dwn of the 100MHz clock |
| signal CLK100MHz_Gated: std_logic; -- Gated Clocks |
| signal CLK100MHz_CE_Cnt: unsigned(6 downto 0) := (others => '0'); -- Gate Signal Counter (min frequency is 1/100 of CLK100MHz |
| -- 1 Hot Clock Select Signals |
| -- CLK100MHz Clock Domain |
| signal SET_CLK_MAX: std_logic := '0'; -- Clock Select Signal - Maximim (150-170Mhz) |
| signal SET_CLK_100MHz: std_logic := '1'; -- Clock Select Signal - 100MHz |
| signal SET_CLK_50MHz: std_logic := '0'; -- Clock Select Signal - 50MHz |
| signal SET_CLK_20Mhz: std_logic := '0'; -- Clock Select Signal - 20MHz |
| signal SET_CLK_10Mhz: std_logic := '0'; -- Clock Select Signal - 10MHz |
| signal SET_CLK_5Mhz: std_logic := '0'; -- Clock Select Signal - 5MHz |
| signal SET_CLK_2Mhz: std_logic := '0'; -- Clock Select Signal - 2MHz |
| signal SET_CLK_1Mhz: std_logic := '0'; -- Clock Select Signal - 1MHz |
| -- Signals from and to ChipScope Virtual IO (set and display frequency) |
| -- CLK_FAST and CLK100MHz time domain |
| signal SYNC_IN: std_logic_vector(7 downto 0); -- Input to ChipScope VIO |
| signal SYNC_OUT: std_logic_vector(7 downto 0); -- Output from ChipScope VIO |
| signal SW_SYNC: std_logic_vector(7 downto 0) := (others => '0'); -- Asyn inputs synced |
| -- LED Ouput with time multiplex |
| -- ============================= |
| signal WideBCD: std_logic_vector(2*5-1 downto 0); -- Constant width of ILA in BCD (2 char wide) |
| signal FrequencyBCD: std_logic_vector(3*5-1 downto 0); -- Selected frequency in BCD (3 char wide) |
| signal Code: std_logic_vector(4 downto 0); -- BCD to 7 Segment Decoder Output |
| signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
| -- Time Multiplex |
| signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
| signal LedEnable: std_logic; -- LED Display Brightness |
| signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
| -- Test Generator signals |
| -- ====================== |
| signal Counter: std_logic_vector(7 downto 0); -- Counter |
| -- ChipScope Signals |
| -- ================= |
| -- Input data |
| -- CLK_FAST Clock Domain |
| signal DataReg: std_logic_vector(P'range); -- Data and Trigger input |
| -- Trigger Output |
| signal TriggerOut: std_logic; -- Trigegr output from ChipScope ILA to pin |
| -- User Outputs from ChipScope Virtual IO |
| signal SYNC_OUT_USER: std_logic_vector(2 downto 0); -- Output from ChipScope VIO |
| -- ChipScope Control Signals |
| signal Control0: std_logic_vector(35 downto 0); |
| signal Control1: std_logic_vector(35 downto 0); |
| signal Control2: std_logic_vector(35 downto 0); |
| -- ChipScope Control Block |
| component ChipScope_ICON |
| port ( |
| CONTROL0: inout std_logic_vector(35 downto 0); |
| CONTROL1: inout std_logic_vector(35 downto 0); |
| CONTROL2: inout std_logic_vector(35 downto 0) |
| ); |
| end component; |
| -- ChipScope Virtual I/O Block |
| component ChipScope_VIO_FreqSel |
| port ( |
| CONTROL: inout std_logic_vector(35 downto 0); |
| CLK: in std_logic; |
| SYNC_IN: in std_logic_vector(7 downto 0); |
| SYNC_OUT: out std_logic_vector(7 downto 0) |
| ); |
| end component; |
| -- ChipScope Virtual I/O Block |
| component ChipScope_VIO_UserOut |
| port ( |
| CONTROL: inout std_logic_vector(35 downto 0); |
| CLK: in std_logic; |
| SYNC_OUT: out std_logic_vector(2 downto 0) |
| ); |
| end component; |
| -- ChipScope Integrated Logic Analyser |
| component ChipScope_ILA_18_1024 |
| port ( |
| CONTROL: inout std_logic_vector(35 downto 0); |
| CLK: in std_logic; |
| DATA: in std_logic_vector(17 downto 0); -- 18 bits wide data |
| TRIG0: in std_logic_vector(23 downto 0); |
| TRIG_OUT: out std_logic |
| ); |
| end component; |
| -- ChipScope Integrated Logic Analyser |
| component ChipScope_ILA_9_2048 |
| port ( |
| CONTROL: inout std_logic_vector(35 downto 0); |
| CLK: in std_logic; |
| DATA: in std_logic_vector(8 downto 0); -- 9 bits wide data |
| TRIG0: in std_logic_vector(23 downto 0); |
| TRIG_OUT: out std_logic |
| ); |
| end component; |
| begin |
| -- =================================================== |
| -- Clock Network and Clock Switching |
| -- =================================================== |
| -- |
| -- The fastest clock signal is generated from 100MHz by DCM. |
| -- The design maximim is 170MHz for selected device. |
| -- |
| -- For lower frequency the 100MHz clocks are gated in BUFGCE |
| -- acording to SET_CLK_xxx signals. |
| -- |
| -- For Logic Analyser we use 170MHz from DCM or gated 100MHz |
| -- switchd by BUFGMUX block. |
| -- DCM_SP: Digital Clock Manager Circuit |
| -- Spartan-3A |
| -- Xilinx HDL Language Template, version 14.5 |
| -- |
| -- CLKFB without BUFG (we do not need phase relation to the original clock) |
| -- |
| -- Design Limits (XC3S50AN-4): |
| -- |
| -- 5/3 -> 166MHz - o.k. (best 5.9ns - 169.5MHz) |
| -- 17/10 -> 170MHz - o.k. (best 5.748ns - 174MHz) <------ Used Here |
| -- 12/7 -> 171MHz - Timing Error |
| -- 7/4 -> 175MHz - Timing Error |
| -- 18/10 -> 180MHz - Timing Error |
| -- |
| DCM_SP_inst: DCM_SP |
| generic map ( |
| CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 |
| CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32 |
| CLKFX_MULTIPLY => 17, -- Can be any integer from 2 to 32 |
| CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature |
| CLKIN_PERIOD => 10.0, -- Specify period of input clock |
| CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" |
| CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" |
| DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15 |
| DLL_FREQUENCY_MODE => "HIGH", -- "HIGH" or "LOW" frequency mode for DLL |
| DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE |
| PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 |
| STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE |
| ) |
| port map ( |
| CLK0 => DCM_CLK0, -- 0 degree DCM CLK ouptput |
| -- CLK180 => CLK180, -- 180 degree DCM CLK output |
| -- CLK270 => CLK270, -- 270 degree DCM CLK output |
| -- CLK2X => CLK2X, -- 2X DCM CLK output |
| -- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out |
| -- CLK90 => CLK90, -- 90 degree DCM CLK output |
| -- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE) |
| CLKFX => DCM_CLKFX, -- DCM CLK synthesis out (M/D) |
| -- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out |
| -- LOCKED => LOCKED, -- DCM LOCK status output |
| -- PSDONE => PSDONE, -- Dynamic phase adjust done output |
| -- STATUS => STATUS, -- 8-bit DCM status bits output |
| CLKFB => DCM_CLK0, -- DCM clock feedback |
| CLKIN => CLK100MHz, -- Clock input (from IBUFG, BUFG or DCM) |
| -- PSCLK => PSCLK, -- Dynamic phase adjust clock input |
| -- PSEN => PSEN, -- Dynamic phase adjust enable input |
| -- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement |
| RST => '0' -- DCM asynchronous reset input |
| ); |
| -- Generate Clock Gate signal for 100MHz Clock |
| process (CLK100MHz) |
| begin |
| if rising_edge(CLK100MHz) then |
| if CLK100MHz_CE_Cnt=0 then |
| CLK100MHz_CE <= '1'; |
| if SET_CLK_100MHz='1' then |
| CLK100MHz_CE_Cnt <= to_unsigned(1-1, CLK100MHz_CE_Cnt'length); |
| elsif SET_CLK_50MHz='1' then |
| CLK100MHz_CE_Cnt <= to_unsigned(2-1, CLK100MHz_CE_Cnt'length); |
| elsif SET_CLK_20MHz='1' then |
| CLK100MHz_CE_Cnt <= to_unsigned(5-1, CLK100MHz_CE_Cnt'length); |
| elsif SET_CLK_10MHz='1' then |
| CLK100MHz_CE_Cnt <= to_unsigned(10-1, CLK100MHz_CE_Cnt'length); |
| elsif SET_CLK_5MHz='1' then |
| CLK100MHz_CE_Cnt <= to_unsigned(20-1, CLK100MHz_CE_Cnt'length); |
| elsif SET_CLK_2MHz='1' then |
| CLK100MHz_CE_Cnt <= to_unsigned(50-1, CLK100MHz_CE_Cnt'length); |
| elsif SET_CLK_1MHz='1' then |
| CLK100MHz_CE_Cnt <= to_unsigned(100-1, CLK100MHz_CE_Cnt'length); |
| end if; |
| else |
| CLK100MHz_CE <= '0'; |
| CLK100MHz_CE_Cnt <= CLK100MHz_CE_Cnt-1; |
| end if; |
| end if; |
| end process; |
| -- Gate 100MHz Clocks (to produce 100/50/20/10/5/2/1 MHz) |
| -- Generates 5ns pulses with 10/20/50/100/200/500/1000ns period |
| BUFGCE_CLK100MHz: BUFGCE |
| port map ( |
| I => CLK100MHz, -- Clock buffer input |
| CE => CLK100MHz_CE, -- Clock enable input |
| O => CLK100MHz_Gated -- Clock buffer ouptput |
| ); |
| -- Switch (gated) 100MHz and the fastest Clock signal from DCM |
| BUFGMUX_CLK_FAST: BUFGMUX |
| port map ( |
| I0 => CLK100MHz_Gated, -- Clock0 input -- 100/50/20/10/50/20/1MHz |
| I1 => DCM_CLKFX, -- Clock1 input -- 170MHz |
| S => SET_CLK_MAX, -- Clock select input |
| O => CLK_FAST -- Clock MUX output |
| ); |
| -- Assynchrnous inputs and inputs from CLK_FAST clock domain must be synchronised |
| -- SYNC_OUT - CLK_FAST clock domain |
| -- DIPSW - External (off-chip) async inputs |
| process (CLK100MHz) |
| begin |
| if rising_edge(CLK100MHz) then |
| SW_SYNC <= SYNC_OUT or DIPSW; |
| end if; |
| end process; |
| -- Ferquency Selector |
| -- FSM - 1 hot |
| process (CLK100MHz) |
| variable TMP: std_logic_vector(SYNC_OUT'range); |
| variable NEW_DATA: std_logic; |
| begin |
| if rising_edge(CLK100MHz) then |
| TMP := (others => '0'); |
| NEW_DATA := '1'; |
| if SW_SYNC(7)='1' then |
| TMP(7) := '1'; |
| elsif SW_SYNC(6)='1' then |
| TMP(6) := '1'; |
| elsif SW_SYNC(5)='1' then |
| TMP(5) := '1'; |
| elsif SW_SYNC(4)='1' then |
| TMP(4) := '1'; |
| elsif SW_SYNC(3)='1' then |
| TMP(3) := '1'; |
| elsif SW_SYNC(2)='1' then |
| TMP(2) := '1'; |
| elsif SW_SYNC(1)='1' then |
| TMP(1) := '1'; |
| elsif SW_SYNC(0)='1' then |
| TMP(0) := '1'; |
| else |
| NEW_DATA := '0'; |
| end if; |
| if NEW_DATA='1' then |
| SET_CLK_MAX <= TMP(7); |
| SET_CLK_100MHz <= TMP(6); |
| SET_CLK_50MHz <= TMP(5); |
| SET_CLK_20MHz <= TMP(4); |
| SET_CLK_10MHz <= TMP(3); |
| SET_CLK_5MHz <= TMP(2); |
| SET_CLK_2MHz <= TMP(1); |
| SET_CLK_1MHz <= TMP(0); |
| end if; |
| end if; |
| end process; |
| -- Send selected frequency to ChipScope Virtual IO |
| -- Sync it to the CLK_FAST timing domain |
| SET_CLK_proc: process (CLK_FAST) |
| begin |
| if rising_edge(CLK_FAST) then |
| SYNC_IN(7) <= SET_CLK_MAX; |
| SYNC_IN(6) <= SET_CLK_100MHz; |
| SYNC_IN(5) <= SET_CLK_50MHz; |
| SYNC_IN(4) <= SET_CLK_20Mhz; |
| SYNC_IN(3) <= SET_CLK_10Mhz; |
| SYNC_IN(2) <= SET_CLK_5Mhz; |
| SYNC_IN(1) <= SET_CLK_2Mhz; |
| SYNC_IN(0) <= SET_CLK_1Mhz; |
| end if; |
| end process; |
| -- =================================================== |
| -- ChipScope Instance - Control / Virtual IO / ILA |
| -- =================================================== |
| -- ChipScope Instance - Control Block |
| MyChipScopeICON: ChipScope_ICON |
| port map ( |
| CONTROL0 => Control0, |
| CONTROL1 => Control1, |
| CONTROL2 => Control2 |
| ); |
| -- ChipScope Instance - Virtual I/O Block |
| MyChipScopeVIO_FreqSel: ChipScope_VIO_FreqSel |
| port map ( |
| CONTROL => Control0, |
| CLK => CLK_FAST, |
| SYNC_IN => SYNC_IN, |
| SYNC_OUT => SYNC_OUT |
| ); |
| -- ChipScope Instance - Virtual I/O Block |
| MyChipScopeVIO_UserOut: ChipScope_VIO_UserOut |
| port map ( |
| CONTROL => Control1, |
| CLK => CLK_FAST, |
| SYNC_OUT => SYNC_OUT_USER |
| ); |
| -- ChipScope Instance - Integrated Logic Analyser |
| ILA_18_1024: if ILA_WIDE generate |
| begin |
| MyChipScopeILA: ChipScope_ILA_18_1024 |
| port map ( |
| CONTROL => Control2, |
| CLK => CLK_FAST, |
| DATA => DataReg(17 downto 0), |
| TRIG0 => DataReg(23 downto 0), |
| TRIG_OUT => TriggerOut |
| ); |
| end generate; |
| ILA_9_2048: if not ILA_WIDE generate |
| begin |
| MyChipScopeILA: ChipScope_ILA_9_2048 |
| port map ( |
| CONTROL => Control2, |
| CLK => CLK_FAST, |
| DATA => DataReg(8 downto 0), |
| TRIG0 => DataReg(23 downto 0), |
| TRIG_OUT => TriggerOut |
| ); |
| end generate; |
| -- Data inputs (ILA does not like to have data inputs connected to io pins) |
| process(CLK_FAST) |
| begin |
| if rising_edge(CLK_FAST) then |
| DataReg <= P(DataReg'range); |
| end if; |
| end process; |
| -- VIO User Outputs |
| VS <= SYNC_OUT_USER; |
| -- Trigger Output (Diferencial signal) |
| OBUFDS_TriggerOut: OBUFDS |
| generic map ( |
| IOSTANDARD => "DEFAULT" |
| ) |
| port map ( |
| I => TriggerOut, -- Buffer input |
| O => DIF1P, -- Diff_p output (connect directly to top-level port) |
| OB => DIF1N -- Diff_n output (connect directly to top-level port) |
| ); |
| -- =================================================== |
| -- LED Display (multiplexed) |
| -- =================================================== |
| -- Frequency in BCD |
| FrequencyBCD <= "00001"&"00111"&"00000" when SET_CLK_MAX='1' else -- 170 MHz |
| "00001"&"00000"&"00000" when SET_CLK_100MHz='1' else -- 100 MHz |
| "11111"&"00101"&"00000" when SET_CLK_50MHz='1' else -- 50 MHz |
| "11111"&"00010"&"00000" when SET_CLK_20MHz='1' else -- 20 MHz |
| "11111"&"00001"&"00000" when SET_CLK_10MHz='1' else -- 10 MHz |
| "11111"&"11111"&"00101" when SET_CLK_5MHz='1' else -- 5 MHz |
| "11111"&"11111"&"00010" when SET_CLK_2MHz='1' else -- 2 MHz |
| "11111"&"11111"&"00001" when SET_CLK_1MHz='1' else -- 1 MHz |
| "11111"&"11111"&"11111"; |
| -- ILA width in BCD |
| ILA_DCD_18_1024: if ILA_WIDE generate |
| begin |
| WideBCD <= "00001"&"01000"; |
| end generate; |
| ILA_DCD_9_2048: if not ILA_WIDE generate |
| begin |
| WideBCD <= "11111"&"01001"; |
| end generate; |
| -- Input data selector ( WIDE / ILA / FREQ ) |
| Code <= FrequencyBCD( 4 downto 0) when Digits="00000001" else |
| FrequencyBCD( 9 downto 5) when Digits="00000010" else |
| FrequencyBCD(14 downto 10) when Digits="00000100" else |
| "10010" when Digits="00001000" else -- A |
| "10001" when Digits="00010000" else -- L |
| "10000" when Digits="00100000" else -- I |
| WideBCD( 4 downto 0) when Digits="01000000" else |
| WideBCD( 9 downto 5) when Digits="10000000" else |
| "11111"; |
| -- Time Multiplex |
| process (CLK100MHz) |
| begin |
| if rising_edge(CLK100MHz) then |
| if MuxCounter < MUXCOUNT-1 then |
| MuxCounter <= MuxCounter + 1; |
| else |
| MuxCounter <= (others => '0'); |
| Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left (1 hot encoded) |
| end if; |
| -- Display brightness (1/2) |
| if MuxCounter > (MUXCOUNT-MUXCOUNT/2) then |
| LedEnable <= '1'; |
| else |
| LedEnable <= '0'; |
| end if; |
| end if; |
| end process; |
| -- BCD to 7 Segmet Decoder |
| -- -- A |
| -- | | F B |
| -- -- G |
| -- | | E C |
| -- -- D H |
| -- HGFEDCBA |
| Segments <= "00111111" when Code="00000" else -- Digit 0 -- Hex Didits |
| "00000110" when Code="00001" else -- Digit 1 |
| "01011011" when Code="00010" else -- Digit 2 |
| "01001111" when Code="00011" else -- Digit 3 |
| "01100110" when Code="00100" else -- Digit 4 |
| "01101101" when Code="00101" else -- Digit 5 |
| "01111101" when Code="00110" else -- Digit 6 |
| "00000111" when Code="00111" else -- Digit 7 |
| "01111111" when Code="01000" else -- Digit 8 |
| "01101111" when Code="01001" else -- Digit 9 |
| "01110111" when Code="01010" else -- Digit A |
| "01111100" when Code="01011" else -- Digit b |
| "00111001" when Code="01100" else -- Digit C |
| "01011110" when Code="01101" else -- Digit d |
| "01111001" when Code="01110" else -- Digit E |
| "00110001" when Code="01111" else -- Digit F |
| "00000110" when Code="10000" else -- Digit I -- User Digits |
| "00111000" when Code="10001" else -- Digit L |
| "01110111" when Code="10010" else -- Digit A |
| "00000000"; -- none |
| -- Connect LED Display Output Ports (negative outputs) |
| LD_CA_n <= not Digits; |
| LD_SEG_n <= not Segments when LedEnable='1' else "11111111"; |
| -- =================================================== |
| -- Test generator (counter) |
| -- =================================================== |
| -- Test counter |
| process(CLK100MHz) |
| begin |
| if rising_edge(CLK100MHz) then |
| Counter <= std_logic_vector(unsigned(Counter) + 1); |
| end if; |
| end process; |
| -- Test outputs |
| LED <= Counter; |
| -- CLK_FAST Output - DDR register |
| ODDR2_FastClk: ODDR2 |
| generic map( |
| DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" |
| INIT => '0', -- Sets initial state of the Q output to '0' or '1' |
| SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset |
| ) |
| port map ( |
| C0 => CLK_FAST, -- 1-bit clock input |
| C1 => not CLK_FAST, -- 1-bit clock input |
| CE => '1', -- 1-bit clock enable input |
| D0 => '0', -- 1-bit data input (associated with C0) |
| D1 => '1', -- 1-bit data input (associated with C1) |
| R => '0', -- 1-bit reset input |
| S => '0', -- 1-bit set input |
| Q => CLK_FAST_Q -- 1-bit output data |
| ); |
| -- CLK_FAST Output - differncial pin buffer |
| OBUFDS_FastClkOut: OBUFDS |
| generic map ( |
| IOSTANDARD => "DEFAULT" |
| ) |
| port map ( |
| I => CLK_FAST_Q, -- Buffer input |
| O => DIF2P, -- Diff_p output (connect directly to top-level port) |
| OB => DIF2N -- Diff_n output (connect directly to top-level port) |
| ); |
| end S3AN01_ChipScope_a; |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/!____!.txt |
|---|
| 0,0 → 1,26 |
| FTDI D2XX library (for Windows), use latest version from http://www.ftdichip.com/Drivers/D2XX.htm |
| lib_win\ftd2xx.h <-- CDM v2.08.28 Certified\ftd2xx.h |
| lib_win\ftd2xx.lib <-- CDM v2.08.28 Certified\i386\ftd2xx.lib |
| FTDI D2XX library (for Linux), use latest version from http://www.ftdichip.com/Drivers/D2XX.htm |
| lib_linux\WinTypes.h <-- libftd2xx1.1.12.tar.gz/release/WinTypes.h |
| lib_linux\ftd2xx.h <-- libftd2xx1.1.12.tar.gz/release/examples/ftd2xx.h |
| lib_linux\i386\libftd2xx.a <-- libftd2xx1.1.12.tar.gz/release/build/i386/libftd2xx.a |
| lib_linux\x86_64\libftd2xx.a <-- libftd2xx1.1.12.tar.gz/release/build/x86_64/libftd2xx.a |
| FTDI D2XX library (for Raspberry Linux), use Raspberry fixed library (I have one from http://lightput.com/download.html) |
| The difference is in vfp setting. |
| lib_linux\arm926vfp\libftd2xx.a <-- libftd2xx1.1.12_Raspberry_Pi_Fix.tar.gz/release/build/arm926/libftd2xx.a |
| Main program, pin configuration is here in .h file |
| mlab_xvcd.h |
| mlab_xvcd.cpp |
| Hardware layer, uses FTDI D2XX library |
| mlab_xvcd_port_FTDI.h |
| mlab_xvcd_port_FTDI.cpp |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd_arm926vfp |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd_i386 |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd_x86_64 |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/10-MLAB-XVC-FTDI.rules |
|---|
| 0,0 → 1,23 |
| # Rule for unbinding XVC_FT220X device from ftdi_sio driver and setting permissions for everyone |
| # Put this file to /etc/udev/rules.d |
| # MLAB Module XVC_FT220X for JTAG programming of Xilinx uses standard VendorID and DeviceID |
| # of used FTDI chips. Unfortunately on latest Linux there is udev automaticaly loading |
| # device driver ftdi_sio which creates ttyUSBxx device for any attached FTDI chip. |
| # This driver prevents XVC program to comunicate with FTDI chip via FT2XX library. |
| # It is necessary to disconnect (unbind) our FTDI device (identifyed by its name) from |
| # ftdi_sio driver. |
| # (c)miho 2013 http://www.mlab.cz |
| # Hints: |
| # lsusb -v |
| # udevadm info -a -p /devices/pci0000:00/0000:00:06.0/usb1/1-2/1-2:1.0 |
| # udevadm control --reload-rules |
| # Ubind "MLAB XVC with FTxxxx" form ftdi_sio driver to release it for mlab_xvc program |
| SUBSYSTEM=="usb", ATTRS{interface}=="MLAB XVC with FT*", RUN="/bin/sh -c 'echo %k > /sys/bus/usb/drivers/ftdi_sio/unbind'" |
| # Set permissions to the device to enable run mlab_xvc program without root permissions |
| # If you do not want everyone remove MODE and add GROUP |
| SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTRS{product}=="MLAB XVC with FT*", MODE:="0666", RUN+="/bin/sh -c 'echo k: %k p: %p >> /tmp/XVC'" |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd.exe |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/buildLinux.sh |
|---|
| 0,0 → 1,9 |
| # For fresh Ubuntu 64bit needs to install tools: |
| # sudo apt-get install build-essential |
| # On 64bit system you need 32bit library support to build 32bit application: |
| # sudo apt-get install g++-multilib |
| # Just compile and link the target executable: |
| gcc mlab_xvcd*.cpp lib_linux/i386/libftd2xx.a -m32 -lstdc++ -ldl -lpthread -lrt -Os -o mlab_xvcd_i386 |
| gcc mlab_xvcd*.cpp lib_linux/x86_64/libftd2xx.a -m64 -lstdc++ -ldl -lpthread -lrt -Os -o mlab_xvcd_x86_64 |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/buildRaspberry.sh |
|---|
| 0,0 → 1,23 |
| # Compile on raspberry. |
| # |
| # Get source |
| # |
| # sudo apt-get install subversion |
| # svn export svn://svn.mlab.cz/MLAB/Modules/CPLD_FPGA/XVC_XILINX/XVC_SOFTWARE/XVC_1x XVC |
| # |
| # Compile |
| # |
| # cd XVC |
| # chmod +x buildRaspberry.sh |
| # buildRaspberry.sh |
| # |
| # Copy udev rules |
| # |
| # sudo cp BIN/10-MLAB*.ules /etc/udev/rules.d |
| # |
| # Run the daemon |
| # |
| # mlab_xvcd_arm926vfp |
| # |
| # Just compile and link the target executable: |
| gcc mlab_xvcd*.cpp lib_linux/arm926vfp/libftd2xx.a -ldl -lpthread -lrt -Os -o mlab_xvcd_arm926vfp |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_linux/arm926vfp/readme.txt |
|---|
| 0,0 → 1,4 |
| For Raspberry Pi you have to use Raspberry version of the library. |
| The difference is in how the fpu is used (calling conventions). |
| The Linux for Raspberry uses vfp (hardware Vector Floating Point |
| coprocessor) but original FTDI library does not have the fpv switched on. |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_linux/arm926/libftd2xx.a |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_linux/i386/libftd2xx.a |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_linux/x86_64/libftd2xx.a |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_linux/WinTypes.h |
|---|
| 0,0 → 1,87 |
| #ifndef __WINDOWS_TYPES__ |
| #define __WINDOWS_TYPES__ |
| #define MAX_NUM_DEVICES 50 |
| #include <sys/time.h> |
| typedef unsigned int DWORD; |
| typedef unsigned int ULONG; |
| typedef unsigned short USHORT; |
| typedef unsigned short SHORT; |
| typedef unsigned char UCHAR; |
| typedef unsigned short WORD; |
| typedef unsigned char BYTE; |
| typedef BYTE *LPBYTE; |
| typedef unsigned int BOOL; |
| typedef unsigned char BOOLEAN; |
| typedef unsigned char CHAR; |
| typedef BOOL *LPBOOL; |
| typedef UCHAR *PUCHAR; |
| typedef const char *LPCSTR; |
| typedef char *PCHAR; |
| typedef void *PVOID; |
| typedef void *HANDLE; |
| typedef unsigned int LONG; |
| typedef int INT; |
| typedef unsigned int UINT; |
| typedef char *LPSTR; |
| typedef char *LPTSTR; |
| typedef DWORD *LPDWORD; |
| typedef WORD *LPWORD; |
| typedef ULONG *PULONG; |
| typedef PVOID LPVOID; |
| typedef void VOID; |
| typedef unsigned long long int ULONGLONG; |
| typedef struct _OVERLAPPED { |
| DWORD Internal; |
| DWORD InternalHigh; |
| DWORD Offset; |
| DWORD OffsetHigh; |
| HANDLE hEvent; |
| } OVERLAPPED, *LPOVERLAPPED; |
| typedef struct _SECURITY_ATTRIBUTES { |
| DWORD nLength; |
| LPVOID lpSecurityDescriptor; |
| BOOL bInheritHandle; |
| } SECURITY_ATTRIBUTES , *LPSECURITY_ATTRIBUTES; |
| typedef struct timeval SYSTEMTIME; |
| typedef struct timeval FILETIME; |
| #ifndef TRUE |
| #define TRUE 1 |
| #endif |
| #ifndef FALSE |
| #define FALSE 0 |
| #endif |
| // |
| // Modem Status Flags |
| // |
| #define MS_CTS_ON ((DWORD)0x0010) |
| #define MS_DSR_ON ((DWORD)0x0020) |
| #define MS_RING_ON ((DWORD)0x0040) |
| #define MS_RLSD_ON ((DWORD)0x0080) |
| // |
| // Error Flags |
| // |
| #define CE_RXOVER 0x0001 // Receive Queue overflow |
| #define CE_OVERRUN 0x0002 // Receive Overrun Error |
| #define CE_RXPARITY 0x0004 // Receive Parity Error |
| #define CE_FRAME 0x0008 // Receive Framing error |
| #define CE_BREAK 0x0010 // Break Detected |
| #define CE_TXFULL 0x0100 // TX Queue is full |
| #define CE_PTO 0x0200 // LPTx Timeout |
| #define CE_IOE 0x0400 // LPTx I/O Error |
| #define CE_DNS 0x0800 // LPTx Device not selected |
| #define CE_OOP 0x1000 // LPTx Out-Of-Paper |
| #define CE_MODE 0x8000 // Requested mode unsupported |
| #ifndef INVALID_HANDLE_VALUE |
| #define INVALID_HANDLE_VALUE 0xFFFFFFFF |
| #endif |
| #endif |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_linux/ftd2xx.h |
|---|
| 0,0 → 1,1087 |
| /*++ |
| Copyright (c) 2001-2011 Future Technology Devices International Limited |
| THIS SOFTWARE IS PROVIDED BY FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED "AS IS" |
| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL |
| FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
| OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) |
| HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR |
| TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
| EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| FTDI DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON FTDI PARTS. |
| FTDI DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE INFORMATION IS NOT MODIFIED. |
| IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, IT IS THE |
| RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES AND SUBSEQUENT WHQL |
| RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. |
| Module Name: |
| ftd2xx.h |
| Abstract: |
| Native USB device driver for FTDI FT232x, FT245x, FT2232x and FT4232x devices |
| FTD2XX library definitions |
| Environment: |
| user mode |
| --*/ |
| #ifndef FTD2XX_H |
| #define FTD2XX_H |
| #ifndef _WINDOWS |
| #include <pthread.h> |
| #define WINAPI |
| #endif |
| // The following ifdef block is the standard way of creating macros |
| // which make exporting from a DLL simpler. All files within this DLL |
| // are compiled with the FTD2XX_EXPORTS symbol defined on the command line. |
| // This symbol should not be defined on any project that uses this DLL. |
| // This way any other project whose source files include this file see |
| // FTD2XX_API functions as being imported from a DLL, whereas this DLL |
| // sees symbols defined with this macro as being exported. |
| #ifdef FTD2XX_EXPORTS |
| #define FTD2XX_API __declspec(dllexport) |
| #else |
| #define FTD2XX_API __declspec(dllimport) |
| #endif |
| #ifndef _WINDOWS |
| #include "WinTypes.h" |
| #ifdef FTD2XX_API |
| #undef FTD2XX_API |
| #define FTD2XX_API |
| #endif |
| #endif |
| typedef struct _EVENT_HANDLE{ |
| pthread_cond_t eCondVar; |
| pthread_mutex_t eMutex; |
| int iVar; |
| } EVENT_HANDLE; |
| typedef PVOID FT_HANDLE; |
| typedef ULONG FT_STATUS; |
| // |
| // Device status |
| // |
| enum { |
| FT_OK, |
| FT_INVALID_HANDLE, |
| FT_DEVICE_NOT_FOUND, |
| FT_DEVICE_NOT_OPENED, |
| FT_IO_ERROR, |
| FT_INSUFFICIENT_RESOURCES, |
| FT_INVALID_PARAMETER, |
| FT_INVALID_BAUD_RATE, //7 |
| FT_DEVICE_NOT_OPENED_FOR_ERASE, |
| FT_DEVICE_NOT_OPENED_FOR_WRITE, |
| FT_FAILED_TO_WRITE_DEVICE, |
| FT_EEPROM_READ_FAILED, |
| FT_EEPROM_WRITE_FAILED, |
| FT_EEPROM_ERASE_FAILED, |
| FT_EEPROM_NOT_PRESENT, |
| FT_EEPROM_NOT_PROGRAMMED, |
| FT_INVALID_ARGS, |
| FT_NOT_SUPPORTED, |
| FT_OTHER_ERROR |
| }; |
| #define FT_SUCCESS(status) ((status) == FT_OK) |
| // |
| // FT_OpenEx Flags |
| // |
| #define FT_OPEN_BY_SERIAL_NUMBER 1 |
| #define FT_OPEN_BY_DESCRIPTION 2 |
| #define FT_OPEN_BY_LOCATION 4 |
| // |
| // FT_ListDevices Flags (used in conjunction with FT_OpenEx Flags |
| // |
| #define FT_LIST_NUMBER_ONLY 0x80000000 |
| #define FT_LIST_BY_INDEX 0x40000000 |
| #define FT_LIST_ALL 0x20000000 |
| #define FT_LIST_MASK (FT_LIST_NUMBER_ONLY|FT_LIST_BY_INDEX|FT_LIST_ALL) |
| // |
| // Baud Rates |
| // |
| #define FT_BAUD_300 300 |
| #define FT_BAUD_600 600 |
| #define FT_BAUD_1200 1200 |
| #define FT_BAUD_2400 2400 |
| #define FT_BAUD_4800 4800 |
| #define FT_BAUD_9600 9600 |
| #define FT_BAUD_14400 14400 |
| #define FT_BAUD_19200 19200 |
| #define FT_BAUD_38400 38400 |
| #define FT_BAUD_57600 57600 |
| #define FT_BAUD_115200 115200 |
| #define FT_BAUD_230400 230400 |
| #define FT_BAUD_460800 460800 |
| #define FT_BAUD_921600 921600 |
| // |
| // Word Lengths |
| // |
| #define FT_BITS_8 (UCHAR) 8 |
| #define FT_BITS_7 (UCHAR) 7 |
| // |
| // Stop Bits |
| // |
| #define FT_STOP_BITS_1 (UCHAR) 0 |
| #define FT_STOP_BITS_2 (UCHAR) 2 |
| // |
| // Parity |
| // |
| #define FT_PARITY_NONE (UCHAR) 0 |
| #define FT_PARITY_ODD (UCHAR) 1 |
| #define FT_PARITY_EVEN (UCHAR) 2 |
| #define FT_PARITY_MARK (UCHAR) 3 |
| #define FT_PARITY_SPACE (UCHAR) 4 |
| // |
| // Flow Control |
| // |
| #define FT_FLOW_NONE 0x0000 |
| #define FT_FLOW_RTS_CTS 0x0100 |
| #define FT_FLOW_DTR_DSR 0x0200 |
| #define FT_FLOW_XON_XOFF 0x0400 |
| // |
| // Purge rx and tx buffers |
| // |
| #define FT_PURGE_RX 1 |
| #define FT_PURGE_TX 2 |
| // |
| // Events |
| // |
| typedef void (*PFT_EVENT_HANDLER)(DWORD,DWORD); |
| #define FT_EVENT_RXCHAR 1 |
| #define FT_EVENT_MODEM_STATUS 2 |
| #define FT_EVENT_LINE_STATUS 4 |
| // |
| // Timeouts |
| // |
| #define FT_DEFAULT_RX_TIMEOUT 300 |
| #define FT_DEFAULT_TX_TIMEOUT 300 |
| // |
| // Device types |
| // |
| typedef ULONG FT_DEVICE; |
| enum { |
| FT_DEVICE_BM, |
| FT_DEVICE_AM, |
| FT_DEVICE_100AX, |
| FT_DEVICE_UNKNOWN, |
| FT_DEVICE_2232C, |
| FT_DEVICE_232R, |
| FT_DEVICE_2232H, |
| FT_DEVICE_4232H, |
| FT_DEVICE_232H |
| }; |
| // |
| // Bit Modes |
| // |
| #define FT_BITMODE_RESET 0x00 |
| #define FT_BITMODE_ASYNC_BITBANG 0x01 |
| #define FT_BITMODE_MPSSE 0x02 |
| #define FT_BITMODE_SYNC_BITBANG 0x04 |
| #define FT_BITMODE_MCU_HOST 0x08 |
| #define FT_BITMODE_FAST_SERIAL 0x10 |
| #define FT_BITMODE_CBUS_BITBANG 0x20 |
| #define FT_BITMODE_SYNC_FIFO 0x40 |
| // |
| // FT232R CBUS Options EEPROM values |
| // |
| #define FT_232R_CBUS_TXDEN 0x00 // Tx Data Enable |
| #define FT_232R_CBUS_PWRON 0x01 // Power On |
| #define FT_232R_CBUS_RXLED 0x02 // Rx LED |
| #define FT_232R_CBUS_TXLED 0x03 // Tx LED |
| #define FT_232R_CBUS_TXRXLED 0x04 // Tx and Rx LED |
| #define FT_232R_CBUS_SLEEP 0x05 // Sleep |
| #define FT_232R_CBUS_CLK48 0x06 // 48MHz clock |
| #define FT_232R_CBUS_CLK24 0x07 // 24MHz clock |
| #define FT_232R_CBUS_CLK12 0x08 // 12MHz clock |
| #define FT_232R_CBUS_CLK6 0x09 // 6MHz clock |
| #define FT_232R_CBUS_IOMODE 0x0A // IO Mode for CBUS bit-bang |
| #define FT_232R_CBUS_BITBANG_WR 0x0B // Bit-bang write strobe |
| #define FT_232R_CBUS_BITBANG_RD 0x0C // Bit-bang read strobe |
| // |
| // FT232H CBUS Options EEPROM values |
| // |
| #define FT_232H_CBUS_TRISTATE 0x00 // Tristate |
| #define FT_232H_CBUS_TXLED 0x01 // Tx LED |
| #define FT_232H_CBUS_RXLED 0x02 // Rx LED |
| #define FT_232H_CBUS_TXRXLED 0x03 // Tx and Rx LED |
| #define FT_232H_CBUS_PWREN 0x04 // Power Enable |
| #define FT_232H_CBUS_SLEEP 0x05 // Sleep |
| #define FT_232H_CBUS_DRIVE_0 0x06 // Drive pin to logic 0 |
| #define FT_232H_CBUS_DRIVE_1 0x07 // Drive pin to logic 1 |
| #define FT_232H_CBUS_IOMODE 0x08 // IO Mode for CBUS bit-bang |
| #define FT_232H_CBUS_TXDEN 0x09 // Tx Data Enable |
| #define FT_232H_CBUS_CLK30 0x0A // 30MHz clock |
| #define FT_232H_CBUS_CLK15 0x0B // 15MHz clock |
| #define FT_232H_CBUS_CLK7_5 0x0C // 7.5MHz clock |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Open( |
| int deviceNumber, |
| FT_HANDLE *pHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_OpenEx( |
| PVOID pArg1, |
| DWORD Flags, |
| FT_HANDLE *pHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ListDevices( |
| PVOID pArg1, |
| PVOID pArg2, |
| DWORD Flags |
| ); |
| FTD2XX_API |
| FT_STATUS FT_SetVIDPID( |
| DWORD dwVID, |
| DWORD dwPID |
| ); |
| FTD2XX_API |
| FT_STATUS FT_GetVIDPID( |
| DWORD * pdwVID, |
| DWORD * pdwPID |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Close( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Read( |
| FT_HANDLE ftHandle, |
| LPVOID lpBuffer, |
| DWORD nBufferSize, |
| LPDWORD lpBytesReturned |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Write( |
| FT_HANDLE ftHandle, |
| LPVOID lpBuffer, |
| DWORD nBufferSize, |
| LPDWORD lpBytesWritten |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_IoCtl( |
| FT_HANDLE ftHandle, |
| DWORD dwIoControlCode, |
| LPVOID lpInBuf, |
| DWORD nInBufSize, |
| LPVOID lpOutBuf, |
| DWORD nOutBufSize, |
| LPDWORD lpBytesReturned, |
| LPOVERLAPPED lpOverlapped |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetBaudRate( |
| FT_HANDLE ftHandle, |
| ULONG BaudRate |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetDivisor( |
| FT_HANDLE ftHandle, |
| USHORT Divisor |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetDataCharacteristics( |
| FT_HANDLE ftHandle, |
| UCHAR WordLength, |
| UCHAR StopBits, |
| UCHAR Parity |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetFlowControl( |
| FT_HANDLE ftHandle, |
| USHORT FlowControl, |
| UCHAR XonChar, |
| UCHAR XoffChar |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ResetDevice( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetDtr( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ClrDtr( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetRts( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ClrRts( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetModemStatus( |
| FT_HANDLE ftHandle, |
| ULONG *pModemStatus |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetChars( |
| FT_HANDLE ftHandle, |
| UCHAR EventChar, |
| UCHAR EventCharEnabled, |
| UCHAR ErrorChar, |
| UCHAR ErrorCharEnabled |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Purge( |
| FT_HANDLE ftHandle, |
| ULONG Mask |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetTimeouts( |
| FT_HANDLE ftHandle, |
| ULONG ReadTimeout, |
| ULONG WriteTimeout |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetQueueStatus( |
| FT_HANDLE ftHandle, |
| DWORD *dwRxBytes |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetQueueStatusEx( |
| FT_HANDLE ftHandle, |
| DWORD *dwRxBytes |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetEventNotification( |
| FT_HANDLE ftHandle, |
| DWORD Mask, |
| PVOID Param |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetStatus( |
| FT_HANDLE ftHandle, |
| DWORD *dwRxBytes, |
| DWORD *dwTxBytes, |
| DWORD *dwEventDWord |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetBreakOn( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetBreakOff( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetWaitMask( |
| FT_HANDLE ftHandle, |
| DWORD Mask |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_WaitOnMask( |
| FT_HANDLE ftHandle, |
| DWORD *Mask |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetEventStatus( |
| FT_HANDLE ftHandle, |
| DWORD *dwEventDWord |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ReadEE( |
| FT_HANDLE ftHandle, |
| DWORD dwWordOffset, |
| LPWORD lpwValue |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_WriteEE( |
| FT_HANDLE ftHandle, |
| DWORD dwWordOffset, |
| WORD wValue |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EraseEE( |
| FT_HANDLE ftHandle |
| ); |
| // |
| // structure to hold program data for FT_Program function |
| // |
| typedef struct ft_program_data { |
| DWORD Signature1; // Header - must be 0x00000000 |
| DWORD Signature2; // Header - must be 0xffffffff |
| DWORD Version; // Header - FT_PROGRAM_DATA version |
| // 0 = original |
| // 1 = FT2232C extensions |
| // 2 = FT232R extensions |
| // 3 = FT2232H extensions |
| // 4 = FT4232H extensions |
| // 5 = FT232H extensions |
| WORD VendorId; // 0x0403 |
| WORD ProductId; // 0x6001 |
| char *Manufacturer; // "FTDI" |
| char *ManufacturerId; // "FT" |
| char *Description; // "USB HS Serial Converter" |
| char *SerialNumber; // "FT000001" if fixed, or NULL |
| WORD MaxPower; // 0 < MaxPower <= 500 |
| WORD PnP; // 0 = disabled, 1 = enabled |
| WORD SelfPowered; // 0 = bus powered, 1 = self powered |
| WORD RemoteWakeup; // 0 = not capable, 1 = capable |
| // |
| // Rev4 (FT232B) extensions |
| // |
| UCHAR Rev4; // non-zero if Rev4 chip, zero otherwise |
| UCHAR IsoIn; // non-zero if in endpoint is isochronous |
| UCHAR IsoOut; // non-zero if out endpoint is isochronous |
| UCHAR PullDownEnable; // non-zero if pull down enabled |
| UCHAR SerNumEnable; // non-zero if serial number to be used |
| UCHAR USBVersionEnable; // non-zero if chip uses USBVersion |
| WORD USBVersion; // BCD (0x0200 => USB2) |
| // |
| // Rev 5 (FT2232) extensions |
| // |
| UCHAR Rev5; // non-zero if Rev5 chip, zero otherwise |
| UCHAR IsoInA; // non-zero if in endpoint is isochronous |
| UCHAR IsoInB; // non-zero if in endpoint is isochronous |
| UCHAR IsoOutA; // non-zero if out endpoint is isochronous |
| UCHAR IsoOutB; // non-zero if out endpoint is isochronous |
| UCHAR PullDownEnable5; // non-zero if pull down enabled |
| UCHAR SerNumEnable5; // non-zero if serial number to be used |
| UCHAR USBVersionEnable5; // non-zero if chip uses USBVersion |
| WORD USBVersion5; // BCD (0x0200 => USB2) |
| UCHAR AIsHighCurrent; // non-zero if interface is high current |
| UCHAR BIsHighCurrent; // non-zero if interface is high current |
| UCHAR IFAIsFifo; // non-zero if interface is 245 FIFO |
| UCHAR IFAIsFifoTar; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IFAIsFastSer; // non-zero if interface is Fast serial |
| UCHAR AIsVCP; // non-zero if interface is to use VCP drivers |
| UCHAR IFBIsFifo; // non-zero if interface is 245 FIFO |
| UCHAR IFBIsFifoTar; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IFBIsFastSer; // non-zero if interface is Fast serial |
| UCHAR BIsVCP; // non-zero if interface is to use VCP drivers |
| // |
| // Rev 6 (FT232R) extensions |
| // |
| UCHAR UseExtOsc; // Use External Oscillator |
| UCHAR HighDriveIOs; // High Drive I/Os |
| UCHAR EndpointSize; // Endpoint size |
| UCHAR PullDownEnableR; // non-zero if pull down enabled |
| UCHAR SerNumEnableR; // non-zero if serial number to be used |
| UCHAR InvertTXD; // non-zero if invert TXD |
| UCHAR InvertRXD; // non-zero if invert RXD |
| UCHAR InvertRTS; // non-zero if invert RTS |
| UCHAR InvertCTS; // non-zero if invert CTS |
| UCHAR InvertDTR; // non-zero if invert DTR |
| UCHAR InvertDSR; // non-zero if invert DSR |
| UCHAR InvertDCD; // non-zero if invert DCD |
| UCHAR InvertRI; // non-zero if invert RI |
| UCHAR Cbus0; // Cbus Mux control |
| UCHAR Cbus1; // Cbus Mux control |
| UCHAR Cbus2; // Cbus Mux control |
| UCHAR Cbus3; // Cbus Mux control |
| UCHAR Cbus4; // Cbus Mux control |
| UCHAR RIsD2XX; // non-zero if using D2XX drivers |
| // |
| // Rev 7 (FT2232H) Extensions |
| // |
| UCHAR PullDownEnable7; // non-zero if pull down enabled |
| UCHAR SerNumEnable7; // non-zero if serial number to be used |
| UCHAR ALSlowSlew; // non-zero if AL pins have slow slew |
| UCHAR ALSchmittInput; // non-zero if AL pins are Schmitt input |
| UCHAR ALDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR AHSlowSlew; // non-zero if AH pins have slow slew |
| UCHAR AHSchmittInput; // non-zero if AH pins are Schmitt input |
| UCHAR AHDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR BLSlowSlew; // non-zero if BL pins have slow slew |
| UCHAR BLSchmittInput; // non-zero if BL pins are Schmitt input |
| UCHAR BLDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR BHSlowSlew; // non-zero if BH pins have slow slew |
| UCHAR BHSchmittInput; // non-zero if BH pins are Schmitt input |
| UCHAR BHDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR IFAIsFifo7; // non-zero if interface is 245 FIFO |
| UCHAR IFAIsFifoTar7; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IFAIsFastSer7; // non-zero if interface is Fast serial |
| UCHAR AIsVCP7; // non-zero if interface is to use VCP drivers |
| UCHAR IFBIsFifo7; // non-zero if interface is 245 FIFO |
| UCHAR IFBIsFifoTar7; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IFBIsFastSer7; // non-zero if interface is Fast serial |
| UCHAR BIsVCP7; // non-zero if interface is to use VCP drivers |
| UCHAR PowerSaveEnable; // non-zero if using BCBUS7 to save power for self-powered designs |
| // |
| // Rev 8 (FT4232H) Extensions |
| // |
| UCHAR PullDownEnable8; // non-zero if pull down enabled |
| UCHAR SerNumEnable8; // non-zero if serial number to be used |
| UCHAR ASlowSlew; // non-zero if AL pins have slow slew |
| UCHAR ASchmittInput; // non-zero if AL pins are Schmitt input |
| UCHAR ADriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR BSlowSlew; // non-zero if AH pins have slow slew |
| UCHAR BSchmittInput; // non-zero if AH pins are Schmitt input |
| UCHAR BDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR CSlowSlew; // non-zero if BL pins have slow slew |
| UCHAR CSchmittInput; // non-zero if BL pins are Schmitt input |
| UCHAR CDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR DSlowSlew; // non-zero if BH pins have slow slew |
| UCHAR DSchmittInput; // non-zero if BH pins are Schmitt input |
| UCHAR DDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR ARIIsTXDEN; // non-zero if port A uses RI as RS485 TXDEN |
| UCHAR BRIIsTXDEN; // non-zero if port B uses RI as RS485 TXDEN |
| UCHAR CRIIsTXDEN; // non-zero if port C uses RI as RS485 TXDEN |
| UCHAR DRIIsTXDEN; // non-zero if port D uses RI as RS485 TXDEN |
| UCHAR AIsVCP8; // non-zero if interface is to use VCP drivers |
| UCHAR BIsVCP8; // non-zero if interface is to use VCP drivers |
| UCHAR CIsVCP8; // non-zero if interface is to use VCP drivers |
| UCHAR DIsVCP8; // non-zero if interface is to use VCP drivers |
| // |
| // Rev 9 (FT232H) Extensions |
| // |
| UCHAR PullDownEnableH; // non-zero if pull down enabled |
| UCHAR SerNumEnableH; // non-zero if serial number to be used |
| UCHAR ACSlowSlewH; // non-zero if AC pins have slow slew |
| UCHAR ACSchmittInputH; // non-zero if AC pins are Schmitt input |
| UCHAR ACDriveCurrentH; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR ADSlowSlewH; // non-zero if AD pins have slow slew |
| UCHAR ADSchmittInputH; // non-zero if AD pins are Schmitt input |
| UCHAR ADDriveCurrentH; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR Cbus0H; // Cbus Mux control |
| UCHAR Cbus1H; // Cbus Mux control |
| UCHAR Cbus2H; // Cbus Mux control |
| UCHAR Cbus3H; // Cbus Mux control |
| UCHAR Cbus4H; // Cbus Mux control |
| UCHAR Cbus5H; // Cbus Mux control |
| UCHAR Cbus6H; // Cbus Mux control |
| UCHAR Cbus7H; // Cbus Mux control |
| UCHAR Cbus8H; // Cbus Mux control |
| UCHAR Cbus9H; // Cbus Mux control |
| UCHAR IsFifoH; // non-zero if interface is 245 FIFO |
| UCHAR IsFifoTarH; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IsFastSerH; // non-zero if interface is Fast serial |
| UCHAR IsFT1248H; // non-zero if interface is FT1248 |
| UCHAR FT1248CpolH; // FT1248 clock polarity - clock idle high (1) or clock idle low (0) |
| UCHAR FT1248LsbH; // FT1248 data is LSB (1) or MSB (0) |
| UCHAR FT1248FlowControlH; // FT1248 flow control enable |
| UCHAR IsVCPH; // non-zero if interface is to use VCP drivers |
| UCHAR PowerSaveEnableH; // non-zero if using ACBUS7 to save power for self-powered designs |
| } FT_PROGRAM_DATA, *PFT_PROGRAM_DATA; |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_Program( |
| FT_HANDLE ftHandle, |
| PFT_PROGRAM_DATA pData |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_ProgramEx( |
| FT_HANDLE ftHandle, |
| PFT_PROGRAM_DATA lpData, |
| char *Manufacturer, |
| char *ManufacturerId, |
| char *Description, |
| char *SerialNumber |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_Read( |
| FT_HANDLE ftHandle, |
| PFT_PROGRAM_DATA pData |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_ReadEx( |
| FT_HANDLE ftHandle, |
| PFT_PROGRAM_DATA lpData, |
| char *Manufacturer, |
| char *ManufacturerId, |
| char *Description, |
| char *SerialNumber |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_UASize( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwSize |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_UAWrite( |
| FT_HANDLE ftHandle, |
| PUCHAR pucData, |
| DWORD dwDataLen |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_UARead( |
| FT_HANDLE ftHandle, |
| PUCHAR pucData, |
| DWORD dwDataLen, |
| LPDWORD lpdwBytesRead |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetLatencyTimer( |
| FT_HANDLE ftHandle, |
| UCHAR ucLatency |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetLatencyTimer( |
| FT_HANDLE ftHandle, |
| PUCHAR pucLatency |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetBitMode( |
| FT_HANDLE ftHandle, |
| UCHAR ucMask, |
| UCHAR ucEnable |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetBitMode( |
| FT_HANDLE ftHandle, |
| PUCHAR pucMode |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetUSBParameters( |
| FT_HANDLE ftHandle, |
| ULONG ulInTransferSize, |
| ULONG ulOutTransferSize |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetDeviceInfo( |
| FT_HANDLE ftHandle, |
| FT_DEVICE *lpftDevice, |
| LPDWORD lpdwID, |
| PCHAR SerialNumber, |
| PCHAR Description, |
| LPVOID Dummy |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetDeviceLocId( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwLocId |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_StopInTask( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_RestartInTask( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetResetPipeRetryCount( |
| FT_HANDLE ftHandle, |
| DWORD dwCount |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ResetPort( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_CyclePort( |
| FT_HANDLE ftHandle |
| ); |
| // |
| // Win32-type functions |
| // |
| FTD2XX_API |
| FT_HANDLE WINAPI FT_W32_CreateFile( |
| LPCSTR lpszName, |
| DWORD dwAccess, |
| DWORD dwShareMode, |
| LPSECURITY_ATTRIBUTES lpSecurityAttributes, |
| DWORD dwCreate, |
| DWORD dwAttrsAndFlags, |
| HANDLE hTemplate |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_CloseHandle( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_ReadFile( |
| FT_HANDLE ftHandle, |
| LPVOID lpBuffer, |
| DWORD nBufferSize, |
| LPDWORD lpBytesReturned, |
| LPOVERLAPPED lpOverlapped |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_WriteFile( |
| FT_HANDLE ftHandle, |
| LPVOID lpBuffer, |
| DWORD nBufferSize, |
| LPDWORD lpBytesWritten, |
| LPOVERLAPPED lpOverlapped |
| ); |
| FTD2XX_API |
| DWORD WINAPI FT_W32_GetLastError( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_GetOverlappedResult( |
| FT_HANDLE ftHandle, |
| LPOVERLAPPED lpOverlapped, |
| LPDWORD lpdwBytesTransferred, |
| BOOL bWait |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_CancelIo( |
| FT_HANDLE ftHandle |
| ); |
| // |
| // Win32 COMM API type functions |
| // |
| typedef struct _FTCOMSTAT { |
| DWORD fCtsHold : 1; |
| DWORD fDsrHold : 1; |
| DWORD fRlsdHold : 1; |
| DWORD fXoffHold : 1; |
| DWORD fXoffSent : 1; |
| DWORD fEof : 1; |
| DWORD fTxim : 1; |
| DWORD fReserved : 25; |
| DWORD cbInQue; |
| DWORD cbOutQue; |
| } FTCOMSTAT, *LPFTCOMSTAT; |
| typedef struct _FTDCB { |
| DWORD DCBlength; /* sizeof(FTDCB) */ |
| DWORD BaudRate; /* Baudrate at which running */ |
| DWORD fBinary: 1; /* Binary Mode (skip EOF check) */ |
| DWORD fParity: 1; /* Enable parity checking */ |
| DWORD fOutxCtsFlow:1; /* CTS handshaking on output */ |
| DWORD fOutxDsrFlow:1; /* DSR handshaking on output */ |
| DWORD fDtrControl:2; /* DTR Flow control */ |
| DWORD fDsrSensitivity:1; /* DSR Sensitivity */ |
| DWORD fTXContinueOnXoff: 1; /* Continue TX when Xoff sent */ |
| DWORD fOutX: 1; /* Enable output X-ON/X-OFF */ |
| DWORD fInX: 1; /* Enable input X-ON/X-OFF */ |
| DWORD fErrorChar: 1; /* Enable Err Replacement */ |
| DWORD fNull: 1; /* Enable Null stripping */ |
| DWORD fRtsControl:2; /* Rts Flow control */ |
| DWORD fAbortOnError:1; /* Abort all reads and writes on Error */ |
| DWORD fDummy2:17; /* Reserved */ |
| WORD wReserved; /* Not currently used */ |
| WORD XonLim; /* Transmit X-ON threshold */ |
| WORD XoffLim; /* Transmit X-OFF threshold */ |
| BYTE ByteSize; /* Number of bits/byte, 4-8 */ |
| BYTE Parity; /* 0-4=None,Odd,Even,Mark,Space */ |
| BYTE StopBits; /* 0,1,2 = 1, 1.5, 2 */ |
| char XonChar; /* Tx and Rx X-ON character */ |
| char XoffChar; /* Tx and Rx X-OFF character */ |
| char ErrorChar; /* Error replacement char */ |
| char EofChar; /* End of Input character */ |
| char EvtChar; /* Received Event character */ |
| WORD wReserved1; /* Fill for now. */ |
| } FTDCB, *LPFTDCB; |
| typedef struct _FTTIMEOUTS { |
| DWORD ReadIntervalTimeout; /* Maximum time between read chars. */ |
| DWORD ReadTotalTimeoutMultiplier; /* Multiplier of characters. */ |
| DWORD ReadTotalTimeoutConstant; /* Constant in milliseconds. */ |
| DWORD WriteTotalTimeoutMultiplier; /* Multiplier of characters. */ |
| DWORD WriteTotalTimeoutConstant; /* Constant in milliseconds. */ |
| } FTTIMEOUTS,*LPFTTIMEOUTS; |
| FTD2XX_API |
| BOOL WINAPI FT_W32_ClearCommBreak( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_ClearCommError( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwErrors, |
| LPFTCOMSTAT lpftComstat |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_EscapeCommFunction( |
| FT_HANDLE ftHandle, |
| DWORD dwFunc |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_GetCommModemStatus( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwModemStatus |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_GetCommState( |
| FT_HANDLE ftHandle, |
| LPFTDCB lpftDcb |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_GetCommTimeouts( |
| FT_HANDLE ftHandle, |
| FTTIMEOUTS *pTimeouts |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_PurgeComm( |
| FT_HANDLE ftHandle, |
| DWORD dwMask |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetCommBreak( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetCommMask( |
| FT_HANDLE ftHandle, |
| ULONG ulEventMask |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetCommState( |
| FT_HANDLE ftHandle, |
| LPFTDCB lpftDcb |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetCommTimeouts( |
| FT_HANDLE ftHandle, |
| FTTIMEOUTS *pTimeouts |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetupComm( |
| FT_HANDLE ftHandle, |
| DWORD dwReadBufferSize, |
| DWORD dwWriteBufferSize |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_WaitCommEvent( |
| FT_HANDLE ftHandle, |
| PULONG pulEvent, |
| LPOVERLAPPED lpOverlapped |
| ); |
| // |
| // Device information |
| // |
| typedef struct _ft_device_list_info_node { |
| ULONG Flags; |
| ULONG Type; |
| ULONG ID; |
| DWORD LocId; |
| char SerialNumber[16]; |
| char Description[64]; |
| FT_HANDLE ftHandle; |
| } FT_DEVICE_LIST_INFO_NODE; |
| // Device information flags |
| enum { |
| FT_FLAGS_OPENED = 1, |
| FT_FLAGS_HISPEED = 2 |
| }; |
| FTD2XX_API |
| FT_STATUS WINAPI FT_CreateDeviceInfoList( |
| LPDWORD lpdwNumDevs |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetDeviceInfoList( |
| FT_DEVICE_LIST_INFO_NODE *pDest, |
| LPDWORD lpdwNumDevs |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetDeviceInfoDetail( |
| DWORD dwIndex, |
| LPDWORD lpdwFlags, |
| LPDWORD lpdwType, |
| LPDWORD lpdwID, |
| LPDWORD lpdwLocId, |
| LPVOID lpSerialNumber, |
| LPVOID lpDescription, |
| FT_HANDLE *pftHandle |
| ); |
| // |
| // Version information |
| // |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetDriverVersion( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwVersion |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetLibraryVersion( |
| LPDWORD lpdwVersion |
| ); |
| // |
| // Events |
| // |
| #define EV_RXCHAR 0x0001 // Any Character received |
| #define EV_RXFLAG 0x0002 // Received certain character |
| #define EV_TXEMPTY 0x0004 // Transmitt Queue Empty |
| #define EV_CTS 0x0008 // CTS changed state |
| #define EV_DSR 0x0010 // DSR changed state |
| #define EV_RLSD 0x0020 // RLSD changed state |
| #define EV_BREAK 0x0040 // BREAK received |
| #define EV_ERR 0x0080 // Line status error occurred |
| #define EV_RING 0x0100 // Ring signal detected |
| #define EV_PERR 0x0200 // Printer error occured |
| #define EV_RX80FULL 0x0400 // Receive buffer is 80 percent full |
| #define EV_EVENT1 0x0800 // Provider specific event 1 |
| #define EV_EVENT2 0x1000 // Provider specific event 2 |
| // |
| // Escape Functions |
| // |
| #define SETXOFF 1 // Simulate XOFF received |
| #define SETXON 2 // Simulate XON received |
| #define SETRTS 3 // Set RTS high |
| #define CLRRTS 4 // Set RTS low |
| #define SETDTR 5 // Set DTR high |
| #define CLRDTR 6 // Set DTR low |
| #define RESETDEV 7 // Reset device if possible |
| #define SETBREAK 8 // Set the device break line. |
| #define CLRBREAK 9 // Clear the device break line. |
| // |
| // PURGE function flags. |
| // |
| #define PURGE_TXABORT 0x0001 // Kill the pending/current writes to the comm port. |
| #define PURGE_RXABORT 0x0002 // Kill the pending/current reads to the comm port. |
| #define PURGE_TXCLEAR 0x0004 // Kill the transmit queue if there. |
| #define PURGE_RXCLEAR 0x0008 // Kill the typeahead buffer if there. |
| #ifdef __cplusplus |
| } |
| #endif |
| #endif /* FTD2XX_H */ |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.cpp |
|---|
| 0,0 → 1,751 |
| // MLAB Xilinx Virtual Cable Network Server |
| // ---------------------------------------- |
| // |
| // (c) miho 2012, 2013 http://www.mlab.cz/PermaLink/XVC_SOFTWARE |
| // |
| // This program if free. |
| // |
| // |
| // History: |
| // |
| // 1.00 2012_09 Proof of concept (no configuration, not for public release) |
| // 1.01 2012_09 Added parameter for device selection |
| // 1.02 2012_12 Error handling and debugged |
| // 1.03 2012_12 Release version ready to publish |
| // 1.04 2013_04 Socket Bind Error with explanation (multiple instance of XVC Server) |
| // 1.05 2013_04 Test FTDI cable during wait for Accept (to stop the server immediately when cable is disconnected) |
| // 1.06 2013_04 Added support for Linux (thanks to Martin Poviser) |
| // 1.07 2013_04 Rewritten Host Address function for Linux (function gethostbyname returns 127.0.1.1 on Debian systems) |
| // Solved compatibility problems on Linux (FT_SetLatncyTimer requires delay, udev problem with ftdi_sio driver) |
| // 1.08 2013_06 Added linux x86_64 variant |
| // |
| // |
| // Purpose: |
| // |
| // XILINX development software (ISE, WebPack) supports several types of JTAG programming |
| // cables. Among them there is one particularly interesting. It is Xilinx Virtual Cable |
| // which uses (documented) XVC network protocol to send JTAG commands across TCP/IP network. |
| // So it is possible to realize own hardware/software and have it directly supported by |
| // XILINX development software (both IMPACT and ChipScope). |
| // |
| // This program listens TCP data send by XILINX ISE IMAPACT (or ChipScope) and sends it |
| // to the JTAG device (typically FPGA) connected to FTDI USB Chip. You can use ordinary |
| // USB/RS232 translator based on FT232R chip or you can use our own module from |
| // http://www.mlab.cz/PermaLink/XVC_FT220X |
| // |
| // Target device JTAG port is connected to pins on FTDI USB chip. Program writes to standard |
| // output Which pins are used. Program writes what to set in ISE to enable XVC plugin. |
| // |
| // |
| // Environment: |
| // |
| // This is Win32 Console Application and run in WinXP / Win7 / Win8 both 32 and 64 bit. |
| // |
| // Program needs to listen to the network so it is necessary to allow doing so. In Windows |
| // firewall configuration enable networking for the exe file. |
| // WinXP: run as Administrator c:\WINDOWS\System32\firewall.cpl and add the exe file |
| // Win7: the system asks directly to do so |
| // |
| // |
| // Technology: |
| // |
| // The program uses Windows WINSOCK2 library for network communication |
| // and FTDI ftd2xx library for communication with FTDI USB chip. |
| // It can be staticly linked to minimize dependencies on libraries. |
| // Program requires FTDI drivers installed. |
| // Because of the usage of standard libraries you don't need to solve how to sign drivers. |
| // |
| // The program was debug with FT232R and FT220X device. |
| // It should work with any similar FTDI USB chip. |
| // |
| // XVC protocol is documented (you have to ask XILINX support to gain access). |
| // The program is inspired by the work http://debugmo.de/2012/02/xvcd-the-xilinx-virtual-cable-daemon/ |
| // Ask Google about Xilinx Virtual Cable. |
| // |
| // |
| // Compilation for Windows: |
| // |
| // MS Visual C++ 2010 Express (free, registration required) |
| // Create new empty project for Win32 Console Application and name project mlab_xvcd (to build mlab_xvcd.exe) |
| // Header Files / Add / Existing Items - all .h files |
| // Source Files / Add / Existing Items - all .cpp files |
| // Library Files / Add / Existing Items - all .lib .h files from lib_win32 directory |
| // Select Release version (no debug info) |
| // Set static linkage Project Properties / Configuration Release / Configuration Properties |
| // / Code Generation / Runtime Library = Multithreaded (/MT) |
| // |
| // Compilation for Linux: |
| // |
| // On Ubuntu 12.04LTS just run the .sh file |
| // |
| // Problems: |
| // |
| // Programming of SPI FLASH configuration memory connected to FPGA does not work. No idea why. |
| // It does not work for internal FLASH of Spartan XC3SxxAN either. |
| // |
| // |
| // Possible improvements: |
| // |
| // External definition of JTAG pins. |
| // Enable Socket Number (to be able to run multiple XVC Servers), now it is constant XVC_TCP_PORT (should be only a default) |
| // Library Definitions |
| // ------------------- |
| #undef UNICODE |
| #define WIN32_LEAN_AND_MEAN |
| #include "mlab_xvcd.h" // Program Configuration |
| #include <stdlib.h> // Standard Library (exit, atoi, ...) |
| #include <stdio.h> // Standard IO (printf, ...) |
| #include <signal.h> // CTRL+C handling |
| #ifdef WIN32 |
| #include <windows.h> // Windows Console Application |
| #include <winsock2.h> // Windows WinSock2 |
| #include <ws2tcpip.h> // Windows WinSock2 |
| // Link with library |
| #pragma comment (lib, "Ws2_32.lib") |
| //#pragma comment (lib, "../lib_win32/ftd2xx.lib") // Add this file to Resources |
| #else // not WIN32 |
| #include "lib_linux/WinTypes.h" |
| #include <sys/types.h> |
| #include <sys/socket.h> |
| #include <fcntl.h> |
| #include <errno.h> |
| #include <unistd.h> |
| #include <netdb.h> |
| #include <net/if.h> |
| #include <sys/ioctl.h> |
| #include <arpa/inet.h> |
| #endif |
| #define XVC_RX_BUFLEN (XVC_JTAG_LEN/8*2+20) // Length of receive buffer in bytes (command+length+TMSbuffer+TDIbuffer) |
| #define XVC_TX_BUFLEN (XVC_JTAG_LEN/8) // Length of transmit buffer in bytes (TDObuffer) |
| #ifdef WIN32 |
| typedef int socklen_t; |
| #else //not WIN32 |
| typedef int SOCKET; |
| #define SOCKET_ERROR -1 |
| #define INVALID_SOCKET -1 |
| void closesocket(int socket) |
| { |
| close(socket); |
| } |
| void WSACleanup() |
| { |
| } |
| int WSAGetLastError() |
| { |
| return errno; |
| } |
| #endif |
| // JTAG state machine |
| // ------------------ |
| // JTAG States |
| enum |
| { |
| test_logic_reset, run_test_idle, // Starts from 0 |
| select_dr_scan, capture_dr, shift_dr, |
| exit1_dr, pause_dr, exit2_dr, update_dr, |
| select_ir_scan, capture_ir, shift_ir, |
| exit1_ir, pause_ir, exit2_ir, update_ir, |
| num_states |
| }; |
| // JTAG State Machine transfer Function |
| static int jtagStep(int state, int tms) |
| { |
| static const int next_state[num_states][2] = |
| { |
| /* JTAG State -->> New State */ |
| /* -------------------------------------------------------------*/ |
| /* | TMS=0 | TMS=1 */ |
| /* -------------------------------------------------------------*/ |
| /* [test_logic_reset] -> */ { run_test_idle, test_logic_reset }, |
| /* [run_test_idle] -> */ { run_test_idle, select_dr_scan }, |
| /* [select_dr_scan] -> */ { capture_dr, select_ir_scan }, |
| /* [capture_dr] -> */ { shift_dr, exit1_dr }, |
| /* [shift_dr] -> */ { shift_dr, exit1_dr }, |
| /* [exit1_dr] -> */ { pause_dr, update_dr }, |
| /* [pause_dr] -> */ { pause_dr, exit2_dr }, |
| /* [exit2_dr] -> */ { shift_dr, update_dr }, |
| /* [update_dr] -> */ { run_test_idle, select_dr_scan }, |
| /* [select_ir_scan] -> */ { capture_ir, test_logic_reset }, |
| /* [capture_ir] -> */ { shift_ir, exit1_ir }, |
| /* [shift_ir] -> */ { shift_ir, exit1_ir }, |
| /* [exit1_ir] -> */ { pause_ir, update_ir }, |
| /* [pause_ir] -> */ { pause_ir, exit2_ir }, |
| /* [exit2_ir] -> */ { shift_ir, update_ir }, |
| /* [update_ir] -> */ { run_test_idle, select_dr_scan } |
| }; |
| return next_state[state][tms]; |
| } |
| int handleData(SOCKET ClientSocket) |
| { |
| bool seen_tlr = false; |
| bool jtagError = false; |
| static int jtag_state; |
| do |
| { |
| int iResult; |
| // Read Command |
| char command[16]; |
| unsigned int commandLen = 0; |
| // Read String terminated by ':' |
| do |
| { |
| iResult = recv(ClientSocket, command+commandLen, 1, 0); |
| if (iResult==0) |
| { |
| printf("\n Connection Closed\n\n"); |
| return -1; |
| } |
| else if (iResult==1) |
| { |
| commandLen++; |
| } |
| else |
| { |
| fprintf(stderr, "Error Reading Command\n"); |
| return -2; |
| } |
| } |
| while (command[commandLen-1]!=':' && commandLen<sizeof(command)-1 ); |
| command[commandLen] = char(0); |
| if (0==strncmp(command, "shift:", sizeof(command))) |
| { |
| } |
| else |
| { |
| fprintf(stderr, "Invalid Command '%s'\n", command); |
| return -2; |
| } |
| // Read Length (in bits, 32bit integer) |
| int len; |
| iResult = recv(ClientSocket, (char *)&len, 4, 0); // pøepsat pøenositelnì |
| if (iResult==0) |
| { |
| printf("\n Connection Closed\n\n"); |
| return -1; |
| } |
| if (iResult != 4) |
| { |
| fprintf(stderr, "Reading Length Failed\n"); |
| return -2; |
| } |
| char buffer[2048]; |
| // Read Data (data string for TMS and TDI) |
| unsigned int nr_bytes = (len + 7) / 8; |
| if (nr_bytes * 2 > sizeof(buffer)) |
| { |
| fprintf(stderr, "Buffer Size Exceeded\n"); |
| return -2; |
| } |
| unsigned int iReceivedBytes=0; |
| while (iReceivedBytes<nr_bytes * 2) |
| { |
| iResult = recv(ClientSocket, buffer+iReceivedBytes, nr_bytes * 2 - iReceivedBytes, 0); |
| if (iResult==0) |
| { |
| printf("\n Connection Closed\n\n"); |
| return -1; |
| } |
| if (iResult<=0) |
| { |
| fprintf(stderr, "Reading Data Failed %d %d\n", iResult, nr_bytes * 2); |
| return -2; |
| } |
| iReceivedBytes += iResult; |
| } |
| char result[1024]; |
| memset(result, 0, nr_bytes); |
| // Deal with JTAG |
| // Only allow exiting if the state is rti and the IR |
| // has the default value (IDCODE) by going through test_logic_reset. |
| // As soon as going through capture_dr or capture_ir no exit is |
| // allowed as this will change DR/IR. |
| seen_tlr = (seen_tlr || jtag_state == test_logic_reset) && (jtag_state != capture_dr) && (jtag_state != capture_ir); |
| // Due to a weird bug(??) xilinx impacts goes through another "capture_ir"/"capture_dr" cycle after |
| // reading IR/DR which unfortunately sets IR to the read-out IR value. |
| // Just ignore these transactions. |
| if ((jtag_state == exit1_ir && len == 5 && buffer[0] == 0x17) || (jtag_state == exit1_dr && len == 4 && buffer[0] == 0x0b)) |
| { |
| // printf("Ignoring Bogus jtag State movement at jtag_state %d\n", jtag_state); |
| } |
| else |
| { |
| for (int i = 0; i < len; ++i) |
| { |
| // |
| // Do the actual cycle. |
| // |
| int tms = !!(buffer[i/8] & (1<<(i&7))); |
| // |
| // Track the state. |
| // |
| jtag_state = jtagStep(jtag_state, tms); |
| } |
| if (jtagScan((unsigned char *) buffer, (unsigned char *) buffer + nr_bytes, (unsigned char *) result, len) < 0) |
| { |
| //fprintf(stderr, "jtagScan failed\n"); |
| // Can't stop now, have to sent (any) answer not to hung the IMPACT |
| jtagError = true; |
| } |
| } |
| // Send the Ansver |
| iResult = send(ClientSocket, result, nr_bytes, 0 ); |
| if (iResult == SOCKET_ERROR) |
| { |
| printf("Send Failed with Error: %d\n", WSAGetLastError()); |
| closesocket(ClientSocket); |
| WSACleanup(); |
| return -2; |
| } |
| // printf("Bytes Sent: %d\n", iSendResult); |
| // printf("jtag state %d\n", jtag_state); |
| } |
| while (!(seen_tlr && jtag_state == run_test_idle)); |
| return jtagError ? -2 : 0; |
| } |
| // Stop Handler - switch JTAG port off and stop program |
| void stopHandler(int) |
| { |
| jtagClosePort(); |
| exit(1); |
| } |
| // Print help and stop program with error |
| void Help(char *progName) |
| { |
| fprintf(stderr, "Bad Parameters\n"); |
| fprintf(stderr, "\n"); |
| fprintf(stderr, "Usage: %s [arg]\n", progName); |
| fprintf(stderr, "\n"); |
| fprintf(stderr, " Where [arg] is one of: \n"); |
| fprintf(stderr, " -d Description Fing FTDI device by Description\n"); |
| fprintf(stderr, " -l Location Fing FTDI device by Loaction\n"); |
| fprintf(stderr, " -s Serial_number Fing FTDI device by it's SN\n"); |
| fprintf(stderr, " -n Number Use N-th FTDI device\n"); |
| fprintf(stderr, " The first FTDI device is used if no argument\n"); |
| exit(2); |
| } |
| int main(int argc, char *argv[]) |
| { |
| // Variables |
| bool verbose = true; |
| // Program Info |
| printf("\n"); |
| printf("Xilinx Virtual Cable Network Server\n"); |
| printf("===================================\n"); |
| printf("(c) miho " YEAR " v " VERSION "\n\n"); |
| // Get program name |
| char *cp; |
| char *progName; |
| cp = argv[0]; |
| progName=cp; |
| while (cp[0]!='\0') |
| { |
| if (cp[0]=='/' || cp[0]=='\\') |
| progName=cp+1; |
| cp++; |
| } |
| // Process command line params |
| char *findDeviceByStr = 0; // String parameter |
| int findDeviceBy = 0; // What does the string means |
| if (argc>1) |
| { |
| if (argc==3) |
| { |
| findDeviceByStr = argv[2]; |
| if (strcmp(argv[1], "-d")==0) |
| { |
| findDeviceBy = OPEN_BY_DESCRIPTION; |
| } |
| else if (strcmp(argv[1], "-l")==0) |
| { |
| findDeviceBy = OPEN_BY_LOCATION; |
| } |
| else if (strcmp(argv[1], "-s")==0) |
| { |
| findDeviceBy = OPEN_BY_SERIAL_NUMBER; |
| } |
| else if (strcmp(argv[1], "-n")==0) |
| { |
| findDeviceBy = 0; |
| } |
| else |
| { |
| Help(progName); |
| } |
| } |
| else |
| { |
| Help(progName); |
| } |
| } |
| else |
| { |
| // Empty String - find device by number and number is empty |
| findDeviceBy = 0; |
| findDeviceByStr = (char *)""; |
| } |
| // Find, Init and Open FTDI USB Chip |
| if (jtagOpenPort(findDeviceBy, findDeviceByStr)<0) { |
| // No Device Found |
| fprintf(stderr, "ERROR: No Device Found\n"); |
| return -1; |
| } |
| // Signal Handler (for CRTL+C) |
| signal(SIGINT, &stopHandler); |
| printf("Starting Network Server\n"); |
| int iResult; |
| SOCKET ListenSocket = INVALID_SOCKET; |
| SOCKET ClientSocket = INVALID_SOCKET; |
| #ifdef WIN32 |
| // Initialize Winsock |
| WSADATA wsaData; |
| iResult = WSAStartup(MAKEWORD(2,2), &wsaData); |
| if (iResult != 0) |
| { |
| fprintf(stderr, "WSAStartup failed with error: %d\n", iResult); |
| jtagClosePort(); |
| return -2; |
| } |
| #endif |
| // Display HostName |
| char sMyName[255]; |
| gethostname(sMyName, sizeof(sMyName)); |
| printf(" Host Name %s\n", sMyName); |
| // Display Address |
| #ifdef WIN32 |
| hostent * pHostInfo; |
| pHostInfo = gethostbyname(sMyName); |
| printf(" Network Name %s\n", pHostInfo->h_name); |
| if (pHostInfo->h_length>0 && pHostInfo->h_length<=16) |
| { |
| printf(" Host Address "); |
| for (int i=0; i<pHostInfo->h_length-1; i++) |
| { |
| printf("%d.", (unsigned char)pHostInfo->h_addr_list[0][i]); |
| } |
| printf("%d\n", (unsigned char)pHostInfo->h_addr_list[0][pHostInfo->h_length-1]); |
| } |
| #else |
| int TempSocket; |
| struct ifreq ifreqs[20]; |
| struct ifconf ic; |
| ic.ifc_len = sizeof ifreqs; |
| ic.ifc_req = ifreqs; |
| TempSocket = socket(AF_INET, SOCK_DGRAM, 0); |
| if (TempSocket < 0) { |
| perror("socket"); |
| return -2; |
| } |
| if (ioctl(TempSocket, SIOCGIFCONF, &ic) < 0) { |
| perror("SIOCGIFCONF"); |
| return -2; |
| } |
| for (int i = 0; i < ic.ifc_len/sizeof(struct ifreq); ++i) |
| { |
| if (ifreqs[i].ifr_name[0]!='l')// remove lo |
| printf(" Host Address %s: %s\n", |
| ifreqs[i].ifr_name, |
| inet_ntoa(((struct sockaddr_in*)&ifreqs[i].ifr_addr)->sin_addr)); |
| } |
| #endif |
| // Create Protocol Structure |
| struct addrinfo hints; |
| memset(&hints, 0, sizeof(hints)); |
| hints.ai_family = AF_INET; // IP6 |
| hints.ai_socktype = SOCK_STREAM; // Reliable two-way connection |
| hints.ai_protocol = IPPROTO_TCP; // Protocol TCP |
| hints.ai_flags = AI_PASSIVE; |
| // Resolve the server address and port (allocate structure "result") |
| struct addrinfo *result = NULL; |
| iResult = getaddrinfo(NULL, XVC_TCP_PORT, &hints, &result); |
| if ( iResult != 0 ) |
| { |
| fprintf(stderr, "getaddrinfo failed with error: %d\n", iResult); |
| WSACleanup(); |
| jtagClosePort(); |
| return -2; |
| } |
| // Create a SOCKET |
| ListenSocket = socket(result->ai_family, result->ai_socktype, result->ai_protocol); |
| if (ListenSocket == INVALID_SOCKET) |
| { |
| fprintf(stderr, "socket failed with error: %d\n", WSAGetLastError()); |
| freeaddrinfo(result); |
| WSACleanup(); |
| jtagClosePort(); |
| return -2; |
| } |
| // Bind the SOCKED (assign the address) |
| iResult = bind(ListenSocket, result->ai_addr, (int)result->ai_addrlen); |
| if (iResult == SOCKET_ERROR) |
| { |
| int LastError=WSAGetLastError(); |
| fprintf(stderr, "Bind failed with error: %d\n", LastError); |
| #ifdef WIN32 |
| if (LastError==WSAEADDRINUSE) |
| #else |
| if (LastError==EADDRINUSE) |
| #endif |
| fprintf(stderr, "Trying to start second instance of XVC Server?\n"); |
| freeaddrinfo(result); |
| closesocket(ListenSocket); |
| WSACleanup(); |
| jtagClosePort(); |
| return -2; |
| } |
| if (verbose) |
| { |
| printf(" Bound Socket %s\n", XVC_TCP_PORT); |
| } |
| // Help for user |
| printf(" Set in IMPACT xilinx_xvc host=%s:%s disableversioncheck=true\n", sMyName, XVC_TCP_PORT); |
| freeaddrinfo(result); |
| // Listen SOCKET |
| iResult = listen(ListenSocket, SOMAXCONN); |
| if (iResult == SOCKET_ERROR) |
| { |
| fprintf(stderr, "listen failed with error: %d\n", WSAGetLastError()); |
| closesocket(ListenSocket); |
| WSACleanup(); |
| jtagClosePort(); |
| return -2; |
| } |
| printf("\n"); |
| do |
| { |
| printf(" Listen\n"); |
| jtagSetLED(true); |
| // Set ListenSocket to non-blocking mode |
| // We need during waiting for Accept to detect FTDI disconnect |
| #ifdef WIN32 |
| u_long iMode = 1; |
| iResult = ioctlsocket(ListenSocket, FIONBIO, &iMode); |
| if (iResult != NO_ERROR) |
| { |
| fprintf(stderr, "ioctlsocket failed with error: %ld\n", iResult); |
| WSACleanup(); |
| jtagClosePort(); |
| return -2; |
| } |
| #else |
| iResult = fcntl(ListenSocket, F_GETFL, 0); |
| if (iResult < 0 || fcntl(ListenSocket, F_SETFL, iResult | O_NONBLOCK) < 0) |
| { |
| fprintf(stderr, "fcntl failed with error: %d\n", errno); |
| jtagClosePort(); |
| return -2; |
| } |
| #endif |
| // Accept a client SOCKET (wait for Accept) |
| sockaddr ClientSocetAddr; |
| socklen_t ClientSocetAddrLen = sizeof(sockaddr); |
| do |
| { |
| // Try Accept (non-blocking) |
| ClientSocket = accept(ListenSocket, &ClientSocetAddr, &ClientSocetAddrLen); |
| if (ClientSocket == INVALID_SOCKET) |
| { |
| // Accept Error |
| #ifdef WIN32 |
| if (WSAGetLastError() != WSAEWOULDBLOCK) |
| #else |
| if (WSAGetLastError() != EAGAIN && WSAGetLastError() != EWOULDBLOCK) |
| #endif |
| { |
| fprintf(stderr, "accept failed with error: %d\n", WSAGetLastError()); |
| closesocket(ListenSocket); |
| WSACleanup(); |
| jtagClosePort(); |
| return -2; |
| } |
| // Not yet Accepted |
| { |
| // Check FTDI |
| if (!CheckCable()) |
| { |
| fprintf(stderr, "XVC Cable unexpectedly disconnected\n"); |
| closesocket(ListenSocket); |
| WSACleanup(); |
| jtagClosePort(); |
| return -2; |
| } |
| // Sleep some time (do not eat CPU time for nothong) |
| #ifdef WIN32 |
| Sleep(100); //ms |
| #else |
| usleep(100000); //us |
| #endif |
| } |
| } |
| } |
| while (ClientSocket == INVALID_SOCKET); |
| // Set (Accepted) Socket to blocking mode |
| #ifdef WIN32 |
| iMode = 0; |
| iResult = ioctlsocket(ClientSocket, FIONBIO, &iMode); |
| if (iResult != NO_ERROR) |
| { |
| fprintf(stderr, "ioctlsocket failed with error: %ld\n", iResult); |
| WSACleanup(); |
| jtagClosePort(); |
| return -2; |
| } |
| #else |
| iResult = fcntl(ListenSocket, F_GETFL, 0); |
| if (iResult < 0 || fcntl(ListenSocket, F_SETFL, iResult & ~O_NONBLOCK) < 0) |
| { |
| fprintf(stderr, "fcntl failed with error: %d\n", errno); |
| jtagClosePort(); |
| return -2; |
| } |
| #endif |
| // Print Accepted + Address |
| printf(" Accepted "); |
| jtagSetLED(false); |
| for (int i=2; i<2+4-1; i++) |
| { |
| printf("%d.", (unsigned char)ClientSocetAddr.sa_data[i]); |
| } |
| printf("%d:%d\n", (unsigned char)ClientSocetAddr.sa_data[2+4-1], (unsigned char)ClientSocetAddr.sa_data[0]*256+(unsigned char)ClientSocetAddr.sa_data[1]); |
| // Process Data until the peer shuts down the connection |
| int Cnt = 0; |
| printf(" Handle Data "); |
| do |
| { |
| iResult = handleData(ClientSocket); |
| if (iResult>=0) |
| { |
| printf("."); |
| fflush(stdout); |
| Cnt++; |
| if (Cnt>40) |
| { |
| Cnt = 0; |
| printf("\n "); |
| } |
| } |
| } |
| while (iResult >= 0); |
| // Connection Closed by peer |
| if (iResult==-1) |
| { |
| // JTAG port |
| jtagSetIdle(); |
| } |
| // Error - shutdown the connection |
| if (iResult==-2) |
| { |
| fprintf(stderr, " Disconnect\n"); |
| #ifdef WIN32 |
| iResult = shutdown(ClientSocket, SD_SEND); |
| #else |
| iResult = shutdown(ClientSocket, SHUT_WR); |
| #endif |
| if (iResult == SOCKET_ERROR) |
| { |
| fprintf(stderr, "shutdown failed with error: %d\n", WSAGetLastError()); |
| } |
| iResult=-2; // Error |
| } |
| // cleanup |
| closesocket(ClientSocket); |
| } |
| // If not Error Listen Again |
| while (iResult!=-2); |
| // cleanup |
| closesocket(ListenSocket); |
| WSACleanup(); |
| jtagClosePort(); |
| return 1; |
| } |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.h |
|---|
| 0,0 → 1,37 |
| // Program Version |
| // --------------- |
| #define VERSION "1.08" // Program version |
| #define YEAR "2013" // Year of the program |
| // JTAG Port Definitions |
| // --------------------- |
| // Use FTDI as Port Interface |
| #include "mlab_xvcd_port_FTDI.h" |
| // JTAG Port Pin Masks (look at mlab_xvcd_port_FTDI.h for pin names) |
| #define PORT_TCK ( FTDI_TXD ) // JTAG TCK (output) |
| #define PORT_TDI ( FTDI_RXD ) // JTAG TDI (output) |
| #define PORT_TDO ( FTDI_RTS ) // JTAG TDO (input) |
| #define PORT_TMS ( FTDI_CTS ) // JTAG TMS (output) |
| #define PORT_LED ( FTDI_RI | CBUS3 ) // Activituy LED (output) |
| // FTDI Settings |
| #define BAUD_RATE 1000000 // Baoud Rate (mult it by 16) |
| #define USB_LATENCY 1 // FTDI USB Latency Timer in ms (FT232R 0, FT2232 1) |
| // Performance Data (configuring XC3S50AN) |
| // ---------------- |
| // BAUD_RATE USB_LATENCY --> FT220X FT232R |
| // 1000000 1 3s 2s |
| // 10000000 1 3s |
| // 1000000 0 2.8s |
| // Network Definitions |
| // ------------------- |
| // TCP/IP |
| #define XVC_TCP_PORT "2542" // TCP Port Number to Listen to (string!) |
| #define XVC_JTAG_LEN (1024*8) // JTAG String Length in bits |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.cpp |
|---|
| 0,0 → 1,504 |
| // Include FTDI library |
| #include "mlab_xvcd_port_FTDI.h" |
| #ifdef WIN32 |
| #include <windows.h> // Windows Console Application (Sleep) |
| #else |
| #include <unistd.h> // sleep |
| #endif |
| // JTAG Output Pin Mask |
| #define IO_OUTPUT_MASK (PORT_TCK|PORT_TDI|PORT_TMS|PORT_LED) // Mask for all Output Pins |
| // Global Variables |
| FT_HANDLE ftHandle; // Handle for FTDI device |
| bool ftHandleValid = false; // Valid Handle |
| unsigned char PinStatus = 0; // Status of DBUS pins |
| unsigned char LedMask = 0; // LED Mask for DBUS data transfer |
| // Convert string to int (both decimal and hex string) |
| int atoiEx(char *s) |
| { |
| if (s[0]=='0' && (s[1]=='x' || s[1]=='X')) |
| { |
| // Hex Value |
| int i; |
| #pragma warning(disable: 4996) // Disable MS warning about scanf |
| sscanf(s, "%x", &i); |
| return i; |
| } |
| else |
| { |
| // Decimal Value |
| return atoi(s); |
| } |
| } |
| // Print FTDI Pin Names (from mask value) |
| void jtagPrintPinNames(int pinMask) |
| { |
| // 16bit (MSB is CBUS, LSB is DBUS) |
| int bit=15; |
| bool useDelimiter=false; |
| do |
| { |
| int mask = 1 << bit; |
| if (pinMask & mask) |
| { |
| if (useDelimiter) |
| { |
| printf("+"); |
| } |
| if (bit > 7) |
| { |
| printf("CBUS%c", '0' + bit - 8); |
| } |
| else |
| { |
| printf("DBUS%c", '0' + bit); |
| switch (mask) |
| { |
| case FTDI_TXD: printf("(TXD)"); break; |
| case FTDI_RXD: printf("(RXD)"); break; |
| case FTDI_RTS: printf("(RTS)"); break; |
| case FTDI_CTS: printf("(CTS)"); break; |
| case FTDI_DTR: printf("(DTR)"); break; |
| case FTDI_DSR: printf("(DSR)"); break; |
| case FTDI_DCD: printf("(DCD)"); break; |
| case FTDI_RI: printf("(RI) "); break; |
| } |
| } |
| useDelimiter = true; |
| } |
| } |
| while (bit-- > 0); |
| } |
| // Verify pin usage |
| void jtagCheckPinConfig() |
| { |
| // Check CBUS usage |
| if ( PORT_TCK > 0x00FF ) |
| fprintf(stderr, "\nFTDI: INTERNAL ERROR: TCK can't use CBUS signal"), exit(2); |
| if ( PORT_TCK == 0 ) |
| fprintf(stderr, "\nFTDI: INTERNAL ERROR: TCK not defined"), exit(2); |
| if ( PORT_TDI > 0x00FF ) |
| fprintf(stderr, "\nFTDI: INTERNAL ERROR: TDI can't use CBUS signal"), exit(2); |
| if ( PORT_TDI == 0 ) |
| fprintf(stderr, "\nFTDI: INTERNAL ERROR: TDI not defined"), exit(2); |
| if ( PORT_TDO > 0x00FF ) |
| fprintf(stderr, "\nFTDI: INTERNAL ERROR: TDO can't use CBUS signal"), exit(2); |
| if ( PORT_TDO == 0 ) |
| fprintf(stderr, "\nFTDI: INTERNAL ERROR: TDO not defined"), exit(2); |
| if ( PORT_TMS > 0x00FF) |
| fprintf(stderr, "\nFTDI: INTERNAL ERROR: TMS can't use CBUS signal"), exit(2); |
| if ( PORT_TMS == 0 ) |
| fprintf(stderr, "\nFTDI: INTERNAL ERROR: TMS not defined"), exit(2); |
| if ( PORT_LED > 0x0FFF) |
| fprintf(stderr, "\nFTDI: INTERNAL ERROR: LED can't use CBUS signal > 3"), exit(2); |
| } |
| // Print JTAG Pin Assignment |
| void jtagPrintPinConfig() |
| { |
| // Print pin masks human readable |
| printf(" JTAG Port Pins "); printf("TCK->"); jtagPrintPinNames(PORT_TCK); printf("\n"); |
| printf(" "); printf("TDI->"); jtagPrintPinNames(PORT_TDI); printf("\n"); |
| printf(" "); printf("TDO->"); jtagPrintPinNames(PORT_TDO); printf("\n"); |
| printf(" "); printf("TMS->"); jtagPrintPinNames(PORT_TMS); printf("\n"); |
| printf(" "); printf("LED->"); jtagPrintPinNames(PORT_LED); printf("\n"); |
| } |
| // Connect to FTDI driver |
| int jtagOpenPort(int findDeviceBy, char *findDeviceByStr) |
| { |
| // Enumerate FTDI Devices |
| // ---------------------- |
| FT_STATUS ftStatus; |
| // Print Library Version |
| printf("FTDI Connect\n"); |
| DWORD dwLibraryVer; |
| ftStatus = FT_GetLibraryVersion(&dwLibraryVer); |
| if (ftStatus == FT_OK) |
| printf(" Library Version 0x%x\n", dwLibraryVer); |
| else |
| fprintf(stderr, "\nFTDI: Error Reading Library Version\n"); |
| // Create Device Information List |
| DWORD numDevs = 0; |
| ftStatus = FT_CreateDeviceInfoList(&numDevs); |
| if (ftStatus == FT_OK) |
| printf(" Devices Found %d\n", numDevs); |
| else |
| printf(" No FTDI Device Found\n"); |
| if (numDevs==0) |
| return -1; |
| // Print Config Info |
| jtagPrintPinConfig(); |
| jtagCheckPinConfig(); |
| printf("\n"); |
| // List All FTDI Devices |
| FT_HANDLE ftHandleTemp; |
| DWORD Flags; |
| DWORD ID; |
| DWORD Type; |
| DWORD LocId; |
| char SerialNumber[16]; |
| char Description[64]; |
| for (DWORD i=0; i<numDevs; i++) |
| { |
| ftStatus = FT_GetDeviceInfoDetail(i, &Flags, &Type, &ID, &LocId, SerialNumber, Description, &ftHandleTemp); |
| if (ftStatus == FT_OK) |
| { |
| printf("Device %d\n", i); |
| if (Flags & FT_FLAGS_OPENED) |
| { |
| printf(" Description Device is used by another process\n"); |
| } |
| else |
| { |
| printf(" Description \"%s\"\n", Description); |
| printf(" SerialNumber \"%s\"\n", SerialNumber); |
| //printf(" Flags 0x%x\n", Flags); |
| //printf(" Type 0x%x\n", Type); |
| //printf(" ID 0x%x\n", ID); |
| printf(" Location 0x%x\n", LocId); |
| } |
| printf("\n"); |
| } |
| } |
| // Select one Device and Open It |
| unsigned int selectedDeviceIndex = 0; |
| if (findDeviceBy==0) |
| { |
| // Select by Device Number |
| selectedDeviceIndex = atoiEx(findDeviceByStr); |
| if (numDevs<=selectedDeviceIndex) |
| { |
| fprintf(stderr, " There is no Device Number %d\n\n", selectedDeviceIndex); |
| return -1; |
| } |
| // Open device |
| ftStatus = FT_Open(selectedDeviceIndex, &ftHandle); |
| } |
| else |
| { |
| // Select by Description / Serial Number / Location |
| if (findDeviceBy==FT_OPEN_BY_LOCATION) |
| { |
| // Open device (location is number, not string) |
| long int findDeviceByInt = atoiEx(findDeviceByStr); |
| ftStatus = FT_OpenEx((void*)findDeviceByInt, findDeviceBy, &ftHandle); |
| } |
| else |
| { |
| ftStatus = FT_OpenEx(findDeviceByStr, findDeviceBy, &ftHandle); |
| } |
| } |
| // Check Status |
| if (ftStatus == FT_OK) |
| { |
| ftHandleValid = true; |
| //printf(" FTDI Device Opened\n"); |
| } |
| else |
| { |
| fprintf(stderr, " Can't Open FTDI Device (error code %d)\n\n", ftStatus); |
| return -1; |
| } |
| // Selected Device |
| ftStatus = FT_GetDeviceInfo(ftHandle, &Type, &ID, SerialNumber, Description, 0); |
| if (ftStatus == FT_OK) |
| { |
| printf("Selected Device\n"); |
| printf(" Description \"%s\"\n", Description); |
| printf(" SerialNumber \"%s\"\n", SerialNumber); |
| //printf(" Type 0x%x\n", Type); |
| //printf(" ID 0x%x\n", ID); |
| } |
| // Get Driver Version |
| DWORD dwDriverVer; |
| ftStatus = FT_GetDriverVersion(ftHandle, &dwDriverVer); |
| if (ftStatus == FT_OK) |
| { |
| printf(" Device Driver Ver 0x%x\n", dwDriverVer); |
| } |
| else |
| { |
| fprintf(stderr, "FTDI: Error Reading Driver Version\n"); |
| } |
| // Set BitBang Mode |
| ftStatus = FT_SetBitMode(ftHandle, (UCHAR)(0xFF & IO_OUTPUT_MASK), FT_BITMODE_SYNC_BITBANG); //FT_BITMODE_SYNC_BITBANG / FT_BITMODE_ASYNC_BITBANG |
| if (ftStatus == FT_OK) |
| { |
| // printf("Set BitBang Mode\n"); |
| } |
| else |
| { |
| fprintf(stderr, "FTDI: Set BitBang Mode Failed %d\n", ftStatus); |
| } |
| // Set Baud Rate |
| ftStatus = FT_SetBaudRate(ftHandle, BAUD_RATE); |
| if (ftStatus == FT_OK) |
| { |
| printf(" Baud Rate %d\n", BAUD_RATE); |
| } |
| else |
| { |
| fprintf(stderr, "FTDI: Set Baud Rate Failed %d\n", ftStatus); |
| } |
| ftStatus = FT_Purge(ftHandle, FT_PURGE_RX | FT_PURGE_TX); // Purge both Rx and Tx buffers |
| if (ftStatus == FT_OK) |
| { |
| // printf("Purge \n"); |
| } |
| else |
| { |
| fprintf(stderr, "FTDI: FT_Purge failed %d\n", ftStatus); |
| } |
| ftStatus = FT_SetLatencyTimer(ftHandle, USB_LATENCY); // Latency in ms |
| if (ftStatus == FT_OK) |
| { |
| printf(" USB Latency %d\n", USB_LATENCY); |
| } |
| else |
| { |
| fprintf(stderr, "FTDI: Set USB Latency Timer Failed %d\n", ftStatus); |
| } |
| // Fix (without this delay the next FT_Read hang for ever) |
| // My Linux i5 notebook requires at least 2500us |
| #ifdef WIN32 |
| Sleep(10); //ms |
| #else |
| usleep(10000); //us |
| #endif |
| printf("\n"); |
| return 0; |
| } |
| // Enable or Disable Activity LED |
| void jtagSetLED(bool LedEnable) |
| { |
| // DBUS Connected LED (BitBang Mode) |
| LedMask = LedEnable ? (0xFF & PORT_LED) : 0; // Set mask for jtagScan function |
| if (PORT_LED & 0xFF) |
| { |
| // Set / Reset LED Pin |
| DWORD BytesWritten; |
| DWORD BytesReceived; |
| unsigned char DataOut = LedMask | (PinStatus & ~PORT_LED); // Preserve PinStatus |
| unsigned char Dummy; |
| FT_Write(ftHandle, &DataOut, 1, &BytesWritten ); // Send 1 byte |
| FT_Read (ftHandle, &Dummy, 1, &BytesReceived); // Read 1 byte |
| } |
| // CBUS Connected LED (BitBang Mode) 1 and 0 state of the port |
| const unsigned char On = ( ((PORT_LED & 0x0F00) >> 4) | ((PORT_LED & 0x0F00) >> 8) ); |
| const unsigned char Off = ( ((PORT_LED & 0x0F00) >> 4) ); |
| if (On) |
| { |
| // Set / Reset LED Pin |
| FT_SetBitMode(ftHandle, LedEnable ? On : Off, FT_BITMODE_CBUS_BITBANG); |
| // Return to used Mode |
| FT_SetBitMode(ftHandle, (UCHAR)(0xFF & IO_OUTPUT_MASK), FT_BITMODE_SYNC_BITBANG); //FT_BITMODE_SYNC_BITBANG / FT_BITMODE_ASYNC_BITBANG |
| } |
| } |
| // Set port to Idle state |
| void jtagSetIdle() |
| { |
| char b = 0; // Idle State for JTAG pins |
| DWORD BytesWritten; |
| DWORD BytesReceived; |
| // Write (idle state of pins) |
| FT_Write(ftHandle, &b, 1, &BytesWritten); |
| // Read (not to left data in input fifo) |
| FT_Read(ftHandle, &b, 1, &BytesReceived); |
| } |
| // Close FTDI connection |
| int jtagClosePort() |
| { |
| if (ftHandleValid) |
| { |
| jtagSetLED(false); |
| // Switch Off the Outputs |
| FT_Purge(ftHandle, FT_PURGE_RX | FT_PURGE_TX); // Purge both Rx and Tx buffers |
| FT_SetBitMode(ftHandle, 0, FT_BITMODE_SYNC_BITBANG); |
| // Close FTDI Lib |
| FT_Close(ftHandle); |
| ftHandleValid = false; |
| } |
| return 0; |
| } |
| // Send data to JTAG port and bring returned data |
| int jtagScan(const unsigned char *TMS, const unsigned char *TDI, unsigned char *TDO, unsigned int bits) |
| { |
| FT_STATUS ftStatus; |
| DWORD BytesWritten; |
| DWORD BytesReceived; |
| unsigned int r, t; |
| // Decompose TDI and TMS byte array to raw bitstream |
| //(1 TDI bit + 1 TMS bit --> 1 byte + 1 byte with TCK) |
| unsigned char buffer[16384]; |
| if (bits > sizeof(buffer)/2) |
| { |
| fprintf(stderr, "\n FTDI: Out of Buffer Space for %d bits\n", bits); |
| return -1; |
| } |
| // Switch LED On |
| jtagSetLED(true); |
| // Prepare transmit data to buffer |
| for (unsigned int i = 0; i < bits; ++i) |
| { |
| unsigned char v = 0 | LedMask; // LED On / Off (on DBUS) |
| if (TMS[i/8] & (1<<(i&7))) |
| { |
| v |= PORT_TMS; |
| // printf("T"); |
| } |
| else |
| { |
| // printf("t"); |
| } |
| if (TDI[i/8] & (1<<(i&7))) |
| { |
| v |= PORT_TDI; |
| // printf("|"); |
| } |
| else |
| { |
| // printf("."); |
| } |
| buffer[i * 2 + 0] = v; |
| buffer[i * 2 + 1] = v | PORT_TCK; |
| } |
| PinStatus = buffer[bits*2-1]; |
| // printf("\n"); |
| // Send data to FTDI |
| r = 0; |
| while (r < bits * 2) |
| { |
| t = bits * 2 - r; |
| if (t > FTDI_MAX_WRITESIZE) |
| { |
| t = FTDI_MAX_WRITESIZE; |
| } |
| // printf("writing %d bytes to FTDI\n", t); |
| ftStatus = FT_Write(ftHandle, buffer+r, t, &BytesWritten); |
| if (ftStatus != FT_OK) |
| { |
| fprintf(stderr, "\n FTDI: Error Writing\n"); |
| return -2; |
| } |
| unsigned int i = 0; |
| while (i < t) |
| { |
| FT_SetTimeouts(ftHandle, 5000, 0); // timeout 5 sec |
| ftStatus = FT_Read(ftHandle, buffer+r+i, t-i, &BytesReceived); |
| if (ftStatus == FT_OK) |
| { |
| if (BytesReceived == t-i) |
| { |
| // FT_Read OK |
| // printf("Read from FTDI %d bytes", BytesReceived); |
| } |
| else |
| { |
| // FT_Read Timeout |
| fprintf(stderr, "\n FTDI: Read Timeout\n"); |
| return -2; |
| } |
| } |
| else |
| { |
| fprintf(stderr, "\n FTDI: Error Reading\n");// Error |
| return -2; |
| } |
| i += BytesReceived; |
| } |
| r += t; |
| } |
| // Pack TDO bitstream from receive buffer to byte array |
| memset(TDO, 0, (bits + 7) / 8); |
| for (unsigned int i = 0; i < bits; ++i) |
| { |
| if (buffer[i * 2 + 1] & PORT_TDO) |
| { |
| TDO[i/8] |= 1 << (i&7); |
| // printf("H"); |
| } |
| else |
| { |
| // printf("L"); |
| } |
| } |
| // printf("\n"); |
| // printf(" Bits %d ", bit_counter); |
| // Switch LED Off |
| jtagSetLED(false); |
| return 0; |
| } |
| // Check if Cable is still connected and accesible |
| // True is o.k. |
| bool CheckCable() |
| { |
| FT_STATUS ftStatus; |
| DWORD lpdwAmountInRxQueue, lpdwAmountInTxQueue, lpdwEventStatus; |
| ftStatus = FT_GetStatus(ftHandle, &lpdwAmountInRxQueue, &lpdwAmountInTxQueue, &lpdwEventStatus); |
| return (ftStatus==FT_OK); |
| } |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.h |
|---|
| 0,0 → 1,93 |
| #ifndef MLAB_XVCD_PORT_FTDI_H |
| #define MLAB_XVCD_PORT_FTDI_H |
| // Pin Defs |
| // -------- |
| // FTDI Pin Mask Definitions (valid for FT232R) |
| #define DBUS0 0x0001 // Bit 0 Data Bus |
| #define DBUS1 0x0002 // Bit 1 |
| #define DBUS2 0x0004 // Bit 2 |
| #define DBUS3 0x0008 // Bit 3 |
| #define DBUS4 0x0010 // Bit 4 |
| #define DBUS5 0x0020 // Bit 5 |
| #define DBUS6 0x0040 // Bit 6 |
| #define DBUS7 0x0080 // Bit 7 |
| #define CBUS0 0x0100 // Bit 0 Control Bus |
| #define CBUS1 0x0200 // Bit 1 |
| #define CBUS2 0x0400 // Bit 2 |
| #define CBUS3 0x0800 // Bit 3 |
| #define FTDI_TXD DBUS0 // Bit 0 RS232 Signal Alias |
| #define FTDI_RXD DBUS1 // Bit 1 |
| #define FTDI_RTS DBUS2 // Bit 2 |
| #define FTDI_CTS DBUS3 // Bit 3 |
| #define FTDI_DTR DBUS4 // Bit 4 |
| #define FTDI_DSR DBUS5 // Bit 5 |
| #define FTDI_DCD DBUS6 // Bit 6 |
| #define FTDI_RI DBUS7 // Bit 7 |
| // Includes |
| // -------- |
| #undef UNICODE |
| #define WIN32_LEAN_AND_MEAN |
| #include <stdlib.h> // Standard Library (exit, atoi, ...) |
| #include <stdio.h> // Standard IO (printf, ...) |
| #include "mlab_xvcd.h" // Program Config (pin defs, settings, ...) |
| #ifdef WIN32 |
| #include <windows.h> // Windows Console Application |
| #else |
| #include <string.h> |
| #endif |
| // Link with library |
| #ifdef WIN32 |
| #include "lib_win32\ftd2xx.h" // FTDI Library |
| #else |
| #include "lib_linux/ftd2xx.h" |
| #endif |
| // Public Definitions |
| // ------------------ |
| // Find Mode (for port open) |
| #define OPEN_BY_DESCRIPTION FT_OPEN_BY_DESCRIPTION // Find device by Description String |
| #define OPEN_BY_LOCATION FT_OPEN_BY_LOCATION // Find device by Bus Location |
| #define OPEN_BY_SERIAL_NUMBER FT_OPEN_BY_SERIAL_NUMBER // Find device by it's Serial Number |
| // Max Data lengt to send to FTDI as one block |
| #define FTDI_MAX_WRITESIZE 1024 |
| // Function Prototypes (public functions only) |
| // ------------------------------------------- |
| // Connect to FTDI driver |
| // Find the device and open driver |
| int jtagOpenPort(int findDeviceBy, char *findDeviceByStr); |
| // Enable or Disable Activity LED |
| void jtagSetLED(bool LedEnable); |
| // Set port to Idle state (all zeroes) |
| void jtagSetIdle(); |
| // Close FTDI connection |
| int jtagClosePort(); |
| // Send data to JTAG port and bring returned data |
| // Turn LED On during processing |
| int jtagScan(const unsigned char *TMS, const unsigned char *TDI, unsigned char *TDO, unsigned int bits); |
| // Check if Cable is still connected and accesible |
| // True is o.k. |
| bool CheckCable(); |
| #endif |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_win32/ftd2xx.h |
|---|
| 0,0 → 1,1341 |
| /*++ |
| Copyright © 2001-2011 Future Technology Devices International Limited |
| THIS SOFTWARE IS PROVIDED BY FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED "AS IS" |
| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL |
| FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
| OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) |
| HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR |
| TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
| EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| FTDI DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON FTDI PARTS. |
| FTDI DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE INFORMATION IS NOT MODIFIED. |
| IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, IT IS THE |
| RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES AND SUBSEQUENT WHQL |
| RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. |
| Module Name: |
| ftd2xx.h |
| Abstract: |
| Native USB device driver for FTDI FT232x, FT245x, FT2232x and FT4232x devices |
| FTD2XX library definitions |
| Environment: |
| kernel & user mode |
| --*/ |
| #ifndef FTD2XX_H |
| #define FTD2XX_H |
| // The following ifdef block is the standard way of creating macros |
| // which make exporting from a DLL simpler. All files within this DLL |
| // are compiled with the FTD2XX_EXPORTS symbol defined on the command line. |
| // This symbol should not be defined on any project that uses this DLL. |
| // This way any other project whose source files include this file see |
| // FTD2XX_API functions as being imported from a DLL, whereas this DLL |
| // sees symbols defined with this macro as being exported. |
| #ifdef FTD2XX_EXPORTS |
| #define FTD2XX_API __declspec(dllexport) |
| #else |
| #define FTD2XX_API __declspec(dllimport) |
| #endif |
| typedef PVOID FT_HANDLE; |
| typedef ULONG FT_STATUS; |
| // |
| // Device status |
| // |
| enum { |
| FT_OK, |
| FT_INVALID_HANDLE, |
| FT_DEVICE_NOT_FOUND, |
| FT_DEVICE_NOT_OPENED, |
| FT_IO_ERROR, |
| FT_INSUFFICIENT_RESOURCES, |
| FT_INVALID_PARAMETER, |
| FT_INVALID_BAUD_RATE, |
| FT_DEVICE_NOT_OPENED_FOR_ERASE, |
| FT_DEVICE_NOT_OPENED_FOR_WRITE, |
| FT_FAILED_TO_WRITE_DEVICE, |
| FT_EEPROM_READ_FAILED, |
| FT_EEPROM_WRITE_FAILED, |
| FT_EEPROM_ERASE_FAILED, |
| FT_EEPROM_NOT_PRESENT, |
| FT_EEPROM_NOT_PROGRAMMED, |
| FT_INVALID_ARGS, |
| FT_NOT_SUPPORTED, |
| FT_OTHER_ERROR, |
| FT_DEVICE_LIST_NOT_READY, |
| }; |
| #define FT_SUCCESS(status) ((status) == FT_OK) |
| // |
| // FT_OpenEx Flags |
| // |
| #define FT_OPEN_BY_SERIAL_NUMBER 1 |
| #define FT_OPEN_BY_DESCRIPTION 2 |
| #define FT_OPEN_BY_LOCATION 4 |
| // |
| // FT_ListDevices Flags (used in conjunction with FT_OpenEx Flags |
| // |
| #define FT_LIST_NUMBER_ONLY 0x80000000 |
| #define FT_LIST_BY_INDEX 0x40000000 |
| #define FT_LIST_ALL 0x20000000 |
| #define FT_LIST_MASK (FT_LIST_NUMBER_ONLY|FT_LIST_BY_INDEX|FT_LIST_ALL) |
| // |
| // Baud Rates |
| // |
| #define FT_BAUD_300 300 |
| #define FT_BAUD_600 600 |
| #define FT_BAUD_1200 1200 |
| #define FT_BAUD_2400 2400 |
| #define FT_BAUD_4800 4800 |
| #define FT_BAUD_9600 9600 |
| #define FT_BAUD_14400 14400 |
| #define FT_BAUD_19200 19200 |
| #define FT_BAUD_38400 38400 |
| #define FT_BAUD_57600 57600 |
| #define FT_BAUD_115200 115200 |
| #define FT_BAUD_230400 230400 |
| #define FT_BAUD_460800 460800 |
| #define FT_BAUD_921600 921600 |
| // |
| // Word Lengths |
| // |
| #define FT_BITS_8 (UCHAR) 8 |
| #define FT_BITS_7 (UCHAR) 7 |
| // |
| // Stop Bits |
| // |
| #define FT_STOP_BITS_1 (UCHAR) 0 |
| #define FT_STOP_BITS_2 (UCHAR) 2 |
| // |
| // Parity |
| // |
| #define FT_PARITY_NONE (UCHAR) 0 |
| #define FT_PARITY_ODD (UCHAR) 1 |
| #define FT_PARITY_EVEN (UCHAR) 2 |
| #define FT_PARITY_MARK (UCHAR) 3 |
| #define FT_PARITY_SPACE (UCHAR) 4 |
| // |
| // Flow Control |
| // |
| #define FT_FLOW_NONE 0x0000 |
| #define FT_FLOW_RTS_CTS 0x0100 |
| #define FT_FLOW_DTR_DSR 0x0200 |
| #define FT_FLOW_XON_XOFF 0x0400 |
| // |
| // Purge rx and tx buffers |
| // |
| #define FT_PURGE_RX 1 |
| #define FT_PURGE_TX 2 |
| // |
| // Events |
| // |
| typedef void (*PFT_EVENT_HANDLER)(DWORD,DWORD); |
| #define FT_EVENT_RXCHAR 1 |
| #define FT_EVENT_MODEM_STATUS 2 |
| #define FT_EVENT_LINE_STATUS 4 |
| // |
| // Timeouts |
| // |
| #define FT_DEFAULT_RX_TIMEOUT 300 |
| #define FT_DEFAULT_TX_TIMEOUT 300 |
| // |
| // Device types |
| // |
| typedef ULONG FT_DEVICE; |
| enum { |
| FT_DEVICE_BM, |
| FT_DEVICE_AM, |
| FT_DEVICE_100AX, |
| FT_DEVICE_UNKNOWN, |
| FT_DEVICE_2232C, |
| FT_DEVICE_232R, |
| FT_DEVICE_2232H, |
| FT_DEVICE_4232H, |
| FT_DEVICE_232H, |
| FT_DEVICE_X_SERIES |
| }; |
| // |
| // Bit Modes |
| // |
| #define FT_BITMODE_RESET 0x00 |
| #define FT_BITMODE_ASYNC_BITBANG 0x01 |
| #define FT_BITMODE_MPSSE 0x02 |
| #define FT_BITMODE_SYNC_BITBANG 0x04 |
| #define FT_BITMODE_MCU_HOST 0x08 |
| #define FT_BITMODE_FAST_SERIAL 0x10 |
| #define FT_BITMODE_CBUS_BITBANG 0x20 |
| #define FT_BITMODE_SYNC_FIFO 0x40 |
| // |
| // FT232R CBUS Options EEPROM values |
| // |
| #define FT_232R_CBUS_TXDEN 0x00 // Tx Data Enable |
| #define FT_232R_CBUS_PWRON 0x01 // Power On |
| #define FT_232R_CBUS_RXLED 0x02 // Rx LED |
| #define FT_232R_CBUS_TXLED 0x03 // Tx LED |
| #define FT_232R_CBUS_TXRXLED 0x04 // Tx and Rx LED |
| #define FT_232R_CBUS_SLEEP 0x05 // Sleep |
| #define FT_232R_CBUS_CLK48 0x06 // 48MHz clock |
| #define FT_232R_CBUS_CLK24 0x07 // 24MHz clock |
| #define FT_232R_CBUS_CLK12 0x08 // 12MHz clock |
| #define FT_232R_CBUS_CLK6 0x09 // 6MHz clock |
| #define FT_232R_CBUS_IOMODE 0x0A // IO Mode for CBUS bit-bang |
| #define FT_232R_CBUS_BITBANG_WR 0x0B // Bit-bang write strobe |
| #define FT_232R_CBUS_BITBANG_RD 0x0C // Bit-bang read strobe |
| // |
| // FT232H CBUS Options EEPROM values |
| // |
| #define FT_232H_CBUS_TRISTATE 0x00 // Tristate |
| #define FT_232H_CBUS_TXLED 0x01 // Tx LED |
| #define FT_232H_CBUS_RXLED 0x02 // Rx LED |
| #define FT_232H_CBUS_TXRXLED 0x03 // Tx and Rx LED |
| #define FT_232H_CBUS_PWREN 0x04 // Power Enable |
| #define FT_232H_CBUS_SLEEP 0x05 // Sleep |
| #define FT_232H_CBUS_DRIVE_0 0x06 // Drive pin to logic 0 |
| #define FT_232H_CBUS_DRIVE_1 0x07 // Drive pin to logic 1 |
| #define FT_232H_CBUS_IOMODE 0x08 // IO Mode for CBUS bit-bang |
| #define FT_232H_CBUS_TXDEN 0x09 // Tx Data Enable |
| #define FT_232H_CBUS_CLK30 0x0A // 30MHz clock |
| #define FT_232H_CBUS_CLK15 0x0B // 15MHz clock |
| #define FT_232H_CBUS_CLK7_5 0x0C // 7.5MHz clock |
| // |
| // FT X Series CBUS Options EEPROM values |
| // |
| #define FT_X_SERIES_CBUS_TRISTATE 0x00 // Tristate |
| #define FT_X_SERIES_CBUS_RXLED 0x01 // Tx LED |
| #define FT_X_SERIES_CBUS_TXLED 0x02 // Rx LED |
| #define FT_X_SERIES_CBUS_TXRXLED 0x03 // Tx and Rx LED |
| #define FT_X_SERIES_CBUS_PWREN 0x04 // Power Enable |
| #define FT_X_SERIES_CBUS_SLEEP 0x05 // Sleep |
| #define FT_X_SERIES_CBUS_DRIVE_0 0x06 // Drive pin to logic 0 |
| #define FT_X_SERIES_CBUS_DRIVE_1 0x07 // Drive pin to logic 1 |
| #define FT_X_SERIES_CBUS_IOMODE 0x08 // IO Mode for CBUS bit-bang |
| #define FT_X_SERIES_CBUS_TXDEN 0x09 // Tx Data Enable |
| #define FT_X_SERIES_CBUS_CLK24 0x0A // 24MHz clock |
| #define FT_X_SERIES_CBUS_CLK12 0x0B // 12MHz clock |
| #define FT_X_SERIES_CBUS_CLK6 0x0C // 6MHz clock |
| #define FT_X_SERIES_CBUS_BCD_CHARGER 0x0D // Battery charger detected |
| #define FT_X_SERIES_CBUS_BCD_CHARGER_N 0x0E // Battery charger detected inverted |
| #define FT_X_SERIES_CBUS_I2C_TXE 0x0F // I2C Tx empty |
| #define FT_X_SERIES_CBUS_I2C_RXF 0x10 // I2C Rx full |
| #define FT_X_SERIES_CBUS_VBUS_SENSE 0x11 // Detect VBUS |
| #define FT_X_SERIES_CBUS_BITBANG_WR 0x12 // Bit-bang write strobe |
| #define FT_X_SERIES_CBUS_BITBANG_RD 0x13 // Bit-bang read strobe |
| #define FT_X_SERIES_CBUS_TIMESTAMP 0x14 // Toggle output when a USB SOF token is received |
| #define FT_X_SERIES_CBUS_KEEP_AWAKE 0x15 // |
| // Driver types |
| #define FT_DRIVER_TYPE_D2XX 0 |
| #define FT_DRIVER_TYPE_VCP 1 |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Open( |
| int deviceNumber, |
| FT_HANDLE *pHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_OpenEx( |
| PVOID pArg1, |
| DWORD Flags, |
| FT_HANDLE *pHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ListDevices( |
| PVOID pArg1, |
| PVOID pArg2, |
| DWORD Flags |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Close( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Read( |
| FT_HANDLE ftHandle, |
| LPVOID lpBuffer, |
| DWORD dwBytesToRead, |
| LPDWORD lpBytesReturned |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Write( |
| FT_HANDLE ftHandle, |
| LPVOID lpBuffer, |
| DWORD dwBytesToWrite, |
| LPDWORD lpBytesWritten |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_IoCtl( |
| FT_HANDLE ftHandle, |
| DWORD dwIoControlCode, |
| LPVOID lpInBuf, |
| DWORD nInBufSize, |
| LPVOID lpOutBuf, |
| DWORD nOutBufSize, |
| LPDWORD lpBytesReturned, |
| LPOVERLAPPED lpOverlapped |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetBaudRate( |
| FT_HANDLE ftHandle, |
| ULONG BaudRate |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetDivisor( |
| FT_HANDLE ftHandle, |
| USHORT Divisor |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetDataCharacteristics( |
| FT_HANDLE ftHandle, |
| UCHAR WordLength, |
| UCHAR StopBits, |
| UCHAR Parity |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetFlowControl( |
| FT_HANDLE ftHandle, |
| USHORT FlowControl, |
| UCHAR XonChar, |
| UCHAR XoffChar |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ResetDevice( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetDtr( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ClrDtr( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetRts( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ClrRts( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetModemStatus( |
| FT_HANDLE ftHandle, |
| ULONG *pModemStatus |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetChars( |
| FT_HANDLE ftHandle, |
| UCHAR EventChar, |
| UCHAR EventCharEnabled, |
| UCHAR ErrorChar, |
| UCHAR ErrorCharEnabled |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Purge( |
| FT_HANDLE ftHandle, |
| ULONG Mask |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetTimeouts( |
| FT_HANDLE ftHandle, |
| ULONG ReadTimeout, |
| ULONG WriteTimeout |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetQueueStatus( |
| FT_HANDLE ftHandle, |
| DWORD *dwRxBytes |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetEventNotification( |
| FT_HANDLE ftHandle, |
| DWORD Mask, |
| PVOID Param |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetStatus( |
| FT_HANDLE ftHandle, |
| DWORD *dwRxBytes, |
| DWORD *dwTxBytes, |
| DWORD *dwEventDWord |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetBreakOn( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetBreakOff( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetWaitMask( |
| FT_HANDLE ftHandle, |
| DWORD Mask |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_WaitOnMask( |
| FT_HANDLE ftHandle, |
| DWORD *Mask |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetEventStatus( |
| FT_HANDLE ftHandle, |
| DWORD *dwEventDWord |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ReadEE( |
| FT_HANDLE ftHandle, |
| DWORD dwWordOffset, |
| LPWORD lpwValue |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_WriteEE( |
| FT_HANDLE ftHandle, |
| DWORD dwWordOffset, |
| WORD wValue |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EraseEE( |
| FT_HANDLE ftHandle |
| ); |
| // |
| // structure to hold program data for FT_EE_Program, FT_EE_ProgramEx, FT_EE_Read |
| // and FT_EE_ReadEx functions |
| // |
| typedef struct ft_program_data { |
| DWORD Signature1; // Header - must be 0x00000000 |
| DWORD Signature2; // Header - must be 0xffffffff |
| DWORD Version; // Header - FT_PROGRAM_DATA version |
| // 0 = original |
| // 1 = FT2232 extensions |
| // 2 = FT232R extensions |
| // 3 = FT2232H extensions |
| // 4 = FT4232H extensions |
| // 5 = FT232H extensions |
| WORD VendorId; // 0x0403 |
| WORD ProductId; // 0x6001 |
| char *Manufacturer; // "FTDI" |
| char *ManufacturerId; // "FT" |
| char *Description; // "USB HS Serial Converter" |
| char *SerialNumber; // "FT000001" if fixed, or NULL |
| WORD MaxPower; // 0 < MaxPower <= 500 |
| WORD PnP; // 0 = disabled, 1 = enabled |
| WORD SelfPowered; // 0 = bus powered, 1 = self powered |
| WORD RemoteWakeup; // 0 = not capable, 1 = capable |
| // |
| // Rev4 (FT232B) extensions |
| // |
| UCHAR Rev4; // non-zero if Rev4 chip, zero otherwise |
| UCHAR IsoIn; // non-zero if in endpoint is isochronous |
| UCHAR IsoOut; // non-zero if out endpoint is isochronous |
| UCHAR PullDownEnable; // non-zero if pull down enabled |
| UCHAR SerNumEnable; // non-zero if serial number to be used |
| UCHAR USBVersionEnable; // non-zero if chip uses USBVersion |
| WORD USBVersion; // BCD (0x0200 => USB2) |
| // |
| // Rev 5 (FT2232) extensions |
| // |
| UCHAR Rev5; // non-zero if Rev5 chip, zero otherwise |
| UCHAR IsoInA; // non-zero if in endpoint is isochronous |
| UCHAR IsoInB; // non-zero if in endpoint is isochronous |
| UCHAR IsoOutA; // non-zero if out endpoint is isochronous |
| UCHAR IsoOutB; // non-zero if out endpoint is isochronous |
| UCHAR PullDownEnable5; // non-zero if pull down enabled |
| UCHAR SerNumEnable5; // non-zero if serial number to be used |
| UCHAR USBVersionEnable5; // non-zero if chip uses USBVersion |
| WORD USBVersion5; // BCD (0x0200 => USB2) |
| UCHAR AIsHighCurrent; // non-zero if interface is high current |
| UCHAR BIsHighCurrent; // non-zero if interface is high current |
| UCHAR IFAIsFifo; // non-zero if interface is 245 FIFO |
| UCHAR IFAIsFifoTar; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IFAIsFastSer; // non-zero if interface is Fast serial |
| UCHAR AIsVCP; // non-zero if interface is to use VCP drivers |
| UCHAR IFBIsFifo; // non-zero if interface is 245 FIFO |
| UCHAR IFBIsFifoTar; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IFBIsFastSer; // non-zero if interface is Fast serial |
| UCHAR BIsVCP; // non-zero if interface is to use VCP drivers |
| // |
| // Rev 6 (FT232R) extensions |
| // |
| UCHAR UseExtOsc; // Use External Oscillator |
| UCHAR HighDriveIOs; // High Drive I/Os |
| UCHAR EndpointSize; // Endpoint size |
| UCHAR PullDownEnableR; // non-zero if pull down enabled |
| UCHAR SerNumEnableR; // non-zero if serial number to be used |
| UCHAR InvertTXD; // non-zero if invert TXD |
| UCHAR InvertRXD; // non-zero if invert RXD |
| UCHAR InvertRTS; // non-zero if invert RTS |
| UCHAR InvertCTS; // non-zero if invert CTS |
| UCHAR InvertDTR; // non-zero if invert DTR |
| UCHAR InvertDSR; // non-zero if invert DSR |
| UCHAR InvertDCD; // non-zero if invert DCD |
| UCHAR InvertRI; // non-zero if invert RI |
| UCHAR Cbus0; // Cbus Mux control |
| UCHAR Cbus1; // Cbus Mux control |
| UCHAR Cbus2; // Cbus Mux control |
| UCHAR Cbus3; // Cbus Mux control |
| UCHAR Cbus4; // Cbus Mux control |
| UCHAR RIsD2XX; // non-zero if using D2XX driver |
| // |
| // Rev 7 (FT2232H) Extensions |
| // |
| UCHAR PullDownEnable7; // non-zero if pull down enabled |
| UCHAR SerNumEnable7; // non-zero if serial number to be used |
| UCHAR ALSlowSlew; // non-zero if AL pins have slow slew |
| UCHAR ALSchmittInput; // non-zero if AL pins are Schmitt input |
| UCHAR ALDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR AHSlowSlew; // non-zero if AH pins have slow slew |
| UCHAR AHSchmittInput; // non-zero if AH pins are Schmitt input |
| UCHAR AHDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR BLSlowSlew; // non-zero if BL pins have slow slew |
| UCHAR BLSchmittInput; // non-zero if BL pins are Schmitt input |
| UCHAR BLDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR BHSlowSlew; // non-zero if BH pins have slow slew |
| UCHAR BHSchmittInput; // non-zero if BH pins are Schmitt input |
| UCHAR BHDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR IFAIsFifo7; // non-zero if interface is 245 FIFO |
| UCHAR IFAIsFifoTar7; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IFAIsFastSer7; // non-zero if interface is Fast serial |
| UCHAR AIsVCP7; // non-zero if interface is to use VCP drivers |
| UCHAR IFBIsFifo7; // non-zero if interface is 245 FIFO |
| UCHAR IFBIsFifoTar7; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IFBIsFastSer7; // non-zero if interface is Fast serial |
| UCHAR BIsVCP7; // non-zero if interface is to use VCP drivers |
| UCHAR PowerSaveEnable; // non-zero if using BCBUS7 to save power for self-powered designs |
| // |
| // Rev 8 (FT4232H) Extensions |
| // |
| UCHAR PullDownEnable8; // non-zero if pull down enabled |
| UCHAR SerNumEnable8; // non-zero if serial number to be used |
| UCHAR ASlowSlew; // non-zero if A pins have slow slew |
| UCHAR ASchmittInput; // non-zero if A pins are Schmitt input |
| UCHAR ADriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR BSlowSlew; // non-zero if B pins have slow slew |
| UCHAR BSchmittInput; // non-zero if B pins are Schmitt input |
| UCHAR BDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR CSlowSlew; // non-zero if C pins have slow slew |
| UCHAR CSchmittInput; // non-zero if C pins are Schmitt input |
| UCHAR CDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR DSlowSlew; // non-zero if D pins have slow slew |
| UCHAR DSchmittInput; // non-zero if D pins are Schmitt input |
| UCHAR DDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR ARIIsTXDEN; // non-zero if port A uses RI as RS485 TXDEN |
| UCHAR BRIIsTXDEN; // non-zero if port B uses RI as RS485 TXDEN |
| UCHAR CRIIsTXDEN; // non-zero if port C uses RI as RS485 TXDEN |
| UCHAR DRIIsTXDEN; // non-zero if port D uses RI as RS485 TXDEN |
| UCHAR AIsVCP8; // non-zero if interface is to use VCP drivers |
| UCHAR BIsVCP8; // non-zero if interface is to use VCP drivers |
| UCHAR CIsVCP8; // non-zero if interface is to use VCP drivers |
| UCHAR DIsVCP8; // non-zero if interface is to use VCP drivers |
| // |
| // Rev 9 (FT232H) Extensions |
| // |
| UCHAR PullDownEnableH; // non-zero if pull down enabled |
| UCHAR SerNumEnableH; // non-zero if serial number to be used |
| UCHAR ACSlowSlewH; // non-zero if AC pins have slow slew |
| UCHAR ACSchmittInputH; // non-zero if AC pins are Schmitt input |
| UCHAR ACDriveCurrentH; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR ADSlowSlewH; // non-zero if AD pins have slow slew |
| UCHAR ADSchmittInputH; // non-zero if AD pins are Schmitt input |
| UCHAR ADDriveCurrentH; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR Cbus0H; // Cbus Mux control |
| UCHAR Cbus1H; // Cbus Mux control |
| UCHAR Cbus2H; // Cbus Mux control |
| UCHAR Cbus3H; // Cbus Mux control |
| UCHAR Cbus4H; // Cbus Mux control |
| UCHAR Cbus5H; // Cbus Mux control |
| UCHAR Cbus6H; // Cbus Mux control |
| UCHAR Cbus7H; // Cbus Mux control |
| UCHAR Cbus8H; // Cbus Mux control |
| UCHAR Cbus9H; // Cbus Mux control |
| UCHAR IsFifoH; // non-zero if interface is 245 FIFO |
| UCHAR IsFifoTarH; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IsFastSerH; // non-zero if interface is Fast serial |
| UCHAR IsFT1248H; // non-zero if interface is FT1248 |
| UCHAR FT1248CpolH; // FT1248 clock polarity - clock idle high (1) or clock idle low (0) |
| UCHAR FT1248LsbH; // FT1248 data is LSB (1) or MSB (0) |
| UCHAR FT1248FlowControlH; // FT1248 flow control enable |
| UCHAR IsVCPH; // non-zero if interface is to use VCP drivers |
| UCHAR PowerSaveEnableH; // non-zero if using ACBUS7 to save power for self-powered designs |
| } FT_PROGRAM_DATA, *PFT_PROGRAM_DATA; |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_Program( |
| FT_HANDLE ftHandle, |
| PFT_PROGRAM_DATA pData |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_ProgramEx( |
| FT_HANDLE ftHandle, |
| PFT_PROGRAM_DATA pData, |
| char *Manufacturer, |
| char *ManufacturerId, |
| char *Description, |
| char *SerialNumber |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_Read( |
| FT_HANDLE ftHandle, |
| PFT_PROGRAM_DATA pData |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_ReadEx( |
| FT_HANDLE ftHandle, |
| PFT_PROGRAM_DATA pData, |
| char *Manufacturer, |
| char *ManufacturerId, |
| char *Description, |
| char *SerialNumber |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_UASize( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwSize |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_UAWrite( |
| FT_HANDLE ftHandle, |
| PUCHAR pucData, |
| DWORD dwDataLen |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_UARead( |
| FT_HANDLE ftHandle, |
| PUCHAR pucData, |
| DWORD dwDataLen, |
| LPDWORD lpdwBytesRead |
| ); |
| typedef struct ft_eeprom_header { |
| FT_DEVICE deviceType; // FTxxxx device type to be programmed |
| // Device descriptor options |
| WORD VendorId; // 0x0403 |
| WORD ProductId; // 0x6001 |
| UCHAR SerNumEnable; // non-zero if serial number to be used |
| // Config descriptor options |
| WORD MaxPower; // 0 < MaxPower <= 500 |
| UCHAR SelfPowered; // 0 = bus powered, 1 = self powered |
| UCHAR RemoteWakeup; // 0 = not capable, 1 = capable |
| // Hardware options |
| UCHAR PullDownEnable; // non-zero if pull down in suspend enabled |
| } FT_EEPROM_HEADER, *PFT_EEPROM_HEADER; |
| // FT232B EEPROM structure for use with FT_EEPROM_Read and FT_EEPROM_Program |
| typedef struct ft_eeprom_232b { |
| // Common header |
| FT_EEPROM_HEADER common; // common elements for all device EEPROMs |
| } FT_EEPROM_232B, *PFT_EEPROM_232B; |
| // FT2232 EEPROM structure for use with FT_EEPROM_Read and FT_EEPROM_Program |
| typedef struct ft_eeprom_2232 { |
| // Common header |
| FT_EEPROM_HEADER common; // common elements for all device EEPROMs |
| // Drive options |
| UCHAR AIsHighCurrent; // non-zero if interface is high current |
| UCHAR BIsHighCurrent; // non-zero if interface is high current |
| // Hardware options |
| UCHAR AIsFifo; // non-zero if interface is 245 FIFO |
| UCHAR AIsFifoTar; // non-zero if interface is 245 FIFO CPU target |
| UCHAR AIsFastSer; // non-zero if interface is Fast serial |
| UCHAR BIsFifo; // non-zero if interface is 245 FIFO |
| UCHAR BIsFifoTar; // non-zero if interface is 245 FIFO CPU target |
| UCHAR BIsFastSer; // non-zero if interface is Fast serial |
| // Driver option |
| UCHAR ADriverType; // |
| UCHAR BDriverType; // |
| } FT_EEPROM_2232, *PFT_EEPROM_2232; |
| // FT232R EEPROM structure for use with FT_EEPROM_Read and FT_EEPROM_Program |
| typedef struct ft_eeprom_232r { |
| // Common header |
| FT_EEPROM_HEADER common; // common elements for all device EEPROMs |
| // Drive options |
| UCHAR IsHighCurrent; // non-zero if interface is high current |
| // Hardware options |
| UCHAR UseExtOsc; // Use External Oscillator |
| UCHAR InvertTXD; // non-zero if invert TXD |
| UCHAR InvertRXD; // non-zero if invert RXD |
| UCHAR InvertRTS; // non-zero if invert RTS |
| UCHAR InvertCTS; // non-zero if invert CTS |
| UCHAR InvertDTR; // non-zero if invert DTR |
| UCHAR InvertDSR; // non-zero if invert DSR |
| UCHAR InvertDCD; // non-zero if invert DCD |
| UCHAR InvertRI; // non-zero if invert RI |
| UCHAR Cbus0; // Cbus Mux control |
| UCHAR Cbus1; // Cbus Mux control |
| UCHAR Cbus2; // Cbus Mux control |
| UCHAR Cbus3; // Cbus Mux control |
| UCHAR Cbus4; // Cbus Mux control |
| // Driver option |
| UCHAR DriverType; // |
| } FT_EEPROM_232R, *PFT_EEPROM_232R; |
| // FT2232H EEPROM structure for use with FT_EEPROM_Read and FT_EEPROM_Program |
| typedef struct ft_eeprom_2232h { |
| // Common header |
| FT_EEPROM_HEADER common; // common elements for all device EEPROMs |
| // Drive options |
| UCHAR ALSlowSlew; // non-zero if AL pins have slow slew |
| UCHAR ALSchmittInput; // non-zero if AL pins are Schmitt input |
| UCHAR ALDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR AHSlowSlew; // non-zero if AH pins have slow slew |
| UCHAR AHSchmittInput; // non-zero if AH pins are Schmitt input |
| UCHAR AHDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR BLSlowSlew; // non-zero if BL pins have slow slew |
| UCHAR BLSchmittInput; // non-zero if BL pins are Schmitt input |
| UCHAR BLDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR BHSlowSlew; // non-zero if BH pins have slow slew |
| UCHAR BHSchmittInput; // non-zero if BH pins are Schmitt input |
| UCHAR BHDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| // Hardware options |
| UCHAR AIsFifo; // non-zero if interface is 245 FIFO |
| UCHAR AIsFifoTar; // non-zero if interface is 245 FIFO CPU target |
| UCHAR AIsFastSer; // non-zero if interface is Fast serial |
| UCHAR BIsFifo; // non-zero if interface is 245 FIFO |
| UCHAR BIsFifoTar; // non-zero if interface is 245 FIFO CPU target |
| UCHAR BIsFastSer; // non-zero if interface is Fast serial |
| UCHAR PowerSaveEnable; // non-zero if using BCBUS7 to save power for self-powered designs |
| // Driver option |
| UCHAR ADriverType; // |
| UCHAR BDriverType; // |
| } FT_EEPROM_2232H, *PFT_EEPROM_2232H; |
| // FT4232H EEPROM structure for use with FT_EEPROM_Read and FT_EEPROM_Program |
| typedef struct ft_eeprom_4232h { |
| // Common header |
| FT_EEPROM_HEADER common; // common elements for all device EEPROMs |
| // Drive options |
| UCHAR ASlowSlew; // non-zero if A pins have slow slew |
| UCHAR ASchmittInput; // non-zero if A pins are Schmitt input |
| UCHAR ADriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR BSlowSlew; // non-zero if B pins have slow slew |
| UCHAR BSchmittInput; // non-zero if B pins are Schmitt input |
| UCHAR BDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR CSlowSlew; // non-zero if C pins have slow slew |
| UCHAR CSchmittInput; // non-zero if C pins are Schmitt input |
| UCHAR CDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR DSlowSlew; // non-zero if D pins have slow slew |
| UCHAR DSchmittInput; // non-zero if D pins are Schmitt input |
| UCHAR DDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| // Hardware options |
| UCHAR ARIIsTXDEN; // non-zero if port A uses RI as RS485 TXDEN |
| UCHAR BRIIsTXDEN; // non-zero if port B uses RI as RS485 TXDEN |
| UCHAR CRIIsTXDEN; // non-zero if port C uses RI as RS485 TXDEN |
| UCHAR DRIIsTXDEN; // non-zero if port D uses RI as RS485 TXDEN |
| // Driver option |
| UCHAR ADriverType; // |
| UCHAR BDriverType; // |
| UCHAR CDriverType; // |
| UCHAR DDriverType; // |
| } FT_EEPROM_4232H, *PFT_EEPROM_4232H; |
| // FT232H EEPROM structure for use with FT_EEPROM_Read and FT_EEPROM_Program |
| typedef struct ft_eeprom_232h { |
| // Common header |
| FT_EEPROM_HEADER common; // common elements for all device EEPROMs |
| // Drive options |
| UCHAR ACSlowSlew; // non-zero if AC bus pins have slow slew |
| UCHAR ACSchmittInput; // non-zero if AC bus pins are Schmitt input |
| UCHAR ACDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR ADSlowSlew; // non-zero if AD bus pins have slow slew |
| UCHAR ADSchmittInput; // non-zero if AD bus pins are Schmitt input |
| UCHAR ADDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| // CBUS options |
| UCHAR Cbus0; // Cbus Mux control |
| UCHAR Cbus1; // Cbus Mux control |
| UCHAR Cbus2; // Cbus Mux control |
| UCHAR Cbus3; // Cbus Mux control |
| UCHAR Cbus4; // Cbus Mux control |
| UCHAR Cbus5; // Cbus Mux control |
| UCHAR Cbus6; // Cbus Mux control |
| UCHAR Cbus7; // Cbus Mux control |
| UCHAR Cbus8; // Cbus Mux control |
| UCHAR Cbus9; // Cbus Mux control |
| // FT1248 options |
| UCHAR FT1248Cpol; // FT1248 clock polarity - clock idle high (1) or clock idle low (0) |
| UCHAR FT1248Lsb; // FT1248 data is LSB (1) or MSB (0) |
| UCHAR FT1248FlowControl; // FT1248 flow control enable |
| // Hardware options |
| UCHAR IsFifo; // non-zero if interface is 245 FIFO |
| UCHAR IsFifoTar; // non-zero if interface is 245 FIFO CPU target |
| UCHAR IsFastSer; // non-zero if interface is Fast serial |
| UCHAR IsFT1248 ; // non-zero if interface is FT1248 |
| UCHAR PowerSaveEnable; // |
| // Driver option |
| UCHAR DriverType; // |
| } FT_EEPROM_232H, *PFT_EEPROM_232H; |
| // FT X Series EEPROM structure for use with FT_EEPROM_Read and FT_EEPROM_Program |
| typedef struct ft_eeprom_x_series { |
| // Common header |
| FT_EEPROM_HEADER common; // common elements for all device EEPROMs |
| // Drive options |
| UCHAR ACSlowSlew; // non-zero if AC bus pins have slow slew |
| UCHAR ACSchmittInput; // non-zero if AC bus pins are Schmitt input |
| UCHAR ACDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| UCHAR ADSlowSlew; // non-zero if AD bus pins have slow slew |
| UCHAR ADSchmittInput; // non-zero if AD bus pins are Schmitt input |
| UCHAR ADDriveCurrent; // valid values are 4mA, 8mA, 12mA, 16mA |
| // CBUS options |
| UCHAR Cbus0; // Cbus Mux control |
| UCHAR Cbus1; // Cbus Mux control |
| UCHAR Cbus2; // Cbus Mux control |
| UCHAR Cbus3; // Cbus Mux control |
| UCHAR Cbus4; // Cbus Mux control |
| UCHAR Cbus5; // Cbus Mux control |
| UCHAR Cbus6; // Cbus Mux control |
| // UART signal options |
| UCHAR InvertTXD; // non-zero if invert TXD |
| UCHAR InvertRXD; // non-zero if invert RXD |
| UCHAR InvertRTS; // non-zero if invert RTS |
| UCHAR InvertCTS; // non-zero if invert CTS |
| UCHAR InvertDTR; // non-zero if invert DTR |
| UCHAR InvertDSR; // non-zero if invert DSR |
| UCHAR InvertDCD; // non-zero if invert DCD |
| UCHAR InvertRI; // non-zero if invert RI |
| // Battery Charge Detect options |
| UCHAR BCDEnable; // Enable Battery Charger Detection |
| UCHAR BCDForceCbusPWREN; // asserts the power enable signal on CBUS when charging port detected |
| UCHAR BCDDisableSleep; // forces the device never to go into sleep mode |
| // I2C options |
| WORD I2CSlaveAddress; // I2C slave device address |
| DWORD I2CDeviceId; // I2C device ID |
| UCHAR I2CDisableSchmitt; // Disable I2C Schmitt trigger |
| // FT1248 options |
| UCHAR FT1248Cpol; // FT1248 clock polarity - clock idle high (1) or clock idle low (0) |
| UCHAR FT1248Lsb; // FT1248 data is LSB (1) or MSB (0) |
| UCHAR FT1248FlowControl; // FT1248 flow control enable |
| // Hardware options |
| UCHAR RS485EchoSuppress; // |
| UCHAR PowerSaveEnable; // |
| // Driver option |
| UCHAR DriverType; // |
| } FT_EEPROM_X_SERIES, *PFT_EEPROM_X_SERIES; |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EEPROM_Read( |
| FT_HANDLE ftHandle, |
| void *eepromData, |
| DWORD eepromDataSize, |
| char *Manufacturer, |
| char *ManufacturerId, |
| char *Description, |
| char *SerialNumber |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EEPROM_Program( |
| FT_HANDLE ftHandle, |
| void *eepromData, |
| DWORD eepromDataSize, |
| char *Manufacturer, |
| char *ManufacturerId, |
| char *Description, |
| char *SerialNumber |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetLatencyTimer( |
| FT_HANDLE ftHandle, |
| UCHAR ucLatency |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetLatencyTimer( |
| FT_HANDLE ftHandle, |
| PUCHAR pucLatency |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetBitMode( |
| FT_HANDLE ftHandle, |
| UCHAR ucMask, |
| UCHAR ucEnable |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetBitMode( |
| FT_HANDLE ftHandle, |
| PUCHAR pucMode |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetUSBParameters( |
| FT_HANDLE ftHandle, |
| ULONG ulInTransferSize, |
| ULONG ulOutTransferSize |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetDeadmanTimeout( |
| FT_HANDLE ftHandle, |
| ULONG ulDeadmanTimeout |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetDeviceInfo( |
| FT_HANDLE ftHandle, |
| FT_DEVICE *lpftDevice, |
| LPDWORD lpdwID, |
| PCHAR SerialNumber, |
| PCHAR Description, |
| LPVOID Dummy |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_StopInTask( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_RestartInTask( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_SetResetPipeRetryCount( |
| FT_HANDLE ftHandle, |
| DWORD dwCount |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_ResetPort( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_CyclePort( |
| FT_HANDLE ftHandle |
| ); |
| // |
| // Win32-type functions |
| // |
| FTD2XX_API |
| FT_HANDLE WINAPI FT_W32_CreateFile( |
| LPCTSTR lpszName, |
| DWORD dwAccess, |
| DWORD dwShareMode, |
| LPSECURITY_ATTRIBUTES lpSecurityAttributes, |
| DWORD dwCreate, |
| DWORD dwAttrsAndFlags, |
| HANDLE hTemplate |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_CloseHandle( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_ReadFile( |
| FT_HANDLE ftHandle, |
| LPVOID lpBuffer, |
| DWORD nBufferSize, |
| LPDWORD lpBytesReturned, |
| LPOVERLAPPED lpOverlapped |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_WriteFile( |
| FT_HANDLE ftHandle, |
| LPVOID lpBuffer, |
| DWORD nBufferSize, |
| LPDWORD lpBytesWritten, |
| LPOVERLAPPED lpOverlapped |
| ); |
| FTD2XX_API |
| DWORD WINAPI FT_W32_GetLastError( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_GetOverlappedResult( |
| FT_HANDLE ftHandle, |
| LPOVERLAPPED lpOverlapped, |
| LPDWORD lpdwBytesTransferred, |
| BOOL bWait |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_CancelIo( |
| FT_HANDLE ftHandle |
| ); |
| // |
| // Win32 COMM API type functions |
| // |
| typedef struct _FTCOMSTAT { |
| DWORD fCtsHold : 1; |
| DWORD fDsrHold : 1; |
| DWORD fRlsdHold : 1; |
| DWORD fXoffHold : 1; |
| DWORD fXoffSent : 1; |
| DWORD fEof : 1; |
| DWORD fTxim : 1; |
| DWORD fReserved : 25; |
| DWORD cbInQue; |
| DWORD cbOutQue; |
| } FTCOMSTAT, *LPFTCOMSTAT; |
| typedef struct _FTDCB { |
| DWORD DCBlength; /* sizeof(FTDCB) */ |
| DWORD BaudRate; /* Baudrate at which running */ |
| DWORD fBinary: 1; /* Binary Mode (skip EOF check) */ |
| DWORD fParity: 1; /* Enable parity checking */ |
| DWORD fOutxCtsFlow:1; /* CTS handshaking on output */ |
| DWORD fOutxDsrFlow:1; /* DSR handshaking on output */ |
| DWORD fDtrControl:2; /* DTR Flow control */ |
| DWORD fDsrSensitivity:1; /* DSR Sensitivity */ |
| DWORD fTXContinueOnXoff: 1; /* Continue TX when Xoff sent */ |
| DWORD fOutX: 1; /* Enable output X-ON/X-OFF */ |
| DWORD fInX: 1; /* Enable input X-ON/X-OFF */ |
| DWORD fErrorChar: 1; /* Enable Err Replacement */ |
| DWORD fNull: 1; /* Enable Null stripping */ |
| DWORD fRtsControl:2; /* Rts Flow control */ |
| DWORD fAbortOnError:1; /* Abort all reads and writes on Error */ |
| DWORD fDummy2:17; /* Reserved */ |
| WORD wReserved; /* Not currently used */ |
| WORD XonLim; /* Transmit X-ON threshold */ |
| WORD XoffLim; /* Transmit X-OFF threshold */ |
| BYTE ByteSize; /* Number of bits/byte, 4-8 */ |
| BYTE Parity; /* 0-4=None,Odd,Even,Mark,Space */ |
| BYTE StopBits; /* 0,1,2 = 1, 1.5, 2 */ |
| char XonChar; /* Tx and Rx X-ON character */ |
| char XoffChar; /* Tx and Rx X-OFF character */ |
| char ErrorChar; /* Error replacement char */ |
| char EofChar; /* End of Input character */ |
| char EvtChar; /* Received Event character */ |
| WORD wReserved1; /* Fill for now. */ |
| } FTDCB, *LPFTDCB; |
| typedef struct _FTTIMEOUTS { |
| DWORD ReadIntervalTimeout; /* Maximum time between read chars. */ |
| DWORD ReadTotalTimeoutMultiplier; /* Multiplier of characters. */ |
| DWORD ReadTotalTimeoutConstant; /* Constant in milliseconds. */ |
| DWORD WriteTotalTimeoutMultiplier; /* Multiplier of characters. */ |
| DWORD WriteTotalTimeoutConstant; /* Constant in milliseconds. */ |
| } FTTIMEOUTS,*LPFTTIMEOUTS; |
| FTD2XX_API |
| BOOL WINAPI FT_W32_ClearCommBreak( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_ClearCommError( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwErrors, |
| LPFTCOMSTAT lpftComstat |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_EscapeCommFunction( |
| FT_HANDLE ftHandle, |
| DWORD dwFunc |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_GetCommModemStatus( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwModemStatus |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_GetCommState( |
| FT_HANDLE ftHandle, |
| LPFTDCB lpftDcb |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_GetCommTimeouts( |
| FT_HANDLE ftHandle, |
| FTTIMEOUTS *pTimeouts |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_PurgeComm( |
| FT_HANDLE ftHandle, |
| DWORD dwMask |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetCommBreak( |
| FT_HANDLE ftHandle |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetCommMask( |
| FT_HANDLE ftHandle, |
| ULONG ulEventMask |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_GetCommMask( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwEventMask |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetCommState( |
| FT_HANDLE ftHandle, |
| LPFTDCB lpftDcb |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetCommTimeouts( |
| FT_HANDLE ftHandle, |
| FTTIMEOUTS *pTimeouts |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_SetupComm( |
| FT_HANDLE ftHandle, |
| DWORD dwReadBufferSize, |
| DWORD dwWriteBufferSize |
| ); |
| FTD2XX_API |
| BOOL WINAPI FT_W32_WaitCommEvent( |
| FT_HANDLE ftHandle, |
| PULONG pulEvent, |
| LPOVERLAPPED lpOverlapped |
| ); |
| // |
| // Device information |
| // |
| typedef struct _ft_device_list_info_node { |
| ULONG Flags; |
| ULONG Type; |
| ULONG ID; |
| DWORD LocId; |
| char SerialNumber[16]; |
| char Description[64]; |
| FT_HANDLE ftHandle; |
| } FT_DEVICE_LIST_INFO_NODE; |
| // Device information flags |
| enum { |
| FT_FLAGS_OPENED = 1, |
| FT_FLAGS_HISPEED = 2 |
| }; |
| FTD2XX_API |
| FT_STATUS WINAPI FT_CreateDeviceInfoList( |
| LPDWORD lpdwNumDevs |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetDeviceInfoList( |
| FT_DEVICE_LIST_INFO_NODE *pDest, |
| LPDWORD lpdwNumDevs |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetDeviceInfoDetail( |
| DWORD dwIndex, |
| LPDWORD lpdwFlags, |
| LPDWORD lpdwType, |
| LPDWORD lpdwID, |
| LPDWORD lpdwLocId, |
| LPVOID lpSerialNumber, |
| LPVOID lpDescription, |
| FT_HANDLE *pftHandle |
| ); |
| // |
| // Version information |
| // |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetDriverVersion( |
| FT_HANDLE ftHandle, |
| LPDWORD lpdwVersion |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetLibraryVersion( |
| LPDWORD lpdwVersion |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Rescan( |
| void |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_Reload( |
| WORD wVid, |
| WORD wPid |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetComPortNumber( |
| FT_HANDLE ftHandle, |
| LPLONG lpdwComPortNumber |
| ); |
| // |
| // FT232H additional EEPROM functions |
| // |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_ReadConfig( |
| FT_HANDLE ftHandle, |
| UCHAR ucAddress, |
| PUCHAR pucValue |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_WriteConfig( |
| FT_HANDLE ftHandle, |
| UCHAR ucAddress, |
| UCHAR ucValue |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_EE_ReadECC( |
| FT_HANDLE ftHandle, |
| UCHAR ucOption, |
| LPWORD lpwValue |
| ); |
| FTD2XX_API |
| FT_STATUS WINAPI FT_GetQueueStatusEx( |
| FT_HANDLE ftHandle, |
| DWORD *dwRxBytes |
| ); |
| #ifdef __cplusplus |
| } |
| #endif |
| #endif /* FTD2XX_H */ |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_win32/ftd2xx.lib |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x |
|---|
| Property changes: |
| Added: svn:ignore |
| +mlab_xvcd |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_SOFTWARE_Small.png |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/PrjInfo.txt |
|---|
| 0,0 → 1,29 |
| // |
| // Toto je popisný soubor pro popis obsahu adresáře (příklad) |
| // |
| [InfoShortDescription.en] |
| Xilinx Virtual Cable Sofware (program mlab_xvcd) |
| [InfoShortDescription.cs] |
| Xilinx Virtual Cable Sofware (program mlab_xvcd) |
| [InfoLongDescription.en] |
| The mlab_xvcd program converts JTAG commands received across TCP/IP |
| network via XVC protocol to outputs of the programming |
| cable (module) which is based on FTDI's USB chips like |
| popular FT232R, FT220X etc. |
| Used XVC protocol is directly supported by XILINX development |
| tools (both configuration tool IMPACT and debugging |
| embedded logic analyzer ChipScope Analyzer). |
| [InfoLongDescription.cs] |
| Program mlab_xvcd je obslužný program, který převádí JTAG příkazy |
| zasílané prostřednictvím XVC protokolu přes TCP/IP síť |
| na příslušné výstupy JTAG kabelu (modulku) založeného |
| na USB převodnících firmy FTDI (FT232R, FT220X, ...). |
| Protokol XVC přímo podporují vývojové nástroje XILINX |
| (nahrávání konfigurace program IMPACT a ladění pomocí |
| logického analyzátoru ChipScope Analyzer). |
| [End] |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/prog_EEPROM.bat |
|---|
| 0,0 → 1,8 |
| @echo off |
| FT_Prog-CmdLine.exe SCAN |
| echo. |
| echo Is the XVC MLAB Module device 0 ? |
| echo If not press CTRL-C |
| pause |
| FT_Prog-CmdLine.exe SCAN PROG 0 XVC_FT220X.xml |
| rem FT_Prog-CmdLine.exe SCAN PROG 0 XVC_FT230X.xml |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/XVC_FT230X.xml |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/XVC_FT230X_Original.xml |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/XVC_FT220X.xml |
|---|
| Cannot display: file marked as a binary type. |
| svn:mime-type = application/octet-stream |
| Property changes: |
| Added: svn:mime-type |
| +application/octet-stream |
| \ No newline at end of property |
| /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs.html |
|---|
| 0,0 → 1,636 |
| <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> |
| <html> |
| <head> |
| <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> |
| <title> XVC_FT220X01A </title> |
| <meta name="keywords" content="stavebnice MLAB univerzální moduly JTAG XVC Xilinx Virtual Cable XVC_FT220X01A FTDI USB"> |
| <meta name="description" content="Xilinx Virtual Cable založený na obvodu FT220X, JTAG programování FPGA a CPLD přes USB"> |
| <!-- AUTOINCLUDE START "Page/Head.cs.ihtml" DO NOT REMOVE --> |
| <link rel="StyleSheet" href="../../../../../../Web/CSS/MLAB.css" type="text/css" title="MLAB základní styl"> |
| <link rel="StyleSheet" href="../../../../../../Web/CSS/MLAB_Print.css" type="text/css" media="print"> |
| <link rel="shortcut icon" type="image/x-icon" href="../../../../../../Web/PIC/MLAB.ico"> |
| <script type="text/javascript" src="../../../../../../Web/JS/MLAB_Menu.js"></script> |
| <!-- AUTOINCLUDE END --> |
| </head> |
| <body lang="cs"> |
| <!-- AUTOINCLUDE START "Page/Header.cs.ihtml" DO NOT REMOVE --> |
| <!-- ============== HLAVICKA ============== --> |
| <div class="Header"> |
| <script type="text/javascript"> |
| <!-- |
| SetRelativePath("../../../../../../"); |
| DrawHeader(); |
| // --> |
| </script> |
| <noscript> |
| <p><b> Pro zobrazení (vložení) hlavičky je potřeba JavaScript </b></p> |
| </noscript> |
| </div> |
| <!-- AUTOINCLUDE END --> |
| <!-- AUTOINCLUDE START "Page/Menu.cs.ihtml" DO NOT REMOVE --> |
| <!-- ============== MENU ============== --> |
| <div class="Menu"> |
| <script type="text/javascript"> |
| <!-- |
| SetRelativePath("../../../../../../"); |
| DrawMenu(); |
| // --> |
| </script> |
| <noscript> |
| <p><b> Pro zobrazení (vložení) menu je potřeba JavaScript </b></p> |
| </noscript> |
| </div> |
| <!-- AUTOINCLUDE END --> |
| <!-- ============== TEXT ============== --> |
| <div class="Text"> |
| <p class="Title"> |
| Xilinx Virtual Cable s USB obvodem FTDI FT220X |
| </p> |
| <p class=Autor> |
| Milan Horkel |
| </p> |
| <p class="Subtitle"> |
| Vývojové prostředí ISE pro práci s obvody programovatelné logiky |
| (FPGA/CPLD) firmy XILINX přímo podporuje protokol XVC, kterým se |
| přenáší JTAG příkazy prostřednictvím sítě TCP/IP. Na vzdáleném konci |
| musí běžet příslušný obslužný program a k němu musí být připojen |
| programovací kabel. Toto je modul programovacího kabelu s obvodem FTDI |
| FT220X s USB rozhraním na jedné straně a JTAG konektorem na straně |
| druhé. |
| </p> |
| <p class="Subtitle"> |
| <img width="302" height="224" src="XVC_FT220X01A.cs_soubory/image001.jpg" |
| alt="Vzhled modulu XVC_FT220X01A"> |
| </p> |
| <p> |
| <a href="../XVC_FT220X01A.cs.pdf"><img class="NoBorder" |
| src="../../../../../../Web/PIC/FileIco_PDF.ico" |
| alt="Acrobat"> PDF verze</a> |
| </p> |
| <h1> Technické parametry </h1> |
| <table> |
| <tr> |
| <th> Parametr </th> |
| <th> Hodnota </th> |
| <th> Poznámka </th> |
| </tr> |
| <tr> |
| <td> Vstupní rozhraní </td> |
| <td> USB 2.0 </td> |
| <td> Standardní velký konektor typu B </td> |
| </tr> |
| <tr> |
| <td> Výstupní rozhraní </td> |
| <td> JTAG </td> |
| <td> Obvyklý jednořadý hřebínek </td> |
| </tr> |
| <tr> |
| <td> Napájení </td> |
| <td> +5V do 100mA </td> |
| <td> Z rozhraní USB </td> |
| </tr> |
| <tr> |
| <td> Signalizační napětí </td> |
| <td> +1.8 až +3.3V / +3.3V </td> |
| <td> Z cílového systému / fixní z FTDI </td> |
| </tr> |
| <tr> |
| <td> Síťový protokol / program </td> |
| <td> XVC / mlab_xvcd.exe </td> |
| <td> UDP, port 2542 / Windows aplikace </td> |
| </tr> |
| <tr> |
| <td> Vývojové prostředí </td> |
| <td> XILINX ISE – IMPACT<br> |
| XILINX ISE – ChipScope </td> |
| <td> Včetně volné verze WebPack,<br> |
| ChipScope vyžaduje licenci </td> |
| </tr> |
| <tr> |
| <td> Rozměry </td> |
| <td> 40x30x18mm </td> |
| <td> Výška nad základnou </td> |
| </tr> |
| </table> |
| <h1> Popis konstrukce </h1> |
| <h2> Úvodem </h2> |
| <p> |
| Pro práci s programovatelnými obvody FPGA a CPLD firmy XILINX je |
| potřeba příslušné vybavení. Jednou z nezbytností je vhodný programovací |
| kabel pro nahrávání konfigurace do cílové součástky. Jelikož LPT port |
| se postupně stěhuje do muzea, jsou programovací kabely vyrobené jako |
| klony známého Parallel Cable III zastaralé a je nutné nalézt nové |
| řešení. |
| </p> |
| <p> |
| Vývojové prostředí ISE přímo podporuje připojení programovacího kabelu |
| prostřednictvím TCP/IP sítě a použitý protokol Xilinx Virtual Cable (ve |
| zkratce XVC) je dokumentovaný. Díky tomu lze realizovat programovací |
| kabel za použití některého vhodného standardního obvodu rozhraní a |
| dopsat jen poměrně jednoduchý obslužný program. |
| </p> |
| <p> |
| <img width="676" height="621" src="XVC_FT220X01A.cs_soubory/image002.png" |
| alt="Schéma toku dat ve vývojovém cyklu"> |
| </p> |
| <p> |
| Volba padla na obvod FTDI FT220X s rozhraním USB. Jedná se o nový (v |
| roce 2012) obvod, jehož cena je překvapivě nízká (cca 40Kč). Obslužný |
| program s obvodem FTDI komunikuje v režimu BitBang, tedy nevyužívá |
| žádné speciální vlastnosti tohoto obvodu a může tak pracovat prakticky |
| se všemi obvody FTDI (včetně populárního FT232R). |
| </p> |
| <p> |
| Tato konstrukce představuje modul s USB rozhraním na jedné straně a |
| JTAG konektorem na straně druhé. Konektor je zapojen dle zvyklostí |
| XILINX programovacích kabelů. Modul podporuje signalizační napětí na |
| JTAG rozhraní v rozmezí 1.8 až 3.3V a navíc obsahuje indikační diody. |
| </p> |
| <p> |
| Obslužný program běží na počítači, ke kterému je připojen programovací |
| kabel a návrhový program ISE (přesněji komponenta IMPACT, případně |
| ChipScope Analyser) se s programem spojí prostřednictvím TCP/IP sítě. |
| Vývojové prostředí může samozřejmě běžet jak na dálku (přes skutečnou |
| síť), tak i na stejném počítači (síťuje se jen uvnitř počítače). |
| Současná verze programu běží pod systémem Windows (WinXP až Win8, |
| 32/64bit), verze pro Linux se připravuje. |
| </p> |
| <p> |
| Obslužný program má samostatnou dokumentaci a stránku, kde lze stáhnout |
| přeložený binární soubor (ale i zdrojové texty). |
| </p> |
| <p> |
| <a href="http://www.mlab.cz/PermaLink/XVC-SOFTWARE">http://www.mlab.cz/PermaLink/XVC-SOFTWARE</a> |
| </p> |
| <h2> Zapojení modulu </h2> |
| <p> |
| <img width="720" height="448" src="XVC_FT220X01A.cs_soubory/image003.png" |
| alt="Elektrické zapojení modulu XVC_FT220X01A"> |
| </p> |
| <p> |
| Obvod U1 FT220X je obvod rozhraní USB/SPI, ale ve skutečnosti se |
| používá v BitBang režimu, kdy se jeho SPI specifické vlastnosti |
| nepoužijí. V zapojení by mělo jít použít i další obvody řady FT200X, |
| zapojení vývodů je stejné. |
| </p> |
| <p> |
| Konektor J4 slouží pro napájení cílového zařízení z napětí +5V z USB |
| rozhraní. Pozor, modul neobsahuje pojistku a některé počítače nemusejí |
| mít napájení USB portů jištěné i když specifikace jištění vyžaduje. |
| Nepřetěžujte napájení USB portu! |
| </p> |
| <p> |
| Hřebínek J3 slouží pro přepínání napájecího napětí IO vývodů USB |
| obvodu. Standardně se používá napětí poskytované cílovou platformou z |
| JTAG konektoru J2.1. Toto napětí může ležet v rozmezí 1.8 až 3.3V. |
| Dioda D4 slouží jako ochranná. |
| </p> |
| <p> |
| Pokud cílová platforma neposkytuje napájecí napětí (někdy bývá značené |
| jako VTG) na JTAG konektoru, lze použít napětí 3.3V z vnitřního |
| stabilizátoru obvodu FTDI. <i>Pozor na to, že některé |
| obvody FPGA nemusejí akceptovat 3.3V.</i> |
| </p> |
| <p> |
| Dioda D1 indikuje přítomnost napájecího napětí cílové platformy. |
| </p> |
| <p> |
| Dioda D2 indikuje aktivitu obslužného programu (spuštění programu a |
| přenos dat). |
| </p> |
| <p> |
| Dioda D3 indikuje zapojení do USB (věci fungují mnohem lépe, když jsou |
| zapojené). |
| </p> |
| <p> |
| Zbývající součástky jsou blokovací kondenzátory, obvody odrušení a |
| ochranné odpory R3 až R6. |
| </p> |
| <h2> Mechanická konstrukce </h2> |
| <p> |
| Jedná se o standardní MLAB modul k přišroubování k základnové desce. |
| </p> |
| <h1> Osazení a oživení </h1> |
| <h2> Osazení </h2> |
| <p> |
| Strana spojů obsahuje SMD součástky. Je vhodné připájet nejdříve C5 a |
| L1 a pak obvod U1. Dioda D4 má anodu připojenou na zemní plochu. |
| </p> |
| <p> |
| <img width="477" height="357" src="XVC_FT220X01A.cs_soubory/image004.png" |
| alt="Osazení součástkami ze strany spojů"> |
| </p> |
| <p> |
| Strana součástí obsahuje jen hřebínky, konektory a 3 diody LED. Anody |
| LED diod jsou označeny písmenem A. Konektor J2 má 3 vývody odstraněné |
| jako klíč. |
| </p> |
| <p> |
| <img width="410" height="307" src="XVC_FT220X01A.cs_soubory/image005.png" |
| alt="Osazení součástkami ze strany součástek"> |
| </p> |
| <table class="Soupiska"> |
| <tr> |
| <th> Reference </th> |
| <th> Hodnota </th> |
| <th> Pouzdro </th> |
| <th> </th> |
| <th> Reference </th> |
| <th> Hodnota </th> |
| <th> Pouzdro </th> |
| </tr> |
| <tr> |
| <th colspan="3"> Odpory </th> |
| <td> </td> |
| <th colspan="3"> Tranzistory </th> |
| </tr> |
| <tr> |
| <td> R1, R2 </td> |
| <td> 27 </td> |
| <td> R0805 </td> |
| <td> </td> |
| <td> Q1, Q2 </td> |
| <td> 2N7000SMD </td> |
| <td> SOT23 </td> |
| </tr> |
| <tr> |
| <td> R3, R4, R5, R6 </td> |
| <td> 100 </td> |
| <td> R0805 </td> |
| <td> </td> |
| <th colspan="3"> Integrované obvody </th> |
| </tr> |
| <tr> |
| <td> R7, R8, R9 </td> |
| <td> 330 </td> |
| <td> R0805 </td> |
| <td> </td> |
| <td> U1 </td> |
| <td> FT220XS </td> |
| <td> SSO16_154 </td> |
| </tr> |
| <tr> |
| <td> R10, R11 </td> |
| <td> 10k </td> |
| <td> R0805 </td> |
| <td> </td> |
| <th colspan="3"> Konektory </th> |
| </tr> |
| <tr> |
| <th colspan="3"> Kondenzátory </th> |
| <td> </td> |
| <td> J1 </td> |
| <td> USB_B_01 </td> |
| <td> USB_B_01 </td> |
| </tr> |
| <tr> |
| <td> C1, C2 </td> |
| <td> 47pF </td> |
| <td> C0805 </td> |
| <td> </td> |
| <td> J2 </td> |
| <td> JUMP9_X3_X5_X8 </td> |
| <td> JUMP9_X3_X5_X8 </td> |
| </tr> |
| <tr> |
| <td> C3 </td> |
| <td> 10nF </td> |
| <td> C0805 </td> |
| <td> </td> |
| <td> J3 </td> |
| <td> JUMP3 </td> |
| <td> JUMP3 </td> |
| </tr> |
| <tr> |
| <td> C4, C6, C7 </td> |
| <td> 100nF </td> |
| <td> C0805 </td> |
| <td> </td> |
| <td> J4 </td> |
| <td> JUMP2X3 </td> |
| <td> JUMP2X3 </td> |
| </tr> |
| <tr> |
| <td> C5 </td> |
| <td> 10uF </td> |
| <td> C0805 </td> |
| <td> </td> |
| <th colspan="3"> Mechanické součásti </th> |
| </tr> |
| <tr> |
| <th colspan="3"> Indukčnosti </th> |
| <td> </td> |
| <td> 1ks </td> |
| <td> XVC_FT220X01A </td> |
| <td> Plošný spoj </td> |
| </tr> |
| <tr> |
| <td> L1 </td> |
| <td> L-BEAD </td> |
| <td> R1206 </td> |
| <td> </td> |
| <td> 4ks </td> |
| <td> Screw M3x12 </td> |
| <td> Šroub pozinkovaný </td> |
| </tr> |
| <tr> |
| <th colspan="3"> Diody </th> |
| <td> </td> |
| <td> 4ks </td> |
| <td> Washer M3 </td> |
| <td> Podložka </td> |
| </tr> |
| <tr> |
| <td> D1, D3 </td> |
| <td> LED3mm_RED </td> |
| <td> LED3 </td> |
| <td> </td> |
| <td> 4ks </td> |
| <td> Standoff M3x5 </td> |
| <td> Distanční sloupek </td> |
| </tr> |
| <tr> |
| <td> D2 </td> |
| <td> LED3mm_GREEN </td> |
| <td> LED3 </td> |
| <td> </td> |
| <td> 1ks </td> |
| <td> JUMPER </td> |
| <td> Propojka </td> |
| </tr> |
| <tr> |
| <td> D4 </td> |
| <td> BZV55-B3V6 </td> |
| <td> MINIMELF </td> |
| <td> </td> |
| <td> </td> |
| <td> </td> |
| <td> </td> |
| </tr> |
| </table> |
| <h2> Oživení </h2> |
| <p> |
| Po umytí desky a optické kontrole (zkraty, otočený U1) přistoupíme k |
| oživení. Nejprve připojíme +5V na prostřední pin J4 a změříme napětí na |
| J3.1 (mělo by být +3.3V). Dioda D3 (s nápisem USB) by měla svítit. |
| </p> |
| <p> |
| Odpojíme zdroj a připojíme USB kabelem k počítači. Počítač by měl najít |
| nový hardware a nainstalovat driver. Ovladač (typu D2XX) se najde na |
| stránce výrobce čipu |
| <a href="http://www.ftdichip.com/Drivers/D2XX.htm">http://www.ftdichip.com/Drivers/D2XX.htm</a>. |
| </p> |
| <p> |
| Dále je třeba nastavit správně konfiguraci obvodu FTDI tak, aby vývod |
| CBUS3 fungoval jako obyčejná IO nožička. Když se to neudělá, nebude |
| fungovat indikace LED D2 (indikuje aktivitu programu a přenos dat). To |
| se dělá pomocným programem FT_Prog od FTDI. Program je zašitý na webu |
| výrobce tak, aby ho laici nenašli <a href= |
| "http://www.ftdichip.com/Support/Utilities.htm">http://www.ftdichip.com/Support/Utilities.htm</a>. |
| </p> |
| <p> |
| Stažený ZIP archiv rozbalíme a můžeme spustit FT_Prog.exe a provést |
| změnu nastavení ručně, případně můžeme použít připravenou konfiguraci |
| ze souboru XVC_FT220X.xml. |
| </p> |
| <p> |
| Na obrázku je zvýrazněné požadované nastavení vývodu CBUS3. |
| </p> |
| <p> |
| <img width="641" height="406" src="XVC_FT220X01A.cs_soubory/image006.png" |
| alt="Nastavení funkce vývodu C3 u obvodu FTDI"> |
| </p> |
| <p> |
| Když už měníme konfiguraci je vhodné zadat smysluplné jméno do položky |
| Product Description. Toto jméno pak bude vypisovat obslužný program a |
| usnadní se tím výběr zařízení v případě, že je v systému více FTDI USB |
| převodníků. Pro operační systém se zařízení bude i nadále tvářit jako |
| USB Serial Converer (kdybychom změnili identifikaci zařízení, museli |
| bychom do systému doplnit INF soubor tak, aby systém věděl, že se má |
| pro zařízení použít FTDI driver). |
| </p> |
| <p> |
| <img width="642" height="448" src="XVC_FT220X01A.cs_soubory/image007.png" |
| alt="Nastavení USB identifikace obvodu FTDI"> |
| </p> |
| <p> |
| Tím by mělo být nastavení dokončené a je možné spustit obslužný program |
| mlab_xvcd.exe a pokud vše funguje správně, program vypíše spoustu |
| informací a na konci slovo „Listen“ a je připraven k navázání síťového |
| spojení ze strany vývojového prostředí. Dále postupujeme podle návodu k |
| použití (abychom se zde neopakovali). |
| </p> |
| <h1> Software a návod k použití </h1> |
| <h2> Instalace programu a první spuštění </h2> |
| <p> |
| Program pro obsluhu XVC_FT220X se jmenuje mlab_xvcd.exe a je k |
| dispozici na adrese |
| <a href="http://www.mlab.cz/PermaLink/XVC-SOFTWARE/XVC-1x/BIN">http://www.mlab.cz/PermaLink/XVC-SOFTWARE/XVC-1x/BIN</a>. |
| Program se neinstaluje (je slinkovaný jako jediný exe soubor), ale |
| potřebuje aby na počítači byly nainstalované drivery FTDI, které jsou |
| ke stažení na stránce výrobce |
| <a href="http://www.ftdichip.com/Drivers/D2XX.htm">http://www.ftdichip.com/Drivers/D2XX.htm</a>. |
| </p> |
| <p> |
| Program při prvním spuštění potřebuje povolit ve firewallu Windows |
| síťovou komunikaci (ve Win7 si o to systém sám řekne, ve starších |
| verzích Windows je třeba spustit konfiguraci systému firewall ručně a |
| povolit programu síťování). Připomínám, že nastavení je třeba |
| zopakovat, když program přesunete do jiného adresáře, nebo |
| přejmenujete, protože nastavení platí pro konkrétní program na |
| konkrétním místě v systému. |
| </p> |
| <h2> Spuštění mlab_xvcd.exe </h2> |
| <p> |
| Program po spuštění vypíše informace a nalezené obvody FTDI a spojí se |
| se zadaným zařízením, a když není zadáno tak s prvním nalezeným. Na |
| příkazové řádce lze zadat spojení podle názvu, sériového čísla, |
| umístění na USB sběrnici nebo podle pořadí nalezených obvodů FTDI. |
| </p> |
| <p> |
| <samp class="Block"> |
| D:\...\BIN>mlab_xvcd.exe |
| Xilinx Virtual Cable Network Server |
| =================================== |
| (c) miho 2012 v 1.03 |
| FTDI Connect |
| Library Version 0x30207 |
| Devices Found 1 |
| JTAG Port Pins TCK->DBUS0(TXD) |
| TDI->DBUS1(RXD) |
| TDO->DBUS2(RTS) |
| TMS->DBUS3(CTS) |
| LED->CBUS3+DBUS7(RI) |
| Device 0 |
| Description "XVC_FT220X" |
| SerialNumber "DAVY7XCB" |
| Location 0x111 |
| Selected Device |
| Description "XVC_FT220X" |
| SerialNumber "DAVY7XCB" |
| Device Driver Ver 0x20824 |
| Baud Rate 1000000 |
| USB Latency 1 |
| Starting Network Server |
| Host Name mihomsi |
| Network Name mihomsi |
| Host Address 192.168.22.14 |
| Bound Socket 2542 |
| Set in IMPACT xilinx_xvc host=mihomsi:2542 disableversioncheck=true |
| Listen |
| </samp> |
| </p> |
| <p> |
| Je-li na konci výpisu slovo Listen, je program připraven k navázání |
| spojení ze strany vývojového systému. Současně se rozsvítí LED indikace |
| aktivity (na plošném spoji označená ACT). |
| </p> |
| <h2> Spuštění a nastavení programu IMPACT </h2> |
| <p> |
| Nyní je třeba ve vývojovém prostředí spustit program IMPACT a v něm |
| nastavit plugin pro XVC protokol. Abychom si nemuseli pamatovat jaké |
| parametry se zadávají, program mlab_xvcd.exe vypisuje přesně to, co je |
| třeba do programu IMPACT zadat. Lze použít klipboard, ale pozor aby na |
| začátku nebyla mezera (není vidět, ale plugin se nenajde a nespustí). |
| Nastavení je v položce Output / Cable Setup. |
| </p> |
| <p> |
| <img width="397" height="440" src="XVC_FT220X01A.cs_soubory/image008.png" |
| alt="Nastavení XVC kabelu v programu iMPACT"> |
| </p> |
| <p> |
| Po odklepnutí dojde k navázání spojení a program mlab_xvcd.exe začne |
| vypisovat tečky (program IMPACT každou sekundu pošle data po síti i |
| když nemá co na práci). Současně zhasne indikační LED a jen poblikává |
| při zpracování dat. |
| </p> |
| <p> |
| <samp class="Block"> |
| Listen |
| Accepted 192.168.22.14:63280 |
| Handle Data ......................................... |
| ......... |
| </samp> |
| </p> |
| <p> |
| Nyní lze nahrát do obvodu FPGA konfiguraci, což bylo cílem našeho |
| snažení. |
| </p> |
| <p> |
| <img width="834" height="432" src="XVC_FT220X01A.cs_soubory/image009.png" |
| alt="Funkční program iMPACT"> |
| </p> |
| <h2> XVC a ChipScope </h2> |
| <p> |
| Použití XVC kabelu není omezeno jen na nahrávání obvodů FPGA, ale lze |
| jej použít i ve spojení s IP jádrem ChipScope (licencované) a zabudovat |
| si tak do obvodu FPGA velmi šikovný logický analyzátor. Tomuto tématu |
| se věnuje samostatný článek na adrese |
| <a href="http://www.mlab.cz/PermaLink/XVC-ChipScope">http://www.mlab.cz/PermaLink/XVC-ChipScope</a>. |
| </p> |
| <h2> Omezení </h2> |
| <p> |
| Řešení má i svá omezení. Zatím se mi nepodařilo rozchodit programování |
| pamětí SPI připojených k obvodu FPGA ani vnitřní SPI paměti obvodů |
| Spartan3AN. Tato funkce totiž nahrává obsah paměti tak, že nejdříve do |
| obvodu FPGA nahraje pomocný obsah (což se povede) a pak pomocí tohoto |
| pomocného zapojení získá přístup k pinům, ke kterým je připojena |
| (vnější nebo vnitřní) sériová FLASH paměť. To už se bohužel nepovede. |
| Zatím nevím proč. |
| </p> |
| <p> |
| Pro nahrávání SPI pamětí tedy i nadále používám LPT port s paralelním |
| kabelem (na některých počítačích to taky občas nefunguje), nebo XILINX |
| USB kabel (když si ho nezapomenu vypůjčit). |
| </p> |
| </div> |
| <!-- AUTOINCLUDE START "Page/Footer.cs.ihtml" DO NOT REMOVE --> |
| <!-- ============== PATIČKA ============== --> |
| <div class="Footer"> |
| <script type="text/javascript"> |
| <!-- |
| SetRelativePath("../../../../../../"); |
| DrawFooter(); |
| // --> |
| </script> |
| <noscript> |
| <p><b> Pro zobrazení (vložení) hlavičky je potřeba JavaScript </b></p> |
| </noscript> |
| </div> |
| <!-- AUTOINCLUDE END --> |
| </body> |
| </html> |
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|---|
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