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/Modules/CPLD_FPGA/S6AN01A/CAM_PROFI/Preview.gvp
0,0 → 1,9
(gerbv-file-version! "2.0A")
(define-layer! 5 (cons 'filename "V2.PHO")(cons 'visible #f)(cons 'color #(53713 6939 26728)))
(define-layer! 4 (cons 'filename "V1.PHO")(cons 'visible #t)(cons 'color #(54741 65021 13107)))
(define-layer! 3 (cons 'filename "T1.PHO")(cons 'visible #t)(cons 'color #(0 50115 50115)))
(define-layer! 2 (cons 'filename "M2.PHO")(cons 'visible #f)(cons 'color #(30069 62194 26471)))
(define-layer! 1 (cons 'filename "M1.PHO")(cons 'visible #t)(cons 'color #(49601 0 57568)))
(define-layer! 0 (cons 'filename "BOARD.PHO")(cons 'visible #t)(cons 'color #(29555 29555 57054)))
(define-layer! -1 (cons 'filename "./")(cons 'visible #f)(cons 'color #(0 0 0)))
(set-render-type! 3)
/Modules/CPLD_FPGA/S6AN01A/PrjInfo.txt
0,0 → 1,13
[InfoShortDescription.en]
Xilinx Spartan 6 XC6SLX9T FPGA Developing Board
 
[InfoShortDescription.cs]
Vývojový modul s FPGA Xilinx Spartan 6 XC6SLX9T
 
[InfoLongDescription.en]
FPGA development module for basic signal and data processing. This breakout board differs from other constructions by high number of differential pairs take out to LVDS or LVPECL connectors.
 
[InfoLongDescription.cs]
FPGA vývojová deska pro základní zpracování signálů. Od běžných vývojových desek se odlišuje hlavně zvýšeným množstvím diferenčňích kanálů vyvedených na konektory.
 
[End]
/Modules/CPLD_FPGA/S6AN01A/pdf/ds160.pdf
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/Modules/CPLD_FPGA/S6AN01A/pdf/ds162.pdf
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