No changes between revisions
/Modules/ADconverters/ADCdual01A/SCH&PCB/ADCdual.kicad_pcb |
0,0 → 1,100 |
(kicad_pcb (version 3) (host pcbnew "(2014-03-14 BZR 4749)-product") |
|
(general |
(links 0) |
(no_connects 0) |
(area 0 0 0 0) |
(thickness 1.6) |
(drawings 0) |
(tracks 0) |
(zones 0) |
(modules 0) |
(nets 1) |
) |
|
(page A4) |
(layers |
(15 F.Cu signal) |
(0 B.Cu signal) |
(16 B.Adhes user) |
(17 F.Adhes user) |
(18 B.Paste user) |
(19 F.Paste user) |
(20 B.SilkS user) |
(21 F.SilkS user) |
(22 B.Mask user) |
(23 F.Mask user) |
(24 Dwgs.User user) |
(25 Cmts.User user) |
(26 Eco1.User user) |
(27 Eco2.User user) |
(28 Edge.Cuts user) |
) |
|
(setup |
(last_trace_width 0.254) |
(trace_clearance 0.254) |
(zone_clearance 0.508) |
(zone_45_only no) |
(trace_min 0.254) |
(segment_width 0.2) |
(edge_width 0.15) |
(via_size 0.889) |
(via_drill 0.635) |
(via_min_size 0.889) |
(via_min_drill 0.508) |
(uvia_size 0.508) |
(uvia_drill 0.127) |
(uvias_allowed no) |
(uvia_min_size 0.508) |
(uvia_min_drill 0.127) |
(pcb_text_width 0.3) |
(pcb_text_size 1 1) |
(mod_edge_width 0.15) |
(mod_text_size 1 1) |
(mod_text_width 0.15) |
(pad_size 1 1) |
(pad_drill 0.6) |
(pad_to_mask_clearance 0) |
(aux_axis_origin 0 0) |
(visible_elements FFFFFF7F) |
(pcbplotparams |
(layerselection 3178497) |
(usegerberextensions true) |
(excludeedgelayer true) |
(linewidth 0.150000) |
(plotframeref false) |
(viasonmask false) |
(mode 1) |
(useauxorigin false) |
(hpglpennumber 1) |
(hpglpenspeed 20) |
(hpglpendiameter 15) |
(hpglpenoverlay 2) |
(psnegative false) |
(psa4output false) |
(plotreference true) |
(plotvalue true) |
(plotothertext true) |
(plotinvisibletext false) |
(padsonsilk false) |
(subtractmaskfromsilk false) |
(outputformat 1) |
(mirror false) |
(drillshape 1) |
(scaleselection 1) |
(outputdirectory "")) |
) |
|
(net 0 "") |
|
(net_class Default "This is the default net class." |
(clearance 0.254) |
(trace_width 0.254) |
(via_dia 0.889) |
(via_drill 0.635) |
(uvia_dia 0.508) |
(uvia_drill 0.127) |
) |
|
) |