WebSVN – MLAB – /Modules/ARM/ODROID-U3/SCH_PCB/ Rev 3951 and /Modules/ARM/ODROID-U3/SCH_PCB/ Rev 3952 – Path Comparison

/Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.cmp
1,4 → 1,4
Cmp-Mod V01 Created by Cvpcb 0.201503110816+5502~22~ubuntu14.10.1-product date = St 11. březen 2015, 16:30:41 CET
Cmp-Mod V01 Created by Cvpcb 0.201503110816+5502~22~ubuntu14.10.1-product date = St 11. březen 2015, 17:38:58 CET

BeginCmp
TimeStamp = /5485FFA7;

 /Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.kicad_pcb
 ,14 → 1,14
 (kicad_pcb (version 4) (host pcbnew 0.201503110816+5502~22~ubuntu14.10.1-product)
   (general
-    (links 51)
-    (no_connects 8)
-    (area 107.622599 35.235799 158.010601 61.111601)
+    (links 43)
+    (no_connects 0)
+    (area 104.4448 30.8356 164.109401 63.017401)
     (thickness 1.6)
     (drawings 18)
     (tracks 76)
     (zones 0)
-    (modules 23)
+    (modules 22)
     (nets 13)
   )
 ,7 → 37,7
   )
   (setup
-    (last_trace_width 1)
+    (last_trace_width 0.3)
     (user_trace_width 0.2)
     (user_trace_width 0.3)
     (user_trace_width 0.4)
 ,9 → 108,9
   (net 7 /UART_TX)
   (net 8 /UART_RX)
   (net 9 /SCLK)
-  (net 10 /MOSI)
-  (net 11 /#SS)
-  (net 12 /MISO)
+  (net 10 /MISO)
+  (net 11 "Net-(J10-Pad1)")
+  (net 12 "Net-(J11-Pad3)")
   (net_class Default "Toto je výchozí třída sítě."
     (clearance 0.15)
 ,15 → 119,15
     (via_drill 0.635)
     (uvia_dia 0.508)
     (uvia_drill 0.127)
-    (add_net /#SS)
     (add_net /GPIO199)
     (add_net /GPIO200)
     (add_net /GPIO204)
     (add_net /MISO)
-    (add_net /MOSI)
     (add_net /SCLK)
     (add_net /UART_RX)
     (add_net /UART_TX)
+    (add_net "Net-(J10-Pad1)")
+    (add_net "Net-(J11-Pad3)")
   )
   (net_class Power ""
 ,39 → 142,39
     (add_net GND)
   )
-  (module MLAB_hreb:2mm_Pin_Header_Straight_2x04 (layer B.Cu) (tedit 5487093A) (tstamp 55015AF1)
-    (at 146.3166 54.9498 270)
+  (module MLAB_hreb:2mm_Pin_Header_Straight_2x04 (layer F.Cu) (tedit 55007440) (tstamp 55015AF1)
+    (at 146.3166 54.9498 90)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /5485F8D0)
-    (fp_text reference J6 (at -3.14 -3.645 540) (layer B.SilkS)
-      (effects (font (size 1.27 1.27) (thickness 0.2032)) (justify mirror))
+    (fp_text reference J6 (at -0.2952 -5.4228 180) (layer F.SilkS)
+      (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
-    (fp_text value IOS_PORT_#1 (at 0 -5.334 270) (layer B.SilkS) hide
-      (effects (font (size 1.27 1.27) (thickness 0.2032)) (justify mirror))
+    (fp_text value IOS_PORT_#1 (at 0 5.334 90) (layer F.SilkS) hide
+      (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
-    (fp_line (start -2 4) (end 0 4) (layer B.SilkS) (width 0.254))
-    (fp_line (start 0 -4) (end 2 -4) (layer B.SilkS) (width 0.254))
-    (fp_line (start 2 -4) (end 2 4) (layer B.SilkS) (width 0.254))
-    (fp_line (start 0 4) (end 2 4) (layer B.SilkS) (width 0.254))
-    (fp_line (start -2 -4) (end -2 4) (layer B.SilkS) (width 0.254))
-    (fp_line (start -2 -4) (end 0 -4) (layer B.SilkS) (width 0.254))
-    (pad 1 thru_hole rect (at -1 3 270) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask B.SilkS)
+    (fp_line (start -2 -4) (end 0 -4) (layer F.SilkS) (width 0.254))
+    (fp_line (start 0 4) (end 2 4) (layer F.SilkS) (width 0.254))
+    (fp_line (start 2 4) (end 2 -4) (layer F.SilkS) (width 0.254))
+    (fp_line (start 0 -4) (end 2 -4) (layer F.SilkS) (width 0.254))
+    (fp_line (start -2 4) (end -2 -4) (layer F.SilkS) (width 0.254))
+    (fp_line (start -2 4) (end 0 4) (layer F.SilkS) (width 0.254))
+    (pad 1 thru_hole rect (at -1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 3 +1.8V))
+    (pad 2 thru_hole rect (at 1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
       (net 4 /GPIO199))
-    (pad 2 thru_hole rect (at 1 3 270) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask B.SilkS)
-      (net 3 +1.8V))
-    (pad 3 thru_hole rect (at -1 1 270) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask B.SilkS)
+    (pad 3 thru_hole rect (at -1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 8 /UART_RX))
+    (pad 4 thru_hole rect (at 1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
       (net 5 /GPIO200))
-    (pad 4 thru_hole rect (at 1 1 270) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask B.SilkS)
-      (net 8 /UART_RX))
-    (pad 5 thru_hole rect (at -1 -1 270) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask B.SilkS)
+    (pad 5 thru_hole rect (at -1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 7 /UART_TX))
+    (pad 6 thru_hole rect (at 1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
       (net 6 /GPIO204))
-    (pad 6 thru_hole rect (at 1 -1 270) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask B.SilkS)
-      (net 7 /UART_TX))
-    (pad 7 thru_hole rect (at -1 -3 270) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask B.SilkS)
+    (pad 7 thru_hole rect (at -1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 2 +5V))
+    (pad 8 thru_hole rect (at 1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
       (net 1 GND))
-    (pad 8 thru_hole rect (at 1 -3 270) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask B.SilkS)
-      (net 2 +5V))
     (model Pin_Headers/Pin_Header_Straight_2x04.wrl
       (at (xyz 0 0 0))
       (scale (xyz 0.7874 0.7874 0.7874))
 ,6 → 182,37
     )
   )
+  (module Capacitors_Tantalum_SMD:TantalC_SizeB_EIA-3528_Reflow (layer B.Cu) (tedit 55005C2F) (tstamp 5500FA8F)
+    (at 138.684 56.1086 180)
+    (descr "Tantal Cap. , Size B, EIA-3528, Reflow,")
+    (tags "Tantal Cap. , Size B, EIA-3528, Reflow,")
+    (path /548601CE)
+    (attr smd)
+    (fp_text reference C2 (at -0.20066 3.29946 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 10uF (at -0.09906 -3.59918 180) (layer B.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user + (at -3.59918 2.49936 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -2.99974 1.89992) (end -2.99974 -1.89992) (layer B.SilkS) (width 0.15))
+    (fp_line (start 2.49936 1.89992) (end -2.49936 1.89992) (layer B.SilkS) (width 0.15))
+    (fp_line (start 2.49682 -1.89992) (end -2.5019 -1.89992) (layer B.SilkS) (width 0.15))
+    (fp_line (start -3.60172 3.00228) (end -3.60172 1.90246) (layer B.SilkS) (width 0.15))
+    (fp_line (start -4.20116 2.5019) (end -3.00228 2.5019) (layer B.SilkS) (width 0.15))
+    (pad 2 smd rect (at 1.5494 0 180) (size 1.95072 2.49936) (layers B.Cu B.Paste B.Mask)
+      (net 1 GND))
+    (pad 1 smd rect (at -1.5494 0 180) (size 1.95072 2.49936) (layers B.Cu B.Paste B.Mask)
+      (net 3 +1.8V))
+    (model Capacitors_Tantalum_SMD/TantalC_SizeB_EIA-3528_Reflow.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 180))
+    )
+  )
   (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54896E7D)
     (at 137.668 40.005)
     (descr "1 pin")
 ,46 → 291,6
     )
   )
-  (module MLAB_hreb:2mm_Pin_Header_Straight_2x04 (layer F.Cu) (tedit 5487093A) (tstamp 54871228)
-    (at 146.3166 54.9498 90)
-    (descr "1 pin")
-    (tags "CONN DEV")
-    (path /5485F8D0)
-    (fp_text reference J6 (at -3.14 3.645 180) (layer F.SilkS)
-      (effects (font (size 1.27 1.27) (thickness 0.2032)))
-    )
-    (fp_text value IOS_PORT_#1 (at 0 5.334 90) (layer F.SilkS) hide
-      (effects (font (size 1.27 1.27) (thickness 0.2032)))
-    )
-    (fp_line (start -2 -4) (end 0 -4) (layer F.SilkS) (width 0.254))
-    (fp_line (start 0 4) (end 2 4) (layer F.SilkS) (width 0.254))
-    (fp_line (start 2 4) (end 2 -4) (layer F.SilkS) (width 0.254))
-    (fp_line (start 0 -4) (end 2 -4) (layer F.SilkS) (width 0.254))
-    (fp_line (start -2 4) (end -2 -4) (layer F.SilkS) (width 0.254))
-    (fp_line (start -2 4) (end 0 4) (layer F.SilkS) (width 0.254))
-    (pad 1 thru_hole rect (at -1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 4 /GPIO199))
-    (pad 2 thru_hole rect (at 1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 3 +1.8V))
-    (pad 3 thru_hole rect (at -1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 5 /GPIO200))
-    (pad 4 thru_hole rect (at 1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 8 /UART_RX))
-    (pad 5 thru_hole rect (at -1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 6 /GPIO204))
-    (pad 6 thru_hole rect (at 1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 7 /UART_TX))
-    (pad 7 thru_hole rect (at -1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 1 GND))
-    (pad 8 thru_hole rect (at 1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 2 +5V))
-    (model Pin_Headers/Pin_Header_Straight_2x04.wrl
-      (at (xyz 0 0 0))
-      (scale (xyz 0.7874 0.7874 0.7874))
-      (rotate (xyz 0 0 90))
-    )
-  )
   (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54896E72)
     (at 140.208 40.005)
     (descr "1 pin")
 ,12 → 343,12
     )
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54874ADA)
+  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 55007496) (tstamp 54874ADA)
     (at 118.0846 40.0558)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /5486082B)
-    (fp_text reference J9 (at 0 -3.81) (layer F.SilkS)
+    (fp_text reference J9 (at -1.2192 -3.6322) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value SCLK (at 0 0) (layer F.SilkS) hide
 ,12 → 369,12
     )
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871250)
+  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 550074A7) (tstamp 54871250)
     (at 120.6246 40.0558)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /54860825)
-    (fp_text reference J10 (at 0 -3.81) (layer F.SilkS)
+    (fp_text reference J10 (at -1.1176 -3.6576) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value MOSI (at 0 0) (layer F.SilkS) hide
 ,9 → 385,9
     (fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
     (fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
     (pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 10 /MOSI))
+      (net 11 "Net-(J10-Pad1)"))
     (pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 10 /MOSI))
+      (net 11 "Net-(J10-Pad1)"))
     (model Pin_Headers/Pin_Header_Straight_2x01.wrl
       (at (xyz 0 0 0))
       (scale (xyz 1 1 1))
 ,12 → 395,12
     )
   )
-  (module MLAB_hreb:2mm_Pin_Header_Straight_2x02 (layer F.Cu) (tedit 54870948) (tstamp 5487125E)
+  (module MLAB_hreb:2mm_Pin_Header_Straight_2x02 (layer F.Cu) (tedit 550074DF) (tstamp 5487125E)
     (at 117.8166 54.9498)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /5485F97F)
-    (fp_text reference J11 (at -0.127 -2.921) (layer F.SilkS)
+    (fp_text reference J11 (at 4.2558 0.0412) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value IO_PORT_#2 (at 0 3.302) (layer F.SilkS) hide
 ,11 → 415,11
     (pad 1 thru_hole rect (at -1 -1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
       (net 9 /SCLK))
     (pad 2 thru_hole rect (at 1 -1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 11 /#SS))
+      (net 11 "Net-(J10-Pad1)"))
     (pad 3 thru_hole rect (at -1 1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 10 /MOSI))
+      (net 12 "Net-(J11-Pad3)"))
     (pad 4 thru_hole rect (at 1 1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 12 /MISO))
+      (net 10 /MISO))
     (model Pin_Headers/Pin_Header_Straight_2x02.wrl
       (at (xyz 0 0 0))
       (scale (xyz 0.7874 0.7874 0.7874))
 ,12 → 427,12
     )
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871268)
+  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 550074AC) (tstamp 54871268)
     (at 125.7046 40.0558)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /54860610)
-    (fp_text reference J12 (at 0 -3.81) (layer F.SilkS)
+    (fp_text reference J12 (at 0.381 -3.5052) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value "#SS" (at 0 0) (layer F.SilkS) hide
 ,9 → 443,9
     (fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
     (fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
     (pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 11 /#SS))
+      (net 12 "Net-(J11-Pad3)"))
     (pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 11 /#SS))
+      (net 12 "Net-(J11-Pad3)"))
     (model Pin_Headers/Pin_Header_Straight_2x01.wrl
       (at (xyz 0 0 0))
       (scale (xyz 1 1 1))
 ,12 → 453,12
     )
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871272)
+  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 550074AA) (tstamp 54871272)
     (at 123.1646 40.0558)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /54860710)
-    (fp_text reference J13 (at 0 -3.81) (layer F.SilkS)
+    (fp_text reference J13 (at -0.4318 -3.5052) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value MISO (at 0 0) (layer F.SilkS) hide
 ,9 → 469,9
     (fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
     (fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
     (pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 12 /MISO))
+      (net 10 /MISO))
     (pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 12 /MISO))
+      (net 10 /MISO))
     (model Pin_Headers/Pin_Header_Straight_2x01.wrl
       (at (xyz 0 0 0))
       (scale (xyz 1 1 1))
 ,12 → 479,12
     )
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 54345FDC) (tstamp 54871277)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 55007470) (tstamp 54871277)
     (at 153.1366 40.1098)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862BF8)
-    (fp_text reference J14 (at 0 0) (layer F.SilkS)
+    (fp_text reference J14 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,12 → 495,12
       (net 1 GND) (clearance 1) (zone_connect 2))
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 54345FDC) (tstamp 5487127C)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 5500745C) (tstamp 5487127C)
     (at 112.4966 40.1098)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862A8F)
-    (fp_text reference J15 (at 0 0) (layer F.SilkS)
+    (fp_text reference J15 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,12 → 511,12
       (net 1 GND) (clearance 1) (zone_connect 2))
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 5489719A) (tstamp 54871281)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 55007468) (tstamp 54871281)
     (at 153.3166 55.5498)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862E35)
-    (fp_text reference J16 (at 0 0) (layer F.SilkS)
+    (fp_text reference J16 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,12 → 527,12
       (net 1 GND) (clearance 1) (zone_connect 2))
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 5489848E) (tstamp 54871286)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 55007453) (tstamp 54871286)
     (at 112.3166 55.5498)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862E8B)
-    (fp_text reference J17 (at 0 0) (layer F.SilkS)
+    (fp_text reference J17 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,12 → 543,12
       (net 1 GND) (clearance 1) (zone_connect 2))
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 54345FDC) (tstamp 5487128B)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 5500748A) (tstamp 5487128B)
     (at 132.8166 50.2698)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862E2F)
-    (fp_text reference J18 (at 0 0) (layer F.SilkS)
+    (fp_text reference J18 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,38 → 663,7
     )
   )
-  (module Capacitors_Tantalum_SMD:TantalC_SizeB_EIA-3528_Reflow (layer B.Cu) (tedit 55005C2F) (tstamp 5500FA8F)
-    (at 138.684 56.1086 180)
-    (descr "Tantal Cap. , Size B, EIA-3528, Reflow,")
-    (tags "Tantal Cap. , Size B, EIA-3528, Reflow,")
-    (path /548601CE)
-    (attr smd)
-    (fp_text reference C2 (at -0.20066 3.29946 180) (layer B.SilkS)
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-    )
-    (fp_text value 10uF (at -0.09906 -3.59918 180) (layer B.SilkS) hide
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-    )
-    (fp_text user + (at -3.59918 2.49936 180) (layer B.SilkS)
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
-    )
-    (fp_line (start -2.99974 1.89992) (end -2.99974 -1.89992) (layer B.SilkS) (width 0.15))
-    (fp_line (start 2.49936 1.89992) (end -2.49936 1.89992) (layer B.SilkS) (width 0.15))
-    (fp_line (start 2.49682 -1.89992) (end -2.5019 -1.89992) (layer B.SilkS) (width 0.15))
-    (fp_line (start -3.60172 3.00228) (end -3.60172 1.90246) (layer B.SilkS) (width 0.15))
-    (fp_line (start -4.20116 2.5019) (end -3.00228 2.5019) (layer B.SilkS) (width 0.15))
-    (pad 2 smd rect (at 1.5494 0 180) (size 1.95072 2.49936) (layers B.Cu B.Paste B.Mask)
-      (net 1 GND))
-    (pad 1 smd rect (at -1.5494 0 180) (size 1.95072 2.49936) (layers B.Cu B.Paste B.Mask)
-      (net 3 +1.8V))
-    (model Capacitors_Tantalum_SMD/TantalC_SizeB_EIA-3528_Reflow.wrl
-      (at (xyz 0 0 0))
-      (scale (xyz 1 1 1))
-      (rotate (xyz 0 0 180))
-    )
-  )
-  (module Mlab_Pin_Headers:Straight_2x03 (layer F.Cu) (tedit 550060BF) (tstamp 55015A75)
+  (module Mlab_Pin_Headers:Straight_2x03 (layer F.Cu) (tedit 55007572) (tstamp 55015A75)
     (at 153.1366 47.4218 270)
     (descr "pin header straight 2x03")
     (tags "pin header straight 2x03")
 ,7 → 674,7
     (fp_text value "5V POWER" (at 0 5.08 270) (layer F.SilkS) hide
       (effects (font (size 1.5 1.5) (thickness 0.15)))
     )
-    (fp_text user 1 (at -2.921 -2.54 270) (layer F.SilkS)
+    (fp_text user 1 (at -2.921 -2.54 270) (layer F.SilkS) hide
       (effects (font (size 0.5 0.5) (thickness 0.05)))
     )
     (fp_line (start -2.54 -3.81) (end 2.54 -3.81) (layer F.SilkS) (width 0.15))
 ,16 → 737,19
     )
   )
-  (gr_text "ODROID-U3 MLAB ADAPTER" (at 132.3086 58.8518) (layer F.SilkS)
+  (gr_text GPIO200 (at 142.8496 47.6758 90) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
-  (gr_text MLAB (at 112.6236 47.8028 90) (layer F.SilkS)
+  (gr_text "ODROID-U3 MLAB BREAKOUT BOARD" (at 132.3086 59.436) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
+  (gr_text "MLAB\n2015" (at 112.4712 47.8028) (layer F.SilkS)
+    (effects (font (size 1.5 1.5) (thickness 0.3)))
+  )
   (gr_text +5V (at 152.6286 51.4858) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
-  (gr_text POWER (at 153.3906 43.8658) (layer F.SilkS)
+  (gr_text POWER (at 153.1874 44.0436) (layer F.SilkS) (tstamp 55007537)
     (effects (font (size 1 1) (thickness 0.2)))
   )
   (gr_text GPIO204 (at 147.9296 47.6758 90) (layer F.SilkS)
 ,9 → 758,6
   (gr_text TX (at 145.3896 44.3738 90) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
-  (gr_text GPIO200 (at 142.8496 47.6758 90) (layer F.SilkS)
-    (effects (font (size 1.5 1.5) (thickness 0.3)))
-  )
   (gr_text RX (at 140.3096 44.5008 90) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
 ,82 → 784,82
   (gr_line (start 107.6726 61.0616) (end 157.9606 61.0616) (angle 90) (layer Edge.Cuts) (width 0.1))
   (gr_line (start 107.6726 35.2858) (end 107.6726 61.0616) (angle 90) (layer Edge.Cuts) (width 0.1))
-  (segment (start 149.2946 55.9718) (end 149.3166 55.9498) (width 1) (layer B.Cu) (net 1))
-  (segment (start 131.63728 59.944) (end 154.102402 59.944) (width 1) (layer B.Cu) (net 2))
-  (segment (start 154.102402 59.944) (end 156.816601 57.229801) (width 1) (layer B.Cu) (net 2))
-  (segment (start 130.67208 58.9788) (end 131.63728 59.944) (width 1) (layer B.Cu) (net 2))
-  (segment (start 128.4224 58.9788) (end 124.36602 58.9788) (width 1) (layer B.Cu) (net 2))
-  (segment (start 124.36602 58.9788) (end 124.2568 58.86958) (width 1) (layer B.Cu) (net 2))
-  (segment (start 153.1366 48.6918) (end 153.1366 50.189798) (width 1) (layer B.Cu) (net 2))
-  (segment (start 153.1366 50.189798) (end 156.816601 53.869799) (width 1) (layer B.Cu) (net 2))
-  (segment (start 156.816601 53.869799) (end 156.816601 57.229801) (width 1) (layer B.Cu) (net 2))
+  (segment (start 149.3166 55.9498) (end 149.3166 57.5998) (width 1) (layer B.Cu) (net 2))
+  (segment (start 149.3166 57.5998) (end 147.9376 58.9788) (width 1) (layer B.Cu) (net 2))
+  (segment (start 147.9376 58.9788) (end 130.67208 58.9788) (width 1) (layer B.Cu) (net 2))
   (segment (start 130.67208 58.9788) (end 128.4224 58.9788) (width 1) (layer B.Cu) (net 2))
-  (segment (start 153.1366 48.6918) (end 153.1366 50.1298) (width 1) (layer B.Cu) (net 2))
-  (segment (start 153.1366 50.1298) (end 149.3166 53.9498) (width 1) (layer B.Cu) (net 2))
+  (segment (start 156.816601 53.869799) (end 153.1366 50.189798) (width 1) (layer B.Cu) (net 2))
+  (segment (start 149.3166 57.5998) (end 150.766601 59.049801) (width 1) (layer B.Cu) (net 2))
+  (segment (start 156.816601 57.229801) (end 156.816601 53.869799) (width 1) (layer B.Cu) (net 2))
+  (segment (start 150.766601 59.049801) (end 154.996601 59.049801) (width 1) (layer B.Cu) (net 2))
+  (segment (start 154.996601 59.049801) (end 156.816601 57.229801) (width 1) (layer B.Cu) (net 2))
+  (segment (start 153.1366 50.189798) (end 153.1366 48.6918) (width 1) (layer B.Cu) (net 2))
+  (segment (start 149.2946 55.9718) (end 149.3166 55.9498) (width 1) (layer B.Cu) (net 2))
+  (segment (start 153.1206 48.7078) (end 153.1366 48.6918) (width 1) (layer B.Cu) (net 2))
   (segment (start 153.1366 46.1518) (end 153.1366 48.6918) (width 1) (layer B.Cu) (net 2))
-  (segment (start 153.1206 48.7078) (end 153.1366 48.6918) (width 1) (layer B.Cu) (net 2))
+  (segment (start 124.36602 58.9788) (end 124.2568 58.86958) (width 1) (layer B.Cu) (net 2))
+  (segment (start 128.4224 58.9788) (end 124.36602 58.9788) (width 1) (layer B.Cu) (net 2))
+  (segment (start 140.2522 56.1594) (end 140.2522 47.0629) (width 1) (layer B.Cu) (net 3))
+  (segment (start 143.3166 55.9498) (end 140.4618 55.9498) (width 1) (layer B.Cu) (net 3))
+  (segment (start 140.4618 55.9498) (end 140.2522 56.1594) (width 1) (layer B.Cu) (net 3))
+  (segment (start 140.2522 47.0629) (end 134.7691 41.5798) (width 1) (layer B.Cu) (net 3))
+  (segment (start 134.7691 41.5798) (end 132.2291 41.5798) (width 1) (layer B.Cu) (net 3))
+  (segment (start 132.2291 41.5798) (end 130.4036 41.5798) (width 1) (layer B.Cu) (net 3))
+  (segment (start 134.7691 41.5798) (end 132.9436 41.5798) (width 1) (layer B.Cu) (net 3))
+  (segment (start 126.28499 45.44314) (end 126.0856 45.44314) (width 1) (layer B.Cu) (net 3))
+  (segment (start 128.6416 41.5798) (end 130.4036 41.5798) (width 1) (layer B.Cu) (net 3))
+  (segment (start 127.334156 42.887244) (end 128.6416 41.5798) (width 1) (layer B.Cu) (net 3))
+  (segment (start 127.334156 44.393974) (end 127.334156 42.887244) (width 1) (layer B.Cu) (net 3))
   (segment (start 127.334156 44.393974) (end 126.28499 45.44314) (width 1) (layer B.Cu) (net 3))
-  (segment (start 127.334156 44.393974) (end 127.334156 42.887244) (width 1) (layer B.Cu) (net 3))
-  (segment (start 127.334156 42.887244) (end 128.6416 41.5798) (width 1) (layer B.Cu) (net 3))
-  (segment (start 128.6416 41.5798) (end 130.4036 41.5798) (width 1) (layer B.Cu) (net 3))
-  (segment (start 126.28499 45.44314) (end 126.0856 45.44314) (width 1) (layer B.Cu) (net 3))
-  (segment (start 134.7691 41.5798) (end 132.9436 41.5798) (width 1) (layer B.Cu) (net 3))
-  (segment (start 132.2291 41.5798) (end 130.4036 41.5798) (width 1) (layer B.Cu) (net 3))
-  (segment (start 134.7691 41.5798) (end 132.2291 41.5798) (width 1) (layer B.Cu) (net 3))
-  (segment (start 140.2522 47.0629) (end 134.7691 41.5798) (width 1) (layer B.Cu) (net 3))
-  (segment (start 140.4618 55.9498) (end 140.2522 56.1594) (width 1) (layer B.Cu) (net 3))
-  (segment (start 143.3166 55.9498) (end 140.4618 55.9498) (width 1) (layer B.Cu) (net 3))
-  (segment (start 140.2522 56.1594) (end 140.2522 47.0629) (width 1) (layer B.Cu) (net 3))
-  (segment (start 143.3166 52.7998) (end 143.3166 53.9498) (width 0.5) (layer B.Cu) (net 3))
-  (segment (start 143.3166 48.2491) (end 143.3166 52.7998) (width 0.5) (layer B.Cu) (net 3))
-  (segment (start 137.668 42.6005) (end 143.3166 48.2491) (width 0.5) (layer B.Cu) (net 3))
+  (segment (start 137.668 42.6005) (end 143.3166 48.2491) (width 0.5) (layer B.Cu) (net 4))
+  (segment (start 143.3166 52.7998) (end 143.3166 53.9498) (width 0.5) (layer B.Cu) (net 4))
+  (segment (start 143.3166 48.2491) (end 143.3166 52.7998) (width 0.5) (layer B.Cu) (net 4))
+  (segment (start 137.668 41.275) (end 137.668 42.6005) (width 0.5) (layer B.Cu) (net 4))
   (segment (start 137.668 38.735) (end 137.668 41.275) (width 0.5) (layer B.Cu) (net 4))
-  (segment (start 137.668 41.275) (end 137.668 42.6005) (width 0.5) (layer B.Cu) (net 4))
+  (segment (start 142.748 41.275) (end 142.748 42.6005) (width 0.5) (layer B.Cu) (net 5))
   (segment (start 142.748 38.735) (end 142.748 41.275) (width 0.5) (layer B.Cu) (net 5))
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-  (segment (start 140.208 42.6005) (end 144.366599 46.759099) (width 0.5) (layer B.Cu) (net 5))
+  (segment (start 145.3166 45.1691) (end 145.3166 52.7998) (width 0.5) (layer B.Cu) (net 5))
   (segment (start 142.748 42.6005) (end 145.3166 45.1691) (width 0.5) (layer B.Cu) (net 5))
-  (segment (start 145.3166 45.1691) (end 145.3166 52.7998) (width 0.5) (layer B.Cu) (net 5))
+  (segment (start 145.3166 52.7998) (end 145.3166 53.9498) (width 0.5) (layer B.Cu) (net 5))
   (segment (start 147.828 38.735) (end 147.828 41.275) (width 0.5) (layer B.Cu) (net 6))
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+  (segment (start 147.828 41.275) (end 147.828 53.4384) (width 0.5) (layer B.Cu) (net 6))
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+  (segment (start 147.3166 53.9498) (end 147.3166 53.7938) (width 0.4) (layer B.Cu) (net 6))
+  (segment (start 147.3166 55.9498) (end 147.3136 55.9498) (width 0.3) (layer B.Cu) (net 7))
+  (segment (start 147.3136 55.9498) (end 146.366599 55.002799) (width 0.3) (layer B.Cu) (net 7))
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+  (segment (start 118.0846 41.3258) (end 118.0846 52.6818) (width 0.5) (layer B.Cu) (net 9))
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+  (segment (start 116.8166 57.0998) (end 116.8166 55.9498) (width 0.5) (layer B.Cu) (net 12))
+  (segment (start 117.2224 57.5056) (end 116.8166 57.0998) (width 0.5) (layer B.Cu) (net 12))
+  (segment (start 119.9388 57.5056) (end 117.2224 57.5056) (width 0.5) (layer B.Cu) (net 12))
+  (segment (start 122.504992 54.939408) (end 119.9388 57.5056) (width 0.5) (layer B.Cu) (net 12))
+  (segment (start 122.504992 45.850908) (end 122.504992 54.939408) (width 0.5) (layer B.Cu) (net 12))
+  (segment (start 125.7046 42.6513) (end 122.504992 45.850908) (width 0.5) (layer B.Cu) (net 12))
+  (segment (start 125.7046 41.3258) (end 125.7046 42.6513) (width 0.5) (layer B.Cu) (net 12))
   (zone (net 1) (net_name GND) (layer B.Cu) (tstamp 0) (hatch edge 0.508)
     (connect_pads yes (clearance 0.508))
 ,38 → 878,43
         (xy 153.8986 44.74236) (xy 152.3746 44.74236) (xy 152.132477 44.789337) (xy 151.919673 44.929127) (xy 151.777223 45.14016)
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         (xy 151.919673 47.469127) (xy 151.777223 47.68016) (xy 151.72716 47.9298) (xy 151.72716 49.4538) (xy 151.774137 49.695923)
-        (xy 151.849943 49.811324) (xy 149.008908 52.65236) (xy 148.713 52.65236) (xy 148.713 42.736395) (xy 148.895623 42.700963)
-        (xy 149.108427 42.561173) (xy 149.250877 42.35014) (xy 149.30094 42.1005) (xy 149.30094 40.4495) (xy 149.253963 40.207377)
-        (xy 149.120194 40.003739) (xy 149.250877 39.81014) (xy 149.30094 39.5605) (xy 149.30094 37.9095) (xy 149.253963 37.667377)
-        (xy 149.114173 37.454573) (xy 148.90314 37.312123) (xy 148.6535 37.26206) (xy 147.0025 37.26206) (xy 146.760377 37.309037)
-        (xy 146.556739 37.442805) (xy 146.36314 37.312123) (xy 146.1135 37.26206) (xy 144.4625 37.26206) (xy 144.220377 37.309037)
-        (xy 144.016739 37.442805) (xy 143.82314 37.312123) (xy 143.5735 37.26206) (xy 141.9225 37.26206) (xy 141.680377 37.309037)
-        (xy 141.476739 37.442805) (xy 141.28314 37.312123) (xy 141.0335 37.26206) (xy 139.3825 37.26206) (xy 139.140377 37.309037)
-        (xy 138.936739 37.442805) (xy 138.74314 37.312123) (xy 138.4935 37.26206) (xy 136.8425 37.26206) (xy 136.600377 37.309037)
-        (xy 136.387573 37.448827) (xy 136.245123 37.65986) (xy 136.19506 37.9095) (xy 136.19506 39.5605) (xy 136.242037 39.802623)
-        (xy 136.375805 40.00626) (xy 136.245123 40.19986) (xy 136.19506 40.4495) (xy 136.19506 41.400628) (xy 135.571666 40.777234)
-        (xy 135.203446 40.531197) (xy 134.7691 40.4448) (xy 134.22009 40.4448) (xy 134.166273 40.362873) (xy 133.95524 40.220423)
-        (xy 133.7056 40.17036) (xy 132.1816 40.17036) (xy 131.939477 40.217337) (xy 131.726673 40.357127) (xy 131.673877 40.435341)
-        (xy 131.626273 40.362873) (xy 131.41524 40.220423) (xy 131.1656 40.17036) (xy 129.6416 40.17036) (xy 129.399477 40.217337)
-        (xy 129.186673 40.357127) (xy 129.127492 40.4448) (xy 128.6416 40.4448) (xy 128.207254 40.531197) (xy 127.839034 40.777234)
-        (xy 127.17754 41.438728) (xy 127.17754 40.5003) (xy 127.130563 40.258177) (xy 126.996794 40.054539) (xy 127.127477 39.86094)
-        (xy 127.17754 39.6113) (xy 127.17754 37.9603) (xy 127.130563 37.718177) (xy 126.990773 37.505373) (xy 126.77974 37.362923)
-        (xy 126.5301 37.31286) (xy 124.8791 37.31286) (xy 124.636977 37.359837) (xy 124.433339 37.493605) (xy 124.23974 37.362923)
-        (xy 123.9901 37.31286) (xy 122.3391 37.31286) (xy 122.096977 37.359837) (xy 121.893339 37.493605) (xy 121.69974 37.362923)
-        (xy 121.4501 37.31286) (xy 119.7991 37.31286) (xy 119.556977 37.359837) (xy 119.353339 37.493605) (xy 119.15974 37.362923)
-        (xy 118.9101 37.31286) (xy 117.2591 37.31286) (xy 117.016977 37.359837) (xy 116.804173 37.499627) (xy 116.661723 37.71066)
-        (xy 116.61166 37.9603) (xy 116.61166 39.6113) (xy 116.658637 39.853423) (xy 116.792405 40.05706) (xy 116.661723 40.25066)
-        (xy 116.61166 40.5003) (xy 116.61166 42.1513) (xy 116.658637 42.393423) (xy 116.798427 42.606227) (xy 117.00946 42.748677)
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-        (xy 115.705927 57.054727) (xy 115.91696 57.197177) (xy 115.952381 57.20428) (xy 115.952382 57.20428) (xy 115.987789 57.382284)
-        (xy 115.998967 57.438475) (xy 116.19081 57.72559) (xy 116.596607 58.131386) (xy 116.59661 58.13139) (xy 116.596611 58.13139)
-        (xy 116.883725 58.323233) (xy 116.883726 58.323233) (xy 116.939915 58.33441) (xy 117.2224 58.390601) (xy 117.2224 58.3906)
-        (xy 117.222405 58.3906) (xy 119.938794 58.3906) (xy 119.9388 58.390601) (xy 119.9388 58.3906) (xy 120.221284 58.33441)
-        (xy 120.277474 58.323233) (xy 120.277475 58.323233) (xy 120.56459 58.13139) (xy 122.011283 56.684695) (xy 122.011287 56.684693)
-        (xy 122.011287 56.684692) (xy 123.434786 55.261192) (xy 123.434789 55.26119) (xy 123.43479 55.26119) (xy 123.626633 54.974075)
-        (xy 123.694 54.6354) (xy 123.694001 54.6354) (xy 123.694 54.635394) (xy 123.694 45.913479) (xy 124.58853 45.018949)
+        (xy 151.913927 49.908727) (xy 152.0016 49.967907) (xy 152.0016 50.189798) (xy 152.087997 50.624144) (xy 152.334034 50.992364)
+        (xy 155.681601 54.339931) (xy 155.681601 56.759669) (xy 154.526469 57.914801) (xy 151.236732 57.914801) (xy 150.4516 57.129668)
+        (xy 150.4516 57.015921) (xy 150.563977 56.84944) (xy 150.61404 56.5998) (xy 150.61404 55.2998) (xy 150.567063 55.057677)
+        (xy 150.427273 54.844873) (xy 150.21624 54.702423) (xy 149.9666 54.65236) (xy 148.6666 54.65236) (xy 148.600944 54.665098)
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+        (xy 148.65681 53.720884) (xy 148.713 53.4384) (xy 148.713001 53.4384) (xy 148.713 53.438394) (xy 148.713 42.736395)
+        (xy 148.895623 42.700963) (xy 149.108427 42.561173) (xy 149.250877 42.35014) (xy 149.30094 42.1005) (xy 149.30094 40.4495)
+        (xy 149.253963 40.207377) (xy 149.120194 40.003739) (xy 149.250877 39.81014) (xy 149.30094 39.5605) (xy 149.30094 37.9095)
+        (xy 149.253963 37.667377) (xy 149.114173 37.454573) (xy 148.90314 37.312123) (xy 148.6535 37.26206) (xy 147.0025 37.26206)
+        (xy 146.760377 37.309037) (xy 146.556739 37.442805) (xy 146.36314 37.312123) (xy 146.1135 37.26206) (xy 144.4625 37.26206)
+        (xy 144.220377 37.309037) (xy 144.016739 37.442805) (xy 143.82314 37.312123) (xy 143.5735 37.26206) (xy 141.9225 37.26206)
+        (xy 141.680377 37.309037) (xy 141.476739 37.442805) (xy 141.28314 37.312123) (xy 141.0335 37.26206) (xy 139.3825 37.26206)
+        (xy 139.140377 37.309037) (xy 138.936739 37.442805) (xy 138.74314 37.312123) (xy 138.4935 37.26206) (xy 136.8425 37.26206)
+        (xy 136.600377 37.309037) (xy 136.387573 37.448827) (xy 136.245123 37.65986) (xy 136.19506 37.9095) (xy 136.19506 39.5605)
+        (xy 136.242037 39.802623) (xy 136.375805 40.00626) (xy 136.245123 40.19986) (xy 136.19506 40.4495) (xy 136.19506 41.400628)
+        (xy 135.571666 40.777234) (xy 135.203446 40.531197) (xy 134.7691 40.4448) (xy 134.22009 40.4448) (xy 134.166273 40.362873)
+        (xy 133.95524 40.220423) (xy 133.7056 40.17036) (xy 132.1816 40.17036) (xy 131.939477 40.217337) (xy 131.726673 40.357127)
+        (xy 131.673877 40.435341) (xy 131.626273 40.362873) (xy 131.41524 40.220423) (xy 131.1656 40.17036) (xy 129.6416 40.17036)
+        (xy 129.399477 40.217337) (xy 129.186673 40.357127) (xy 129.127492 40.4448) (xy 128.6416 40.4448) (xy 128.207254 40.531197)
+        (xy 127.839034 40.777234) (xy 127.17754 41.438728) (xy 127.17754 40.5003) (xy 127.130563 40.258177) (xy 126.996794 40.054539)
+        (xy 127.127477 39.86094) (xy 127.17754 39.6113) (xy 127.17754 37.9603) (xy 127.130563 37.718177) (xy 126.990773 37.505373)
+        (xy 126.77974 37.362923) (xy 126.5301 37.31286) (xy 124.8791 37.31286) (xy 124.636977 37.359837) (xy 124.433339 37.493605)
+        (xy 124.23974 37.362923) (xy 123.9901 37.31286) (xy 122.3391 37.31286) (xy 122.096977 37.359837) (xy 121.893339 37.493605)
+        (xy 121.69974 37.362923) (xy 121.4501 37.31286) (xy 119.7991 37.31286) (xy 119.556977 37.359837) (xy 119.353339 37.493605)
+        (xy 119.15974 37.362923) (xy 118.9101 37.31286) (xy 117.2591 37.31286) (xy 117.016977 37.359837) (xy 116.804173 37.499627)
+        (xy 116.661723 37.71066) (xy 116.61166 37.9603) (xy 116.61166 39.6113) (xy 116.658637 39.853423) (xy 116.792405 40.05706)
+        (xy 116.661723 40.25066) (xy 116.61166 40.5003) (xy 116.61166 42.1513) (xy 116.658637 42.393423) (xy 116.798427 42.606227)
+        (xy 117.00946 42.748677) (xy 117.1996 42.786807) (xy 117.1996 52.31522) (xy 116.86246 52.65236) (xy 116.1666 52.65236)
+        (xy 115.924477 52.699337) (xy 115.711673 52.839127) (xy 115.569223 53.05016) (xy 115.51916 53.2998) (xy 115.51916 54.5998)
+        (xy 115.566137 54.841923) (xy 115.636984 54.949774) (xy 115.569223 55.05016) (xy 115.51916 55.2998) (xy 115.51916 56.5998)
+        (xy 115.566137 56.841923) (xy 115.705927 57.054727) (xy 115.91696 57.197177) (xy 115.952381 57.20428) (xy 115.952382 57.20428)
+        (xy 115.987789 57.382284) (xy 115.998967 57.438475) (xy 116.19081 57.72559) (xy 116.596607 58.131386) (xy 116.59661 58.13139)
+        (xy 116.596611 58.13139) (xy 116.883725 58.323233) (xy 116.883726 58.323233) (xy 116.939915 58.33441) (xy 117.2224 58.390601)
+        (xy 117.2224 58.3906) (xy 117.222405 58.3906) (xy 119.938794 58.3906) (xy 119.9388 58.390601) (xy 119.9388 58.3906)
+        (xy 120.221284 58.33441) (xy 120.277474 58.323233) (xy 120.277475 58.323233) (xy 120.56459 58.13139) (xy 123.130778 55.5652)
+        (xy 123.130782 55.565198) (xy 123.130782 55.565197) (xy 123.258967 55.373354) (xy 123.322625 55.278083) (xy 123.322626 55.278082)
+        (xy 123.389992 54.939408) (xy 123.389993 54.939408) (xy 123.389992 54.939402) (xy 123.389992 46.217487) (xy 124.58853 45.018949)
         (xy 124.58853 46.09338) (xy 124.635507 46.335503) (xy 124.775297 46.548307) (xy 124.98633 46.690757) (xy 125.23597 46.74082)
         (xy 126.93523 46.74082) (xy 127.177353 46.693843) (xy 127.390157 46.554053) (xy 127.532607 46.34302) (xy 127.58267 46.09338)
         (xy 127.58267 45.750592) (xy 128.136722 45.19654) (xy 128.382759 44.82832) (xy 128.382759 44.828319) (xy 128.469156 44.393974)
 ,21 → 923,13
         (xy 131.720927 42.796727) (xy 131.93196 42.939177) (xy 132.1816 42.98924) (xy 133.7056 42.98924) (xy 133.947723 42.942263)
         (xy 134.160527 42.802473) (xy 134.219707 42.7148) (xy 134.298968 42.7148) (xy 139.1172 47.533032) (xy 139.1172 54.238805)
         (xy 139.015917 54.258457) (xy 138.803113 54.398247) (xy 138.660663 54.60928) (xy 138.6106 54.85892) (xy 138.6106 57.35828)
-        (xy 138.657577 57.600403) (xy 138.797367 57.813207) (xy 139.0084 57.955657) (xy 139.25804 58.00572) (xy 141.20876 58.00572)
-        (xy 141.450883 57.958743) (xy 141.663687 57.818953) (xy 141.806137 57.60792) (xy 141.8562 57.35828) (xy 141.8562 57.0848)
-        (xy 142.250478 57.0848) (xy 142.41696 57.197177) (xy 142.6666 57.24724) (xy 143.9666 57.24724) (xy 144.208723 57.200263)
-        (xy 144.316574 57.129415) (xy 144.41696 57.197177) (xy 144.6666 57.24724) (xy 145.9666 57.24724) (xy 146.208723 57.200263)
-        (xy 146.316574 57.129415) (xy 146.41696 57.197177) (xy 146.6666 57.24724) (xy 147.9666 57.24724) (xy 148.208723 57.200263)
-        (xy 148.421527 57.060473) (xy 148.563977 56.84944) (xy 148.61404 56.5998) (xy 148.61404 55.2998) (xy 148.601301 55.234144)
-        (xy 148.6666 55.24724) (xy 149.9666 55.24724) (xy 150.208723 55.200263) (xy 150.421527 55.060473) (xy 150.563977 54.84944)
-        (xy 150.61404 54.5998) (xy 150.61404 54.257492) (xy 153.106601 51.76493) (xy 155.681601 54.339931) (xy 155.681601 56.759669)
-        (xy 153.632269 58.809) (xy 132.107412 58.809) (xy 131.474646 58.176234) (xy 131.106426 57.930197) (xy 130.67208 57.8438)
-        (xy 130.288546 57.8438) (xy 130.272543 57.761317) (xy 130.132753 57.548513) (xy 129.92172 57.406063) (xy 129.67208 57.356)
-        (xy 127.17272 57.356) (xy 126.930597 57.402977) (xy 126.717793 57.542767) (xy 126.575343 57.7538) (xy 126.557294 57.8438)
-        (xy 125.80467 57.8438) (xy 125.80467 57.6199) (xy 125.757693 57.377777) (xy 125.617903 57.164973) (xy 125.40687 57.022523)
-        (xy 125.15723 56.97246) (xy 123.35637 56.97246) (xy 123.114247 57.019437) (xy 122.901443 57.159227) (xy 122.758993 57.37026)
-        (xy 122.70893 57.6199) (xy 122.70893 60.11926) (xy 122.755907 60.361383) (xy 122.765902 60.3766) (xy 108.3576 60.3766)
-        (xy 108.3576 35.9708) (xy 157.2756 35.9708) (xy 157.2756 52.723666)
+        (xy 138.657577 57.600403) (xy 138.797367 57.813207) (xy 138.842689 57.8438) (xy 130.67208 57.8438) (xy 130.288546 57.8438)
+        (xy 130.272543 57.761317) (xy 130.132753 57.548513) (xy 129.92172 57.406063) (xy 129.67208 57.356) (xy 127.17272 57.356)
+        (xy 126.930597 57.402977) (xy 126.717793 57.542767) (xy 126.575343 57.7538) (xy 126.557294 57.8438) (xy 125.80467 57.8438)
+        (xy 125.80467 57.6199) (xy 125.757693 57.377777) (xy 125.617903 57.164973) (xy 125.40687 57.022523) (xy 125.15723 56.97246)
+        (xy 123.35637 56.97246) (xy 123.114247 57.019437) (xy 122.901443 57.159227) (xy 122.758993 57.37026) (xy 122.70893 57.6199)
+        (xy 122.70893 60.11926) (xy 122.755907 60.361383) (xy 122.765902 60.3766) (xy 108.3576 60.3766) (xy 108.3576 35.9708)
+        (xy 157.2756 35.9708) (xy 157.2756 52.723666)
       )
     )
   )

 /Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.kicad_pcb-bak
 ,11 → 2,11
   (general
     (links 43)
-    (no_connects 18)
-    (area 107.622599 35.235799 158.010601 61.111601)
+    (no_connects 0)
+    (area 104.4448 30.8356 164.109401 63.017401)
     (thickness 1.6)
     (drawings 18)
-    (tracks 62)
+    (tracks 76)
     (zones 0)
     (modules 22)
     (nets 13)
 ,9 → 108,9
   (net 7 /UART_TX)
   (net 8 /UART_RX)
   (net 9 /SCLK)
-  (net 10 /MOSI)
-  (net 11 /#SS)
-  (net 12 /MISO)
+  (net 10 /MISO)
+  (net 11 "Net-(J10-Pad1)")
+  (net 12 "Net-(J11-Pad3)")
   (net_class Default "Toto je výchozí třída sítě."
     (clearance 0.15)
 ,15 → 119,15
     (via_drill 0.635)
     (uvia_dia 0.508)
     (uvia_drill 0.127)
-    (add_net /#SS)
     (add_net /GPIO199)
     (add_net /GPIO200)
     (add_net /GPIO204)
     (add_net /MISO)
-    (add_net /MOSI)
     (add_net /SCLK)
     (add_net /UART_RX)
     (add_net /UART_TX)
+    (add_net "Net-(J10-Pad1)")
+    (add_net "Net-(J11-Pad3)")
   )
   (net_class Power ""
 ,39 → 142,74
     (add_net GND)
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x03 placed (layer F.Cu) (tedit 54870C46) (tstamp 54896DC4)
-    (at 153.1366 47.4218 180)
+  (module MLAB_hreb:2mm_Pin_Header_Straight_2x04 (layer F.Cu) (tedit 55007440) (tstamp 55015AF1)
+    (at 146.3166 54.9498 90)
     (descr "1 pin")
     (tags "CONN DEV")
-    (path /5485F9FC)
-    (fp_text reference J1 (at 1.524 0.127 180) (layer F.SilkS)
+    (path /5485F8D0)
+    (fp_text reference J6 (at -0.2952 -5.4228 180) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
-    (fp_text value "5V POWER" (at 0 0 180) (layer F.SilkS) hide
+    (fp_text value IOS_PORT_#1 (at 0 5.334 90) (layer F.SilkS) hide
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
-    (fp_line (start -3.81 2.54) (end 3.81 2.54) (layer F.SilkS) (width 0.254))
-    (fp_line (start 3.81 2.54) (end 3.81 -2.54) (layer F.SilkS) (width 0.254))
-    (fp_line (start 3.81 -2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
-    (fp_line (start -3.81 2.54) (end -3.81 0) (layer F.SilkS) (width 0.254))
-    (fp_line (start -3.81 -2.54) (end -3.81 0) (layer F.SilkS) (width 0.254))
-    (fp_line (start -1.27 -2.54) (end -3.81 -2.54) (layer F.SilkS) (width 0.254))
-    (pad 1 thru_hole rect (at -2.54 1.27 180) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 1 GND))
-    (pad 2 thru_hole rect (at 0 1.27 180) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 1 GND))
-    (pad 3 thru_hole rect (at 2.54 1.27 180) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
+    (fp_line (start -2 -4) (end 0 -4) (layer F.SilkS) (width 0.254))
+    (fp_line (start 0 4) (end 2 4) (layer F.SilkS) (width 0.254))
+    (fp_line (start 2 4) (end 2 -4) (layer F.SilkS) (width 0.254))
+    (fp_line (start 0 -4) (end 2 -4) (layer F.SilkS) (width 0.254))
+    (fp_line (start -2 4) (end -2 -4) (layer F.SilkS) (width 0.254))
+    (fp_line (start -2 4) (end 0 4) (layer F.SilkS) (width 0.254))
+    (pad 1 thru_hole rect (at -1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 3 +1.8V))
+    (pad 2 thru_hole rect (at 1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 4 /GPIO199))
+    (pad 3 thru_hole rect (at -1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 8 /UART_RX))
+    (pad 4 thru_hole rect (at 1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 5 /GPIO200))
+    (pad 5 thru_hole rect (at -1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 7 /UART_TX))
+    (pad 6 thru_hole rect (at 1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
+      (net 6 /GPIO204))
+    (pad 7 thru_hole rect (at -1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
       (net 2 +5V))
-    (pad 4 thru_hole rect (at 2.54 -1.27 180) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 2 +5V))
-    (pad 5 thru_hole rect (at 0 -1.27 180) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
+    (pad 8 thru_hole rect (at 1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
       (net 1 GND))
-    (pad 6 thru_hole rect (at -2.54 -1.27 180) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
+    (model Pin_Headers/Pin_Header_Straight_2x04.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 0.7874 0.7874 0.7874))
+      (rotate (xyz 0 0 90))
+    )
+  )
+  (module Capacitors_Tantalum_SMD:TantalC_SizeB_EIA-3528_Reflow (layer B.Cu) (tedit 55005C2F) (tstamp 5500FA8F)
+    (at 138.684 56.1086 180)
+    (descr "Tantal Cap. , Size B, EIA-3528, Reflow,")
+    (tags "Tantal Cap. , Size B, EIA-3528, Reflow,")
+    (path /548601CE)
+    (attr smd)
+    (fp_text reference C2 (at -0.20066 3.29946 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 10uF (at -0.09906 -3.59918 180) (layer B.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user + (at -3.59918 2.49936 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -2.99974 1.89992) (end -2.99974 -1.89992) (layer B.SilkS) (width 0.15))
+    (fp_line (start 2.49936 1.89992) (end -2.49936 1.89992) (layer B.SilkS) (width 0.15))
+    (fp_line (start 2.49682 -1.89992) (end -2.5019 -1.89992) (layer B.SilkS) (width 0.15))
+    (fp_line (start -3.60172 3.00228) (end -3.60172 1.90246) (layer B.SilkS) (width 0.15))
+    (fp_line (start -4.20116 2.5019) (end -3.00228 2.5019) (layer B.SilkS) (width 0.15))
+    (pad 2 smd rect (at 1.5494 0 180) (size 1.95072 2.49936) (layers B.Cu B.Paste B.Mask)
       (net 1 GND))
-    (model Pin_Headers/Pin_Header_Straight_2x03.wrl
+    (pad 1 smd rect (at -1.5494 0 180) (size 1.95072 2.49936) (layers B.Cu B.Paste B.Mask)
+      (net 3 +1.8V))
+    (model Capacitors_Tantalum_SMD/TantalC_SizeB_EIA-3528_Reflow.wrl
       (at (xyz 0 0 0))
       (scale (xyz 1 1 1))
-      (rotate (xyz 0 0 0))
+      (rotate (xyz 0 0 180))
     )
   )
 ,82 → 291,6
     )
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x03 placed (layer F.Cu) (tedit 54870C46) (tstamp 5489807D)
-    (at 131.6736 41.5798 90)
-    (descr "1 pin")
-    (tags "CONN DEV")
-    (path /548601AA)
-    (fp_text reference J5 (at -0.127 3.683 90) (layer F.SilkS)
-      (effects (font (size 1.27 1.27) (thickness 0.2032)))
-    )
-    (fp_text value "1,8V CPU Core" (at 0 0 90) (layer F.SilkS) hide
-      (effects (font (size 1.27 1.27) (thickness 0.2032)))
-    )
-    (fp_line (start -3.81 2.54) (end 3.81 2.54) (layer F.SilkS) (width 0.254))
-    (fp_line (start 3.81 2.54) (end 3.81 -2.54) (layer F.SilkS) (width 0.254))
-    (fp_line (start 3.81 -2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
-    (fp_line (start -3.81 2.54) (end -3.81 0) (layer F.SilkS) (width 0.254))
-    (fp_line (start -3.81 -2.54) (end -3.81 0) (layer F.SilkS) (width 0.254))
-    (fp_line (start -1.27 -2.54) (end -3.81 -2.54) (layer F.SilkS) (width 0.254))
-    (pad 1 thru_hole rect (at -2.54 1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 1 GND))
-    (pad 2 thru_hole rect (at 0 1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 1 GND))
-    (pad 3 thru_hole rect (at 2.54 1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 3 +1.8V))
-    (pad 4 thru_hole rect (at 2.54 -1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 3 +1.8V))
-    (pad 5 thru_hole rect (at 0 -1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 1 GND))
-    (pad 6 thru_hole rect (at -2.54 -1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 1 GND))
-    (model Pin_Headers/Pin_Header_Straight_2x03.wrl
-      (at (xyz 0 0 0))
-      (scale (xyz 1 1 1))
-      (rotate (xyz 0 0 0))
-    )
-  )
-  (module MLAB_hreb:2mm_Pin_Header_Straight_2x04 (layer F.Cu) (tedit 5487093A) (tstamp 54871228)
-    (at 146.3166 54.9498 90)
-    (descr "1 pin")
-    (tags "CONN DEV")
-    (path /5485F8D0)
-    (fp_text reference J6 (at -3.14 3.645 180) (layer F.SilkS)
-      (effects (font (size 1.27 1.27) (thickness 0.2032)))
-    )
-    (fp_text value IOS_PORT_#1 (at 0 5.334 90) (layer F.SilkS) hide
-      (effects (font (size 1.27 1.27) (thickness 0.2032)))
-    )
-    (fp_line (start -2 -4) (end 0 -4) (layer F.SilkS) (width 0.254))
-    (fp_line (start 0 4) (end 2 4) (layer F.SilkS) (width 0.254))
-    (fp_line (start 2 4) (end 2 -4) (layer F.SilkS) (width 0.254))
-    (fp_line (start 0 -4) (end 2 -4) (layer F.SilkS) (width 0.254))
-    (fp_line (start -2 4) (end -2 -4) (layer F.SilkS) (width 0.254))
-    (fp_line (start -2 4) (end 0 4) (layer F.SilkS) (width 0.254))
-    (pad 1 thru_hole rect (at -1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 4 /GPIO199))
-    (pad 2 thru_hole rect (at 1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 3 +1.8V))
-    (pad 3 thru_hole rect (at -1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 5 /GPIO200))
-    (pad 4 thru_hole rect (at 1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 8 /UART_RX))
-    (pad 5 thru_hole rect (at -1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 6 /GPIO204))
-    (pad 6 thru_hole rect (at 1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 7 /UART_TX))
-    (pad 7 thru_hole rect (at -1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 1 GND))
-    (pad 8 thru_hole rect (at 1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 2 +5V))
-    (model Pin_Headers/Pin_Header_Straight_2x04.wrl
-      (at (xyz 0 0 0))
-      (scale (xyz 0.7874 0.7874 0.7874))
-      (rotate (xyz 0 0 90))
-    )
-  )
   (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54896E72)
     (at 140.208 40.005)
     (descr "1 pin")
 ,12 → 343,12
     )
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54874ADA)
+  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 55007496) (tstamp 54874ADA)
     (at 118.0846 40.0558)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /5486082B)
-    (fp_text reference J9 (at 0 -3.81) (layer F.SilkS)
+    (fp_text reference J9 (at -1.2192 -3.6322) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value SCLK (at 0 0) (layer F.SilkS) hide
 ,12 → 369,12
     )
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871250)
+  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 550074A7) (tstamp 54871250)
     (at 120.6246 40.0558)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /54860825)
-    (fp_text reference J10 (at 0 -3.81) (layer F.SilkS)
+    (fp_text reference J10 (at -1.1176 -3.6576) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value MOSI (at 0 0) (layer F.SilkS) hide
 ,9 → 385,9
     (fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
     (fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
     (pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 10 /MOSI))
+      (net 11 "Net-(J10-Pad1)"))
     (pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 10 /MOSI))
+      (net 11 "Net-(J10-Pad1)"))
     (model Pin_Headers/Pin_Header_Straight_2x01.wrl
       (at (xyz 0 0 0))
       (scale (xyz 1 1 1))
 ,12 → 395,12
     )
   )
-  (module MLAB_hreb:2mm_Pin_Header_Straight_2x02 (layer F.Cu) (tedit 54870948) (tstamp 5487125E)
+  (module MLAB_hreb:2mm_Pin_Header_Straight_2x02 (layer F.Cu) (tedit 550074DF) (tstamp 5487125E)
     (at 117.8166 54.9498)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /5485F97F)
-    (fp_text reference J11 (at -0.127 -2.921) (layer F.SilkS)
+    (fp_text reference J11 (at 4.2558 0.0412) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value IO_PORT_#2 (at 0 3.302) (layer F.SilkS) hide
 ,11 → 415,11
     (pad 1 thru_hole rect (at -1 -1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
       (net 9 /SCLK))
     (pad 2 thru_hole rect (at 1 -1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 11 /#SS))
+      (net 11 "Net-(J10-Pad1)"))
     (pad 3 thru_hole rect (at -1 1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 10 /MOSI))
+      (net 12 "Net-(J11-Pad3)"))
     (pad 4 thru_hole rect (at 1 1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
-      (net 12 /MISO))
+      (net 10 /MISO))
     (model Pin_Headers/Pin_Header_Straight_2x02.wrl
       (at (xyz 0 0 0))
       (scale (xyz 0.7874 0.7874 0.7874))
 ,12 → 427,12
     )
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871268)
+  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 550074AC) (tstamp 54871268)
     (at 125.7046 40.0558)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /54860610)
-    (fp_text reference J12 (at 0 -3.81) (layer F.SilkS)
+    (fp_text reference J12 (at 0.381 -3.5052) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value "#SS" (at 0 0) (layer F.SilkS) hide
 ,9 → 443,9
     (fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
     (fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
     (pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 11 /#SS))
+      (net 12 "Net-(J11-Pad3)"))
     (pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 11 /#SS))
+      (net 12 "Net-(J11-Pad3)"))
     (model Pin_Headers/Pin_Header_Straight_2x01.wrl
       (at (xyz 0 0 0))
       (scale (xyz 1 1 1))
 ,12 → 453,12
     )
   )
-  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871272)
+  (module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 550074AA) (tstamp 54871272)
     (at 123.1646 40.0558)
     (descr "1 pin")
     (tags "CONN DEV")
     (path /54860710)
-    (fp_text reference J13 (at 0 -3.81) (layer F.SilkS)
+    (fp_text reference J13 (at -0.4318 -3.5052) (layer F.SilkS)
       (effects (font (size 1.27 1.27) (thickness 0.2032)))
     )
     (fp_text value MISO (at 0 0) (layer F.SilkS) hide
 ,9 → 469,9
     (fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
     (fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
     (pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 12 /MISO))
+      (net 10 /MISO))
     (pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
-      (net 12 /MISO))
+      (net 10 /MISO))
     (model Pin_Headers/Pin_Header_Straight_2x01.wrl
       (at (xyz 0 0 0))
       (scale (xyz 1 1 1))
 ,12 → 479,12
     )
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 54345FDC) (tstamp 54871277)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 55007470) (tstamp 54871277)
     (at 153.1366 40.1098)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862BF8)
-    (fp_text reference J14 (at 0 0) (layer F.SilkS)
+    (fp_text reference J14 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,12 → 495,12
       (net 1 GND) (clearance 1) (zone_connect 2))
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 54345FDC) (tstamp 5487127C)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 5500745C) (tstamp 5487127C)
     (at 112.4966 40.1098)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862A8F)
-    (fp_text reference J15 (at 0 0) (layer F.SilkS)
+    (fp_text reference J15 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,12 → 511,12
       (net 1 GND) (clearance 1) (zone_connect 2))
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 5489719A) (tstamp 54871281)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 55007468) (tstamp 54871281)
     (at 153.3166 55.5498)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862E35)
-    (fp_text reference J16 (at 0 0) (layer F.SilkS)
+    (fp_text reference J16 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,12 → 527,12
       (net 1 GND) (clearance 1) (zone_connect 2))
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 5489848E) (tstamp 54871286)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 55007453) (tstamp 54871286)
     (at 112.3166 55.5498)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862E8B)
-    (fp_text reference J17 (at 0 0) (layer F.SilkS)
+    (fp_text reference J17 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,12 → 543,12
       (net 1 GND) (clearance 1) (zone_connect 2))
   )
-  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 54345FDC) (tstamp 5487128B)
+  (module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 5500748A) (tstamp 5487128B)
     (at 132.8166 50.2698)
     (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
     (path /54862E2F)
-    (fp_text reference J18 (at 0 0) (layer F.SilkS)
+    (fp_text reference J18 (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.15)))
     )
     (fp_text value M3 (at 1 5) (layer F.SilkS) hide
 ,8 → 597,8
     )
   )
-  (module Diodes_SMD:Diode-MiniMELF_Standard (layer B.Cu) (tedit 55005B0E) (tstamp 5500F146)
-    (at 128.1176 42.9768 90)
+  (module Diodes_SMD:Diode-MiniMELF_Standard (layer B.Cu) (tedit 55005B0E) (tstamp 55015ACE)
+    (at 126.0856 47.1932 90)
     (descr "Diode Mini-MELF Standard")
     (tags "Diode Mini-MELF Standard")
     (path /548601BC)
 ,43 → 663,89
     )
   )
-  (module Capacitors_Tantalum_SMD:TantalC_SizeB_EIA-3528_Reflow (layer B.Cu) (tedit 55005C2F) (tstamp 5500FA8F)
-    (at 138.684 56.1086 180)
-    (descr "Tantal Cap. , Size B, EIA-3528, Reflow,")
-    (tags "Tantal Cap. , Size B, EIA-3528, Reflow,")
-    (path /548601CE)
-    (attr smd)
-    (fp_text reference C2 (at -0.20066 3.29946 180) (layer B.SilkS)
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+  (module Mlab_Pin_Headers:Straight_2x03 (layer F.Cu) (tedit 550060BF) (tstamp 55015A75)
+    (at 153.1366 47.4218 270)
+    (descr "pin header straight 2x03")
+    (tags "pin header straight 2x03")
+    (path /5485F9FC)
+    (fp_text reference J1 (at 0 -5.08 270) (layer F.SilkS) hide
+      (effects (font (size 1.5 1.5) (thickness 0.15)))
     )
-    (fp_text value 10uF (at -0.09906 -3.59918 180) (layer B.SilkS) hide
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    (fp_text value "5V POWER" (at 0 5.08 270) (layer F.SilkS) hide
+      (effects (font (size 1.5 1.5) (thickness 0.15)))
     )
-    (fp_text user + (at -3.59918 2.49936 180) (layer B.SilkS)
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    (fp_text user 1 (at -2.921 -2.54 270) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.05)))
     )
-    (fp_line (start -2.99974 1.89992) (end -2.99974 -1.89992) (layer B.SilkS) (width 0.15))
-    (fp_line (start 2.49936 1.89992) (end -2.49936 1.89992) (layer B.SilkS) (width 0.15))
-    (fp_line (start 2.49682 -1.89992) (end -2.5019 -1.89992) (layer B.SilkS) (width 0.15))
-    (fp_line (start -3.60172 3.00228) (end -3.60172 1.90246) (layer B.SilkS) (width 0.15))
-    (fp_line (start -4.20116 2.5019) (end -3.00228 2.5019) (layer B.SilkS) (width 0.15))
-    (pad 2 smd rect (at 1.5494 0 180) (size 1.95072 2.49936) (layers B.Cu B.Paste B.Mask)
+    (fp_line (start -2.54 -3.81) (end 2.54 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.54 -3.81) (end 2.54 3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.54 3.81) (end -2.54 3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.54 3.81) (end -2.54 -3.81) (layer F.SilkS) (width 0.15))
+    (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
       (net 1 GND))
-    (pad 1 smd rect (at -1.5494 0 180) (size 1.95072 2.49936) (layers B.Cu B.Paste B.Mask)
+    (pad 2 thru_hole rect (at 1.27 -2.54 270) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 1 GND))
+    (pad 3 thru_hole rect (at -1.27 0 270) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 2 +5V))
+    (pad 4 thru_hole rect (at 1.27 0 270) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 2 +5V))
+    (pad 5 thru_hole rect (at -1.27 2.54 270) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 1 GND))
+    (pad 6 thru_hole rect (at 1.27 2.54 270) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 1 GND))
+    (model Pin_Headers/Pin_Header_Straight_2x03.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 90))
+    )
+  )
+  (module Mlab_Pin_Headers:Straight_2x03 (layer F.Cu) (tedit 550060C5) (tstamp 55015A83)
+    (at 131.6736 41.5798 180)
+    (descr "pin header straight 2x03")
+    (tags "pin header straight 2x03")
+    (path /548601AA)
+    (fp_text reference J5 (at 0 -5.08 180) (layer F.SilkS) hide
+      (effects (font (size 1.5 1.5) (thickness 0.15)))
+    )
+    (fp_text value "1,8V CPU Core" (at 0 5.08 180) (layer F.SilkS) hide
+      (effects (font (size 1.5 1.5) (thickness 0.15)))
+    )
+    (fp_text user 1 (at -2.921 -2.54 180) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.05)))
+    )
+    (fp_line (start -2.54 -3.81) (end 2.54 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.54 -3.81) (end 2.54 3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.54 3.81) (end -2.54 3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.54 3.81) (end -2.54 -3.81) (layer F.SilkS) (width 0.15))
+    (pad 1 thru_hole rect (at -1.27 -2.54 180) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 1 GND))
+    (pad 2 thru_hole rect (at 1.27 -2.54 180) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 1 GND))
+    (pad 3 thru_hole rect (at -1.27 0 180) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
       (net 3 +1.8V))
-    (model Capacitors_Tantalum_SMD/TantalC_SizeB_EIA-3528_Reflow.wrl
+    (pad 4 thru_hole rect (at 1.27 0 180) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 3 +1.8V))
+    (pad 5 thru_hole rect (at -1.27 2.54 180) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 1 GND))
+    (pad 6 thru_hole rect (at 1.27 2.54 180) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask F.SilkS)
+      (net 1 GND))
+    (model Pin_Headers/Pin_Header_Straight_2x03.wrl
       (at (xyz 0 0 0))
       (scale (xyz 1 1 1))
-      (rotate (xyz 0 0 180))
+      (rotate (xyz 0 0 90))
     )
   )
-  (gr_text "ODROID-U3 MLAB ADAPTER" (at 132.3086 58.8518) (layer F.SilkS)
+  (gr_text GPIO200 (at 142.8496 47.6758 90) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
-  (gr_text MLAB (at 112.6236 47.8028 90) (layer F.SilkS)
+  (gr_text "ODROID-U3 MLAB BREAKOUT BOARD" (at 132.3086 59.436) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
+  (gr_text "MLAB\n2015" (at 112.4712 47.8028) (layer F.SilkS)
+    (effects (font (size 1.5 1.5) (thickness 0.3)))
+  )
   (gr_text +5V (at 152.6286 51.4858) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
 ,9 → 758,6
   (gr_text TX (at 145.3896 44.3738 90) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
-  (gr_text GPIO200 (at 142.8496 47.6758 90) (layer F.SilkS)
-    (effects (font (size 1.5 1.5) (thickness 0.3)))
-  )
   (gr_text RX (at 140.3096 44.5008 90) (layer F.SilkS)
     (effects (font (size 1.5 1.5) (thickness 0.3)))
   )
 ,68 → 784,82
   (gr_line (start 107.6726 61.0616) (end 157.9606 61.0616) (angle 90) (layer Edge.Cuts) (width 0.1))
   (gr_line (start 107.6726 35.2858) (end 107.6726 61.0616) (angle 90) (layer Edge.Cuts) (width 0.1))
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/Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.pro
1,4 → 1,4
update=St 11. březen 2015, 16:54:46 CET
update=St 11. březen 2015, 18:08:04 CET
version=1
last_client=kicad
[cvpcb]

 /Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.sch
 ,7 → 31,6
 LIBS:valves
 LIBS:header
 LIBS:konektory
-LIBS:Jumpers
 LIBS:U3_MLAB_ADAPTER-cache
 EELAYER 25 0
 EELAYER END
 ,7 → 51,7
 U 1 1 5485F8D0
 P 3600 3400
 F 0 "J6" H 3600 3150 60  0000 C CNN
-F 1 "IOS_PORT_#1" H 3600 3650 60  0000 C CNN
+F 1 "IOS_PORT_#1" H 3780 3750 60  0000 C CNN
 F 2 "MLAB_hreb:2mm_Pin_Header_Straight_2x04" H 3600 3550 60  0001 C CNN
 F 3 "" H 3600 3550 60  0000 C CNN
 3600 3400
 ,13 → 263,13
 $Comp
 L HEADER_2x01_PARALLEL J12
 U 1 1 54860610
-P 8350 3100
-F 0 "J12" H 8350 3200 60  0000 C CNN
-F 1 "#SS" H 8600 3100 60  0000 C CNN
-F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 8350 3100 60  0001 C CNN
-F 3 "" H 8350 3100 60  0000 C CNN
-8350 3100
-0    0    -1
+P 6650 3510
+F 0 "J12" H 6650 3610 60  0000 C CNN
+F 1 "#SS" H 6900 3510 60  0000 C CNN
+F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 6650 3510 60  0001 C CNN
+F 3 "" H 6650 3510 60  0000 C CNN
+6650 3510
+        -1   0    0    1
 $EndComp
 $Comp
 L HEADER_2x01_PARALLEL J13
 ,13 → 285,13
 $Comp
 L HEADER_2x01_PARALLEL J10
 U 1 1 54860825
-P 6650 3500
-F 0 "J10" H 6650 3400 60  0000 C CNN
-F 1 "MOSI" H 6900 3500 60  0000 C CNN
-F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 6650 3500 60  0001 C CNN
-F 3 "" H 6650 3500 60  0000 C CNN
-6650 3500
-        -1   0    0    1
+P 8500 3090
+F 0 "J10" H 8500 2990 60  0000 C CNN
+F 1 "MOSI" H 8750 3090 60  0000 C CNN
+F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 8500 3090 60  0001 C CNN
+F 3 "" H 8500 3090 60  0000 C CNN
+8500 3090
+0    0    1
 $EndComp
 $Comp
 L HEADER_2x01_PARALLEL J9
 ,10 → 313,6
 Wire Wire Line
 3250 8000 3250
 Wire Wire Line
-3250 8000 3100
-Wire Wire Line
-3100 8100 3100
-Wire Wire Line
 3250 7150 3250
 Wire Wire Line
 3250 7150 3150
 ,141 → 319,119
 Wire Wire Line
 3150 6900 3150
 Wire Wire Line
-3500 7150 3500
+3090 8000 3090
 Wire Wire Line
-3500 7150 3350
-Wire Wire Line
 3350 7300 3350
 $Comp
 L +5V #PWR09
 U 1 1 54860E24
-P 4100 2950
-F 0 "#PWR09" H 4100 3040 20  0001 C CNN
-F 1 "+5V" H 4100 3040 30  0000 C CNN
-F 2 "" H 4100 2950 60  0000 C CNN
-F 3 "" H 4100 2950 60  0000 C CNN
-4100 2950
-0    0    -1
+P 3280 3550
+F 0 "#PWR09" H 3280 3640 20  0001 C CNN
+F 1 "+5V" V 3210 3610 30  0000 C CNN
+F 2 "" H 3280 3550 60  0000 C CNN
+F 3 "" H 3280 3550 60  0000 C CNN
+3280 3550
+-1   -1   0
 $EndComp
-Wire Wire Line
-2950 4100 3550
-Wire Wire Line
-3550 3850 3550
 $Comp
 L +1.8V #PWR010
 U 1 1 54860E81
-P 3950 2950
-F 0 "#PWR010" H 3950 3090 20  0001 C CNN
-F 1 "+1.8V" H 3950 3060 30  0000 C CNN
-F 2 "" H 3950 2950 60  0000 C CNN
-F 3 "" H 3950 2950 60  0000 C CNN
-3950 2950
+P 3240 3060
+F 0 "#PWR010" H 3240 3200 20  0001 C CNN
+F 1 "+1.8V" H 3240 3170 30  0000 C CNN
+F 2 "" H 3240 3060 60  0000 C CNN
+F 3 "" H 3240 3060 60  0000 C CNN
+3240 3060
 0    0    -1
 $EndComp
-Wire Wire Line
-3250 3950 3250
-Wire Wire Line
-3250 3950 2950
 $Comp
 L HEADER_2x01_PARALLEL J2
 U 1 1 5486108C
-P 2550 3100
-F 0 "J2" H 2550 3000 60  0000 C CNN
-F 1 "GPIO199" H 2900 3100 60  0000 C CNN
-F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 2550 3100 60  0001 C CNN
-F 3 "" H 2550 3100 60  0000 C CNN
-2550 3100
-        -1   0    0    1
+P 4650 3100
+F 0 "J2" H 4650 3000 60  0000 C CNN
+F 1 "GPIO199" H 5000 3100 60  0000 C CNN
+F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 4650 3100 60  0001 C CNN
+F 3 "" H 4650 3100 60  0000 C CNN
+4650 3100
+0    0    1
 $EndComp
 $Comp
 L HEADER_2x01_PARALLEL J3
 U 1 1 54861113
-P 2550 3300
-F 0 "J3" H 2550 3200 60  0000 C CNN
-F 1 "GPIO200" H 2900 3300 60  0000 C CNN
-F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 2550 3300 60  0001 C CNN
-F 3 "" H 2550 3300 60  0000 C CNN
-2550 3300
-        -1   0    0    1
+P 4650 3290
+F 0 "J3" H 4650 3190 60  0000 C CNN
+F 1 "GPIO200" H 5000 3290 60  0000 C CNN
+F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 4650 3290 60  0001 C CNN
+F 3 "" H 4650 3290 60  0000 C CNN
+4650 3290
+0    0    1
 $EndComp
 $Comp
 L HEADER_2x01_PARALLEL J4
 U 1 1 54861163
-P 2550 3500
-F 0 "J4" H 2550 3400 60  0000 C CNN
-F 1 "GPIO204" H 2900 3500 60  0000 C CNN
-F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 2550 3500 60  0001 C CNN
-F 3 "" H 2550 3500 60  0000 C CNN
-2550 3500
-        -1   0    0    1
+P 4650 3500
+F 0 "J4" H 4650 3400 60  0000 C CNN
+F 1 "GPIO204" H 5000 3500 60  0000 C CNN
+F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 4650 3500 60  0001 C CNN
+F 3 "" H 4650 3500 60  0000 C CNN
+4650 3500
+0    0    1
 $EndComp
 $Comp
 L HEADER_2x01_PARALLEL J8
 U 1 1 5486130F
-P 4950 3500
-F 0 "J8" H 4950 3600 60  0000 C CNN
-F 1 "UART_TX" H 5300 3500 60  0000 C CNN
-F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 4950 3500 60  0001 C CNN
-F 3 "" H 4950 3500 60  0000 C CNN
-4950 3500
-0    0    -1
+P 2750 3500
+F 0 "J8" H 2750 3600 60  0000 C CNN
+F 1 "UART_TX" H 3100 3500 60  0000 C CNN
+F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 2750 3500 60  0001 C CNN
+F 3 "" H 2750 3500 60  0000 C CNN
+2750 3500
+        -1   0    0    -1
 $EndComp
 $Comp
 L HEADER_2x01_PARALLEL J7
 U 1 1 54861315
-P 4950 3300
-F 0 "J7" H 4950 3400 60  0000 C CNN
-F 1 "UART_RX" H 5300 3300 60  0000 C CNN
-F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 4950 3300 60  0001 C CNN
-F 3 "" H 4950 3300 60  0000 C CNN
-4950 3300
-0    0    -1
+P 2750 3350
+F 0 "J7" H 2750 3450 60  0000 C CNN
+F 1 "UART_RX" H 3100 3350 60  0000 C CNN
+F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 2750 3350 60  0001 C CNN
+F 3 "" H 2750 3350 60  0000 C CNN
+2750 3350
+        -1   0    0    -1
 $EndComp
 Wire Wire Line
-3450 4350 3450
+3100 4250 3100
 Wire Wire Line
-3100 2950 3100
+3100 4250 3250
 Wire Wire Line
-3100 2950 3250
+3250 3850 3250
 Wire Wire Line
-3250 3350 3250
+3500 4300 3500
 Wire Wire Line
-3350 2900 3350
+3500 4300 3450
 Wire Wire Line
-3350 2900 3300
+3450 3850 3450
 Wire Wire Line
-3300 2800 3300
+3450 3350 3500
 Wire Wire Line
-3500 2900 3500
+3500 3000 3500
 Wire Wire Line
-3500 2900 3450
+3350 3350 3350
 Wire Wire Line
-3450 3350 3450
+3290 4350 3350
 Wire Wire Line
-3450 4350 3500
-Wire Wire Line
-3500 4700 3500
-Wire Wire Line
-3300 4350 3300
-Wire Wire Line
-3300 4350 3350
-Wire Wire Line
 3350 3850 3350
 $Comp
 L GND #PWR011
 U 1 1 54861F1A
-P 3250 3650
-F 0 "#PWR011" H 3250 3650 30  0001 C CNN
-F 1 "GND" H 3250 3580 30  0001 C CNN
-F 2 "" H 3250 3650 60  0000 C CNN
-F 3 "" H 3250 3650 60  0000 C CNN
-3250 3650
+P 3910 3600
+F 0 "#PWR011" H 3910 3600 30  0001 C CNN
+F 1 "GND" H 3910 3530 30  0001 C CNN
+F 2 "" H 3910 3600 60  0000 C CNN
+F 3 "" H 3910 3600 60  0000 C CNN
+3910 3600
 0    0    -1
 $EndComp
-Wire Wire Line
-3550 3250 3650
-Wire Wire Line
-3550 3250 3550
 $Comp
 L CONN1_1 J15
 U 1 1 54862A8F
 ,20 → 526,38
 4500 8100 5250
 Text Label 6900 3150 0    60   ~ 0
 SCLK
-Text Label 6900 3500 0    60   ~ 0
-MOSI
-Text Label 7800 3250 0    60   ~ 0
+Text Label 6940 3470 0    60   ~ 0
 #SS
 Text Label 7800 3350 0    60   ~ 0
 MISO
-Text Label 4350 3300 0    60   ~ 0
+Text Label 3350 3350 2    60   ~ 0
 UART_RX
-Text Label 4350 3500 0    60   ~ 0
+Text Label 3350 3500 2    60   ~ 0
 UART_TX
-Text Label 2950 3250 0    60   ~ 0
+Text Label 4250 3250 2    60   ~ 0
 GPIO199
-Text Label 2950 3350 0    60   ~ 0
+Text Label 4250 3350 2    60   ~ 0
 GPIO200
-Text Label 2950 3450 0    60   ~ 0
+Text Label 4250 3450 2    60   ~ 0
 GPIO204
+Text Label 8200 3080 2    60   ~ 0
+MOSI
+Wire Wire Line
+3350 7150 3510
+Wire Wire Line
+3510 6900 3510
+Wire Wire Line
+3090 8000 3250
+Wire Wire Line
+3550 3910 3550
+Wire Wire Line
+3550 3910 3600
+Wire Wire Line
+3290 4350 3290
+Wire Wire Line
+3550 3280 3550
+Wire Wire Line
+3250 3240 3250
+Wire Wire Line
+3250 3240 3060
 $EndSCHEMATC

Subversion Repositories – MLAB

/Modules/ARM/ODROID-U3/SCH_PCB/ @ 3951 → /Modules/ARM/ODROID-U3/SCH_PCB/ @ 3952

Compare Path:	Rev
With Path:	Rev