Problem with comparison.
/Modules/ARM/STM32F10xRxT/SW/LED_blink/LED_Blink_Main.c |
---|
0,0 → 1,129 |
#include "stm32f10x_it.h" |
GPIO_InitTypeDef GPIO_InitStructure; |
ErrorStatus HSEStartUpStatus; |
void RCC_Configuration(void); |
void Delay(vu32 nCount); |
void SystemInit() |
{ |
/* Configure the system clocks */ |
RCC_Configuration(); |
/* NVIC Configuration */ |
// NVIC_Configuration(); |
/* Enable GPIOC clock */ |
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); |
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); |
/* Configure PC.4 as Output push-pull */ |
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5; |
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz; |
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; |
GPIO_Init(GPIOC, &GPIO_InitStructure); |
/* Configure PC.4 as Output push-pull */ |
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8; |
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz; |
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; |
GPIO_Init(GPIOB, &GPIO_InitStructure); |
} |
int main(void) |
{ |
while (1) |
{ |
GPIO_SetBits(GPIOC, GPIO_Pin_5); |
GPIO_ResetBits(GPIOC, GPIO_Pin_4); |
GPIO_SetBits(GPIOB, GPIO_Pin_7); |
GPIO_ResetBits(GPIOB, GPIO_Pin_8); |
Delay(0x4fFFFF); |
GPIO_SetBits(GPIOC, GPIO_Pin_4); |
GPIO_ResetBits(GPIOC, GPIO_Pin_5); |
GPIO_SetBits(GPIOB, GPIO_Pin_8); |
GPIO_ResetBits(GPIOB, GPIO_Pin_7); |
Delay(0x4fFFFF); |
} |
} |
/******************************************************************************* |
* Function Name : RCC_Configuration |
* Description : Configures the different system clocks. |
* Input : None |
* Output : None |
* Return : None |
*******************************************************************************/ |
void RCC_Configuration(void) |
{ |
/* RCC system reset(for debug purpose) */ |
RCC_DeInit(); |
/* Enable HSE */ |
RCC_HSEConfig(RCC_HSE_ON); |
/* Wait till HSE is ready */ |
HSEStartUpStatus = RCC_WaitForHSEStartUp(); |
if(HSEStartUpStatus == SUCCESS) |
{ |
/* Enable Prefetch Buffer */ |
// FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); |
/* Flash 2 wait state */ |
// FLASH_SetLatency(FLASH_Latency_2); |
/* HCLK = SYSCLK */ |
RCC_HCLKConfig(RCC_SYSCLK_Div1); |
/* PCLK2 = HCLK */ |
RCC_PCLK2Config(RCC_HCLK_Div1); |
/* PCLK1 = HCLK/2 */ |
RCC_PCLK1Config(RCC_HCLK_Div2); |
/* PLLCLK = 8MHz * 4 = 32 MHz */ |
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_2); |
/* Enable PLL */ |
RCC_PLLCmd(ENABLE); |
/* Wait till PLL is ready */ |
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) |
{ |
} |
/* Select PLL as system clock source */ |
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); |
/* Wait till PLL is used as system clock source */ |
while(RCC_GetSYSCLKSource() != 0x08) |
{ |
} |
} |
} |
/******************************************************************************* |
* Function Name : Delay |
* Description : Inserts a delay time. |
* Input : nCount: specifies the delay time length. |
* Output : None |
* Return : None |
*******************************************************************************/ |
void Delay(vu32 nCount) |
{ |
for(; nCount != 0; nCount--); |
} |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/LED_Blink.cbp |
---|
0,0 → 1,96 |
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> |
<CodeBlocks_project_file> |
<FileVersion major="1" minor="6" /> |
<Project> |
<Option title="LED_Blink" /> |
<Option makefile="makefile" /> |
<Option pch_mode="2" /> |
<Option compiler="arm_codesourcery" /> |
<Build> |
<Target title="Release"> |
<Option output="bin\LED_Blink.elf" prefix_auto="0" extension_auto="0" /> |
<Option working_dir="" /> |
<Option object_output="obj\" /> |
<Option type="5" /> |
<Option compiler="arm_codesourcery" /> |
<Compiler> |
<Add option="-O2" /> |
<Add option="-Wall" /> |
</Compiler> |
<Linker> |
<Add option="-s" /> |
</Linker> |
</Target> |
<Target title="Debug"> |
<Option output="bin\LED_Blink.elf" prefix_auto="0" extension_auto="0" /> |
<Option working_dir="" /> |
<Option object_output="obj\" /> |
<Option type="5" /> |
<Option compiler="arm_codesourcery" /> |
<Compiler> |
<Add option="-Wall" /> |
<Add option="-g" /> |
</Compiler> |
</Target> |
<Environment> |
<Variable name="VSPROG_DEV" value="stm32_md" /> |
<Variable name="ARMDEVICE" value="STM32_Med-density_128K" /> |
<Variable name="DEST_ADDR" value="0x08000000" /> |
</Environment> |
</Build> |
<Compiler> |
<Add option="-O2" /> |
<Add option="-Wall" /> |
<Add option="-mcpu=cortex-m3 -mthumb -g" /> |
<Add option="-DSTM32F10X_MD" /> |
<Add option="-DUSE_STDPERIPH_DRIVER" /> |
<Add option="-DUSE_STM32_DISCOVERY" /> |
<Add directory="." /> |
<Add directory=".\lib" /> |
</Compiler> |
<Linker> |
<Add option="-mcpu=cortex-m3 -mthumb" /> |
<Add option="-T stm32_128K_20K.ld" /> |
<Add option="-Wl,--gc-sections,-Map=$(TARGET_OBJECT_DIR)$(TARGET_OUTPUT_BASENAME).map,-cref,-u,Reset_Handler" /> |
<Add directory="." /> |
<Add directory=".\lib" /> |
</Linker> |
<ExtraCommands> |
<Add after="arm-none-eabi-objcopy -O ihex $(TARGET_OUTPUT_FILE) $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME).hex" /> |
<Add after="arm-none-eabi-objcopy -O binary $(TARGET_OUTPUT_FILE) $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME).bin" /> |
<Add after="arm-none-eabi-objdump -h -w $(TARGET_OUTPUT_FILE)" /> |
<Add after='cmd /c arm-none-eabi-objdump -h -S $(TARGET_OUTPUT_FILE) > $(TARGET_OUTPUT_FILE).lss"' /> |
<Mode after="always" /> |
</ExtraCommands> |
<Unit filename="LED_Blink_Main.c"> |
<Option compilerVar="CC" /> |
</Unit> |
<Unit filename="lib\stm32f10x_gpio.c"> |
<Option compilerVar="CC" /> |
</Unit> |
<Unit filename="lib\stm32f10x_rcc.c"> |
<Option compilerVar="CC" /> |
</Unit> |
<Unit filename="startup_stm32f10x_md.s" /> |
<Unit filename="stm32f10x_conf.h" /> |
<Unit filename="stm32f10x_it.c"> |
<Option compilerVar="CC" /> |
</Unit> |
<Extensions> |
<code_completion /> |
<envvars /> |
<debugger> |
<remote_debugging> |
<options conn_type="0" serial_baud="115200" ip_address="127.0.0.1" ip_port="3333" /> |
</remote_debugging> |
<remote_debugging target="Release"> |
<options conn_type="0" serial_baud="115200" ip_address="127.0.0.1" ip_port="3333" /> |
</remote_debugging> |
<remote_debugging target="Debug"> |
<options conn_type="0" serial_baud="115200" ip_address="127.0.0.1" ip_port="3333" /> |
</remote_debugging> |
</debugger> |
<lib_finder disable_auto="1" /> |
</Extensions> |
</Project> |
</CodeBlocks_project_file> |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/definitions.h |
---|
0,0 → 1,43 |
// |
// definitions.h - Include file for general definitions |
// |
#ifndef _DEFINITIONS_H_ |
#define _DEFINITIONS_H_ |
#include "common.h" |
#include <STM32F_Common.h> |
extern vu32 g_nFlags; |
#define g_flgTimerReady (*((vu32*)BITBAND_SRAM(&g_nFlags, 0))) |
//********************************************************** |
//Definitions for STM32F_Common module - clock subsystem |
#define RCC_USE_HCE |
#define SET_FLASH_Latency (FLASH_Latency_2 | FLASH_PrefetchBuffer_Enable) |
#define CLK_Config |
#define AHB_CLK_Div RCC_SYSCLK_Div1 |
#define APB1_CLK_Div RCC_HCLK_Div2 |
#define APB2_CLK_Div RCC_HCLK_Div1 |
#define RCC_USE_PLL |
#define RCC_PLL_MUL RCC_PLLMul_9 |
#define RCC_PLL_DIV RCC_PLLSource_HSE_Div1 |
//********************************************************** |
//Definitions for Timer module |
#define SYSTEM_CLOCK 72000000 |
#define SYS_CLOCK_DIV8 |
// 0x15F90 = 90000 = 72000000 / 8 / 100 ~ 10 msec |
// 0x0EA60 = 60000 = 48000000 / 8 / 100 ~ 10 msec |
// 0x07530 = 30000 = 24000000 / 8 / 100 ~ 10 msec |
// 0x02710 = 10000 = 08000000 / 8 / 100 ~ 10 msec |
#define CounterPreset 0x15F90 |
#define NumOfTimers 8 |
//#define _USE_DELAY_US_ |
#endif |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/core_cm3.c |
---|
0,0 → 1,784 |
/**************************************************************************//** |
* @file core_cm3.c |
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File |
* @version V1.30 |
* @date 30. October 2009 |
* |
* @note |
* Copyright (C) 2009 ARM Limited. All rights reserved. |
* |
* @par |
* ARM Limited (ARM) is supplying this software for use with Cortex-M |
* processor based microcontrollers. This file can be freely distributed |
* within development tools that are supporting such ARM based processors. |
* |
* @par |
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
* |
******************************************************************************/ |
#include <stdint.h> |
/* define compiler specific symbols */ |
#if defined ( __CC_ARM ) |
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
#elif defined ( __ICCARM__ ) |
#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
#elif defined ( __GNUC__ ) |
#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
#elif defined ( __TASKING__ ) |
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
#endif |
/* ################### Compiler specific Intrinsics ########################### */ |
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
/* ARM armcc specific functions */ |
/** |
* @brief Return the Process Stack Pointer |
* |
* @return ProcessStackPointer |
* |
* Return the actual process stack pointer |
*/ |
__ASM uint32_t __get_PSP(void) |
{ |
mrs r0, psp |
bx lr |
} |
/** |
* @brief Set the Process Stack Pointer |
* |
* @param topOfProcStack Process Stack Pointer |
* |
* Assign the value ProcessStackPointer to the MSP |
* (process stack pointer) Cortex processor register |
*/ |
__ASM void __set_PSP(uint32_t topOfProcStack) |
{ |
msr psp, r0 |
bx lr |
} |
/** |
* @brief Return the Main Stack Pointer |
* |
* @return Main Stack Pointer |
* |
* Return the current value of the MSP (main stack pointer) |
* Cortex processor register |
*/ |
__ASM uint32_t __get_MSP(void) |
{ |
mrs r0, msp |
bx lr |
} |
/** |
* @brief Set the Main Stack Pointer |
* |
* @param topOfMainStack Main Stack Pointer |
* |
* Assign the value mainStackPointer to the MSP |
* (main stack pointer) Cortex processor register |
*/ |
__ASM void __set_MSP(uint32_t mainStackPointer) |
{ |
msr msp, r0 |
bx lr |
} |
/** |
* @brief Reverse byte order in unsigned short value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in unsigned short value |
*/ |
__ASM uint32_t __REV16(uint16_t value) |
{ |
rev16 r0, r0 |
bx lr |
} |
/** |
* @brief Reverse byte order in signed short value with sign extension to integer |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in signed short value with sign extension to integer |
*/ |
__ASM int32_t __REVSH(int16_t value) |
{ |
revsh r0, r0 |
bx lr |
} |
#if (__ARMCC_VERSION < 400000) |
/** |
* @brief Remove the exclusive lock created by ldrex |
* |
* Removes the exclusive lock which is created by ldrex. |
*/ |
__ASM void __CLREX(void) |
{ |
clrex |
} |
/** |
* @brief Return the Base Priority value |
* |
* @return BasePriority |
* |
* Return the content of the base priority register |
*/ |
__ASM uint32_t __get_BASEPRI(void) |
{ |
mrs r0, basepri |
bx lr |
} |
/** |
* @brief Set the Base Priority value |
* |
* @param basePri BasePriority |
* |
* Set the base priority register |
*/ |
__ASM void __set_BASEPRI(uint32_t basePri) |
{ |
msr basepri, r0 |
bx lr |
} |
/** |
* @brief Return the Priority Mask value |
* |
* @return PriMask |
* |
* Return state of the priority mask bit from the priority mask register |
*/ |
__ASM uint32_t __get_PRIMASK(void) |
{ |
mrs r0, primask |
bx lr |
} |
/** |
* @brief Set the Priority Mask value |
* |
* @param priMask PriMask |
* |
* Set the priority mask bit in the priority mask register |
*/ |
__ASM void __set_PRIMASK(uint32_t priMask) |
{ |
msr primask, r0 |
bx lr |
} |
/** |
* @brief Return the Fault Mask value |
* |
* @return FaultMask |
* |
* Return the content of the fault mask register |
*/ |
__ASM uint32_t __get_FAULTMASK(void) |
{ |
mrs r0, faultmask |
bx lr |
} |
/** |
* @brief Set the Fault Mask value |
* |
* @param faultMask faultMask value |
* |
* Set the fault mask register |
*/ |
__ASM void __set_FAULTMASK(uint32_t faultMask) |
{ |
msr faultmask, r0 |
bx lr |
} |
/** |
* @brief Return the Control Register value |
* |
* @return Control value |
* |
* Return the content of the control register |
*/ |
__ASM uint32_t __get_CONTROL(void) |
{ |
mrs r0, control |
bx lr |
} |
/** |
* @brief Set the Control Register value |
* |
* @param control Control value |
* |
* Set the control register |
*/ |
__ASM void __set_CONTROL(uint32_t control) |
{ |
msr control, r0 |
bx lr |
} |
#endif /* __ARMCC_VERSION */ |
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
/* IAR iccarm specific functions */ |
#pragma diag_suppress=Pe940 |
/** |
* @brief Return the Process Stack Pointer |
* |
* @return ProcessStackPointer |
* |
* Return the actual process stack pointer |
*/ |
uint32_t __get_PSP(void) |
{ |
__ASM("mrs r0, psp"); |
__ASM("bx lr"); |
} |
/** |
* @brief Set the Process Stack Pointer |
* |
* @param topOfProcStack Process Stack Pointer |
* |
* Assign the value ProcessStackPointer to the MSP |
* (process stack pointer) Cortex processor register |
*/ |
void __set_PSP(uint32_t topOfProcStack) |
{ |
__ASM("msr psp, r0"); |
__ASM("bx lr"); |
} |
/** |
* @brief Return the Main Stack Pointer |
* |
* @return Main Stack Pointer |
* |
* Return the current value of the MSP (main stack pointer) |
* Cortex processor register |
*/ |
uint32_t __get_MSP(void) |
{ |
__ASM("mrs r0, msp"); |
__ASM("bx lr"); |
} |
/** |
* @brief Set the Main Stack Pointer |
* |
* @param topOfMainStack Main Stack Pointer |
* |
* Assign the value mainStackPointer to the MSP |
* (main stack pointer) Cortex processor register |
*/ |
void __set_MSP(uint32_t topOfMainStack) |
{ |
__ASM("msr msp, r0"); |
__ASM("bx lr"); |
} |
/** |
* @brief Reverse byte order in unsigned short value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in unsigned short value |
*/ |
uint32_t __REV16(uint16_t value) |
{ |
__ASM("rev16 r0, r0"); |
__ASM("bx lr"); |
} |
/** |
* @brief Reverse bit order of value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse bit order of value |
*/ |
uint32_t __RBIT(uint32_t value) |
{ |
__ASM("rbit r0, r0"); |
__ASM("bx lr"); |
} |
/** |
* @brief LDR Exclusive (8 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 8 bit values) |
*/ |
uint8_t __LDREXB(uint8_t *addr) |
{ |
__ASM("ldrexb r0, [r0]"); |
__ASM("bx lr"); |
} |
/** |
* @brief LDR Exclusive (16 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 16 bit values |
*/ |
uint16_t __LDREXH(uint16_t *addr) |
{ |
__ASM("ldrexh r0, [r0]"); |
__ASM("bx lr"); |
} |
/** |
* @brief LDR Exclusive (32 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 32 bit values |
*/ |
uint32_t __LDREXW(uint32_t *addr) |
{ |
__ASM("ldrex r0, [r0]"); |
__ASM("bx lr"); |
} |
/** |
* @brief STR Exclusive (8 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 8 bit values |
*/ |
uint32_t __STREXB(uint8_t value, uint8_t *addr) |
{ |
__ASM("strexb r0, r0, [r1]"); |
__ASM("bx lr"); |
} |
/** |
* @brief STR Exclusive (16 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 16 bit values |
*/ |
uint32_t __STREXH(uint16_t value, uint16_t *addr) |
{ |
__ASM("strexh r0, r0, [r1]"); |
__ASM("bx lr"); |
} |
/** |
* @brief STR Exclusive (32 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 32 bit values |
*/ |
uint32_t __STREXW(uint32_t value, uint32_t *addr) |
{ |
__ASM("strex r0, r0, [r1]"); |
__ASM("bx lr"); |
} |
#pragma diag_default=Pe940 |
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
/* GNU gcc specific functions */ |
/** |
* @brief Return the Process Stack Pointer |
* |
* @return ProcessStackPointer |
* |
* Return the actual process stack pointer |
*/ |
uint32_t __get_PSP(void) __attribute__( ( naked ) ); |
uint32_t __get_PSP(void) |
{ |
uint32_t result=0; |
__ASM volatile ("MRS %0, psp\n\t" |
"MOV r0, %0 \n\t" |
"BX lr \n\t" : "=r" (result) ); |
return(result); |
} |
/** |
* @brief Set the Process Stack Pointer |
* |
* @param topOfProcStack Process Stack Pointer |
* |
* Assign the value ProcessStackPointer to the MSP |
* (process stack pointer) Cortex processor register |
*/ |
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); |
void __set_PSP(uint32_t topOfProcStack) |
{ |
__ASM volatile ("MSR psp, %0\n\t" |
"BX lr \n\t" : : "r" (topOfProcStack) ); |
} |
/** |
* @brief Return the Main Stack Pointer |
* |
* @return Main Stack Pointer |
* |
* Return the current value of the MSP (main stack pointer) |
* Cortex processor register |
*/ |
uint32_t __get_MSP(void) __attribute__( ( naked ) ); |
uint32_t __get_MSP(void) |
{ |
uint32_t result=0; |
__ASM volatile ("MRS %0, msp\n\t" |
"MOV r0, %0 \n\t" |
"BX lr \n\t" : "=r" (result) ); |
return(result); |
} |
/** |
* @brief Set the Main Stack Pointer |
* |
* @param topOfMainStack Main Stack Pointer |
* |
* Assign the value mainStackPointer to the MSP |
* (main stack pointer) Cortex processor register |
*/ |
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); |
void __set_MSP(uint32_t topOfMainStack) |
{ |
__ASM volatile ("MSR msp, %0\n\t" |
"BX lr \n\t" : : "r" (topOfMainStack) ); |
} |
/** |
* @brief Return the Base Priority value |
* |
* @return BasePriority |
* |
* Return the content of the base priority register |
*/ |
uint32_t __get_BASEPRI(void) |
{ |
uint32_t result=0; |
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); |
return(result); |
} |
/** |
* @brief Set the Base Priority value |
* |
* @param basePri BasePriority |
* |
* Set the base priority register |
*/ |
void __set_BASEPRI(uint32_t value) |
{ |
__ASM volatile ("MSR basepri, %0" : : "r" (value) ); |
} |
/** |
* @brief Return the Priority Mask value |
* |
* @return PriMask |
* |
* Return state of the priority mask bit from the priority mask register |
*/ |
uint32_t __get_PRIMASK(void) |
{ |
uint32_t result=0; |
__ASM volatile ("MRS %0, primask" : "=r" (result) ); |
return(result); |
} |
/** |
* @brief Set the Priority Mask value |
* |
* @param priMask PriMask |
* |
* Set the priority mask bit in the priority mask register |
*/ |
void __set_PRIMASK(uint32_t priMask) |
{ |
__ASM volatile ("MSR primask, %0" : : "r" (priMask) ); |
} |
/** |
* @brief Return the Fault Mask value |
* |
* @return FaultMask |
* |
* Return the content of the fault mask register |
*/ |
uint32_t __get_FAULTMASK(void) |
{ |
uint32_t result=0; |
__ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
return(result); |
} |
/** |
* @brief Set the Fault Mask value |
* |
* @param faultMask faultMask value |
* |
* Set the fault mask register |
*/ |
void __set_FAULTMASK(uint32_t faultMask) |
{ |
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); |
} |
/** |
* @brief Return the Control Register value |
* |
* @return Control value |
* |
* Return the content of the control register |
*/ |
uint32_t __get_CONTROL(void) |
{ |
uint32_t result=0; |
__ASM volatile ("MRS %0, control" : "=r" (result) ); |
return(result); |
} |
/** |
* @brief Set the Control Register value |
* |
* @param control Control value |
* |
* Set the control register |
*/ |
void __set_CONTROL(uint32_t control) |
{ |
__ASM volatile ("MSR control, %0" : : "r" (control) ); |
} |
/** |
* @brief Reverse byte order in integer value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in integer value |
*/ |
uint32_t __REV(uint32_t value) |
{ |
uint32_t result=0; |
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); |
return(result); |
} |
/** |
* @brief Reverse byte order in unsigned short value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in unsigned short value |
*/ |
uint32_t __REV16(uint16_t value) |
{ |
uint32_t result=0; |
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); |
return(result); |
} |
/** |
* @brief Reverse byte order in signed short value with sign extension to integer |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in signed short value with sign extension to integer |
*/ |
int32_t __REVSH(int16_t value) |
{ |
uint32_t result=0; |
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); |
return(result); |
} |
/** |
* @brief Reverse bit order of value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse bit order of value |
*/ |
uint32_t __RBIT(uint32_t value) |
{ |
uint32_t result=0; |
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
return(result); |
} |
/** |
* @brief LDR Exclusive (8 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 8 bit value |
*/ |
uint8_t __LDREXB(uint8_t *addr) |
{ |
uint8_t result=0; |
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); |
return(result); |
} |
/** |
* @brief LDR Exclusive (16 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 16 bit values |
*/ |
uint16_t __LDREXH(uint16_t *addr) |
{ |
uint16_t result=0; |
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); |
return(result); |
} |
/** |
* @brief LDR Exclusive (32 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 32 bit values |
*/ |
uint32_t __LDREXW(uint32_t *addr) |
{ |
uint32_t result=0; |
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); |
return(result); |
} |
/** |
* @brief STR Exclusive (8 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 8 bit values |
*/ |
uint32_t __STREXB(uint8_t value, uint8_t *addr) |
{ |
uint32_t result=0; |
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
return(result); |
} |
/** |
* @brief STR Exclusive (16 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 16 bit values |
*/ |
uint32_t __STREXH(uint16_t value, uint16_t *addr) |
{ |
uint32_t result=0; |
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
return(result); |
} |
/** |
* @brief STR Exclusive (32 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 32 bit values |
*/ |
uint32_t __STREXW(uint32_t value, uint32_t *addr) |
{ |
uint32_t result=0; |
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
return(result); |
} |
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
/* TASKING carm specific functions */ |
/* |
* The CMSIS functions have been implemented as intrinsics in the compiler. |
* Please use "carm -?i" to get an up to date list of all instrinsics, |
* Including the CMSIS ones. |
*/ |
#endif |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/core_cm3.h |
---|
0,0 → 1,1818 |
/**************************************************************************//** |
* @file core_cm3.h |
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File |
* @version V1.30 |
* @date 30. October 2009 |
* |
* @note |
* Copyright (C) 2009 ARM Limited. All rights reserved. |
* |
* @par |
* ARM Limited (ARM) is supplying this software for use with Cortex-M |
* processor based microcontrollers. This file can be freely distributed |
* within development tools that are supporting such ARM based processors. |
* |
* @par |
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
* |
******************************************************************************/ |
#ifndef __CM3_CORE_H__ |
#define __CM3_CORE_H__ |
/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration |
* |
* List of Lint messages which will be suppressed and not shown: |
* - Error 10: \n |
* register uint32_t __regBasePri __asm("basepri"); \n |
* Error 10: Expecting ';' |
* . |
* - Error 530: \n |
* return(__regBasePri); \n |
* Warning 530: Symbol '__regBasePri' (line 264) not initialized |
* . |
* - Error 550: \n |
* __regBasePri = (basePri & 0x1ff); \n |
* Warning 550: Symbol '__regBasePri' (line 271) not accessed |
* . |
* - Error 754: \n |
* uint32_t RESERVED0[24]; \n |
* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced |
* . |
* - Error 750: \n |
* #define __CM3_CORE_H__ \n |
* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced |
* . |
* - Error 528: \n |
* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n |
* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced |
* . |
* - Error 751: \n |
* } InterruptType_Type; \n |
* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced |
* . |
* Note: To re-enable a Message, insert a space before 'lint' * |
* |
*/ |
/*lint -save */ |
/*lint -e10 */ |
/*lint -e530 */ |
/*lint -e550 */ |
/*lint -e754 */ |
/*lint -e750 */ |
/*lint -e528 */ |
/*lint -e751 */ |
/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions |
This file defines all structures and symbols for CMSIS core: |
- CMSIS version number |
- Cortex-M core registers and bitfields |
- Cortex-M core peripheral base address |
@{ |
*/ |
#ifdef __cplusplus |
extern "C" { |
#endif |
#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ |
#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ |
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ |
#define __CORTEX_M (0x03) /*!< Cortex core */ |
#include <stdint.h> /* Include standard types */ |
#if defined (__ICCARM__) |
#include <intrinsics.h> /* IAR Intrinsics */ |
#endif |
#ifndef __NVIC_PRIO_BITS |
#define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ |
#endif |
/** |
* IO definitions |
* |
* define access restrictions to peripheral registers |
*/ |
#ifdef __cplusplus |
#define __I volatile /*!< defines 'read only' permissions */ |
#else |
#define __I volatile const /*!< defines 'read only' permissions */ |
#endif |
#define __O volatile /*!< defines 'write only' permissions */ |
#define __IO volatile /*!< defines 'read / write' permissions */ |
/******************************************************************************* |
* Register Abstraction |
******************************************************************************/ |
/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register |
@{ |
*/ |
/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC |
memory mapped structure for Nested Vectored Interrupt Controller (NVIC) |
@{ |
*/ |
typedef struct |
{ |
__IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ |
uint32_t RESERVED0[24]; |
__IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ |
uint32_t RSERVED1[24]; |
__IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ |
uint32_t RESERVED2[24]; |
__IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ |
uint32_t RESERVED3[24]; |
__IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ |
uint32_t RESERVED4[56]; |
__IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ |
uint32_t RESERVED5[644]; |
__O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ |
} NVIC_Type; |
/*@}*/ /* end of group CMSIS_CM3_NVIC */ |
/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB |
memory mapped structure for System Control Block (SCB) |
@{ |
*/ |
typedef struct |
{ |
__I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ |
__IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ |
__IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ |
__IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ |
__IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ |
__IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ |
__IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
__IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ |
__IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ |
__IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ |
__IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ |
__IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ |
__IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ |
__IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ |
__I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ |
__I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ |
__I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ |
__I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ |
__I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ |
} SCB_Type; |
/* SCB CPUID Register Definitions */ |
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
/* SCB Interrupt Control State Register Definitions */ |
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ |
#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
/* SCB Interrupt Control State Register Definitions */ |
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ |
#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ |
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
/* SCB Application Interrupt and Reset Control Register Definitions */ |
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ |
#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ |
#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ |
/* SCB System Control Register Definitions */ |
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
/* SCB Configuration Control Register Definitions */ |
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ |
#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ |
#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ |
#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ |
#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ |
/* SCB System Handler Control and State Register Definitions */ |
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ |
#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ |
#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ |
#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ |
#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ |
#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ |
#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ |
#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ |
#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ |
#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ |
#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ |
#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
/* SCB Configurable Fault Status Registers Definitions */ |
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ |
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ |
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
/* SCB Hard Fault Status Registers Definitions */ |
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ |
#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ |
#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ |
#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
/* SCB Debug Fault Status Register Definitions */ |
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ |
#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ |
#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ |
#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ |
#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ |
#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ |
/*@}*/ /* end of group CMSIS_CM3_SCB */ |
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick |
memory mapped structure for SysTick |
@{ |
*/ |
typedef struct |
{ |
__IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ |
__IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ |
__IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ |
__I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ |
} SysTick_Type; |
/* SysTick Control / Status Register Definitions */ |
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
/* SysTick Reload Register Definitions */ |
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
/* SysTick Current Register Definitions */ |
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
/* SysTick Calibration Register Definitions */ |
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ |
/*@}*/ /* end of group CMSIS_CM3_SysTick */ |
/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM |
memory mapped structure for Instrumentation Trace Macrocell (ITM) |
@{ |
*/ |
typedef struct |
{ |
__O union |
{ |
__O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ |
__O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ |
__O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ |
} PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ |
uint32_t RESERVED0[864]; |
__IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ |
uint32_t RESERVED1[15]; |
__IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ |
uint32_t RESERVED2[15]; |
__IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ |
uint32_t RESERVED3[29]; |
__IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ |
__IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ |
__IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ |
uint32_t RESERVED4[43]; |
__IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ |
__IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ |
uint32_t RESERVED5[6]; |
__I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ |
__I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ |
__I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ |
__I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ |
__I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ |
__I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ |
__I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ |
__I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ |
__I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ |
__I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ |
__I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ |
__I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ |
} ITM_Type; |
/* ITM Trace Privilege Register Definitions */ |
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ |
#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ |
/* ITM Trace Control Register Definitions */ |
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ |
#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ |
#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ |
#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ |
#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ |
#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ |
#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ |
#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ |
#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ |
#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ |
/* ITM Integration Write Register Definitions */ |
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ |
#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ |
/* ITM Integration Read Register Definitions */ |
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ |
#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ |
/* ITM Integration Mode Control Register Definitions */ |
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ |
#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ |
/* ITM Lock Status Register Definitions */ |
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ |
#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ |
#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ |
#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ |
/*@}*/ /* end of group CMSIS_CM3_ITM */ |
/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type |
memory mapped structure for Interrupt Type |
@{ |
*/ |
typedef struct |
{ |
uint32_t RESERVED0; |
__I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ |
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) |
__IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ |
#else |
uint32_t RESERVED1; |
#endif |
} InterruptType_Type; |
/* Interrupt Controller Type Register Definitions */ |
#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ |
#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ |
/* Auxiliary Control Register Definitions */ |
#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ |
#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ |
#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ |
#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ |
#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ |
#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ |
/*@}*/ /* end of group CMSIS_CM3_InterruptType */ |
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) |
/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU |
memory mapped structure for Memory Protection Unit (MPU) |
@{ |
*/ |
typedef struct |
{ |
__I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ |
__IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ |
__IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ |
__IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ |
__IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ |
__IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ |
__IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ |
__IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ |
__IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ |
__IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ |
__IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ |
} MPU_Type; |
/* MPU Type Register */ |
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ |
/* MPU Control Register */ |
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ |
/* MPU Region Number Register */ |
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ |
/* MPU Region Base Address Register */ |
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ |
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ |
/* MPU Region Attribute and Size Register */ |
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ |
#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ |
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ |
#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ |
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ |
#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ |
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ |
#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ |
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ |
#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ |
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ |
#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ |
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ |
/*@}*/ /* end of group CMSIS_CM3_MPU */ |
#endif |
/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug |
memory mapped structure for Core Debug Register |
@{ |
*/ |
typedef struct |
{ |
__IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ |
__O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ |
__IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ |
__IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ |
} CoreDebug_Type; |
/* Debug Halting Control and Status Register */ |
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ |
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ |
#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ |
#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ |
#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ |
#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ |
#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
/* Debug Core Register Selector Register */ |
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ |
#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ |
#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ |
/* Debug Exception and Monitor Control Register */ |
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ |
#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ |
#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ |
#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ |
#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ |
#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ |
#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ |
#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ |
#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ |
/* Memory mapping of Cortex-M3 Hardware */ |
#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ |
#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ |
#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ |
#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ |
#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ |
#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ |
#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ |
#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ |
#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ |
#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ |
#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ |
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) |
#define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ |
#define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ |
#endif |
/*@}*/ /* end of group CMSIS_CM3_core_register */ |
/******************************************************************************* |
* Hardware Abstraction Layer |
******************************************************************************/ |
#if defined ( __CC_ARM ) |
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
#elif defined ( __ICCARM__ ) |
#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
#elif defined ( __GNUC__ ) |
#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
#elif defined ( __TASKING__ ) |
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
#endif |
/* ################### Compiler specific Intrinsics ########################### */ |
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
/* ARM armcc specific functions */ |
#define __enable_fault_irq __enable_fiq |
#define __disable_fault_irq __disable_fiq |
#define __NOP __nop |
#define __WFI __wfi |
#define __WFE __wfe |
#define __SEV __sev |
#define __ISB() __isb(0) |
#define __DSB() __dsb(0) |
#define __DMB() __dmb(0) |
#define __REV __rev |
#define __RBIT __rbit |
#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) |
#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) |
#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) |
#define __STREXB(value, ptr) __strex(value, ptr) |
#define __STREXH(value, ptr) __strex(value, ptr) |
#define __STREXW(value, ptr) __strex(value, ptr) |
/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ |
/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ |
/* intrinsic void __enable_irq(); */ |
/* intrinsic void __disable_irq(); */ |
/** |
* @brief Return the Process Stack Pointer |
* |
* @return ProcessStackPointer |
* |
* Return the actual process stack pointer |
*/ |
extern uint32_t __get_PSP(void); |
/** |
* @brief Set the Process Stack Pointer |
* |
* @param topOfProcStack Process Stack Pointer |
* |
* Assign the value ProcessStackPointer to the MSP |
* (process stack pointer) Cortex processor register |
*/ |
extern void __set_PSP(uint32_t topOfProcStack); |
/** |
* @brief Return the Main Stack Pointer |
* |
* @return Main Stack Pointer |
* |
* Return the current value of the MSP (main stack pointer) |
* Cortex processor register |
*/ |
extern uint32_t __get_MSP(void); |
/** |
* @brief Set the Main Stack Pointer |
* |
* @param topOfMainStack Main Stack Pointer |
* |
* Assign the value mainStackPointer to the MSP |
* (main stack pointer) Cortex processor register |
*/ |
extern void __set_MSP(uint32_t topOfMainStack); |
/** |
* @brief Reverse byte order in unsigned short value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in unsigned short value |
*/ |
extern uint32_t __REV16(uint16_t value); |
/** |
* @brief Reverse byte order in signed short value with sign extension to integer |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in signed short value with sign extension to integer |
*/ |
extern int32_t __REVSH(int16_t value); |
#if (__ARMCC_VERSION < 400000) |
/** |
* @brief Remove the exclusive lock created by ldrex |
* |
* Removes the exclusive lock which is created by ldrex. |
*/ |
extern void __CLREX(void); |
/** |
* @brief Return the Base Priority value |
* |
* @return BasePriority |
* |
* Return the content of the base priority register |
*/ |
extern uint32_t __get_BASEPRI(void); |
/** |
* @brief Set the Base Priority value |
* |
* @param basePri BasePriority |
* |
* Set the base priority register |
*/ |
extern void __set_BASEPRI(uint32_t basePri); |
/** |
* @brief Return the Priority Mask value |
* |
* @return PriMask |
* |
* Return state of the priority mask bit from the priority mask register |
*/ |
extern uint32_t __get_PRIMASK(void); |
/** |
* @brief Set the Priority Mask value |
* |
* @param priMask PriMask |
* |
* Set the priority mask bit in the priority mask register |
*/ |
extern void __set_PRIMASK(uint32_t priMask); |
/** |
* @brief Return the Fault Mask value |
* |
* @return FaultMask |
* |
* Return the content of the fault mask register |
*/ |
extern uint32_t __get_FAULTMASK(void); |
/** |
* @brief Set the Fault Mask value |
* |
* @param faultMask faultMask value |
* |
* Set the fault mask register |
*/ |
extern void __set_FAULTMASK(uint32_t faultMask); |
/** |
* @brief Return the Control Register value |
* |
* @return Control value |
* |
* Return the content of the control register |
*/ |
extern uint32_t __get_CONTROL(void); |
/** |
* @brief Set the Control Register value |
* |
* @param control Control value |
* |
* Set the control register |
*/ |
extern void __set_CONTROL(uint32_t control); |
#else /* (__ARMCC_VERSION >= 400000) */ |
/** |
* @brief Remove the exclusive lock created by ldrex |
* |
* Removes the exclusive lock which is created by ldrex. |
*/ |
#define __CLREX __clrex |
/** |
* @brief Return the Base Priority value |
* |
* @return BasePriority |
* |
* Return the content of the base priority register |
*/ |
static __INLINE uint32_t __get_BASEPRI(void) |
{ |
register uint32_t __regBasePri __ASM("basepri"); |
return(__regBasePri); |
} |
/** |
* @brief Set the Base Priority value |
* |
* @param basePri BasePriority |
* |
* Set the base priority register |
*/ |
static __INLINE void __set_BASEPRI(uint32_t basePri) |
{ |
register uint32_t __regBasePri __ASM("basepri"); |
__regBasePri = (basePri & 0xff); |
} |
/** |
* @brief Return the Priority Mask value |
* |
* @return PriMask |
* |
* Return state of the priority mask bit from the priority mask register |
*/ |
static __INLINE uint32_t __get_PRIMASK(void) |
{ |
register uint32_t __regPriMask __ASM("primask"); |
return(__regPriMask); |
} |
/** |
* @brief Set the Priority Mask value |
* |
* @param priMask PriMask |
* |
* Set the priority mask bit in the priority mask register |
*/ |
static __INLINE void __set_PRIMASK(uint32_t priMask) |
{ |
register uint32_t __regPriMask __ASM("primask"); |
__regPriMask = (priMask); |
} |
/** |
* @brief Return the Fault Mask value |
* |
* @return FaultMask |
* |
* Return the content of the fault mask register |
*/ |
static __INLINE uint32_t __get_FAULTMASK(void) |
{ |
register uint32_t __regFaultMask __ASM("faultmask"); |
return(__regFaultMask); |
} |
/** |
* @brief Set the Fault Mask value |
* |
* @param faultMask faultMask value |
* |
* Set the fault mask register |
*/ |
static __INLINE void __set_FAULTMASK(uint32_t faultMask) |
{ |
register uint32_t __regFaultMask __ASM("faultmask"); |
__regFaultMask = (faultMask & 1); |
} |
/** |
* @brief Return the Control Register value |
* |
* @return Control value |
* |
* Return the content of the control register |
*/ |
static __INLINE uint32_t __get_CONTROL(void) |
{ |
register uint32_t __regControl __ASM("control"); |
return(__regControl); |
} |
/** |
* @brief Set the Control Register value |
* |
* @param control Control value |
* |
* Set the control register |
*/ |
static __INLINE void __set_CONTROL(uint32_t control) |
{ |
register uint32_t __regControl __ASM("control"); |
__regControl = control; |
} |
#endif /* __ARMCC_VERSION */ |
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
/* IAR iccarm specific functions */ |
#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ |
#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ |
static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } |
static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } |
#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ |
static __INLINE void __WFI() { __ASM ("wfi"); } |
static __INLINE void __WFE() { __ASM ("wfe"); } |
static __INLINE void __SEV() { __ASM ("sev"); } |
static __INLINE void __CLREX() { __ASM ("clrex"); } |
/* intrinsic void __ISB(void) */ |
/* intrinsic void __DSB(void) */ |
/* intrinsic void __DMB(void) */ |
/* intrinsic void __set_PRIMASK(); */ |
/* intrinsic void __get_PRIMASK(); */ |
/* intrinsic void __set_FAULTMASK(); */ |
/* intrinsic void __get_FAULTMASK(); */ |
/* intrinsic uint32_t __REV(uint32_t value); */ |
/* intrinsic uint32_t __REVSH(uint32_t value); */ |
/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ |
/* intrinsic unsigned long __LDREX(unsigned long *); */ |
/** |
* @brief Return the Process Stack Pointer |
* |
* @return ProcessStackPointer |
* |
* Return the actual process stack pointer |
*/ |
extern uint32_t __get_PSP(void); |
/** |
* @brief Set the Process Stack Pointer |
* |
* @param topOfProcStack Process Stack Pointer |
* |
* Assign the value ProcessStackPointer to the MSP |
* (process stack pointer) Cortex processor register |
*/ |
extern void __set_PSP(uint32_t topOfProcStack); |
/** |
* @brief Return the Main Stack Pointer |
* |
* @return Main Stack Pointer |
* |
* Return the current value of the MSP (main stack pointer) |
* Cortex processor register |
*/ |
extern uint32_t __get_MSP(void); |
/** |
* @brief Set the Main Stack Pointer |
* |
* @param topOfMainStack Main Stack Pointer |
* |
* Assign the value mainStackPointer to the MSP |
* (main stack pointer) Cortex processor register |
*/ |
extern void __set_MSP(uint32_t topOfMainStack); |
/** |
* @brief Reverse byte order in unsigned short value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in unsigned short value |
*/ |
extern uint32_t __REV16(uint16_t value); |
/** |
* @brief Reverse bit order of value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse bit order of value |
*/ |
extern uint32_t __RBIT(uint32_t value); |
/** |
* @brief LDR Exclusive (8 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 8 bit values) |
*/ |
extern uint8_t __LDREXB(uint8_t *addr); |
/** |
* @brief LDR Exclusive (16 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 16 bit values |
*/ |
extern uint16_t __LDREXH(uint16_t *addr); |
/** |
* @brief LDR Exclusive (32 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 32 bit values |
*/ |
extern uint32_t __LDREXW(uint32_t *addr); |
/** |
* @brief STR Exclusive (8 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 8 bit values |
*/ |
extern uint32_t __STREXB(uint8_t value, uint8_t *addr); |
/** |
* @brief STR Exclusive (16 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 16 bit values |
*/ |
extern uint32_t __STREXH(uint16_t value, uint16_t *addr); |
/** |
* @brief STR Exclusive (32 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 32 bit values |
*/ |
extern uint32_t __STREXW(uint32_t value, uint32_t *addr); |
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
/* GNU gcc specific functions */ |
static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } |
static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } |
static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } |
static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } |
static __INLINE void __NOP() { __ASM volatile ("nop"); } |
static __INLINE void __WFI() { __ASM volatile ("wfi"); } |
static __INLINE void __WFE() { __ASM volatile ("wfe"); } |
static __INLINE void __SEV() { __ASM volatile ("sev"); } |
static __INLINE void __ISB() { __ASM volatile ("isb"); } |
static __INLINE void __DSB() { __ASM volatile ("dsb"); } |
static __INLINE void __DMB() { __ASM volatile ("dmb"); } |
static __INLINE void __CLREX() { __ASM volatile ("clrex"); } |
/** |
* @brief Return the Process Stack Pointer |
* |
* @return ProcessStackPointer |
* |
* Return the actual process stack pointer |
*/ |
extern uint32_t __get_PSP(void); |
/** |
* @brief Set the Process Stack Pointer |
* |
* @param topOfProcStack Process Stack Pointer |
* |
* Assign the value ProcessStackPointer to the MSP |
* (process stack pointer) Cortex processor register |
*/ |
extern void __set_PSP(uint32_t topOfProcStack); |
/** |
* @brief Return the Main Stack Pointer |
* |
* @return Main Stack Pointer |
* |
* Return the current value of the MSP (main stack pointer) |
* Cortex processor register |
*/ |
extern uint32_t __get_MSP(void); |
/** |
* @brief Set the Main Stack Pointer |
* |
* @param topOfMainStack Main Stack Pointer |
* |
* Assign the value mainStackPointer to the MSP |
* (main stack pointer) Cortex processor register |
*/ |
extern void __set_MSP(uint32_t topOfMainStack); |
/** |
* @brief Return the Base Priority value |
* |
* @return BasePriority |
* |
* Return the content of the base priority register |
*/ |
extern uint32_t __get_BASEPRI(void); |
/** |
* @brief Set the Base Priority value |
* |
* @param basePri BasePriority |
* |
* Set the base priority register |
*/ |
extern void __set_BASEPRI(uint32_t basePri); |
/** |
* @brief Return the Priority Mask value |
* |
* @return PriMask |
* |
* Return state of the priority mask bit from the priority mask register |
*/ |
extern uint32_t __get_PRIMASK(void); |
/** |
* @brief Set the Priority Mask value |
* |
* @param priMask PriMask |
* |
* Set the priority mask bit in the priority mask register |
*/ |
extern void __set_PRIMASK(uint32_t priMask); |
/** |
* @brief Return the Fault Mask value |
* |
* @return FaultMask |
* |
* Return the content of the fault mask register |
*/ |
extern uint32_t __get_FAULTMASK(void); |
/** |
* @brief Set the Fault Mask value |
* |
* @param faultMask faultMask value |
* |
* Set the fault mask register |
*/ |
extern void __set_FAULTMASK(uint32_t faultMask); |
/** |
* @brief Return the Control Register value |
* |
* @return Control value |
* |
* Return the content of the control register |
*/ |
extern uint32_t __get_CONTROL(void); |
/** |
* @brief Set the Control Register value |
* |
* @param control Control value |
* |
* Set the control register |
*/ |
extern void __set_CONTROL(uint32_t control); |
/** |
* @brief Reverse byte order in integer value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in integer value |
*/ |
extern uint32_t __REV(uint32_t value); |
/** |
* @brief Reverse byte order in unsigned short value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in unsigned short value |
*/ |
extern uint32_t __REV16(uint16_t value); |
/** |
* @brief Reverse byte order in signed short value with sign extension to integer |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse byte order in signed short value with sign extension to integer |
*/ |
extern int32_t __REVSH(int16_t value); |
/** |
* @brief Reverse bit order of value |
* |
* @param value value to reverse |
* @return reversed value |
* |
* Reverse bit order of value |
*/ |
extern uint32_t __RBIT(uint32_t value); |
/** |
* @brief LDR Exclusive (8 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 8 bit value |
*/ |
extern uint8_t __LDREXB(uint8_t *addr); |
/** |
* @brief LDR Exclusive (16 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 16 bit values |
*/ |
extern uint16_t __LDREXH(uint16_t *addr); |
/** |
* @brief LDR Exclusive (32 bit) |
* |
* @param *addr address pointer |
* @return value of (*address) |
* |
* Exclusive LDR command for 32 bit values |
*/ |
extern uint32_t __LDREXW(uint32_t *addr); |
/** |
* @brief STR Exclusive (8 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 8 bit values |
*/ |
extern uint32_t __STREXB(uint8_t value, uint8_t *addr); |
/** |
* @brief STR Exclusive (16 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 16 bit values |
*/ |
extern uint32_t __STREXH(uint16_t value, uint16_t *addr); |
/** |
* @brief STR Exclusive (32 bit) |
* |
* @param value value to store |
* @param *addr address pointer |
* @return successful / failed |
* |
* Exclusive STR command for 32 bit values |
*/ |
extern uint32_t __STREXW(uint32_t value, uint32_t *addr); |
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
/* TASKING carm specific functions */ |
/* |
* The CMSIS functions have been implemented as intrinsics in the compiler. |
* Please use "carm -?i" to get an up to date list of all instrinsics, |
* Including the CMSIS ones. |
*/ |
#endif |
/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface |
Core Function Interface containing: |
- Core NVIC Functions |
- Core SysTick Functions |
- Core Reset Functions |
*/ |
/*@{*/ |
/* ########################## NVIC functions #################################### */ |
/** |
* @brief Set the Priority Grouping in NVIC Interrupt Controller |
* |
* @param PriorityGroup is priority grouping field |
* |
* Set the priority grouping field using the required unlock sequence. |
* The parameter priority_grouping is assigned to the field |
* SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. |
* In case of a conflict between priority grouping and available |
* priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
*/ |
static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
{ |
uint32_t reg_value; |
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
reg_value = SCB->AIRCR; /* read old register configuration */ |
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ |
reg_value = (reg_value | |
(0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */ |
SCB->AIRCR = reg_value; |
} |
/** |
* @brief Get the Priority Grouping from NVIC Interrupt Controller |
* |
* @return priority grouping field |
* |
* Get the priority grouping from NVIC Interrupt Controller. |
* priority grouping is SCB->AIRCR [10:8] PRIGROUP field. |
*/ |
static __INLINE uint32_t NVIC_GetPriorityGrouping(void) |
{ |
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ |
} |
/** |
* @brief Enable Interrupt in NVIC Interrupt Controller |
* |
* @param IRQn The positive number of the external interrupt to enable |
* |
* Enable a device specific interupt in the NVIC interrupt controller. |
* The interrupt number cannot be a negative value. |
*/ |
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
{ |
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ |
} |
/** |
* @brief Disable the interrupt line for external interrupt specified |
* |
* @param IRQn The positive number of the external interrupt to disable |
* |
* Disable a device specific interupt in the NVIC interrupt controller. |
* The interrupt number cannot be a negative value. |
*/ |
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
{ |
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ |
} |
/** |
* @brief Read the interrupt pending bit for a device specific interrupt source |
* |
* @param IRQn The number of the device specifc interrupt |
* @return 1 = interrupt pending, 0 = interrupt not pending |
* |
* Read the pending register in NVIC and return 1 if its status is pending, |
* otherwise it returns 0 |
*/ |
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
{ |
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ |
} |
/** |
* @brief Set the pending bit for an external interrupt |
* |
* @param IRQn The number of the interrupt for set pending |
* |
* Set the pending bit for the specified interrupt. |
* The interrupt number cannot be a negative value. |
*/ |
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
{ |
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ |
} |
/** |
* @brief Clear the pending bit for an external interrupt |
* |
* @param IRQn The number of the interrupt for clear pending |
* |
* Clear the pending bit for the specified interrupt. |
* The interrupt number cannot be a negative value. |
*/ |
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
{ |
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
} |
/** |
* @brief Read the active bit for an external interrupt |
* |
* @param IRQn The number of the interrupt for read active bit |
* @return 1 = interrupt active, 0 = interrupt not active |
* |
* Read the active register in NVIC and returns 1 if its status is active, |
* otherwise it returns 0. |
*/ |
static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) |
{ |
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ |
} |
/** |
* @brief Set the priority for an interrupt |
* |
* @param IRQn The number of the interrupt for set priority |
* @param priority The priority to set |
* |
* Set the priority for the specified interrupt. The interrupt |
* number can be positive to specify an external (device specific) |
* interrupt, or negative to specify an internal (core) interrupt. |
* |
* Note: The priority cannot be set for every core interrupt. |
*/ |
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
{ |
if(IRQn < 0) { |
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ |
else { |
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ |
} |
/** |
* @brief Read the priority for an interrupt |
* |
* @param IRQn The number of the interrupt for get priority |
* @return The priority for the interrupt |
* |
* Read the priority for the specified interrupt. The interrupt |
* number can be positive to specify an external (device specific) |
* interrupt, or negative to specify an internal (core) interrupt. |
* |
* The returned priority value is automatically aligned to the implemented |
* priority bits of the microcontroller. |
* |
* Note: The priority cannot be set for every core interrupt. |
*/ |
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
{ |
if(IRQn < 0) { |
return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ |
else { |
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
} |
/** |
* @brief Encode the priority for an interrupt |
* |
* @param PriorityGroup The used priority group |
* @param PreemptPriority The preemptive priority value (starting from 0) |
* @param SubPriority The sub priority value (starting from 0) |
* @return The encoded priority for the interrupt |
* |
* Encode the priority for an interrupt with the given priority group, |
* preemptive priority value and sub priority value. |
* In case of a conflict between priority grouping and available |
* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. |
* |
* The returned priority value can be used for NVIC_SetPriority(...) function |
*/ |
static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
{ |
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
uint32_t PreemptPriorityBits; |
uint32_t SubPriorityBits; |
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
return ( |
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | |
((SubPriority & ((1 << (SubPriorityBits )) - 1))) |
); |
} |
/** |
* @brief Decode the priority of an interrupt |
* |
* @param Priority The priority for the interrupt |
* @param PriorityGroup The used priority group |
* @param pPreemptPriority The preemptive priority value (starting from 0) |
* @param pSubPriority The sub priority value (starting from 0) |
* |
* Decode an interrupt priority value with the given priority group to |
* preemptive priority value and sub priority value. |
* In case of a conflict between priority grouping and available |
* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. |
* |
* The priority value can be retrieved with NVIC_GetPriority(...) function |
*/ |
static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
{ |
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
uint32_t PreemptPriorityBits; |
uint32_t SubPriorityBits; |
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); |
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); |
} |
/* ################################## SysTick function ############################################ */ |
#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) |
/** |
* @brief Initialize and start the SysTick counter and its interrupt. |
* |
* @param ticks number of ticks between two interrupts |
* @return 1 = failed, 0 = successful |
* |
* Initialise the system tick timer and its interrupt and start the |
* system tick timer / counter in free running mode to generate |
* periodical interrupts. |
*/ |
static __INLINE uint32_t SysTick_Config(uint32_t ticks) |
{ |
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ |
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ |
SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
SysTick_CTRL_TICKINT_Msk | |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
return (0); /* Function successful */ |
} |
#endif |
/* ################################## Reset function ############################################ */ |
/** |
* @brief Initiate a system reset request. |
* |
* Initiate a system reset request to reset the MCU |
*/ |
static __INLINE void NVIC_SystemReset(void) |
{ |
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ |
__DSB(); /* Ensure completion of memory access */ |
while(1); /* wait until reset */ |
} |
/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ |
/* ##################################### Debug In/Output function ########################################### */ |
/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface |
Core Debug Interface containing: |
- Core Debug Receive / Transmit Functions |
- Core Debug Defines |
- Core Debug Variables |
*/ |
/*@{*/ |
extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ |
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ |
/** |
* @brief Outputs a character via the ITM channel 0 |
* |
* @param ch character to output |
* @return character to output |
* |
* The function outputs a character via the ITM channel 0. |
* The function returns when no debugger is connected that has booked the output. |
* It is blocking when a debugger is connected, but the previous character send is not transmitted. |
*/ |
static __INLINE uint32_t ITM_SendChar (uint32_t ch) |
{ |
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ |
(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ |
(ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ |
{ |
while (ITM->PORT[0].u32 == 0); |
ITM->PORT[0].u8 = (uint8_t) ch; |
} |
return (ch); |
} |
/** |
* @brief Inputs a character via variable ITM_RxBuffer |
* |
* @return received character, -1 = no character received |
* |
* The function inputs a character via variable ITM_RxBuffer. |
* The function returns when no debugger is connected that has booked the output. |
* It is blocking when a debugger is connected, but the previous character send is not transmitted. |
*/ |
static __INLINE int ITM_ReceiveChar (void) { |
int ch = -1; /* no character available */ |
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { |
ch = ITM_RxBuffer; |
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
} |
return (ch); |
} |
/** |
* @brief Check if a character via variable ITM_RxBuffer is available |
* |
* @return 1 = character available, 0 = no character available |
* |
* The function checks variable ITM_RxBuffer whether a character is available or not. |
* The function returns '1' if a character is available and '0' if no character is available. |
*/ |
static __INLINE int ITM_CheckChar (void) { |
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { |
return (0); /* no character available */ |
} else { |
return (1); /* character available */ |
} |
} |
/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ |
#ifdef __cplusplus |
} |
#endif |
/*@}*/ /* end of group CMSIS_CM3_core_definitions */ |
#endif /* __CM3_CORE_H__ */ |
/*lint -restore */ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/misc.c |
---|
0,0 → 1,223 |
/** |
****************************************************************************** |
* @file misc.c |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief This file provides all the miscellaneous firmware functions (add-on |
* to CMSIS functions). |
****************************************************************************** |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
/* Includes ------------------------------------------------------------------*/ |
#include "misc.h" |
/** @addtogroup STM32F10x_StdPeriph_Driver |
* @{ |
*/ |
/** @defgroup MISC |
* @brief MISC driver modules |
* @{ |
*/ |
/** @defgroup MISC_Private_TypesDefinitions |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup MISC_Private_Defines |
* @{ |
*/ |
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) |
/** |
* @} |
*/ |
/** @defgroup MISC_Private_Macros |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup MISC_Private_Variables |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup MISC_Private_FunctionPrototypes |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup MISC_Private_Functions |
* @{ |
*/ |
/** |
* @brief Configures the priority grouping: pre-emption priority and subpriority. |
* @param NVIC_PriorityGroup: specifies the priority grouping bits length. |
* This parameter can be one of the following values: |
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority |
* 4 bits for subpriority |
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority |
* 3 bits for subpriority |
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority |
* 2 bits for subpriority |
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority |
* 1 bits for subpriority |
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority |
* 0 bits for subpriority |
* @retval None |
*/ |
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) |
{ |
/* Check the parameters */ |
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); |
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ |
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; |
} |
/** |
* @brief Initializes the NVIC peripheral according to the specified |
* parameters in the NVIC_InitStruct. |
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains |
* the configuration information for the specified NVIC peripheral. |
* @retval None |
*/ |
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) |
{ |
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); |
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); |
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); |
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) |
{ |
/* Compute the Corresponding IRQ Priority --------------------------------*/ |
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; |
tmppre = (0x4 - tmppriority); |
tmpsub = tmpsub >> tmppriority; |
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; |
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; |
tmppriority = tmppriority << 0x04; |
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; |
/* Enable the Selected IRQ Channels --------------------------------------*/ |
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = |
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); |
} |
else |
{ |
/* Disable the Selected IRQ Channels -------------------------------------*/ |
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = |
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); |
} |
} |
/** |
* @brief Sets the vector table location and Offset. |
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. |
* This parameter can be one of the following values: |
* @arg NVIC_VectTab_RAM |
* @arg NVIC_VectTab_FLASH |
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x100. |
* @retval None |
*/ |
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) |
{ |
/* Check the parameters */ |
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); |
assert_param(IS_NVIC_OFFSET(Offset)); |
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); |
} |
/** |
* @brief Selects the condition for the system to enter low power mode. |
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode. |
* This parameter can be one of the following values: |
* @arg NVIC_LP_SEVONPEND |
* @arg NVIC_LP_SLEEPDEEP |
* @arg NVIC_LP_SLEEPONEXIT |
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_NVIC_LP(LowPowerMode)); |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
if (NewState != DISABLE) |
{ |
SCB->SCR |= LowPowerMode; |
} |
else |
{ |
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); |
} |
} |
/** |
* @brief Configures the SysTick clock source. |
* @param SysTick_CLKSource: specifies the SysTick clock source. |
* This parameter can be one of the following values: |
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. |
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. |
* @retval None |
*/ |
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) |
{ |
/* Check the parameters */ |
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); |
if (SysTick_CLKSource == SysTick_CLKSource_HCLK) |
{ |
SysTick->CTRL |= SysTick_CLKSource_HCLK; |
} |
else |
{ |
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; |
} |
} |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/misc.h |
---|
0,0 → 1,219 |
/** |
****************************************************************************** |
* @file misc.h |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief This file contains all the functions prototypes for the miscellaneous |
* firmware library functions (add-on to CMSIS functions). |
****************************************************************************** |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
/* Define to prevent recursive inclusion -------------------------------------*/ |
#ifndef __MISC_H |
#define __MISC_H |
#ifdef __cplusplus |
extern "C" { |
#endif |
/* Includes ------------------------------------------------------------------*/ |
#include "stm32f10x.h" |
/** @addtogroup STM32F10x_StdPeriph_Driver |
* @{ |
*/ |
/** @addtogroup MISC |
* @{ |
*/ |
/** @defgroup MISC_Exported_Types |
* @{ |
*/ |
/** |
* @brief NVIC Init Structure definition |
*/ |
typedef struct |
{ |
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. |
This parameter can be a value of @ref IRQn_Type |
(For the complete STM32 Devices IRQ Channels list, please |
refer to stm32f10x.h file) */ |
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel |
specified in NVIC_IRQChannel. This parameter can be a value |
between 0 and 15 as described in the table @ref NVIC_Priority_Table */ |
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified |
in NVIC_IRQChannel. This parameter can be a value |
between 0 and 15 as described in the table @ref NVIC_Priority_Table */ |
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel |
will be enabled or disabled. |
This parameter can be set either to ENABLE or DISABLE */ |
} NVIC_InitTypeDef; |
/** |
* @} |
*/ |
/** @defgroup NVIC_Priority_Table |
* @{ |
*/ |
/** |
@code |
The table below gives the allowed values of the pre-emption priority and subpriority according |
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function |
============================================================================================================================ |
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description |
============================================================================================================================ |
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority |
| | | 4 bits for subpriority |
---------------------------------------------------------------------------------------------------------------------------- |
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority |
| | | 3 bits for subpriority |
---------------------------------------------------------------------------------------------------------------------------- |
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority |
| | | 2 bits for subpriority |
---------------------------------------------------------------------------------------------------------------------------- |
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority |
| | | 1 bits for subpriority |
---------------------------------------------------------------------------------------------------------------------------- |
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority |
| | | 0 bits for subpriority |
============================================================================================================================ |
@endcode |
*/ |
/** |
* @} |
*/ |
/** @defgroup MISC_Exported_Constants |
* @{ |
*/ |
/** @defgroup Vector_Table_Base |
* @{ |
*/ |
#define NVIC_VectTab_RAM ((uint32_t)0x20000000) |
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) |
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ |
((VECTTAB) == NVIC_VectTab_FLASH)) |
/** |
* @} |
*/ |
/** @defgroup System_Low_Power |
* @{ |
*/ |
#define NVIC_LP_SEVONPEND ((uint8_t)0x10) |
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) |
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) |
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ |
((LP) == NVIC_LP_SLEEPDEEP) || \ |
((LP) == NVIC_LP_SLEEPONEXIT)) |
/** |
* @} |
*/ |
/** @defgroup Preemption_Priority_Group |
* @{ |
*/ |
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority |
4 bits for subpriority */ |
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority |
3 bits for subpriority */ |
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority |
2 bits for subpriority */ |
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority |
1 bits for subpriority */ |
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority |
0 bits for subpriority */ |
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ |
((GROUP) == NVIC_PriorityGroup_1) || \ |
((GROUP) == NVIC_PriorityGroup_2) || \ |
((GROUP) == NVIC_PriorityGroup_3) || \ |
((GROUP) == NVIC_PriorityGroup_4)) |
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) |
/** |
* @} |
*/ |
/** @defgroup SysTick_clock_source |
* @{ |
*/ |
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) |
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) |
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ |
((SOURCE) == SysTick_CLKSource_HCLK_Div8)) |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/** @defgroup MISC_Exported_Macros |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup MISC_Exported_Functions |
* @{ |
*/ |
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); |
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); |
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); |
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); |
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); |
#ifdef __cplusplus |
} |
#endif |
#endif /* __MISC_H */ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/stm32f10x.h |
---|
0,0 → 1,8319 |
/** |
****************************************************************************** |
* @file stm32f10x.h |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
* This file contains all the peripheral register's definitions, bits |
* definitions and memory mapping for STM32F10x Connectivity line, |
* High density, High density value line, Medium density, |
* Medium density Value line, Low density, Low density Value line |
* and XL-density devices. |
****************************************************************************** |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
****************************************************************************** |
*/ |
/** @addtogroup CMSIS |
* @{ |
*/ |
/** @addtogroup stm32f10x |
* @{ |
*/ |
#ifndef __STM32F10x_H |
#define __STM32F10x_H |
#ifdef __cplusplus |
extern "C" { |
#endif |
/** @addtogroup Library_configuration_section |
* @{ |
*/ |
/* Uncomment the line below according to the target STM32 device used in your |
application |
*/ |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) |
/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ |
/* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ |
/* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ |
/* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ |
/* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ |
/* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ |
/* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ |
/* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ |
#endif |
/* Tip: To avoid modifying this file each time you need to switch between these |
devices, you can define the device in your toolchain compiler preprocessor. |
- Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers |
where the Flash memory density ranges between 16 and 32 Kbytes. |
- Low-density value line devices are STM32F100xx microcontrollers where the Flash |
memory density ranges between 16 and 32 Kbytes. |
- Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers |
where the Flash memory density ranges between 64 and 128 Kbytes. |
- Medium-density value line devices are STM32F100xx microcontrollers where the |
Flash memory density ranges between 64 and 128 Kbytes. |
- High-density devices are STM32F101xx and STM32F103xx microcontrollers where |
the Flash memory density ranges between 256 and 512 Kbytes. |
- High-density value line devices are STM32F100xx microcontrollers where the |
Flash memory density ranges between 256 and 512 Kbytes. |
- XL-density devices are STM32F101xx and STM32F103xx microcontrollers where |
the Flash memory density ranges between 512 and 1024 Kbytes. |
- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. |
*/ |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) |
#error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" |
#endif |
#if !defined USE_STDPERIPH_DRIVER |
/** |
* @brief Comment the line below if you will not use the peripherals drivers. |
In this case, these drivers will not be included and the application code will |
be based on direct access to peripherals registers |
*/ |
/*#define USE_STDPERIPH_DRIVER*/ |
#endif |
/** |
* @brief In the following line adjust the value of External High Speed oscillator (HSE) |
used in your application |
Tip: To avoid modifying this file each time you need to use different HSE, you |
can define the HSE value in your toolchain compiler preprocessor. |
*/ |
#if !defined HSE_VALUE |
#ifdef STM32F10X_CL |
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ |
#else |
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ |
#endif /* STM32F10X_CL */ |
#endif /* HSE_VALUE */ |
/** |
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup |
Timeout value |
*/ |
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ |
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ |
/** |
* @brief STM32F10x Standard Peripheral Library version number |
*/ |
#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ |
#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ |
#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ |
#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ |
| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ |
| __STM32F10X_STDPERIPH_VERSION_SUB2) |
/** |
* @} |
*/ |
/** @addtogroup Configuration_section_for_CMSIS |
* @{ |
*/ |
/** |
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
*/ |
#ifdef STM32F10X_XL |
#define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ |
#else |
#define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ |
#endif /* STM32F10X_XL */ |
#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ |
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
/** |
* @brief STM32F10x Interrupt Number Definition, according to the selected device |
* in @ref Library_configuration_section |
*/ |
typedef enum IRQn |
{ |
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
/****** STM32 specific Interrupt Numbers *********************************************************/ |
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
RTC_IRQn = 3, /*!< RTC global Interrupt */ |
FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
RCC_IRQn = 5, /*!< RCC global Interrupt */ |
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
#ifdef STM32F10X_LD |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
#endif /* STM32F10X_LD */ |
#ifdef STM32F10X_LD_VL |
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
TIM7_IRQn = 55 /*!< TIM7 Interrupt */ |
#endif /* STM32F10X_LD_VL */ |
#ifdef STM32F10X_MD |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
#endif /* STM32F10X_MD */ |
#ifdef STM32F10X_MD_VL |
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
TIM7_IRQn = 55 /*!< TIM7 Interrupt */ |
#endif /* STM32F10X_MD_VL */ |
#ifdef STM32F10X_HD |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ |
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ |
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ |
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
#endif /* STM32F10X_HD */ |
#ifdef STM32F10X_HD_VL |
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ |
TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ |
TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
TIM7_IRQn = 55, /*!< TIM7 Interrupt */ |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is |
mapped at postion 60 only if the MISC_REMAP bit in |
the AFIO_MAPR2 register is set) */ |
#endif /* STM32F10X_HD_VL */ |
#ifdef STM32F10X_XL |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ |
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ |
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ |
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ |
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ |
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
#endif /* STM32F10X_XL */ |
#ifdef STM32F10X_CL |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
ETH_IRQn = 61, /*!< Ethernet global Interrupt */ |
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ |
CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ |
CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ |
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ |
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ |
OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ |
#endif /* STM32F10X_CL */ |
} IRQn_Type; |
/** |
* @} |
*/ |
#include "core_cm3.h" |
#include "system_stm32f10x.h" |
#include <stdint.h> |
/** @addtogroup Exported_types |
* @{ |
*/ |
/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ |
typedef int32_t s32; |
typedef int16_t s16; |
typedef int8_t s8; |
typedef const int32_t sc32; /*!< Read Only */ |
typedef const int16_t sc16; /*!< Read Only */ |
typedef const int8_t sc8; /*!< Read Only */ |
typedef __IO int32_t vs32; |
typedef __IO int16_t vs16; |
typedef __IO int8_t vs8; |
typedef __I int32_t vsc32; /*!< Read Only */ |
typedef __I int16_t vsc16; /*!< Read Only */ |
typedef __I int8_t vsc8; /*!< Read Only */ |
typedef uint32_t u32; |
typedef uint16_t u16; |
typedef uint8_t u8; |
typedef const uint32_t uc32; /*!< Read Only */ |
typedef const uint16_t uc16; /*!< Read Only */ |
typedef const uint8_t uc8; /*!< Read Only */ |
typedef __IO uint32_t vu32; |
typedef __IO uint16_t vu16; |
typedef __IO uint8_t vu8; |
typedef __I uint32_t vuc32; /*!< Read Only */ |
typedef __I uint16_t vuc16; /*!< Read Only */ |
typedef __I uint8_t vuc8; /*!< Read Only */ |
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; |
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; |
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; |
/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ |
#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT |
#define HSE_Value HSE_VALUE |
#define HSI_Value HSI_VALUE |
/** |
* @} |
*/ |
/** @addtogroup Peripheral_registers_structures |
* @{ |
*/ |
/** |
* @brief Analog to Digital Converter |
*/ |
typedef struct |
{ |
__IO uint32_t SR; |
__IO uint32_t CR1; |
__IO uint32_t CR2; |
__IO uint32_t SMPR1; |
__IO uint32_t SMPR2; |
__IO uint32_t JOFR1; |
__IO uint32_t JOFR2; |
__IO uint32_t JOFR3; |
__IO uint32_t JOFR4; |
__IO uint32_t HTR; |
__IO uint32_t LTR; |
__IO uint32_t SQR1; |
__IO uint32_t SQR2; |
__IO uint32_t SQR3; |
__IO uint32_t JSQR; |
__IO uint32_t JDR1; |
__IO uint32_t JDR2; |
__IO uint32_t JDR3; |
__IO uint32_t JDR4; |
__IO uint32_t DR; |
} ADC_TypeDef; |
/** |
* @brief Backup Registers |
*/ |
typedef struct |
{ |
uint32_t RESERVED0; |
__IO uint16_t DR1; |
uint16_t RESERVED1; |
__IO uint16_t DR2; |
uint16_t RESERVED2; |
__IO uint16_t DR3; |
uint16_t RESERVED3; |
__IO uint16_t DR4; |
uint16_t RESERVED4; |
__IO uint16_t DR5; |
uint16_t RESERVED5; |
__IO uint16_t DR6; |
uint16_t RESERVED6; |
__IO uint16_t DR7; |
uint16_t RESERVED7; |
__IO uint16_t DR8; |
uint16_t RESERVED8; |
__IO uint16_t DR9; |
uint16_t RESERVED9; |
__IO uint16_t DR10; |
uint16_t RESERVED10; |
__IO uint16_t RTCCR; |
uint16_t RESERVED11; |
__IO uint16_t CR; |
uint16_t RESERVED12; |
__IO uint16_t CSR; |
uint16_t RESERVED13[5]; |
__IO uint16_t DR11; |
uint16_t RESERVED14; |
__IO uint16_t DR12; |
uint16_t RESERVED15; |
__IO uint16_t DR13; |
uint16_t RESERVED16; |
__IO uint16_t DR14; |
uint16_t RESERVED17; |
__IO uint16_t DR15; |
uint16_t RESERVED18; |
__IO uint16_t DR16; |
uint16_t RESERVED19; |
__IO uint16_t DR17; |
uint16_t RESERVED20; |
__IO uint16_t DR18; |
uint16_t RESERVED21; |
__IO uint16_t DR19; |
uint16_t RESERVED22; |
__IO uint16_t DR20; |
uint16_t RESERVED23; |
__IO uint16_t DR21; |
uint16_t RESERVED24; |
__IO uint16_t DR22; |
uint16_t RESERVED25; |
__IO uint16_t DR23; |
uint16_t RESERVED26; |
__IO uint16_t DR24; |
uint16_t RESERVED27; |
__IO uint16_t DR25; |
uint16_t RESERVED28; |
__IO uint16_t DR26; |
uint16_t RESERVED29; |
__IO uint16_t DR27; |
uint16_t RESERVED30; |
__IO uint16_t DR28; |
uint16_t RESERVED31; |
__IO uint16_t DR29; |
uint16_t RESERVED32; |
__IO uint16_t DR30; |
uint16_t RESERVED33; |
__IO uint16_t DR31; |
uint16_t RESERVED34; |
__IO uint16_t DR32; |
uint16_t RESERVED35; |
__IO uint16_t DR33; |
uint16_t RESERVED36; |
__IO uint16_t DR34; |
uint16_t RESERVED37; |
__IO uint16_t DR35; |
uint16_t RESERVED38; |
__IO uint16_t DR36; |
uint16_t RESERVED39; |
__IO uint16_t DR37; |
uint16_t RESERVED40; |
__IO uint16_t DR38; |
uint16_t RESERVED41; |
__IO uint16_t DR39; |
uint16_t RESERVED42; |
__IO uint16_t DR40; |
uint16_t RESERVED43; |
__IO uint16_t DR41; |
uint16_t RESERVED44; |
__IO uint16_t DR42; |
uint16_t RESERVED45; |
} BKP_TypeDef; |
/** |
* @brief Controller Area Network TxMailBox |
*/ |
typedef struct |
{ |
__IO uint32_t TIR; |
__IO uint32_t TDTR; |
__IO uint32_t TDLR; |
__IO uint32_t TDHR; |
} CAN_TxMailBox_TypeDef; |
/** |
* @brief Controller Area Network FIFOMailBox |
*/ |
typedef struct |
{ |
__IO uint32_t RIR; |
__IO uint32_t RDTR; |
__IO uint32_t RDLR; |
__IO uint32_t RDHR; |
} CAN_FIFOMailBox_TypeDef; |
/** |
* @brief Controller Area Network FilterRegister |
*/ |
typedef struct |
{ |
__IO uint32_t FR1; |
__IO uint32_t FR2; |
} CAN_FilterRegister_TypeDef; |
/** |
* @brief Controller Area Network |
*/ |
typedef struct |
{ |
__IO uint32_t MCR; |
__IO uint32_t MSR; |
__IO uint32_t TSR; |
__IO uint32_t RF0R; |
__IO uint32_t RF1R; |
__IO uint32_t IER; |
__IO uint32_t ESR; |
__IO uint32_t BTR; |
uint32_t RESERVED0[88]; |
CAN_TxMailBox_TypeDef sTxMailBox[3]; |
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; |
uint32_t RESERVED1[12]; |
__IO uint32_t FMR; |
__IO uint32_t FM1R; |
uint32_t RESERVED2; |
__IO uint32_t FS1R; |
uint32_t RESERVED3; |
__IO uint32_t FFA1R; |
uint32_t RESERVED4; |
__IO uint32_t FA1R; |
uint32_t RESERVED5[8]; |
#ifndef STM32F10X_CL |
CAN_FilterRegister_TypeDef sFilterRegister[14]; |
#else |
CAN_FilterRegister_TypeDef sFilterRegister[28]; |
#endif /* STM32F10X_CL */ |
} CAN_TypeDef; |
/** |
* @brief Consumer Electronics Control (CEC) |
*/ |
typedef struct |
{ |
__IO uint32_t CFGR; |
__IO uint32_t OAR; |
__IO uint32_t PRES; |
__IO uint32_t ESR; |
__IO uint32_t CSR; |
__IO uint32_t TXD; |
__IO uint32_t RXD; |
} CEC_TypeDef; |
/** |
* @brief CRC calculation unit |
*/ |
typedef struct |
{ |
__IO uint32_t DR; |
__IO uint8_t IDR; |
uint8_t RESERVED0; |
uint16_t RESERVED1; |
__IO uint32_t CR; |
} CRC_TypeDef; |
/** |
* @brief Digital to Analog Converter |
*/ |
typedef struct |
{ |
__IO uint32_t CR; |
__IO uint32_t SWTRIGR; |
__IO uint32_t DHR12R1; |
__IO uint32_t DHR12L1; |
__IO uint32_t DHR8R1; |
__IO uint32_t DHR12R2; |
__IO uint32_t DHR12L2; |
__IO uint32_t DHR8R2; |
__IO uint32_t DHR12RD; |
__IO uint32_t DHR12LD; |
__IO uint32_t DHR8RD; |
__IO uint32_t DOR1; |
__IO uint32_t DOR2; |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
__IO uint32_t SR; |
#endif |
} DAC_TypeDef; |
/** |
* @brief Debug MCU |
*/ |
typedef struct |
{ |
__IO uint32_t IDCODE; |
__IO uint32_t CR; |
}DBGMCU_TypeDef; |
/** |
* @brief DMA Controller |
*/ |
typedef struct |
{ |
__IO uint32_t CCR; |
__IO uint32_t CNDTR; |
__IO uint32_t CPAR; |
__IO uint32_t CMAR; |
} DMA_Channel_TypeDef; |
typedef struct |
{ |
__IO uint32_t ISR; |
__IO uint32_t IFCR; |
} DMA_TypeDef; |
/** |
* @brief Ethernet MAC |
*/ |
typedef struct |
{ |
__IO uint32_t MACCR; |
__IO uint32_t MACFFR; |
__IO uint32_t MACHTHR; |
__IO uint32_t MACHTLR; |
__IO uint32_t MACMIIAR; |
__IO uint32_t MACMIIDR; |
__IO uint32_t MACFCR; |
__IO uint32_t MACVLANTR; /* 8 */ |
uint32_t RESERVED0[2]; |
__IO uint32_t MACRWUFFR; /* 11 */ |
__IO uint32_t MACPMTCSR; |
uint32_t RESERVED1[2]; |
__IO uint32_t MACSR; /* 15 */ |
__IO uint32_t MACIMR; |
__IO uint32_t MACA0HR; |
__IO uint32_t MACA0LR; |
__IO uint32_t MACA1HR; |
__IO uint32_t MACA1LR; |
__IO uint32_t MACA2HR; |
__IO uint32_t MACA2LR; |
__IO uint32_t MACA3HR; |
__IO uint32_t MACA3LR; /* 24 */ |
uint32_t RESERVED2[40]; |
__IO uint32_t MMCCR; /* 65 */ |
__IO uint32_t MMCRIR; |
__IO uint32_t MMCTIR; |
__IO uint32_t MMCRIMR; |
__IO uint32_t MMCTIMR; /* 69 */ |
uint32_t RESERVED3[14]; |
__IO uint32_t MMCTGFSCCR; /* 84 */ |
__IO uint32_t MMCTGFMSCCR; |
uint32_t RESERVED4[5]; |
__IO uint32_t MMCTGFCR; |
uint32_t RESERVED5[10]; |
__IO uint32_t MMCRFCECR; |
__IO uint32_t MMCRFAECR; |
uint32_t RESERVED6[10]; |
__IO uint32_t MMCRGUFCR; |
uint32_t RESERVED7[334]; |
__IO uint32_t PTPTSCR; |
__IO uint32_t PTPSSIR; |
__IO uint32_t PTPTSHR; |
__IO uint32_t PTPTSLR; |
__IO uint32_t PTPTSHUR; |
__IO uint32_t PTPTSLUR; |
__IO uint32_t PTPTSAR; |
__IO uint32_t PTPTTHR; |
__IO uint32_t PTPTTLR; |
uint32_t RESERVED8[567]; |
__IO uint32_t DMABMR; |
__IO uint32_t DMATPDR; |
__IO uint32_t DMARPDR; |
__IO uint32_t DMARDLAR; |
__IO uint32_t DMATDLAR; |
__IO uint32_t DMASR; |
__IO uint32_t DMAOMR; |
__IO uint32_t DMAIER; |
__IO uint32_t DMAMFBOCR; |
uint32_t RESERVED9[9]; |
__IO uint32_t DMACHTDR; |
__IO uint32_t DMACHRDR; |
__IO uint32_t DMACHTBAR; |
__IO uint32_t DMACHRBAR; |
} ETH_TypeDef; |
/** |
* @brief External Interrupt/Event Controller |
*/ |
typedef struct |
{ |
__IO uint32_t IMR; |
__IO uint32_t EMR; |
__IO uint32_t RTSR; |
__IO uint32_t FTSR; |
__IO uint32_t SWIER; |
__IO uint32_t PR; |
} EXTI_TypeDef; |
/** |
* @brief FLASH Registers |
*/ |
typedef struct |
{ |
__IO uint32_t ACR; |
__IO uint32_t KEYR; |
__IO uint32_t OPTKEYR; |
__IO uint32_t SR; |
__IO uint32_t CR; |
__IO uint32_t AR; |
__IO uint32_t RESERVED; |
__IO uint32_t OBR; |
__IO uint32_t WRPR; |
#ifdef STM32F10X_XL |
uint32_t RESERVED1[8]; |
__IO uint32_t KEYR2; |
uint32_t RESERVED2; |
__IO uint32_t SR2; |
__IO uint32_t CR2; |
__IO uint32_t AR2; |
#endif /* STM32F10X_XL */ |
} FLASH_TypeDef; |
/** |
* @brief Option Bytes Registers |
*/ |
typedef struct |
{ |
__IO uint16_t RDP; |
__IO uint16_t USER; |
__IO uint16_t Data0; |
__IO uint16_t Data1; |
__IO uint16_t WRP0; |
__IO uint16_t WRP1; |
__IO uint16_t WRP2; |
__IO uint16_t WRP3; |
} OB_TypeDef; |
/** |
* @brief Flexible Static Memory Controller |
*/ |
typedef struct |
{ |
__IO uint32_t BTCR[8]; |
} FSMC_Bank1_TypeDef; |
/** |
* @brief Flexible Static Memory Controller Bank1E |
*/ |
typedef struct |
{ |
__IO uint32_t BWTR[7]; |
} FSMC_Bank1E_TypeDef; |
/** |
* @brief Flexible Static Memory Controller Bank2 |
*/ |
typedef struct |
{ |
__IO uint32_t PCR2; |
__IO uint32_t SR2; |
__IO uint32_t PMEM2; |
__IO uint32_t PATT2; |
uint32_t RESERVED0; |
__IO uint32_t ECCR2; |
} FSMC_Bank2_TypeDef; |
/** |
* @brief Flexible Static Memory Controller Bank3 |
*/ |
typedef struct |
{ |
__IO uint32_t PCR3; |
__IO uint32_t SR3; |
__IO uint32_t PMEM3; |
__IO uint32_t PATT3; |
uint32_t RESERVED0; |
__IO uint32_t ECCR3; |
} FSMC_Bank3_TypeDef; |
/** |
* @brief Flexible Static Memory Controller Bank4 |
*/ |
typedef struct |
{ |
__IO uint32_t PCR4; |
__IO uint32_t SR4; |
__IO uint32_t PMEM4; |
__IO uint32_t PATT4; |
__IO uint32_t PIO4; |
} FSMC_Bank4_TypeDef; |
/** |
* @brief General Purpose I/O |
*/ |
typedef struct |
{ |
__IO uint32_t CRL; |
__IO uint32_t CRH; |
__IO uint32_t IDR; |
__IO uint32_t ODR; |
__IO uint32_t BSRR; |
__IO uint32_t BRR; |
__IO uint32_t LCKR; |
} GPIO_TypeDef; |
/** |
* @brief Alternate Function I/O |
*/ |
typedef struct |
{ |
__IO uint32_t EVCR; |
__IO uint32_t MAPR; |
__IO uint32_t EXTICR[4]; |
uint32_t RESERVED0; |
__IO uint32_t MAPR2; |
} AFIO_TypeDef; |
/** |
* @brief Inter-integrated Circuit Interface |
*/ |
typedef struct |
{ |
__IO uint16_t CR1; |
uint16_t RESERVED0; |
__IO uint16_t CR2; |
uint16_t RESERVED1; |
__IO uint16_t OAR1; |
uint16_t RESERVED2; |
__IO uint16_t OAR2; |
uint16_t RESERVED3; |
__IO uint16_t DR; |
uint16_t RESERVED4; |
__IO uint16_t SR1; |
uint16_t RESERVED5; |
__IO uint16_t SR2; |
uint16_t RESERVED6; |
__IO uint16_t CCR; |
uint16_t RESERVED7; |
__IO uint16_t TRISE; |
uint16_t RESERVED8; |
} I2C_TypeDef; |
/** |
* @brief Independent WATCHDOG |
*/ |
typedef struct |
{ |
__IO uint32_t KR; |
__IO uint32_t PR; |
__IO uint32_t RLR; |
__IO uint32_t SR; |
} IWDG_TypeDef; |
/** |
* @brief Power Control |
*/ |
typedef struct |
{ |
__IO uint32_t CR; |
__IO uint32_t CSR; |
} PWR_TypeDef; |
/** |
* @brief Reset and Clock Control |
*/ |
typedef struct |
{ |
__IO uint32_t CR; |
__IO uint32_t CFGR; |
__IO uint32_t CIR; |
__IO uint32_t APB2RSTR; |
__IO uint32_t APB1RSTR; |
__IO uint32_t AHBENR; |
__IO uint32_t APB2ENR; |
__IO uint32_t APB1ENR; |
__IO uint32_t BDCR; |
__IO uint32_t CSR; |
#ifdef STM32F10X_CL |
__IO uint32_t AHBRSTR; |
__IO uint32_t CFGR2; |
#endif /* STM32F10X_CL */ |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
uint32_t RESERVED0; |
__IO uint32_t CFGR2; |
#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ |
} RCC_TypeDef; |
/** |
* @brief Real-Time Clock |
*/ |
typedef struct |
{ |
__IO uint16_t CRH; |
uint16_t RESERVED0; |
__IO uint16_t CRL; |
uint16_t RESERVED1; |
__IO uint16_t PRLH; |
uint16_t RESERVED2; |
__IO uint16_t PRLL; |
uint16_t RESERVED3; |
__IO uint16_t DIVH; |
uint16_t RESERVED4; |
__IO uint16_t DIVL; |
uint16_t RESERVED5; |
__IO uint16_t CNTH; |
uint16_t RESERVED6; |
__IO uint16_t CNTL; |
uint16_t RESERVED7; |
__IO uint16_t ALRH; |
uint16_t RESERVED8; |
__IO uint16_t ALRL; |
uint16_t RESERVED9; |
} RTC_TypeDef; |
/** |
* @brief SD host Interface |
*/ |
typedef struct |
{ |
__IO uint32_t POWER; |
__IO uint32_t CLKCR; |
__IO uint32_t ARG; |
__IO uint32_t CMD; |
__I uint32_t RESPCMD; |
__I uint32_t RESP1; |
__I uint32_t RESP2; |
__I uint32_t RESP3; |
__I uint32_t RESP4; |
__IO uint32_t DTIMER; |
__IO uint32_t DLEN; |
__IO uint32_t DCTRL; |
__I uint32_t DCOUNT; |
__I uint32_t STA; |
__IO uint32_t ICR; |
__IO uint32_t MASK; |
uint32_t RESERVED0[2]; |
__I uint32_t FIFOCNT; |
uint32_t RESERVED1[13]; |
__IO uint32_t FIFO; |
} SDIO_TypeDef; |
/** |
* @brief Serial Peripheral Interface |
*/ |
typedef struct |
{ |
__IO uint16_t CR1; |
uint16_t RESERVED0; |
__IO uint16_t CR2; |
uint16_t RESERVED1; |
__IO uint16_t SR; |
uint16_t RESERVED2; |
__IO uint16_t DR; |
uint16_t RESERVED3; |
__IO uint16_t CRCPR; |
uint16_t RESERVED4; |
__IO uint16_t RXCRCR; |
uint16_t RESERVED5; |
__IO uint16_t TXCRCR; |
uint16_t RESERVED6; |
__IO uint16_t I2SCFGR; |
uint16_t RESERVED7; |
__IO uint16_t I2SPR; |
uint16_t RESERVED8; |
} SPI_TypeDef; |
/** |
* @brief TIM |
*/ |
typedef struct |
{ |
__IO uint16_t CR1; |
uint16_t RESERVED0; |
__IO uint16_t CR2; |
uint16_t RESERVED1; |
__IO uint16_t SMCR; |
uint16_t RESERVED2; |
__IO uint16_t DIER; |
uint16_t RESERVED3; |
__IO uint16_t SR; |
uint16_t RESERVED4; |
__IO uint16_t EGR; |
uint16_t RESERVED5; |
__IO uint16_t CCMR1; |
uint16_t RESERVED6; |
__IO uint16_t CCMR2; |
uint16_t RESERVED7; |
__IO uint16_t CCER; |
uint16_t RESERVED8; |
__IO uint16_t CNT; |
uint16_t RESERVED9; |
__IO uint16_t PSC; |
uint16_t RESERVED10; |
__IO uint16_t ARR; |
uint16_t RESERVED11; |
__IO uint16_t RCR; |
uint16_t RESERVED12; |
__IO uint16_t CCR1; |
uint16_t RESERVED13; |
__IO uint16_t CCR2; |
uint16_t RESERVED14; |
__IO uint16_t CCR3; |
uint16_t RESERVED15; |
__IO uint16_t CCR4; |
uint16_t RESERVED16; |
__IO uint16_t BDTR; |
uint16_t RESERVED17; |
__IO uint16_t DCR; |
uint16_t RESERVED18; |
__IO uint16_t DMAR; |
uint16_t RESERVED19; |
} TIM_TypeDef; |
/** |
* @brief Universal Synchronous Asynchronous Receiver Transmitter |
*/ |
typedef struct |
{ |
__IO uint16_t SR; |
uint16_t RESERVED0; |
__IO uint16_t DR; |
uint16_t RESERVED1; |
__IO uint16_t BRR; |
uint16_t RESERVED2; |
__IO uint16_t CR1; |
uint16_t RESERVED3; |
__IO uint16_t CR2; |
uint16_t RESERVED4; |
__IO uint16_t CR3; |
uint16_t RESERVED5; |
__IO uint16_t GTPR; |
uint16_t RESERVED6; |
} USART_TypeDef; |
/** |
* @brief Window WATCHDOG |
*/ |
typedef struct |
{ |
__IO uint32_t CR; |
__IO uint32_t CFR; |
__IO uint32_t SR; |
} WWDG_TypeDef; |
/** |
* @} |
*/ |
/** @addtogroup Peripheral_memory_map |
* @{ |
*/ |
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ |
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ |
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ |
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ |
/*!< Peripheral memory map */ |
#define APB1PERIPH_BASE PERIPH_BASE |
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
#define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
#define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
#define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
#define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
#define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
#define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
#define CEC_BASE (APB1PERIPH_BASE + 0x7800) |
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
#define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
#define SDIO_BASE (PERIPH_BASE + 0x18000) |
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
#define RCC_BASE (AHBPERIPH_BASE + 0x1000) |
#define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ |
#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ |
#define ETH_BASE (AHBPERIPH_BASE + 0x8000) |
#define ETH_MAC_BASE (ETH_BASE) |
#define ETH_MMC_BASE (ETH_BASE + 0x0100) |
#define ETH_PTP_BASE (ETH_BASE + 0x0700) |
#define ETH_DMA_BASE (ETH_BASE + 0x1000) |
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ |
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ |
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ |
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ |
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ |
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ |
/** |
* @} |
*/ |
/** @addtogroup Peripheral_declaration |
* @{ |
*/ |
#define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
#define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
#define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
#define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
#define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
#define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
#define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
#define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
#define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
#define RTC ((RTC_TypeDef *) RTC_BASE) |
#define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
#define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
#define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
#define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
#define USART2 ((USART_TypeDef *) USART2_BASE) |
#define USART3 ((USART_TypeDef *) USART3_BASE) |
#define UART4 ((USART_TypeDef *) UART4_BASE) |
#define UART5 ((USART_TypeDef *) UART5_BASE) |
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
#define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
#define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
#define CAN2 ((CAN_TypeDef *) CAN2_BASE) |
#define BKP ((BKP_TypeDef *) BKP_BASE) |
#define PWR ((PWR_TypeDef *) PWR_BASE) |
#define DAC ((DAC_TypeDef *) DAC_BASE) |
#define CEC ((CEC_TypeDef *) CEC_BASE) |
#define AFIO ((AFIO_TypeDef *) AFIO_BASE) |
#define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
#define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
#define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
#define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
#define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
#define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
#define USART1 ((USART_TypeDef *) USART1_BASE) |
#define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
#define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
#define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
#define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
#define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
#define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
#define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
#define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
#define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
#define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
#define RCC ((RCC_TypeDef *) RCC_BASE) |
#define CRC ((CRC_TypeDef *) CRC_BASE) |
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
#define OB ((OB_TypeDef *) OB_BASE) |
#define ETH ((ETH_TypeDef *) ETH_BASE) |
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) |
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) |
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) |
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) |
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) |
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
/** |
* @} |
*/ |
/** @addtogroup Exported_constants |
* @{ |
*/ |
/** @addtogroup Peripheral_Registers_Bits_Definition |
* @{ |
*/ |
/******************************************************************************/ |
/* Peripheral Registers_Bits_Definition */ |
/******************************************************************************/ |
/******************************************************************************/ |
/* */ |
/* CRC calculation unit */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for CRC_DR register *********************/ |
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
/******************* Bit definition for CRC_IDR register ********************/ |
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
/******************** Bit definition for CRC_CR register ********************/ |
#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ |
/******************************************************************************/ |
/* */ |
/* Power Control */ |
/* */ |
/******************************************************************************/ |
/******************** Bit definition for PWR_CR register ********************/ |
#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ |
#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ |
#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ |
#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ |
#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ |
#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ |
#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ |
#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ |
#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ |
/*!< PVD level configuration */ |
#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ |
#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ |
#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ |
#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ |
#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ |
#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ |
#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ |
#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ |
#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ |
/******************* Bit definition for PWR_CSR register ********************/ |
#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ |
#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ |
#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ |
#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ |
/******************************************************************************/ |
/* */ |
/* Backup registers */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for BKP_DR1 register ********************/ |
#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR2 register ********************/ |
#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR3 register ********************/ |
#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR4 register ********************/ |
#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR5 register ********************/ |
#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR6 register ********************/ |
#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR7 register ********************/ |
#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR8 register ********************/ |
#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR9 register ********************/ |
#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR10 register *******************/ |
#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR11 register *******************/ |
#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR12 register *******************/ |
#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR13 register *******************/ |
#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR14 register *******************/ |
#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR15 register *******************/ |
#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR16 register *******************/ |
#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR17 register *******************/ |
#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/****************** Bit definition for BKP_DR18 register ********************/ |
#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR19 register *******************/ |
#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR20 register *******************/ |
#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR21 register *******************/ |
#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR22 register *******************/ |
#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR23 register *******************/ |
#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR24 register *******************/ |
#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR25 register *******************/ |
#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR26 register *******************/ |
#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR27 register *******************/ |
#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR28 register *******************/ |
#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR29 register *******************/ |
#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR30 register *******************/ |
#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR31 register *******************/ |
#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR32 register *******************/ |
#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR33 register *******************/ |
#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR34 register *******************/ |
#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR35 register *******************/ |
#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR36 register *******************/ |
#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR37 register *******************/ |
#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR38 register *******************/ |
#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR39 register *******************/ |
#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR40 register *******************/ |
#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR41 register *******************/ |
#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/******************* Bit definition for BKP_DR42 register *******************/ |
#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ |
/****************** Bit definition for BKP_RTCCR register *******************/ |
#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ |
#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ |
#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ |
#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ |
/******************** Bit definition for BKP_CR register ********************/ |
#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ |
#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ |
/******************* Bit definition for BKP_CSR register ********************/ |
#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ |
#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ |
#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ |
#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ |
#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ |
/******************************************************************************/ |
/* */ |
/* Reset and Clock Control */ |
/* */ |
/******************************************************************************/ |
/******************** Bit definition for RCC_CR register ********************/ |
#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ |
#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ |
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ |
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ |
#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ |
#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ |
#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ |
#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ |
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ |
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ |
#ifdef STM32F10X_CL |
#define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ |
#define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ |
#define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ |
#define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ |
#endif /* STM32F10X_CL */ |
/******************* Bit definition for RCC_CFGR register *******************/ |
/*!< SW configuration */ |
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ |
/*!< SWS configuration */ |
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ |
/*!< HPRE configuration */ |
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
/*!< PPRE1 configuration */ |
#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ |
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ |
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ |
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ |
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ |
/*!< PPRE2 configuration */ |
#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ |
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ |
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ |
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ |
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ |
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ |
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ |
/*!< ADCPPRE configuration */ |
#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ |
#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ |
#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ |
#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ |
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ |
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ |
/*!< PLLMUL configuration */ |
#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ |
#ifdef STM32F10X_CL |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ |
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ |
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ |
#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ |
#define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ |
/*!< MCO configuration */ |
#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
#define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ |
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ |
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ |
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ |
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ |
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ |
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ |
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
/*!< MCO configuration */ |
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
#else |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ |
#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ |
#define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ |
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ |
/*!< MCO configuration */ |
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
#endif /* STM32F10X_CL */ |
/*!<****************** Bit definition for RCC_CIR register ********************/ |
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ |
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ |
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ |
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ |
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ |
#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ |
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ |
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ |
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ |
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ |
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ |
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ |
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ |
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ |
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ |
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ |
#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ |
#ifdef STM32F10X_CL |
#define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ |
#define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ |
#define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ |
#define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ |
#define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ |
#define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ |
#endif /* STM32F10X_CL */ |
/***************** Bit definition for RCC_APB2RSTR register *****************/ |
#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ |
#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ |
#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ |
#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ |
#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ |
#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ |
#endif |
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ |
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ |
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ |
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ |
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ |
#endif |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
#if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ |
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ |
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ |
#define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ |
#endif |
#if defined (STM32F10X_HD_VL) |
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ |
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ |
#endif |
#ifdef STM32F10X_XL |
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ |
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ |
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ |
#endif /* STM32F10X_XL */ |
/***************** Bit definition for RCC_APB1RSTR register *****************/ |
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ |
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ |
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ |
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ |
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ |
#endif |
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ |
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ |
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ |
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ |
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) |
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ |
#endif |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) |
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ |
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ |
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ |
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ |
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ |
#endif |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ |
#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ |
#endif |
#if defined (STM32F10X_HD_VL) |
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ |
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ |
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ |
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ |
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ |
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ |
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ |
#endif |
#ifdef STM32F10X_CL |
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ |
#endif /* STM32F10X_CL */ |
#ifdef STM32F10X_XL |
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ |
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ |
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ |
#endif /* STM32F10X_XL */ |
/****************** Bit definition for RCC_AHBENR register ******************/ |
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ |
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ |
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ |
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) |
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ |
#endif |
#if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ |
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ |
#endif |
#if defined (STM32F10X_HD_VL) |
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ |
#endif |
#ifdef STM32F10X_CL |
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ |
#define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ |
#define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ |
#define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ |
#endif /* STM32F10X_CL */ |
/****************** Bit definition for RCC_APB2ENR register *****************/ |
#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ |
#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ |
#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ |
#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ |
#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ |
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ |
#endif |
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ |
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ |
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ |
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ |
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ |
#endif |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
#if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ |
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ |
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ |
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ |
#endif |
#if defined (STM32F10X_HD_VL) |
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ |
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ |
#endif |
#ifdef STM32F10X_XL |
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ |
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ |
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ |
#endif |
/***************** Bit definition for RCC_APB1ENR register ******************/ |
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ |
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ |
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ |
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ |
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ |
#endif |
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ |
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ |
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ |
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ |
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) |
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ |
#endif |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) |
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ |
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ |
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ |
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ |
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ |
#endif |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ |
#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ |
#endif |
#ifdef STM32F10X_HD_VL |
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ |
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ |
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ |
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ |
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ |
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ |
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ |
#endif /* STM32F10X_HD_VL */ |
#ifdef STM32F10X_CL |
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ |
#endif /* STM32F10X_CL */ |
#ifdef STM32F10X_XL |
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ |
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ |
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ |
#endif /* STM32F10X_XL */ |
/******************* Bit definition for RCC_BDCR register *******************/ |
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ |
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ |
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ |
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
/*!< RTC congiguration */ |
#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ |
#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ |
#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ |
#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ |
/******************* Bit definition for RCC_CSR register ********************/ |
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ |
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ |
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ |
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ |
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ |
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ |
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ |
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ |
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ |
#ifdef STM32F10X_CL |
/******************* Bit definition for RCC_AHBRSTR register ****************/ |
#define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ |
#define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ |
/******************* Bit definition for RCC_CFGR2 register ******************/ |
/*!< PREDIV1 configuration */ |
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ |
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ |
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ |
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ |
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ |
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ |
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ |
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ |
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ |
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ |
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ |
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ |
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ |
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ |
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ |
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ |
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ |
/*!< PREDIV2 configuration */ |
#define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ |
#define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
#define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
#define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
#define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ |
#define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ |
#define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ |
#define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ |
#define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ |
#define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ |
#define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ |
#define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ |
#define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ |
#define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ |
#define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ |
#define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ |
#define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ |
#define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ |
#define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ |
#define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ |
/*!< PLL2MUL configuration */ |
#define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ |
#define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
#define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
#define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
#define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
#define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ |
#define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ |
#define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ |
#define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ |
#define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ |
#define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ |
#define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ |
#define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ |
#define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ |
/*!< PLL3MUL configuration */ |
#define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ |
#define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
#define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
#define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
#define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ |
#define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ |
#define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ |
#define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ |
#define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ |
#define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ |
#define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ |
#define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ |
#define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ |
#define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ |
#define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ |
#define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ |
#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ |
#define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ |
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ |
#endif /* STM32F10X_CL */ |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
/******************* Bit definition for RCC_CFGR2 register ******************/ |
/*!< PREDIV1 configuration */ |
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ |
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ |
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ |
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ |
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ |
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ |
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ |
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ |
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ |
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ |
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ |
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ |
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ |
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ |
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ |
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ |
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ |
#endif |
/******************************************************************************/ |
/* */ |
/* General Purpose and Alternate Function I/O */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for GPIO_CRL register *******************/ |
#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
/******************* Bit definition for GPIO_CRH register *******************/ |
#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
/*!<****************** Bit definition for GPIO_IDR register *******************/ |
#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ |
#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ |
#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ |
#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ |
#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ |
#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ |
#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ |
#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ |
#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ |
#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ |
#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ |
#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ |
#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ |
#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ |
#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ |
#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ |
/******************* Bit definition for GPIO_ODR register *******************/ |
#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ |
#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ |
#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ |
#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ |
#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ |
#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ |
#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ |
#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ |
#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ |
#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ |
#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ |
#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ |
#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ |
#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ |
#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ |
#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ |
/****************** Bit definition for GPIO_BSRR register *******************/ |
#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ |
#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ |
#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ |
#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ |
#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ |
#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ |
#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ |
#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ |
#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ |
#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ |
#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ |
#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ |
#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ |
#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ |
#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ |
#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ |
#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ |
#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ |
#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ |
#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ |
#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ |
#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ |
#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ |
#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ |
#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ |
#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ |
#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ |
#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ |
#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ |
#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ |
#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ |
#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ |
/******************* Bit definition for GPIO_BRR register *******************/ |
#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ |
#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ |
#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ |
#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ |
#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ |
#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ |
#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ |
#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ |
#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ |
#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ |
#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ |
#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ |
#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ |
#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ |
#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ |
#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ |
/****************** Bit definition for GPIO_LCKR register *******************/ |
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ |
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ |
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ |
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ |
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ |
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ |
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ |
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ |
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ |
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ |
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ |
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ |
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ |
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ |
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ |
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ |
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ |
/*----------------------------------------------------------------------------*/ |
/****************** Bit definition for AFIO_EVCR register *******************/ |
#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ |
#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ |
#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ |
#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ |
#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ |
/*!< PIN configuration */ |
#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ |
#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ |
#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ |
#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ |
#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ |
#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ |
#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ |
#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ |
#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ |
#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ |
#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ |
#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ |
#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ |
#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ |
#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ |
#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ |
#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ |
#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ |
#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ |
#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ |
/*!< PORT configuration */ |
#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ |
#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ |
#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ |
#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ |
#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ |
#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ |
/****************** Bit definition for AFIO_MAPR register *******************/ |
#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ |
#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ |
#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ |
#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ |
#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
/* USART3_REMAP configuration */ |
#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
/*!< TIM1_REMAP configuration */ |
#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
/*!< TIM2_REMAP configuration */ |
#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
/*!< TIM3_REMAP configuration */ |
#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ |
#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ |
#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
/*!< CAN_REMAP configuration */ |
#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ |
#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ |
#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ |
#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ |
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ |
#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ |
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ |
#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ |
/*!< SWJ_CFG configuration */ |
#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ |
#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ |
#ifdef STM32F10X_CL |
/*!< ETH_REMAP configuration */ |
#define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ |
/*!< CAN2_REMAP configuration */ |
#define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ |
/*!< MII_RMII_SEL configuration */ |
#define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ |
/*!< SPI3_REMAP configuration */ |
#define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ |
/*!< TIM2ITR1_IREMAP configuration */ |
#define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ |
/*!< PTP_PPS_REMAP configuration */ |
#define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ |
#endif |
/***************** Bit definition for AFIO_EXTICR1 register *****************/ |
#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ |
#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ |
#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ |
#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ |
/*!< EXTI0 configuration */ |
#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ |
#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ |
#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ |
#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ |
#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ |
#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ |
#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ |
/*!< EXTI1 configuration */ |
#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ |
#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ |
#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ |
#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ |
#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ |
#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ |
#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ |
/*!< EXTI2 configuration */ |
#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ |
#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ |
#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ |
#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ |
#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ |
#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ |
#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ |
/*!< EXTI3 configuration */ |
#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ |
#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ |
#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ |
#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ |
#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ |
#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ |
#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ |
/***************** Bit definition for AFIO_EXTICR2 register *****************/ |
#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ |
#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ |
#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ |
#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ |
/*!< EXTI4 configuration */ |
#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ |
#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ |
#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ |
#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ |
#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ |
#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ |
#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ |
/* EXTI5 configuration */ |
#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ |
#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ |
#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ |
#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ |
#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ |
#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ |
#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ |
/*!< EXTI6 configuration */ |
#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ |
#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ |
#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ |
#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ |
#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ |
#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ |
#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ |
/*!< EXTI7 configuration */ |
#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ |
#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ |
#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ |
#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ |
#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ |
#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ |
#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ |
/***************** Bit definition for AFIO_EXTICR3 register *****************/ |
#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ |
#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ |
#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ |
#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ |
/*!< EXTI8 configuration */ |
#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ |
#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ |
#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ |
#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ |
#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ |
#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ |
#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ |
/*!< EXTI9 configuration */ |
#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ |
#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ |
#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ |
#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ |
#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ |
#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ |
#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ |
/*!< EXTI10 configuration */ |
#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ |
#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ |
#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ |
#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ |
#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ |
#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ |
#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ |
/*!< EXTI11 configuration */ |
#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ |
#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ |
#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ |
#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ |
#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ |
#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ |
#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ |
/***************** Bit definition for AFIO_EXTICR4 register *****************/ |
#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ |
#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ |
#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ |
#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ |
/* EXTI12 configuration */ |
#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ |
#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ |
#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ |
#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ |
#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ |
#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ |
#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ |
/* EXTI13 configuration */ |
#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ |
#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ |
#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ |
#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ |
#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ |
#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ |
#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ |
/*!< EXTI14 configuration */ |
#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ |
#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ |
#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ |
#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ |
#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ |
#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ |
#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ |
/*!< EXTI15 configuration */ |
#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ |
#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ |
#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ |
#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ |
#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ |
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ |
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
/****************** Bit definition for AFIO_MAPR2 register ******************/ |
#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ |
#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ |
#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ |
#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ |
#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ |
#endif |
#ifdef STM32F10X_HD_VL |
#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ |
#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ |
#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ |
#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ |
#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ |
#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ |
#endif |
#ifdef STM32F10X_XL |
/****************** Bit definition for AFIO_MAPR2 register ******************/ |
#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ |
#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ |
#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ |
#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ |
#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ |
#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ |
#endif |
/******************************************************************************/ |
/* */ |
/* SystemTick */ |
/* */ |
/******************************************************************************/ |
/***************** Bit definition for SysTick_CTRL register *****************/ |
#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ |
#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ |
#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ |
#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ |
/***************** Bit definition for SysTick_LOAD register *****************/ |
#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ |
/***************** Bit definition for SysTick_VAL register ******************/ |
#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ |
/***************** Bit definition for SysTick_CALIB register ****************/ |
#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ |
#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ |
#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ |
/******************************************************************************/ |
/* */ |
/* Nested Vectored Interrupt Controller */ |
/* */ |
/******************************************************************************/ |
/****************** Bit definition for NVIC_ISER register *******************/ |
#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ |
#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
/****************** Bit definition for NVIC_ICER register *******************/ |
#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ |
#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
/****************** Bit definition for NVIC_ISPR register *******************/ |
#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ |
#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
/****************** Bit definition for NVIC_ICPR register *******************/ |
#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ |
#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
/****************** Bit definition for NVIC_IABR register *******************/ |
#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ |
#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
/****************** Bit definition for NVIC_PRI0 register *******************/ |
#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ |
#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ |
#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ |
#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ |
/****************** Bit definition for NVIC_PRI1 register *******************/ |
#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ |
#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ |
#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ |
#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ |
/****************** Bit definition for NVIC_PRI2 register *******************/ |
#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ |
#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ |
#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ |
#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ |
/****************** Bit definition for NVIC_PRI3 register *******************/ |
#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ |
#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ |
#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ |
#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ |
/****************** Bit definition for NVIC_PRI4 register *******************/ |
#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ |
#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ |
#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ |
#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ |
/****************** Bit definition for NVIC_PRI5 register *******************/ |
#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ |
#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ |
#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ |
#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ |
/****************** Bit definition for NVIC_PRI6 register *******************/ |
#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ |
#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ |
#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ |
#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ |
/****************** Bit definition for NVIC_PRI7 register *******************/ |
#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ |
#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ |
#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ |
#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ |
/****************** Bit definition for SCB_CPUID register *******************/ |
#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ |
#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ |
#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ |
#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ |
#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ |
/******************* Bit definition for SCB_ICSR register *******************/ |
#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ |
#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ |
#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ |
#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ |
#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ |
#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ |
#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ |
#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ |
#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ |
#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ |
/******************* Bit definition for SCB_VTOR register *******************/ |
#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ |
#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ |
/*!<***************** Bit definition for SCB_AIRCR register *******************/ |
#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ |
#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ |
#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ |
#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ |
#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
/* prority group configuration */ |
#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ |
#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ |
#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ |
#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ |
#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ |
#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ |
#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ |
#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ |
#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ |
#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ |
/******************* Bit definition for SCB_SCR register ********************/ |
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ |
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ |
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ |
/******************** Bit definition for SCB_CCR register *******************/ |
#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ |
#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ |
#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ |
#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ |
#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ |
#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ |
/******************* Bit definition for SCB_SHPR register ********************/ |
#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ |
#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ |
#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ |
#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ |
/****************** Bit definition for SCB_SHCSR register *******************/ |
#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ |
#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ |
#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ |
#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ |
#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ |
#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ |
#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ |
#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ |
#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ |
#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ |
#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ |
#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ |
#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ |
#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ |
/******************* Bit definition for SCB_CFSR register *******************/ |
/*!< MFSR */ |
#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ |
#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ |
#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ |
#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ |
#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ |
/*!< BFSR */ |
#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ |
#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ |
#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ |
#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ |
#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ |
#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ |
/*!< UFSR */ |
#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ |
#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ |
#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ |
#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ |
#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ |
#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ |
/******************* Bit definition for SCB_HFSR register *******************/ |
#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ |
#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ |
#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ |
/******************* Bit definition for SCB_DFSR register *******************/ |
#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ |
#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ |
#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ |
#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ |
#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ |
/******************* Bit definition for SCB_MMFAR register ******************/ |
#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ |
/******************* Bit definition for SCB_BFAR register *******************/ |
#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ |
/******************* Bit definition for SCB_afsr register *******************/ |
#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ |
/******************************************************************************/ |
/* */ |
/* External Interrupt/Event Controller */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for EXTI_IMR register *******************/ |
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
/******************* Bit definition for EXTI_EMR register *******************/ |
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
/****************** Bit definition for EXTI_RTSR register *******************/ |
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ |
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
/****************** Bit definition for EXTI_FTSR register *******************/ |
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ |
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
/****************** Bit definition for EXTI_SWIER register ******************/ |
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ |
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
/******************* Bit definition for EXTI_PR register ********************/ |
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ |
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
/******************************************************************************/ |
/* */ |
/* DMA Controller */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for DMA_ISR register ********************/ |
#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ |
#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ |
#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ |
#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ |
#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ |
#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ |
#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ |
#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ |
#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ |
#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ |
#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ |
#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ |
#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ |
#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ |
#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ |
#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ |
#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ |
#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ |
#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ |
#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ |
#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ |
#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ |
#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ |
#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ |
#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ |
#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ |
#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ |
#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ |
/******************* Bit definition for DMA_IFCR register *******************/ |
#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ |
#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ |
#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ |
#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ |
#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ |
#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ |
#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ |
#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ |
#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ |
#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ |
#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ |
#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ |
#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ |
#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ |
#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ |
#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ |
#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ |
#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ |
#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ |
#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ |
#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ |
#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ |
#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ |
#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ |
#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ |
#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ |
#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ |
#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ |
/******************* Bit definition for DMA_CCR1 register *******************/ |
#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ |
#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ |
#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
/******************* Bit definition for DMA_CCR2 register *******************/ |
#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ |
#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ |
#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
/******************* Bit definition for DMA_CCR3 register *******************/ |
#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ |
#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
/*!<****************** Bit definition for DMA_CCR4 register *******************/ |
#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */ |
#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */ |
/****************** Bit definition for DMA_CCR5 register *******************/ |
#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */ |
#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */ |
/******************* Bit definition for DMA_CCR6 register *******************/ |
#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */ |
#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */ |
/******************* Bit definition for DMA_CCR7 register *******************/ |
#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */ |
#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */ |
/****************** Bit definition for DMA_CNDTR1 register ******************/ |
#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
/****************** Bit definition for DMA_CNDTR2 register ******************/ |
#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
/****************** Bit definition for DMA_CNDTR3 register ******************/ |
#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
/****************** Bit definition for DMA_CNDTR4 register ******************/ |
#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
/****************** Bit definition for DMA_CNDTR5 register ******************/ |
#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
/****************** Bit definition for DMA_CNDTR6 register ******************/ |
#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
/****************** Bit definition for DMA_CNDTR7 register ******************/ |
#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
/****************** Bit definition for DMA_CPAR1 register *******************/ |
#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
/****************** Bit definition for DMA_CPAR2 register *******************/ |
#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
/****************** Bit definition for DMA_CPAR3 register *******************/ |
#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
/****************** Bit definition for DMA_CPAR4 register *******************/ |
#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
/****************** Bit definition for DMA_CPAR5 register *******************/ |
#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
/****************** Bit definition for DMA_CPAR6 register *******************/ |
#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
/****************** Bit definition for DMA_CPAR7 register *******************/ |
#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
/****************** Bit definition for DMA_CMAR1 register *******************/ |
#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
/****************** Bit definition for DMA_CMAR2 register *******************/ |
#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
/****************** Bit definition for DMA_CMAR3 register *******************/ |
#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
/****************** Bit definition for DMA_CMAR4 register *******************/ |
#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
/****************** Bit definition for DMA_CMAR5 register *******************/ |
#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
/****************** Bit definition for DMA_CMAR6 register *******************/ |
#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
/****************** Bit definition for DMA_CMAR7 register *******************/ |
#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
/******************************************************************************/ |
/* */ |
/* Analog to Digital Converter */ |
/* */ |
/******************************************************************************/ |
/******************** Bit definition for ADC_SR register ********************/ |
#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */ |
#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */ |
#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */ |
#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */ |
#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */ |
/******************* Bit definition for ADC_CR1 register ********************/ |
#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */ |
#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */ |
#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */ |
#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */ |
#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */ |
#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */ |
#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */ |
#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */ |
#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */ |
#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */ |
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */ |
/******************* Bit definition for ADC_CR2 register ********************/ |
#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */ |
#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */ |
#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */ |
#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */ |
#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */ |
#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */ |
#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */ |
#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */ |
#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */ |
#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */ |
#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */ |
#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */ |
#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */ |
/****************** Bit definition for ADC_SMPR1 register *******************/ |
#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ |
#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ |
#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ |
#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ |
#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ |
#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ |
#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ |
#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */ |
#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ |
#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
/****************** Bit definition for ADC_SMPR2 register *******************/ |
#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ |
#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ |
#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ |
#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ |
#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ |
#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ |
#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ |
#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */ |
#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ |
#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ |
#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ |
#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */ |
#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */ |
#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */ |
/****************** Bit definition for ADC_JOFR1 register *******************/ |
#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */ |
/****************** Bit definition for ADC_JOFR2 register *******************/ |
#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */ |
/****************** Bit definition for ADC_JOFR3 register *******************/ |
#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */ |
/****************** Bit definition for ADC_JOFR4 register *******************/ |
#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */ |
/******************* Bit definition for ADC_HTR register ********************/ |
#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */ |
/******************* Bit definition for ADC_LTR register ********************/ |
#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */ |
/******************* Bit definition for ADC_SQR1 register *******************/ |
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ |
#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ |
#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ |
#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ |
#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */ |
#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
/******************* Bit definition for ADC_SQR2 register *******************/ |
#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ |
#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ |
#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ |
#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ |
#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ |
#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */ |
#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ |
#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */ |
#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */ |
#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */ |
#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */ |
#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */ |
/******************* Bit definition for ADC_SQR3 register *******************/ |
#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ |
#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ |
#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ |
#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ |
#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ |
#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */ |
#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ |
#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */ |
#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */ |
#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */ |
#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */ |
#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */ |
/******************* Bit definition for ADC_JSQR register *******************/ |
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ |
#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ |
#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */ |
#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
/******************* Bit definition for ADC_JDR1 register *******************/ |
#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
/******************* Bit definition for ADC_JDR2 register *******************/ |
#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
/******************* Bit definition for ADC_JDR3 register *******************/ |
#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
/******************* Bit definition for ADC_JDR4 register *******************/ |
#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
/******************** Bit definition for ADC_DR register ********************/ |
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */ |
#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */ |
/******************************************************************************/ |
/* */ |
/* Digital to Analog Converter */ |
/* */ |
/******************************************************************************/ |
/******************** Bit definition for DAC_CR register ********************/ |
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */ |
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */ |
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */ |
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ |
#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */ |
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */ |
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */ |
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */ |
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ |
#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */ |
#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */ |
#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */ |
#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */ |
#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */ |
#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */ |
/***************** Bit definition for DAC_SWTRIGR register ******************/ |
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */ |
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */ |
/***************** Bit definition for DAC_DHR12R1 register ******************/ |
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */ |
/***************** Bit definition for DAC_DHR12L1 register ******************/ |
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */ |
/****************** Bit definition for DAC_DHR8R1 register ******************/ |
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */ |
/***************** Bit definition for DAC_DHR12R2 register ******************/ |
#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */ |
/***************** Bit definition for DAC_DHR12L2 register ******************/ |
#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */ |
/****************** Bit definition for DAC_DHR8R2 register ******************/ |
#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */ |
/***************** Bit definition for DAC_DHR12RD register ******************/ |
#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */ |
#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */ |
/***************** Bit definition for DAC_DHR12LD register ******************/ |
#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */ |
#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */ |
/****************** Bit definition for DAC_DHR8RD register ******************/ |
#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */ |
#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */ |
/******************* Bit definition for DAC_DOR1 register *******************/ |
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */ |
/******************* Bit definition for DAC_DOR2 register *******************/ |
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */ |
/******************** Bit definition for DAC_SR register ********************/ |
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */ |
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */ |
/******************************************************************************/ |
/* */ |
/* CEC */ |
/* */ |
/******************************************************************************/ |
/******************** Bit definition for CEC_CFGR register ******************/ |
#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ |
#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ |
#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ |
#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ |
/******************** Bit definition for CEC_OAR register ******************/ |
#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ |
#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ |
#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ |
/******************** Bit definition for CEC_PRES register ******************/ |
#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ |
/******************** Bit definition for CEC_ESR register ******************/ |
#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ |
#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ |
#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ |
#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ |
#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ |
#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ |
#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */ |
/******************** Bit definition for CEC_CSR register ******************/ |
#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ |
#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ |
#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ |
#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ |
#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ |
#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ |
#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ |
#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ |
/******************** Bit definition for CEC_TXD register ******************/ |
#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ |
/******************** Bit definition for CEC_RXD register ******************/ |
#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ |
/******************************************************************************/ |
/* */ |
/* TIM */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for TIM_CR1 register ********************/ |
#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */ |
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ |
#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */ |
#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */ |
#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */ |
#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */ |
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */ |
#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */ |
#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ |
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
/******************* Bit definition for TIM_CR2 register ********************/ |
#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */ |
#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */ |
#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */ |
#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */ |
#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */ |
#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ |
#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ |
#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ |
#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ |
#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ |
#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ |
#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ |
/******************* Bit definition for TIM_SMCR register *******************/ |
#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */ |
#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */ |
#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */ |
#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */ |
#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */ |
#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */ |
#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */ |
#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */ |
#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */ |
/******************* Bit definition for TIM_DIER register *******************/ |
#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */ |
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ |
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ |
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ |
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ |
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */ |
#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */ |
#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */ |
#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */ |
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ |
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ |
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ |
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ |
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */ |
#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */ |
/******************** Bit definition for TIM_SR register ********************/ |
#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */ |
#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ |
#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ |
#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ |
#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ |
#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */ |
#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */ |
#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */ |
#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ |
#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ |
#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ |
#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ |
/******************* Bit definition for TIM_EGR register ********************/ |
#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */ |
#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */ |
#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */ |
#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */ |
#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */ |
#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */ |
#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */ |
#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */ |
/****************** Bit definition for TIM_CCMR1 register *******************/ |
#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */ |
#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */ |
#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */ |
#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */ |
#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */ |
#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */ |
/*----------------------------------------------------------------------------*/ |
#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ |
#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ |
#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */ |
/****************** Bit definition for TIM_CCMR2 register *******************/ |
#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */ |
#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */ |
#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */ |
#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */ |
#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */ |
#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */ |
/*----------------------------------------------------------------------------*/ |
#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ |
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ |
#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */ |
/******************* Bit definition for TIM_CCER register *******************/ |
#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */ |
#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */ |
#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ |
#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ |
#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */ |
#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */ |
#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ |
#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ |
#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */ |
#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */ |
#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ |
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ |
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */ |
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */ |
#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ |
/******************* Bit definition for TIM_CNT register ********************/ |
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */ |
/******************* Bit definition for TIM_PSC register ********************/ |
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */ |
/******************* Bit definition for TIM_ARR register ********************/ |
#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */ |
/******************* Bit definition for TIM_RCR register ********************/ |
#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */ |
/******************* Bit definition for TIM_CCR1 register *******************/ |
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ |
/******************* Bit definition for TIM_CCR2 register *******************/ |
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ |
/******************* Bit definition for TIM_CCR3 register *******************/ |
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ |
/******************* Bit definition for TIM_CCR4 register *******************/ |
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ |
/******************* Bit definition for TIM_BDTR register *******************/ |
#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */ |
#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */ |
#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */ |
#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */ |
#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */ |
#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */ |
#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */ |
#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */ |
#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */ |
#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */ |
/******************* Bit definition for TIM_DCR register ********************/ |
#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ |
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ |
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */ |
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */ |
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */ |
/******************* Bit definition for TIM_DMAR register *******************/ |
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ |
/******************************************************************************/ |
/* */ |
/* Real-Time Clock */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for RTC_CRH register ********************/ |
#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */ |
#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */ |
#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */ |
/******************* Bit definition for RTC_CRL register ********************/ |
#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */ |
#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */ |
#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */ |
#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */ |
#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */ |
#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */ |
/******************* Bit definition for RTC_PRLH register *******************/ |
#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */ |
/******************* Bit definition for RTC_PRLL register *******************/ |
#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */ |
/******************* Bit definition for RTC_DIVH register *******************/ |
#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */ |
/******************* Bit definition for RTC_DIVL register *******************/ |
#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */ |
/******************* Bit definition for RTC_CNTH register *******************/ |
#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */ |
/******************* Bit definition for RTC_CNTL register *******************/ |
#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */ |
/******************* Bit definition for RTC_ALRH register *******************/ |
#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */ |
/******************* Bit definition for RTC_ALRL register *******************/ |
#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */ |
/******************************************************************************/ |
/* */ |
/* Independent WATCHDOG */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for IWDG_KR register ********************/ |
#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */ |
/******************* Bit definition for IWDG_PR register ********************/ |
#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */ |
#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */ |
#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */ |
#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */ |
/******************* Bit definition for IWDG_RLR register *******************/ |
#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */ |
/******************* Bit definition for IWDG_SR register ********************/ |
#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */ |
#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */ |
/******************************************************************************/ |
/* */ |
/* Window WATCHDOG */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for WWDG_CR register ********************/ |
#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */ |
#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */ |
#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */ |
#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */ |
#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */ |
#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */ |
#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */ |
#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */ |
/******************* Bit definition for WWDG_CFR register *******************/ |
#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */ |
#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */ |
#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */ |
#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */ |
#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */ |
#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */ |
#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */ |
#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */ |
#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */ |
#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */ |
#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */ |
#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */ |
/******************* Bit definition for WWDG_SR register ********************/ |
#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */ |
/******************************************************************************/ |
/* */ |
/* Flexible Static Memory Controller */ |
/* */ |
/******************************************************************************/ |
/****************** Bit definition for FSMC_BCR1 register *******************/ |
#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
/****************** Bit definition for FSMC_BCR2 register *******************/ |
#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
/****************** Bit definition for FSMC_BCR3 register *******************/ |
#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */ |
#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
/****************** Bit definition for FSMC_BCR4 register *******************/ |
#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
/****************** Bit definition for FSMC_BTR1 register ******************/ |
#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
/****************** Bit definition for FSMC_BTR2 register *******************/ |
#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
/******************* Bit definition for FSMC_BTR3 register *******************/ |
#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
/****************** Bit definition for FSMC_BTR4 register *******************/ |
#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
/****************** Bit definition for FSMC_BWTR1 register ******************/ |
#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
/****************** Bit definition for FSMC_BWTR2 register ******************/ |
#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ |
#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
/****************** Bit definition for FSMC_BWTR3 register ******************/ |
#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
/****************** Bit definition for FSMC_BWTR4 register ******************/ |
#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
/****************** Bit definition for FSMC_PCR2 register *******************/ |
#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */ |
#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
/****************** Bit definition for FSMC_PCR3 register *******************/ |
#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ |
#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
/****************** Bit definition for FSMC_PCR4 register *******************/ |
#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ |
#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
/******************* Bit definition for FSMC_SR2 register *******************/ |
#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ |
#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ |
#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ |
#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ |
#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ |
/******************* Bit definition for FSMC_SR3 register *******************/ |
#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ |
#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ |
#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ |
#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ |
#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ |
/******************* Bit definition for FSMC_SR4 register *******************/ |
#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ |
#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ |
#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ |
#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ |
#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ |
/****************** Bit definition for FSMC_PMEM2 register ******************/ |
#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ |
#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ |
#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ |
#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ |
#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
/****************** Bit definition for FSMC_PMEM3 register ******************/ |
#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */ |
#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */ |
#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */ |
#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ |
#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
/****************** Bit definition for FSMC_PMEM4 register ******************/ |
#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */ |
#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */ |
#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */ |
#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ |
#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
/****************** Bit definition for FSMC_PATT2 register ******************/ |
#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ |
#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ |
#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ |
#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ |
#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
/****************** Bit definition for FSMC_PATT3 register ******************/ |
#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */ |
#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ |
#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ |
#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ |
#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
/****************** Bit definition for FSMC_PATT4 register ******************/ |
#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */ |
#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ |
#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ |
#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ |
#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
/****************** Bit definition for FSMC_PIO4 register *******************/ |
#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */ |
#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */ |
#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */ |
#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ |
#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
/****************** Bit definition for FSMC_ECCR2 register ******************/ |
#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ |
/****************** Bit definition for FSMC_ECCR3 register ******************/ |
#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ |
/******************************************************************************/ |
/* */ |
/* SD host Interface */ |
/* */ |
/******************************************************************************/ |
/****************** Bit definition for SDIO_POWER register ******************/ |
#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */ |
#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */ |
#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */ |
/****************** Bit definition for SDIO_CLKCR register ******************/ |
#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */ |
#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */ |
#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */ |
#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */ |
#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */ |
#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */ |
#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */ |
#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */ |
/******************* Bit definition for SDIO_ARG register *******************/ |
#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */ |
/******************* Bit definition for SDIO_CMD register *******************/ |
#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */ |
#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */ |
#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ |
#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ |
#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */ |
#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */ |
#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */ |
#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */ |
#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */ |
#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */ |
/***************** Bit definition for SDIO_RESPCMD register *****************/ |
#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */ |
/****************** Bit definition for SDIO_RESP0 register ******************/ |
#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
/****************** Bit definition for SDIO_RESP1 register ******************/ |
#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
/****************** Bit definition for SDIO_RESP2 register ******************/ |
#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
/****************** Bit definition for SDIO_RESP3 register ******************/ |
#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
/****************** Bit definition for SDIO_RESP4 register ******************/ |
#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
/****************** Bit definition for SDIO_DTIMER register *****************/ |
#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */ |
/****************** Bit definition for SDIO_DLEN register *******************/ |
#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */ |
/****************** Bit definition for SDIO_DCTRL register ******************/ |
#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */ |
#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */ |
#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */ |
#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */ |
#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */ |
#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */ |
#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */ |
#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */ |
#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */ |
/****************** Bit definition for SDIO_DCOUNT register *****************/ |
#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */ |
/****************** Bit definition for SDIO_STA register ********************/ |
#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */ |
#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */ |
#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */ |
#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */ |
#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */ |
#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */ |
#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */ |
#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */ |
#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */ |
#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */ |
#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */ |
#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */ |
#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */ |
#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */ |
#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */ |
#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */ |
#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */ |
#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */ |
#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */ |
#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */ |
#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */ |
#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */ |
/******************* Bit definition for SDIO_ICR register *******************/ |
#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */ |
#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */ |
#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */ |
#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */ |
#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */ |
#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */ |
#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */ |
#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */ |
#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */ |
#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */ |
#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */ |
#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */ |
#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */ |
/****************** Bit definition for SDIO_MASK register *******************/ |
#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */ |
#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */ |
#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */ |
#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */ |
#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */ |
#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */ |
#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */ |
#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */ |
#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */ |
#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */ |
#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */ |
#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */ |
#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */ |
#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */ |
#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */ |
#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */ |
#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */ |
#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */ |
#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */ |
#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */ |
#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */ |
#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */ |
#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */ |
#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */ |
/***************** Bit definition for SDIO_FIFOCNT register *****************/ |
#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */ |
/****************** Bit definition for SDIO_FIFO register *******************/ |
#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */ |
/******************************************************************************/ |
/* */ |
/* USB Device FS */ |
/* */ |
/******************************************************************************/ |
/*!<Endpoint-specific registers */ |
/******************* Bit definition for USB_EP0R register *******************/ |
#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
/******************* Bit definition for USB_EP1R register *******************/ |
#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
/******************* Bit definition for USB_EP2R register *******************/ |
#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
/******************* Bit definition for USB_EP3R register *******************/ |
#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
/******************* Bit definition for USB_EP4R register *******************/ |
#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
/******************* Bit definition for USB_EP5R register *******************/ |
#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
/******************* Bit definition for USB_EP6R register *******************/ |
#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
/******************* Bit definition for USB_EP7R register *******************/ |
#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
/*!<Common registers */ |
/******************* Bit definition for USB_CNTR register *******************/ |
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */ |
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */ |
#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */ |
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */ |
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */ |
#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */ |
#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */ |
#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */ |
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */ |
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */ |
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */ |
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */ |
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */ |
/******************* Bit definition for USB_ISTR register *******************/ |
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */ |
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */ |
#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */ |
#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */ |
#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */ |
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */ |
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */ |
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */ |
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */ |
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */ |
/******************* Bit definition for USB_FNR register ********************/ |
#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */ |
#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */ |
#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */ |
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */ |
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */ |
/****************** Bit definition for USB_DADDR register *******************/ |
#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */ |
#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */ |
#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */ |
#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */ |
#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */ |
#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */ |
#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */ |
#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */ |
#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */ |
/****************** Bit definition for USB_BTABLE register ******************/ |
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */ |
/*!<Buffer descriptor table */ |
/***************** Bit definition for USB_ADDR0_TX register *****************/ |
#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */ |
/***************** Bit definition for USB_ADDR1_TX register *****************/ |
#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */ |
/***************** Bit definition for USB_ADDR2_TX register *****************/ |
#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */ |
/***************** Bit definition for USB_ADDR3_TX register *****************/ |
#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */ |
/***************** Bit definition for USB_ADDR4_TX register *****************/ |
#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */ |
/***************** Bit definition for USB_ADDR5_TX register *****************/ |
#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */ |
/***************** Bit definition for USB_ADDR6_TX register *****************/ |
#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */ |
/***************** Bit definition for USB_ADDR7_TX register *****************/ |
#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */ |
/*----------------------------------------------------------------------------*/ |
/***************** Bit definition for USB_COUNT0_TX register ****************/ |
#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */ |
/***************** Bit definition for USB_COUNT1_TX register ****************/ |
#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */ |
/***************** Bit definition for USB_COUNT2_TX register ****************/ |
#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */ |
/***************** Bit definition for USB_COUNT3_TX register ****************/ |
#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */ |
/***************** Bit definition for USB_COUNT4_TX register ****************/ |
#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */ |
/***************** Bit definition for USB_COUNT5_TX register ****************/ |
#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */ |
/***************** Bit definition for USB_COUNT6_TX register ****************/ |
#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */ |
/***************** Bit definition for USB_COUNT7_TX register ****************/ |
#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */ |
/*----------------------------------------------------------------------------*/ |
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ |
#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */ |
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ |
#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */ |
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ |
#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */ |
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ |
#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */ |
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ |
#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */ |
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ |
#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */ |
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ |
#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */ |
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ |
#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */ |
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ |
#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */ |
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ |
#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */ |
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ |
#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */ |
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ |
#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */ |
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ |
#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */ |
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ |
#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */ |
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ |
#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */ |
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ |
#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */ |
/*----------------------------------------------------------------------------*/ |
/***************** Bit definition for USB_ADDR0_RX register *****************/ |
#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */ |
/***************** Bit definition for USB_ADDR1_RX register *****************/ |
#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */ |
/***************** Bit definition for USB_ADDR2_RX register *****************/ |
#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */ |
/***************** Bit definition for USB_ADDR3_RX register *****************/ |
#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */ |
/***************** Bit definition for USB_ADDR4_RX register *****************/ |
#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */ |
/***************** Bit definition for USB_ADDR5_RX register *****************/ |
#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */ |
/***************** Bit definition for USB_ADDR6_RX register *****************/ |
#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */ |
/***************** Bit definition for USB_ADDR7_RX register *****************/ |
#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */ |
/*----------------------------------------------------------------------------*/ |
/***************** Bit definition for USB_COUNT0_RX register ****************/ |
#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
/***************** Bit definition for USB_COUNT1_RX register ****************/ |
#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
/***************** Bit definition for USB_COUNT2_RX register ****************/ |
#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
/***************** Bit definition for USB_COUNT3_RX register ****************/ |
#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
/***************** Bit definition for USB_COUNT4_RX register ****************/ |
#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
/***************** Bit definition for USB_COUNT5_RX register ****************/ |
#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
/***************** Bit definition for USB_COUNT6_RX register ****************/ |
#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
/***************** Bit definition for USB_COUNT7_RX register ****************/ |
#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
/*----------------------------------------------------------------------------*/ |
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ |
#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ |
#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */ |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ |
#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ |
#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ |
#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ |
#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ |
#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ |
#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ |
#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ |
#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ |
#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ |
#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ |
#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ |
#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ |
#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ |
#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
/******************************************************************************/ |
/* */ |
/* Controller Area Network */ |
/* */ |
/******************************************************************************/ |
/*!<CAN control and status registers */ |
/******************* Bit definition for CAN_MCR register ********************/ |
#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */ |
#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */ |
#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */ |
#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */ |
#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */ |
#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */ |
#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */ |
#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */ |
#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */ |
/******************* Bit definition for CAN_MSR register ********************/ |
#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */ |
#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */ |
#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */ |
#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */ |
#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */ |
#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */ |
#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */ |
#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */ |
#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */ |
/******************* Bit definition for CAN_TSR register ********************/ |
#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ |
#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ |
#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ |
#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ |
#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ |
#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ |
#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ |
#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ |
#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ |
#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ |
#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ |
#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ |
#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ |
#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ |
#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ |
#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ |
#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ |
#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ |
#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ |
#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ |
#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ |
#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ |
#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ |
#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ |
/******************* Bit definition for CAN_RF0R register *******************/ |
#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */ |
#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */ |
#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */ |
#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */ |
/******************* Bit definition for CAN_RF1R register *******************/ |
#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */ |
#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */ |
#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */ |
#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */ |
/******************** Bit definition for CAN_IER register *******************/ |
#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ |
#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ |
#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ |
#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ |
#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ |
#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ |
#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ |
#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ |
#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ |
#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ |
#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ |
#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ |
#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ |
#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ |
/******************** Bit definition for CAN_ESR register *******************/ |
#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ |
#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ |
#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ |
#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ |
#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ |
/******************* Bit definition for CAN_BTR register ********************/ |
#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ |
#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ |
#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ |
#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ |
#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ |
#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ |
/*!<Mailbox registers */ |
/****************** Bit definition for CAN_TI0R register ********************/ |
#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
/****************** Bit definition for CAN_TDT0R register *******************/ |
#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
/****************** Bit definition for CAN_TDL0R register *******************/ |
#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
/****************** Bit definition for CAN_TDH0R register *******************/ |
#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
/******************* Bit definition for CAN_TI1R register *******************/ |
#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
/******************* Bit definition for CAN_TDT1R register ******************/ |
#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
/******************* Bit definition for CAN_TDL1R register ******************/ |
#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
/******************* Bit definition for CAN_TDH1R register ******************/ |
#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
/******************* Bit definition for CAN_TI2R register *******************/ |
#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
/******************* Bit definition for CAN_TDT2R register ******************/ |
#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
/******************* Bit definition for CAN_TDL2R register ******************/ |
#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
/******************* Bit definition for CAN_TDH2R register ******************/ |
#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
/******************* Bit definition for CAN_RI0R register *******************/ |
#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
/******************* Bit definition for CAN_RDT0R register ******************/ |
#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
/******************* Bit definition for CAN_RDL0R register ******************/ |
#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
/******************* Bit definition for CAN_RDH0R register ******************/ |
#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
/******************* Bit definition for CAN_RI1R register *******************/ |
#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
/******************* Bit definition for CAN_RDT1R register ******************/ |
#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
/******************* Bit definition for CAN_RDL1R register ******************/ |
#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
/******************* Bit definition for CAN_RDH1R register ******************/ |
#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
/*!<CAN filter registers */ |
/******************* Bit definition for CAN_FMR register ********************/ |
#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */ |
/******************* Bit definition for CAN_FM1R register *******************/ |
#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */ |
#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */ |
#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */ |
#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */ |
#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */ |
#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */ |
#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */ |
#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */ |
#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */ |
#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */ |
#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */ |
#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */ |
#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */ |
#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */ |
#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */ |
/******************* Bit definition for CAN_FS1R register *******************/ |
#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */ |
#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */ |
#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */ |
#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */ |
#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */ |
#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */ |
#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */ |
#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */ |
#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */ |
#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */ |
#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */ |
#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */ |
#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */ |
#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */ |
#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */ |
/****************** Bit definition for CAN_FFA1R register *******************/ |
#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */ |
#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ |
#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ |
#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ |
#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ |
#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ |
#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ |
#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ |
#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ |
#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ |
#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ |
#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ |
#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ |
#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ |
#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ |
/******************* Bit definition for CAN_FA1R register *******************/ |
#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */ |
#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */ |
#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */ |
#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */ |
#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */ |
#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */ |
#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */ |
#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */ |
#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */ |
#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */ |
#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */ |
#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */ |
#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */ |
#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */ |
#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */ |
/******************* Bit definition for CAN_F0R1 register *******************/ |
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F1R1 register *******************/ |
#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F2R1 register *******************/ |
#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F3R1 register *******************/ |
#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F4R1 register *******************/ |
#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F5R1 register *******************/ |
#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F6R1 register *******************/ |
#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F7R1 register *******************/ |
#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F8R1 register *******************/ |
#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F9R1 register *******************/ |
#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F10R1 register ******************/ |
#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F11R1 register ******************/ |
#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F12R1 register ******************/ |
#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F13R1 register ******************/ |
#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F0R2 register *******************/ |
#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F1R2 register *******************/ |
#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F2R2 register *******************/ |
#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F3R2 register *******************/ |
#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F4R2 register *******************/ |
#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F5R2 register *******************/ |
#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F6R2 register *******************/ |
#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F7R2 register *******************/ |
#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F8R2 register *******************/ |
#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F9R2 register *******************/ |
#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F10R2 register ******************/ |
#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F11R2 register ******************/ |
#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F12R2 register ******************/ |
#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************* Bit definition for CAN_F13R2 register ******************/ |
#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
/******************************************************************************/ |
/* */ |
/* Serial Peripheral Interface */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for SPI_CR1 register ********************/ |
#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */ |
#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */ |
#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */ |
#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */ |
#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */ |
#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */ |
#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */ |
#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */ |
#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */ |
#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */ |
#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */ |
#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */ |
#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */ |
#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */ |
#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */ |
#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */ |
#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */ |
/******************* Bit definition for SPI_CR2 register ********************/ |
#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */ |
#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */ |
#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */ |
#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */ |
#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */ |
#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */ |
/******************** Bit definition for SPI_SR register ********************/ |
#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */ |
#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */ |
#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */ |
#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */ |
#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */ |
#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */ |
#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */ |
#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */ |
/******************** Bit definition for SPI_DR register ********************/ |
#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */ |
/******************* Bit definition for SPI_CRCPR register ******************/ |
#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */ |
/****************** Bit definition for SPI_RXCRCR register ******************/ |
#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */ |
/****************** Bit definition for SPI_TXCRCR register ******************/ |
#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */ |
/****************** Bit definition for SPI_I2SCFGR register *****************/ |
#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ |
#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ |
#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */ |
#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */ |
#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */ |
#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ |
#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */ |
#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ |
#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */ |
#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */ |
/****************** Bit definition for SPI_I2SPR register *******************/ |
#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ |
#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ |
#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */ |
/******************************************************************************/ |
/* */ |
/* Inter-integrated Circuit Interface */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for I2C_CR1 register ********************/ |
#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */ |
#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */ |
#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */ |
#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */ |
#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */ |
#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */ |
#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */ |
#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */ |
#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */ |
#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */ |
#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */ |
#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */ |
#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */ |
#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */ |
/******************* Bit definition for I2C_CR2 register ********************/ |
#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ |
#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */ |
#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */ |
#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */ |
#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */ |
#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */ |
#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */ |
/******************* Bit definition for I2C_OAR1 register *******************/ |
#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */ |
#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */ |
#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */ |
#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */ |
#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */ |
#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */ |
#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */ |
#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */ |
#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */ |
#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */ |
#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */ |
#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */ |
#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */ |
/******************* Bit definition for I2C_OAR2 register *******************/ |
#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */ |
#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */ |
/******************** Bit definition for I2C_DR register ********************/ |
#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */ |
/******************* Bit definition for I2C_SR1 register ********************/ |
#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */ |
#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */ |
#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */ |
#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */ |
#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */ |
#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */ |
#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */ |
#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */ |
#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */ |
#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */ |
#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */ |
#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */ |
#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */ |
#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */ |
/******************* Bit definition for I2C_SR2 register ********************/ |
#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */ |
#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */ |
#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */ |
#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */ |
#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */ |
#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */ |
#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */ |
#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */ |
/******************* Bit definition for I2C_CCR register ********************/ |
#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */ |
#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */ |
#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */ |
/****************** Bit definition for I2C_TRISE register *******************/ |
#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ |
/******************************************************************************/ |
/* */ |
/* Universal Synchronous Asynchronous Receiver Transmitter */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for USART_SR register *******************/ |
#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */ |
#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */ |
#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */ |
#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */ |
#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */ |
#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */ |
#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */ |
#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */ |
#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */ |
#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */ |
/******************* Bit definition for USART_DR register *******************/ |
#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */ |
/****************** Bit definition for USART_BRR register *******************/ |
#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */ |
#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */ |
/****************** Bit definition for USART_CR1 register *******************/ |
#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */ |
#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */ |
#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */ |
#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */ |
#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */ |
#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */ |
#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */ |
#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */ |
#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */ |
#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */ |
#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */ |
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */ |
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */ |
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */ |
#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */ |
/****************** Bit definition for USART_CR2 register *******************/ |
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */ |
#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */ |
#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */ |
#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */ |
#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */ |
#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */ |
#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */ |
#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */ |
#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */ |
/****************** Bit definition for USART_CR3 register *******************/ |
#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */ |
#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */ |
#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */ |
#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */ |
#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */ |
#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */ |
#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */ |
#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */ |
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */ |
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */ |
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */ |
#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */ |
/****************** Bit definition for USART_GTPR register ******************/ |
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */ |
#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */ |
#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */ |
#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */ |
#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */ |
/******************************************************************************/ |
/* */ |
/* Debug MCU */ |
/* */ |
/******************************************************************************/ |
/**************** Bit definition for DBGMCU_IDCODE register *****************/ |
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */ |
#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */ |
#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */ |
#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */ |
#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */ |
#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */ |
#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */ |
#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */ |
#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */ |
#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */ |
/****************** Bit definition for DBGMCU_CR register *******************/ |
#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */ |
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */ |
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */ |
#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */ |
#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */ |
#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */ |
#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */ |
#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */ |
#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */ |
#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */ |
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */ |
#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */ |
#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */ |
#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */ |
#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */ |
#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */ |
/******************************************************************************/ |
/* */ |
/* FLASH and Option Bytes Registers */ |
/* */ |
/******************************************************************************/ |
/******************* Bit definition for FLASH_ACR register ******************/ |
#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */ |
#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */ |
#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */ |
#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */ |
#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */ |
#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */ |
#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */ |
/****************** Bit definition for FLASH_KEYR register ******************/ |
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */ |
/***************** Bit definition for FLASH_OPTKEYR register ****************/ |
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */ |
/****************** Bit definition for FLASH_SR register *******************/ |
#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */ |
#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */ |
#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */ |
#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */ |
/******************* Bit definition for FLASH_CR register *******************/ |
#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */ |
#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */ |
#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */ |
#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */ |
#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */ |
#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */ |
#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */ |
#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */ |
#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */ |
#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */ |
/******************* Bit definition for FLASH_AR register *******************/ |
#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */ |
/****************** Bit definition for FLASH_OBR register *******************/ |
#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */ |
#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */ |
#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */ |
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */ |
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */ |
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */ |
#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */ |
/****************** Bit definition for FLASH_WRPR register ******************/ |
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */ |
/*----------------------------------------------------------------------------*/ |
/****************** Bit definition for FLASH_RDP register *******************/ |
#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */ |
#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */ |
/****************** Bit definition for FLASH_USER register ******************/ |
#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */ |
#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */ |
/****************** Bit definition for FLASH_Data0 register *****************/ |
#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */ |
#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */ |
/****************** Bit definition for FLASH_Data1 register *****************/ |
#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */ |
#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */ |
/****************** Bit definition for FLASH_WRP0 register ******************/ |
#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */ |
#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */ |
/****************** Bit definition for FLASH_WRP1 register ******************/ |
#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */ |
#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */ |
/****************** Bit definition for FLASH_WRP2 register ******************/ |
#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */ |
#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */ |
/****************** Bit definition for FLASH_WRP3 register ******************/ |
#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */ |
#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */ |
#ifdef STM32F10X_CL |
/******************************************************************************/ |
/* Ethernet MAC Registers bits definitions */ |
/******************************************************************************/ |
/* Bit definition for Ethernet MAC Control Register register */ |
#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling |
a transmission attempt during retries after a collision: 0 =< r <2^k */ |
#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
/* Bit definition for Ethernet MAC Frame Filter Register */ |
#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
/* Bit definition for Ethernet MAC Hash Table High Register */ |
#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
/* Bit definition for Ethernet MAC Hash Table Low Register */ |
#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
/* Bit definition for Ethernet MAC MII Address Register */ |
#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ |
#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
/* Bit definition for Ethernet MAC MII Data Register */ |
#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
/* Bit definition for Ethernet MAC Flow Control Register */ |
#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
/* Bit definition for Ethernet MAC VLAN Tag Register */ |
#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ |
#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. |
Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ |
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask |
Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask |
Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask |
Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask |
Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - |
RSVD - Filter1 Command - RSVD - Filter0 Command |
Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset |
Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 |
Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ |
/* Bit definition for Ethernet MAC PMT Control and Status Register */ |
#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
/* Bit definition for Ethernet MAC Status Register */ |
#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
/* Bit definition for Ethernet MAC Interrupt Mask Register */ |
#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
/* Bit definition for Ethernet MAC Address0 High Register */ |
#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
/* Bit definition for Ethernet MAC Address0 Low Register */ |
#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
/* Bit definition for Ethernet MAC Address1 High Register */ |
#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
/* Bit definition for Ethernet MAC Address1 Low Register */ |
#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
/* Bit definition for Ethernet MAC Address2 High Register */ |
#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
/* Bit definition for Ethernet MAC Address2 Low Register */ |
#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
/* Bit definition for Ethernet MAC Address3 High Register */ |
#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
/* Bit definition for Ethernet MAC Address3 Low Register */ |
#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
/******************************************************************************/ |
/* Ethernet MMC Registers bits definition */ |
/******************************************************************************/ |
/* Bit definition for Ethernet MMC Contol Register */ |
#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
/* Bit definition for Ethernet MMC Receive Interrupt Register */ |
#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
/* Bit definition for Ethernet MMC Transmit Interrupt Register */ |
#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ |
#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ |
#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ |
#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ |
#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ |
#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ |
#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ |
#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ |
#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
/******************************************************************************/ |
/* Ethernet PTP Registers bits definition */ |
/******************************************************************************/ |
/* Bit definition for Ethernet PTP Time Stamp Contol Register */ |
#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
/* Bit definition for Ethernet PTP Sub-Second Increment Register */ |
#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
/* Bit definition for Ethernet PTP Time Stamp High Register */ |
#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
/* Bit definition for Ethernet PTP Time Stamp Low Register */ |
#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
/* Bit definition for Ethernet PTP Time Stamp High Update Register */ |
#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ |
#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
/* Bit definition for Ethernet PTP Time Stamp Addend Register */ |
#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
/* Bit definition for Ethernet PTP Target Time High Register */ |
#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
/* Bit definition for Ethernet PTP Target Time Low Register */ |
#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
/******************************************************************************/ |
/* Ethernet DMA Registers bits definition */ |
/******************************************************************************/ |
/* Bit definition for Ethernet DMA Bus Mode Register */ |
#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ |
#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
/* Bit definition for Ethernet DMA Receive Poll Demand Register */ |
#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ |
#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ |
#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
/* Bit definition for Ethernet DMA Status Register */ |
#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
/* combination with EBS[2:0] for GetFlagStatus function */ |
#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
/* Bit definition for Ethernet DMA Operation Mode Register */ |
#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
/* Bit definition for Ethernet DMA Interrupt Enable Register */ |
#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ |
#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ |
#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ |
#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ |
#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ |
#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
#endif /* STM32F10X_CL */ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
#ifdef USE_STDPERIPH_DRIVER |
#include "stm32f10x_conf.h" |
#endif |
/** @addtogroup Exported_macro |
* @{ |
*/ |
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
#define READ_BIT(REG, BIT) ((REG) & (BIT)) |
#define CLEAR_REG(REG) ((REG) = (0x0)) |
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
#define READ_REG(REG) ((REG)) |
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
/** |
* @} |
*/ |
#ifdef __cplusplus |
} |
#endif |
#endif /* __STM32F10x_H */ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/stm32f10x_gpio.c |
---|
0,0 → 1,647 |
/** |
****************************************************************************** |
* @file stm32f10x_gpio.c |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief This file provides all the GPIO firmware functions. |
****************************************************************************** |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
/* Includes ------------------------------------------------------------------*/ |
#include "stm32f10x_gpio.h" |
#include "stm32f10x_rcc.h" |
/** @addtogroup STM32F10x_StdPeriph_Driver |
* @{ |
*/ |
/** @defgroup GPIO |
* @brief GPIO driver modules |
* @{ |
*/ |
/** @defgroup GPIO_Private_TypesDefinitions |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup GPIO_Private_Defines |
* @{ |
*/ |
/* ------------ RCC registers bit address in the alias region ----------------*/ |
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) |
/* --- EVENTCR Register -----*/ |
/* Alias word address of EVOE bit */ |
#define EVCR_OFFSET (AFIO_OFFSET + 0x00) |
#define EVOE_BitNumber ((uint8_t)0x07) |
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) |
/* --- MAPR Register ---*/ |
/* Alias word address of MII_RMII_SEL bit */ |
#define MAPR_OFFSET (AFIO_OFFSET + 0x04) |
#define MII_RMII_SEL_BitNumber ((u8)0x17) |
#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) |
#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) |
#define LSB_MASK ((uint16_t)0xFFFF) |
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) |
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) |
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) |
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) |
/** |
* @} |
*/ |
/** @defgroup GPIO_Private_Macros |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup GPIO_Private_Variables |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup GPIO_Private_FunctionPrototypes |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup GPIO_Private_Functions |
* @{ |
*/ |
/** |
* @brief Deinitializes the GPIOx peripheral registers to their default reset values. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @retval None |
*/ |
void GPIO_DeInit(GPIO_TypeDef* GPIOx) |
{ |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
if (GPIOx == GPIOA) |
{ |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); |
} |
else if (GPIOx == GPIOB) |
{ |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); |
} |
else if (GPIOx == GPIOC) |
{ |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); |
} |
else if (GPIOx == GPIOD) |
{ |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); |
} |
else if (GPIOx == GPIOE) |
{ |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); |
} |
else if (GPIOx == GPIOF) |
{ |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); |
} |
else |
{ |
if (GPIOx == GPIOG) |
{ |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); |
} |
} |
} |
/** |
* @brief Deinitializes the Alternate Functions (remap, event control |
* and EXTI configuration) registers to their default reset values. |
* @param None |
* @retval None |
*/ |
void GPIO_AFIODeInit(void) |
{ |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); |
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); |
} |
/** |
* @brief Initializes the GPIOx peripheral according to the specified |
* parameters in the GPIO_InitStruct. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that |
* contains the configuration information for the specified GPIO peripheral. |
* @retval None |
*/ |
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) |
{ |
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; |
uint32_t tmpreg = 0x00, pinmask = 0x00; |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); |
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); |
/*---------------------------- GPIO Mode Configuration -----------------------*/ |
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); |
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) |
{ |
/* Check the parameters */ |
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); |
/* Output mode */ |
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; |
} |
/*---------------------------- GPIO CRL Configuration ------------------------*/ |
/* Configure the eight low port pins */ |
if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) |
{ |
tmpreg = GPIOx->CRL; |
for (pinpos = 0x00; pinpos < 0x08; pinpos++) |
{ |
pos = ((uint32_t)0x01) << pinpos; |
/* Get the port pins position */ |
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; |
if (currentpin == pos) |
{ |
pos = pinpos << 2; |
/* Clear the corresponding low control register bits */ |
pinmask = ((uint32_t)0x0F) << pos; |
tmpreg &= ~pinmask; |
/* Write the mode configuration in the corresponding bits */ |
tmpreg |= (currentmode << pos); |
/* Reset the corresponding ODR bit */ |
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) |
{ |
GPIOx->BRR = (((uint32_t)0x01) << pinpos); |
} |
else |
{ |
/* Set the corresponding ODR bit */ |
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) |
{ |
GPIOx->BSRR = (((uint32_t)0x01) << pinpos); |
} |
} |
} |
} |
GPIOx->CRL = tmpreg; |
} |
/*---------------------------- GPIO CRH Configuration ------------------------*/ |
/* Configure the eight high port pins */ |
if (GPIO_InitStruct->GPIO_Pin > 0x00FF) |
{ |
tmpreg = GPIOx->CRH; |
for (pinpos = 0x00; pinpos < 0x08; pinpos++) |
{ |
pos = (((uint32_t)0x01) << (pinpos + 0x08)); |
/* Get the port pins position */ |
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); |
if (currentpin == pos) |
{ |
pos = pinpos << 2; |
/* Clear the corresponding high control register bits */ |
pinmask = ((uint32_t)0x0F) << pos; |
tmpreg &= ~pinmask; |
/* Write the mode configuration in the corresponding bits */ |
tmpreg |= (currentmode << pos); |
/* Reset the corresponding ODR bit */ |
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) |
{ |
GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); |
} |
/* Set the corresponding ODR bit */ |
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) |
{ |
GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); |
} |
} |
} |
GPIOx->CRH = tmpreg; |
} |
} |
/** |
* @brief Fills each GPIO_InitStruct member with its default value. |
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will |
* be initialized. |
* @retval None |
*/ |
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) |
{ |
/* Reset GPIO init structure parameters values */ |
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; |
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; |
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; |
} |
/** |
* @brief Reads the specified input port pin. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @param GPIO_Pin: specifies the port bit to read. |
* This parameter can be GPIO_Pin_x where x can be (0..15). |
* @retval The input port pin value. |
*/ |
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
{ |
uint8_t bitstatus = 0x00; |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); |
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) |
{ |
bitstatus = (uint8_t)Bit_SET; |
} |
else |
{ |
bitstatus = (uint8_t)Bit_RESET; |
} |
return bitstatus; |
} |
/** |
* @brief Reads the specified GPIO input data port. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @retval GPIO input data port value. |
*/ |
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) |
{ |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
return ((uint16_t)GPIOx->IDR); |
} |
/** |
* @brief Reads the specified output data port bit. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @param GPIO_Pin: specifies the port bit to read. |
* This parameter can be GPIO_Pin_x where x can be (0..15). |
* @retval The output port pin value. |
*/ |
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
{ |
uint8_t bitstatus = 0x00; |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); |
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) |
{ |
bitstatus = (uint8_t)Bit_SET; |
} |
else |
{ |
bitstatus = (uint8_t)Bit_RESET; |
} |
return bitstatus; |
} |
/** |
* @brief Reads the specified GPIO output data port. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @retval GPIO output data port value. |
*/ |
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) |
{ |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
return ((uint16_t)GPIOx->ODR); |
} |
/** |
* @brief Sets the selected data port bits. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @param GPIO_Pin: specifies the port bits to be written. |
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). |
* @retval None |
*/ |
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
{ |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
GPIOx->BSRR = GPIO_Pin; |
} |
/** |
* @brief Clears the selected data port bits. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @param GPIO_Pin: specifies the port bits to be written. |
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). |
* @retval None |
*/ |
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
{ |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
GPIOx->BRR = GPIO_Pin; |
} |
/** |
* @brief Sets or clears the selected data port bit. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @param GPIO_Pin: specifies the port bit to be written. |
* This parameter can be one of GPIO_Pin_x where x can be (0..15). |
* @param BitVal: specifies the value to be written to the selected bit. |
* This parameter can be one of the BitAction enum values: |
* @arg Bit_RESET: to clear the port pin |
* @arg Bit_SET: to set the port pin |
* @retval None |
*/ |
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) |
{ |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); |
assert_param(IS_GPIO_BIT_ACTION(BitVal)); |
if (BitVal != Bit_RESET) |
{ |
GPIOx->BSRR = GPIO_Pin; |
} |
else |
{ |
GPIOx->BRR = GPIO_Pin; |
} |
} |
/** |
* @brief Writes data to the specified GPIO data port. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @param PortVal: specifies the value to be written to the port output data register. |
* @retval None |
*/ |
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) |
{ |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
GPIOx->ODR = PortVal; |
} |
/** |
* @brief Locks GPIO Pins configuration registers. |
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. |
* @param GPIO_Pin: specifies the port bit to be written. |
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). |
* @retval None |
*/ |
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
{ |
uint32_t tmp = 0x00010000; |
/* Check the parameters */ |
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
tmp |= GPIO_Pin; |
/* Set LCKK bit */ |
GPIOx->LCKR = tmp; |
/* Reset LCKK bit */ |
GPIOx->LCKR = GPIO_Pin; |
/* Set LCKK bit */ |
GPIOx->LCKR = tmp; |
/* Read LCKK bit*/ |
tmp = GPIOx->LCKR; |
/* Read LCKK bit*/ |
tmp = GPIOx->LCKR; |
} |
/** |
* @brief Selects the GPIO pin used as Event output. |
* @param GPIO_PortSource: selects the GPIO port to be used as source |
* for Event output. |
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). |
* @param GPIO_PinSource: specifies the pin for the Event output. |
* This parameter can be GPIO_PinSourcex where x can be (0..15). |
* @retval None |
*/ |
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) |
{ |
uint32_t tmpreg = 0x00; |
/* Check the parameters */ |
assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); |
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); |
tmpreg = AFIO->EVCR; |
/* Clear the PORT[6:4] and PIN[3:0] bits */ |
tmpreg &= EVCR_PORTPINCONFIG_MASK; |
tmpreg |= (uint32_t)GPIO_PortSource << 0x04; |
tmpreg |= GPIO_PinSource; |
AFIO->EVCR = tmpreg; |
} |
/** |
* @brief Enables or disables the Event Output. |
* @param NewState: new state of the Event output. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void GPIO_EventOutputCmd(FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
*(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; |
} |
/** |
* @brief Changes the mapping of the specified pin. |
* @param GPIO_Remap: selects the pin to remap. |
* This parameter can be one of the following values: |
* @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping |
* @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping |
* @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping |
* @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping |
* @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping |
* @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping |
* @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping |
* @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping |
* @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping |
* @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping |
* @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping |
* @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping |
* @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping |
* @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping |
* @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping |
* @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping |
* @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping |
* @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration |
* @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping |
* @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping |
* @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping |
* @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping |
* @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices) |
* @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices) |
* @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST |
* @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled |
* @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) |
* @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) |
* @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected |
* to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) |
* If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to |
* Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. |
* @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) |
* @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices) |
* @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices) |
* @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices) |
* @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices) |
* @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices) |
* @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices) |
* @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices) |
* @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices) |
* @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) |
* @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) |
* @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) |
* @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) |
* @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices) |
* @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, |
* only for High density Value line devices) |
* @param NewState: new state of the port pin remapping. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) |
{ |
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; |
/* Check the parameters */ |
assert_param(IS_GPIO_REMAP(GPIO_Remap)); |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
if((GPIO_Remap & 0x80000000) == 0x80000000) |
{ |
tmpreg = AFIO->MAPR2; |
} |
else |
{ |
tmpreg = AFIO->MAPR; |
} |
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; |
tmp = GPIO_Remap & LSB_MASK; |
if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) |
{ |
tmpreg &= DBGAFR_SWJCFG_MASK; |
AFIO->MAPR &= DBGAFR_SWJCFG_MASK; |
} |
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) |
{ |
tmp1 = ((uint32_t)0x03) << tmpmask; |
tmpreg &= ~tmp1; |
tmpreg |= ~DBGAFR_SWJCFG_MASK; |
} |
else |
{ |
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); |
tmpreg |= ~DBGAFR_SWJCFG_MASK; |
} |
if (NewState != DISABLE) |
{ |
tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); |
} |
if((GPIO_Remap & 0x80000000) == 0x80000000) |
{ |
AFIO->MAPR2 = tmpreg; |
} |
else |
{ |
AFIO->MAPR = tmpreg; |
} |
} |
/** |
* @brief Selects the GPIO pin used as EXTI Line. |
* @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. |
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). |
* @param GPIO_PinSource: specifies the EXTI line to be configured. |
* This parameter can be GPIO_PinSourcex where x can be (0..15). |
* @retval None |
*/ |
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) |
{ |
uint32_t tmp = 0x00; |
/* Check the parameters */ |
assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); |
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); |
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); |
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; |
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); |
} |
/** |
* @brief Selects the Ethernet media interface. |
* @note This function applies only to STM32 Connectivity line devices. |
* @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. |
* This parameter can be one of the following values: |
* @arg GPIO_ETH_MediaInterface_MII: MII mode |
* @arg GPIO_ETH_MediaInterface_RMII: RMII mode |
* @retval None |
*/ |
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) |
{ |
assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); |
/* Configure MII_RMII selection bit */ |
*(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; |
} |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/stm32f10x_gpio.h |
---|
0,0 → 1,384 |
/** |
****************************************************************************** |
* @file stm32f10x_gpio.h |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief This file contains all the functions prototypes for the GPIO |
* firmware library. |
****************************************************************************** |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
/* Define to prevent recursive inclusion -------------------------------------*/ |
#ifndef __STM32F10x_GPIO_H |
#define __STM32F10x_GPIO_H |
#ifdef __cplusplus |
extern "C" { |
#endif |
/* Includes ------------------------------------------------------------------*/ |
#include "stm32f10x.h" |
/** @addtogroup STM32F10x_StdPeriph_Driver |
* @{ |
*/ |
/** @addtogroup GPIO |
* @{ |
*/ |
/** @defgroup GPIO_Exported_Types |
* @{ |
*/ |
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ |
((PERIPH) == GPIOB) || \ |
((PERIPH) == GPIOC) || \ |
((PERIPH) == GPIOD) || \ |
((PERIPH) == GPIOE) || \ |
((PERIPH) == GPIOF) || \ |
((PERIPH) == GPIOG)) |
/** |
* @brief Output Maximum frequency selection |
*/ |
typedef enum |
{ |
GPIO_Speed_10MHz = 1, |
GPIO_Speed_2MHz, |
GPIO_Speed_50MHz |
}GPIOSpeed_TypeDef; |
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ |
((SPEED) == GPIO_Speed_50MHz)) |
/** |
* @brief Configuration Mode enumeration |
*/ |
typedef enum |
{ GPIO_Mode_AIN = 0x0, |
GPIO_Mode_IN_FLOATING = 0x04, |
GPIO_Mode_IPD = 0x28, |
GPIO_Mode_IPU = 0x48, |
GPIO_Mode_Out_OD = 0x14, |
GPIO_Mode_Out_PP = 0x10, |
GPIO_Mode_AF_OD = 0x1C, |
GPIO_Mode_AF_PP = 0x18 |
}GPIOMode_TypeDef; |
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ |
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ |
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ |
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) |
/** |
* @brief GPIO Init structure definition |
*/ |
typedef struct |
{ |
uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. |
This parameter can be any value of @ref GPIO_pins_define */ |
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. |
This parameter can be a value of @ref GPIOSpeed_TypeDef */ |
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. |
This parameter can be a value of @ref GPIOMode_TypeDef */ |
}GPIO_InitTypeDef; |
/** |
* @brief Bit_SET and Bit_RESET enumeration |
*/ |
typedef enum |
{ Bit_RESET = 0, |
Bit_SET |
}BitAction; |
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) |
/** |
* @} |
*/ |
/** @defgroup GPIO_Exported_Constants |
* @{ |
*/ |
/** @defgroup GPIO_pins_define |
* @{ |
*/ |
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ |
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ |
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ |
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ |
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ |
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ |
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ |
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ |
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ |
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ |
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ |
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ |
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ |
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ |
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ |
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ |
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ |
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) |
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ |
((PIN) == GPIO_Pin_1) || \ |
((PIN) == GPIO_Pin_2) || \ |
((PIN) == GPIO_Pin_3) || \ |
((PIN) == GPIO_Pin_4) || \ |
((PIN) == GPIO_Pin_5) || \ |
((PIN) == GPIO_Pin_6) || \ |
((PIN) == GPIO_Pin_7) || \ |
((PIN) == GPIO_Pin_8) || \ |
((PIN) == GPIO_Pin_9) || \ |
((PIN) == GPIO_Pin_10) || \ |
((PIN) == GPIO_Pin_11) || \ |
((PIN) == GPIO_Pin_12) || \ |
((PIN) == GPIO_Pin_13) || \ |
((PIN) == GPIO_Pin_14) || \ |
((PIN) == GPIO_Pin_15)) |
/** |
* @} |
*/ |
/** @defgroup GPIO_Remap_define |
* @{ |
*/ |
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ |
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ |
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ |
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ |
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ |
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ |
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ |
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ |
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ |
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ |
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ |
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ |
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ |
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ |
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ |
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ |
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ |
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ |
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ |
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ |
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ |
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ |
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ |
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ |
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ |
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ |
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ |
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ |
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected |
to TIM2 Internal Trigger 1 for calibration |
(only for Connectivity line devices) */ |
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ |
#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ |
#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ |
#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ |
#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ |
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ |
#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ |
#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ |
#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ |
#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ |
#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ |
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ |
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ |
#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ |
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, |
only for High density Value line devices) */ |
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ |
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ |
((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ |
((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ |
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ |
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ |
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ |
((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ |
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ |
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ |
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ |
((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ |
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ |
((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ |
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ |
((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ |
((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ |
((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ |
((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ |
((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ |
((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ |
((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) |
/** |
* @} |
*/ |
/** @defgroup GPIO_Port_Sources |
* @{ |
*/ |
#define GPIO_PortSourceGPIOA ((uint8_t)0x00) |
#define GPIO_PortSourceGPIOB ((uint8_t)0x01) |
#define GPIO_PortSourceGPIOC ((uint8_t)0x02) |
#define GPIO_PortSourceGPIOD ((uint8_t)0x03) |
#define GPIO_PortSourceGPIOE ((uint8_t)0x04) |
#define GPIO_PortSourceGPIOF ((uint8_t)0x05) |
#define GPIO_PortSourceGPIOG ((uint8_t)0x06) |
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOE)) |
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ |
((PORTSOURCE) == GPIO_PortSourceGPIOG)) |
/** |
* @} |
*/ |
/** @defgroup GPIO_Pin_sources |
* @{ |
*/ |
#define GPIO_PinSource0 ((uint8_t)0x00) |
#define GPIO_PinSource1 ((uint8_t)0x01) |
#define GPIO_PinSource2 ((uint8_t)0x02) |
#define GPIO_PinSource3 ((uint8_t)0x03) |
#define GPIO_PinSource4 ((uint8_t)0x04) |
#define GPIO_PinSource5 ((uint8_t)0x05) |
#define GPIO_PinSource6 ((uint8_t)0x06) |
#define GPIO_PinSource7 ((uint8_t)0x07) |
#define GPIO_PinSource8 ((uint8_t)0x08) |
#define GPIO_PinSource9 ((uint8_t)0x09) |
#define GPIO_PinSource10 ((uint8_t)0x0A) |
#define GPIO_PinSource11 ((uint8_t)0x0B) |
#define GPIO_PinSource12 ((uint8_t)0x0C) |
#define GPIO_PinSource13 ((uint8_t)0x0D) |
#define GPIO_PinSource14 ((uint8_t)0x0E) |
#define GPIO_PinSource15 ((uint8_t)0x0F) |
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ |
((PINSOURCE) == GPIO_PinSource1) || \ |
((PINSOURCE) == GPIO_PinSource2) || \ |
((PINSOURCE) == GPIO_PinSource3) || \ |
((PINSOURCE) == GPIO_PinSource4) || \ |
((PINSOURCE) == GPIO_PinSource5) || \ |
((PINSOURCE) == GPIO_PinSource6) || \ |
((PINSOURCE) == GPIO_PinSource7) || \ |
((PINSOURCE) == GPIO_PinSource8) || \ |
((PINSOURCE) == GPIO_PinSource9) || \ |
((PINSOURCE) == GPIO_PinSource10) || \ |
((PINSOURCE) == GPIO_PinSource11) || \ |
((PINSOURCE) == GPIO_PinSource12) || \ |
((PINSOURCE) == GPIO_PinSource13) || \ |
((PINSOURCE) == GPIO_PinSource14) || \ |
((PINSOURCE) == GPIO_PinSource15)) |
/** |
* @} |
*/ |
/** @defgroup Ethernet_Media_Interface |
* @{ |
*/ |
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) |
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) |
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ |
((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/** @defgroup GPIO_Exported_Macros |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup GPIO_Exported_Functions |
* @{ |
*/ |
void GPIO_DeInit(GPIO_TypeDef* GPIOx); |
void GPIO_AFIODeInit(void); |
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); |
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); |
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); |
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); |
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); |
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); |
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); |
void GPIO_EventOutputCmd(FunctionalState NewState); |
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); |
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); |
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); |
#ifdef __cplusplus |
} |
#endif |
#endif /* __STM32F10x_GPIO_H */ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/stm32f10x_rcc.c |
---|
0,0 → 1,1469 |
/** |
****************************************************************************** |
* @file stm32f10x_rcc.c |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief This file provides all the RCC firmware functions. |
****************************************************************************** |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
/* Includes ------------------------------------------------------------------*/ |
#include "stm32f10x_rcc.h" |
/** @addtogroup STM32F10x_StdPeriph_Driver |
* @{ |
*/ |
/** @defgroup RCC |
* @brief RCC driver modules |
* @{ |
*/ |
/** @defgroup RCC_Private_TypesDefinitions |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup RCC_Private_Defines |
* @{ |
*/ |
/* ------------ RCC registers bit address in the alias region ----------- */ |
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
/* --- CR Register ---*/ |
/* Alias word address of HSION bit */ |
#define CR_OFFSET (RCC_OFFSET + 0x00) |
#define HSION_BitNumber 0x00 |
#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
/* Alias word address of PLLON bit */ |
#define PLLON_BitNumber 0x18 |
#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
#ifdef STM32F10X_CL |
/* Alias word address of PLL2ON bit */ |
#define PLL2ON_BitNumber 0x1A |
#define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) |
/* Alias word address of PLL3ON bit */ |
#define PLL3ON_BitNumber 0x1C |
#define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) |
#endif /* STM32F10X_CL */ |
/* Alias word address of CSSON bit */ |
#define CSSON_BitNumber 0x13 |
#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
/* --- CFGR Register ---*/ |
/* Alias word address of USBPRE bit */ |
#define CFGR_OFFSET (RCC_OFFSET + 0x04) |
#ifndef STM32F10X_CL |
#define USBPRE_BitNumber 0x16 |
#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) |
#else |
#define OTGFSPRE_BitNumber 0x16 |
#define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) |
#endif /* STM32F10X_CL */ |
/* --- BDCR Register ---*/ |
/* Alias word address of RTCEN bit */ |
#define BDCR_OFFSET (RCC_OFFSET + 0x20) |
#define RTCEN_BitNumber 0x0F |
#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
/* Alias word address of BDRST bit */ |
#define BDRST_BitNumber 0x10 |
#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
/* --- CSR Register ---*/ |
/* Alias word address of LSION bit */ |
#define CSR_OFFSET (RCC_OFFSET + 0x24) |
#define LSION_BitNumber 0x00 |
#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
#ifdef STM32F10X_CL |
/* --- CFGR2 Register ---*/ |
/* Alias word address of I2S2SRC bit */ |
#define CFGR2_OFFSET (RCC_OFFSET + 0x2C) |
#define I2S2SRC_BitNumber 0x11 |
#define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) |
/* Alias word address of I2S3SRC bit */ |
#define I2S3SRC_BitNumber 0x12 |
#define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) |
#endif /* STM32F10X_CL */ |
/* ---------------------- RCC registers bit mask ------------------------ */ |
/* CR register bit mask */ |
#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) |
#define CR_HSEBYP_Set ((uint32_t)0x00040000) |
#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) |
#define CR_HSEON_Set ((uint32_t)0x00010000) |
#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) |
/* CFGR register bit mask */ |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
#define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) |
#else |
#define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) |
#endif /* STM32F10X_CL */ |
#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) |
#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) |
#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) |
#define CFGR_SWS_Mask ((uint32_t)0x0000000C) |
#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) |
#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) |
#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) |
#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) |
#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) |
#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) |
#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) |
#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) |
#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) |
/* CSR register bit mask */ |
#define CSR_RMVF_Set ((uint32_t)0x01000000) |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
/* CFGR2 register bit mask */ |
#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) |
#define CFGR2_PREDIV1 ((uint32_t)0x0000000F) |
#endif |
#ifdef STM32F10X_CL |
#define CFGR2_PREDIV2 ((uint32_t)0x000000F0) |
#define CFGR2_PLL2MUL ((uint32_t)0x00000F00) |
#define CFGR2_PLL3MUL ((uint32_t)0x0000F000) |
#endif /* STM32F10X_CL */ |
/* RCC Flag Mask */ |
#define FLAG_Mask ((uint8_t)0x1F) |
/* CIR register byte 2 (Bits[15:8]) base address */ |
#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) |
/* CIR register byte 3 (Bits[23:16]) base address */ |
#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) |
/* CFGR register byte 4 (Bits[31:24]) base address */ |
#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) |
/* BDCR register base address */ |
#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) |
/** |
* @} |
*/ |
/** @defgroup RCC_Private_Macros |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup RCC_Private_Variables |
* @{ |
*/ |
static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; |
static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; |
/** |
* @} |
*/ |
/** @defgroup RCC_Private_FunctionPrototypes |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup RCC_Private_Functions |
* @{ |
*/ |
/** |
* @brief Resets the RCC clock configuration to the default reset state. |
* @param None |
* @retval None |
*/ |
void RCC_DeInit(void) |
{ |
/* Set HSION bit */ |
RCC->CR |= (uint32_t)0x00000001; |
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ |
#ifndef STM32F10X_CL |
RCC->CFGR &= (uint32_t)0xF8FF0000; |
#else |
RCC->CFGR &= (uint32_t)0xF0FF0000; |
#endif /* STM32F10X_CL */ |
/* Reset HSEON, CSSON and PLLON bits */ |
RCC->CR &= (uint32_t)0xFEF6FFFF; |
/* Reset HSEBYP bit */ |
RCC->CR &= (uint32_t)0xFFFBFFFF; |
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ |
RCC->CFGR &= (uint32_t)0xFF80FFFF; |
#ifdef STM32F10X_CL |
/* Reset PLL2ON and PLL3ON bits */ |
RCC->CR &= (uint32_t)0xEBFFFFFF; |
/* Disable all interrupts and clear pending bits */ |
RCC->CIR = 0x00FF0000; |
/* Reset CFGR2 register */ |
RCC->CFGR2 = 0x00000000; |
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
/* Disable all interrupts and clear pending bits */ |
RCC->CIR = 0x009F0000; |
/* Reset CFGR2 register */ |
RCC->CFGR2 = 0x00000000; |
#else |
/* Disable all interrupts and clear pending bits */ |
RCC->CIR = 0x009F0000; |
#endif /* STM32F10X_CL */ |
} |
/** |
* @brief Configures the External High Speed oscillator (HSE). |
* @note HSE can not be stopped if it is used directly or through the PLL as system clock. |
* @param RCC_HSE: specifies the new state of the HSE. |
* This parameter can be one of the following values: |
* @arg RCC_HSE_OFF: HSE oscillator OFF |
* @arg RCC_HSE_ON: HSE oscillator ON |
* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock |
* @retval None |
*/ |
void RCC_HSEConfig(uint32_t RCC_HSE) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_HSE(RCC_HSE)); |
/* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ |
/* Reset HSEON bit */ |
RCC->CR &= CR_HSEON_Reset; |
/* Reset HSEBYP bit */ |
RCC->CR &= CR_HSEBYP_Reset; |
/* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ |
switch(RCC_HSE) |
{ |
case RCC_HSE_ON: |
/* Set HSEON bit */ |
RCC->CR |= CR_HSEON_Set; |
break; |
case RCC_HSE_Bypass: |
/* Set HSEBYP and HSEON bits */ |
RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; |
break; |
default: |
break; |
} |
} |
/** |
* @brief Waits for HSE start-up. |
* @param None |
* @retval An ErrorStatus enumuration value: |
* - SUCCESS: HSE oscillator is stable and ready to use |
* - ERROR: HSE oscillator not yet ready |
*/ |
ErrorStatus RCC_WaitForHSEStartUp(void) |
{ |
__IO uint32_t StartUpCounter = 0; |
ErrorStatus status = ERROR; |
FlagStatus HSEStatus = RESET; |
/* Wait till HSE is ready and if Time out is reached exit */ |
do |
{ |
HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); |
StartUpCounter++; |
} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); |
if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) |
{ |
status = SUCCESS; |
} |
else |
{ |
status = ERROR; |
} |
return (status); |
} |
/** |
* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. |
* @param HSICalibrationValue: specifies the calibration trimming value. |
* This parameter must be a number between 0 and 0x1F. |
* @retval None |
*/ |
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); |
tmpreg = RCC->CR; |
/* Clear HSITRIM[4:0] bits */ |
tmpreg &= CR_HSITRIM_Mask; |
/* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ |
tmpreg |= (uint32_t)HSICalibrationValue << 3; |
/* Store the new value */ |
RCC->CR = tmpreg; |
} |
/** |
* @brief Enables or disables the Internal High Speed oscillator (HSI). |
* @note HSI can not be stopped if it is used directly or through the PLL as system clock. |
* @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_HSICmd(FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
*(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; |
} |
/** |
* @brief Configures the PLL clock source and multiplication factor. |
* @note This function must be used only when the PLL is disabled. |
* @param RCC_PLLSource: specifies the PLL entry clock source. |
* For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, |
* this parameter can be one of the following values: |
* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry |
* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry |
* For @b other_STM32_devices, this parameter can be one of the following values: |
* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry |
* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry |
* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry |
* @param RCC_PLLMul: specifies the PLL multiplication factor. |
* For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} |
* For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] |
* @retval None |
*/ |
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); |
assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); |
tmpreg = RCC->CFGR; |
/* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ |
tmpreg &= CFGR_PLL_Mask; |
/* Set the PLL configuration bits */ |
tmpreg |= RCC_PLLSource | RCC_PLLMul; |
/* Store the new value */ |
RCC->CFGR = tmpreg; |
} |
/** |
* @brief Enables or disables the PLL. |
* @note The PLL can not be disabled if it is used as system clock. |
* @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_PLLCmd(FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
*(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; |
} |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
/** |
* @brief Configures the PREDIV1 division factor. |
* @note |
* - This function must be used only when the PLL is disabled. |
* - This function applies only to STM32 Connectivity line and Value line |
* devices. |
* @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. |
* This parameter can be one of the following values: |
* @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock |
* @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock |
* @note |
* For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE |
* @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. |
* This parameter can be RCC_PREDIV1_Divx where x:[1,16] |
* @retval None |
*/ |
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); |
assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); |
tmpreg = RCC->CFGR2; |
/* Clear PREDIV1[3:0] and PREDIV1SRC bits */ |
tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); |
/* Set the PREDIV1 clock source and division factor */ |
tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; |
/* Store the new value */ |
RCC->CFGR2 = tmpreg; |
} |
#endif |
#ifdef STM32F10X_CL |
/** |
* @brief Configures the PREDIV2 division factor. |
* @note |
* - This function must be used only when both PLL2 and PLL3 are disabled. |
* - This function applies only to STM32 Connectivity line devices. |
* @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. |
* This parameter can be RCC_PREDIV2_Divx where x:[1,16] |
* @retval None |
*/ |
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); |
tmpreg = RCC->CFGR2; |
/* Clear PREDIV2[3:0] bits */ |
tmpreg &= ~CFGR2_PREDIV2; |
/* Set the PREDIV2 division factor */ |
tmpreg |= RCC_PREDIV2_Div; |
/* Store the new value */ |
RCC->CFGR2 = tmpreg; |
} |
/** |
* @brief Configures the PLL2 multiplication factor. |
* @note |
* - This function must be used only when the PLL2 is disabled. |
* - This function applies only to STM32 Connectivity line devices. |
* @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. |
* This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} |
* @retval None |
*/ |
void RCC_PLL2Config(uint32_t RCC_PLL2Mul) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); |
tmpreg = RCC->CFGR2; |
/* Clear PLL2Mul[3:0] bits */ |
tmpreg &= ~CFGR2_PLL2MUL; |
/* Set the PLL2 configuration bits */ |
tmpreg |= RCC_PLL2Mul; |
/* Store the new value */ |
RCC->CFGR2 = tmpreg; |
} |
/** |
* @brief Enables or disables the PLL2. |
* @note |
* - The PLL2 can not be disabled if it is used indirectly as system clock |
* (i.e. it is used as PLL clock entry that is used as System clock). |
* - This function applies only to STM32 Connectivity line devices. |
* @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_PLL2Cmd(FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
*(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; |
} |
/** |
* @brief Configures the PLL3 multiplication factor. |
* @note |
* - This function must be used only when the PLL3 is disabled. |
* - This function applies only to STM32 Connectivity line devices. |
* @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. |
* This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} |
* @retval None |
*/ |
void RCC_PLL3Config(uint32_t RCC_PLL3Mul) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); |
tmpreg = RCC->CFGR2; |
/* Clear PLL3Mul[3:0] bits */ |
tmpreg &= ~CFGR2_PLL3MUL; |
/* Set the PLL3 configuration bits */ |
tmpreg |= RCC_PLL3Mul; |
/* Store the new value */ |
RCC->CFGR2 = tmpreg; |
} |
/** |
* @brief Enables or disables the PLL3. |
* @note This function applies only to STM32 Connectivity line devices. |
* @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_PLL3Cmd(FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
*(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; |
} |
#endif /* STM32F10X_CL */ |
/** |
* @brief Configures the system clock (SYSCLK). |
* @param RCC_SYSCLKSource: specifies the clock source used as system clock. |
* This parameter can be one of the following values: |
* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock |
* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock |
* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock |
* @retval None |
*/ |
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); |
tmpreg = RCC->CFGR; |
/* Clear SW[1:0] bits */ |
tmpreg &= CFGR_SW_Mask; |
/* Set SW[1:0] bits according to RCC_SYSCLKSource value */ |
tmpreg |= RCC_SYSCLKSource; |
/* Store the new value */ |
RCC->CFGR = tmpreg; |
} |
/** |
* @brief Returns the clock source used as system clock. |
* @param None |
* @retval The clock source used as system clock. The returned value can |
* be one of the following: |
* - 0x00: HSI used as system clock |
* - 0x04: HSE used as system clock |
* - 0x08: PLL used as system clock |
*/ |
uint8_t RCC_GetSYSCLKSource(void) |
{ |
return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); |
} |
/** |
* @brief Configures the AHB clock (HCLK). |
* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from |
* the system clock (SYSCLK). |
* This parameter can be one of the following values: |
* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK |
* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 |
* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 |
* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 |
* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 |
* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 |
* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 |
* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 |
* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 |
* @retval None |
*/ |
void RCC_HCLKConfig(uint32_t RCC_SYSCLK) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_HCLK(RCC_SYSCLK)); |
tmpreg = RCC->CFGR; |
/* Clear HPRE[3:0] bits */ |
tmpreg &= CFGR_HPRE_Reset_Mask; |
/* Set HPRE[3:0] bits according to RCC_SYSCLK value */ |
tmpreg |= RCC_SYSCLK; |
/* Store the new value */ |
RCC->CFGR = tmpreg; |
} |
/** |
* @brief Configures the Low Speed APB clock (PCLK1). |
* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from |
* the AHB clock (HCLK). |
* This parameter can be one of the following values: |
* @arg RCC_HCLK_Div1: APB1 clock = HCLK |
* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 |
* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 |
* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 |
* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 |
* @retval None |
*/ |
void RCC_PCLK1Config(uint32_t RCC_HCLK) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_PCLK(RCC_HCLK)); |
tmpreg = RCC->CFGR; |
/* Clear PPRE1[2:0] bits */ |
tmpreg &= CFGR_PPRE1_Reset_Mask; |
/* Set PPRE1[2:0] bits according to RCC_HCLK value */ |
tmpreg |= RCC_HCLK; |
/* Store the new value */ |
RCC->CFGR = tmpreg; |
} |
/** |
* @brief Configures the High Speed APB clock (PCLK2). |
* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from |
* the AHB clock (HCLK). |
* This parameter can be one of the following values: |
* @arg RCC_HCLK_Div1: APB2 clock = HCLK |
* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 |
* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 |
* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 |
* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 |
* @retval None |
*/ |
void RCC_PCLK2Config(uint32_t RCC_HCLK) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_PCLK(RCC_HCLK)); |
tmpreg = RCC->CFGR; |
/* Clear PPRE2[2:0] bits */ |
tmpreg &= CFGR_PPRE2_Reset_Mask; |
/* Set PPRE2[2:0] bits according to RCC_HCLK value */ |
tmpreg |= RCC_HCLK << 3; |
/* Store the new value */ |
RCC->CFGR = tmpreg; |
} |
/** |
* @brief Enables or disables the specified RCC interrupts. |
* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. |
* |
* For @b STM32_Connectivity_line_devices, this parameter can be any combination |
* of the following values |
* @arg RCC_IT_LSIRDY: LSI ready interrupt |
* @arg RCC_IT_LSERDY: LSE ready interrupt |
* @arg RCC_IT_HSIRDY: HSI ready interrupt |
* @arg RCC_IT_HSERDY: HSE ready interrupt |
* @arg RCC_IT_PLLRDY: PLL ready interrupt |
* @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
* @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
* |
* For @b other_STM32_devices, this parameter can be any combination of the |
* following values |
* @arg RCC_IT_LSIRDY: LSI ready interrupt |
* @arg RCC_IT_LSERDY: LSE ready interrupt |
* @arg RCC_IT_HSIRDY: HSI ready interrupt |
* @arg RCC_IT_HSERDY: HSE ready interrupt |
* @arg RCC_IT_PLLRDY: PLL ready interrupt |
* |
* @param NewState: new state of the specified RCC interrupts. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_IT(RCC_IT)); |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
if (NewState != DISABLE) |
{ |
/* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ |
*(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; |
} |
else |
{ |
/* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ |
*(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; |
} |
} |
#ifndef STM32F10X_CL |
/** |
* @brief Configures the USB clock (USBCLK). |
* @param RCC_USBCLKSource: specifies the USB clock source. This clock is |
* derived from the PLL output. |
* This parameter can be one of the following values: |
* @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB |
* clock source |
* @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source |
* @retval None |
*/ |
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); |
*(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; |
} |
#else |
/** |
* @brief Configures the USB OTG FS clock (OTGFSCLK). |
* This function applies only to STM32 Connectivity line devices. |
* @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. |
* This clock is derived from the PLL output. |
* This parameter can be one of the following values: |
* @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source |
* @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source |
* @retval None |
*/ |
void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); |
*(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; |
} |
#endif /* STM32F10X_CL */ |
/** |
* @brief Configures the ADC clock (ADCCLK). |
* @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from |
* the APB2 clock (PCLK2). |
* This parameter can be one of the following values: |
* @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 |
* @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 |
* @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 |
* @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 |
* @retval None |
*/ |
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) |
{ |
uint32_t tmpreg = 0; |
/* Check the parameters */ |
assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); |
tmpreg = RCC->CFGR; |
/* Clear ADCPRE[1:0] bits */ |
tmpreg &= CFGR_ADCPRE_Reset_Mask; |
/* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ |
tmpreg |= RCC_PCLK2; |
/* Store the new value */ |
RCC->CFGR = tmpreg; |
} |
#ifdef STM32F10X_CL |
/** |
* @brief Configures the I2S2 clock source(I2S2CLK). |
* @note |
* - This function must be called before enabling I2S2 APB clock. |
* - This function applies only to STM32 Connectivity line devices. |
* @param RCC_I2S2CLKSource: specifies the I2S2 clock source. |
* This parameter can be one of the following values: |
* @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry |
* @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry |
* @retval None |
*/ |
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); |
*(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; |
} |
/** |
* @brief Configures the I2S3 clock source(I2S2CLK). |
* @note |
* - This function must be called before enabling I2S3 APB clock. |
* - This function applies only to STM32 Connectivity line devices. |
* @param RCC_I2S3CLKSource: specifies the I2S3 clock source. |
* This parameter can be one of the following values: |
* @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry |
* @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry |
* @retval None |
*/ |
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); |
*(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; |
} |
#endif /* STM32F10X_CL */ |
/** |
* @brief Configures the External Low Speed oscillator (LSE). |
* @param RCC_LSE: specifies the new state of the LSE. |
* This parameter can be one of the following values: |
* @arg RCC_LSE_OFF: LSE oscillator OFF |
* @arg RCC_LSE_ON: LSE oscillator ON |
* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock |
* @retval None |
*/ |
void RCC_LSEConfig(uint8_t RCC_LSE) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_LSE(RCC_LSE)); |
/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ |
/* Reset LSEON bit */ |
*(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; |
/* Reset LSEBYP bit */ |
*(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; |
/* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ |
switch(RCC_LSE) |
{ |
case RCC_LSE_ON: |
/* Set LSEON bit */ |
*(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; |
break; |
case RCC_LSE_Bypass: |
/* Set LSEBYP and LSEON bits */ |
*(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; |
break; |
default: |
break; |
} |
} |
/** |
* @brief Enables or disables the Internal Low Speed oscillator (LSI). |
* @note LSI can not be disabled if the IWDG is running. |
* @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_LSICmd(FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
*(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; |
} |
/** |
* @brief Configures the RTC clock (RTCCLK). |
* @note Once the RTC clock is selected it cant be changed unless the Backup domain is reset. |
* @param RCC_RTCCLKSource: specifies the RTC clock source. |
* This parameter can be one of the following values: |
* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock |
* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock |
* @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock |
* @retval None |
*/ |
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); |
/* Select the RTC clock source */ |
RCC->BDCR |= RCC_RTCCLKSource; |
} |
/** |
* @brief Enables or disables the RTC clock. |
* @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. |
* @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_RTCCLKCmd(FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
*(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; |
} |
/** |
* @brief Returns the frequencies of different on chip clocks. |
* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold |
* the clocks frequencies. |
* @note The result of this function could be not correct when using |
* fractional value for HSE crystal. |
* @retval None |
*/ |
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) |
{ |
uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; |
#ifdef STM32F10X_CL |
uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; |
#endif /* STM32F10X_CL */ |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
uint32_t prediv1factor = 0; |
#endif |
/* Get SYSCLK source -------------------------------------------------------*/ |
tmp = RCC->CFGR & CFGR_SWS_Mask; |
switch (tmp) |
{ |
case 0x00: /* HSI used as system clock */ |
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; |
break; |
case 0x04: /* HSE used as system clock */ |
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; |
break; |
case 0x08: /* PLL used as system clock */ |
/* Get PLL clock source and multiplication factor ----------------------*/ |
pllmull = RCC->CFGR & CFGR_PLLMull_Mask; |
pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; |
#ifndef STM32F10X_CL |
pllmull = ( pllmull >> 18) + 2; |
if (pllsource == 0x00) |
{/* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; |
} |
else |
{ |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; |
/* HSE oscillator clock selected as PREDIV1 clock entry */ |
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; |
#else |
/* HSE selected as PLL clock entry */ |
if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) |
{/* HSE oscillator clock divided by 2 */ |
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; |
} |
else |
{ |
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; |
} |
#endif |
} |
#else |
pllmull = pllmull >> 18; |
if (pllmull != 0x0D) |
{ |
pllmull += 2; |
} |
else |
{ /* PLL multiplication factor = PLL input clock * 6.5 */ |
pllmull = 13 / 2; |
} |
if (pllsource == 0x00) |
{/* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; |
} |
else |
{/* PREDIV1 selected as PLL clock entry */ |
/* Get PREDIV1 clock source and division factor */ |
prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; |
prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; |
if (prediv1source == 0) |
{ /* HSE oscillator clock selected as PREDIV1 clock entry */ |
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; |
} |
else |
{/* PLL2 clock selected as PREDIV1 clock entry */ |
/* Get PREDIV2 division factor and PLL2 multiplication factor */ |
prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; |
pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; |
RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; |
} |
} |
#endif /* STM32F10X_CL */ |
break; |
default: |
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; |
break; |
} |
/* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ |
/* Get HCLK prescaler */ |
tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; |
tmp = tmp >> 4; |
presc = APBAHBPrescTable[tmp]; |
/* HCLK clock frequency */ |
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; |
/* Get PCLK1 prescaler */ |
tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; |
tmp = tmp >> 8; |
presc = APBAHBPrescTable[tmp]; |
/* PCLK1 clock frequency */ |
RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; |
/* Get PCLK2 prescaler */ |
tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; |
tmp = tmp >> 11; |
presc = APBAHBPrescTable[tmp]; |
/* PCLK2 clock frequency */ |
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; |
/* Get ADCCLK prescaler */ |
tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; |
tmp = tmp >> 14; |
presc = ADCPrescTable[tmp]; |
/* ADCCLK clock frequency */ |
RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; |
} |
/** |
* @brief Enables or disables the AHB peripheral clock. |
* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. |
* |
* For @b STM32_Connectivity_line_devices, this parameter can be any combination |
* of the following values: |
* @arg RCC_AHBPeriph_DMA1 |
* @arg RCC_AHBPeriph_DMA2 |
* @arg RCC_AHBPeriph_SRAM |
* @arg RCC_AHBPeriph_FLITF |
* @arg RCC_AHBPeriph_CRC |
* @arg RCC_AHBPeriph_OTG_FS |
* @arg RCC_AHBPeriph_ETH_MAC |
* @arg RCC_AHBPeriph_ETH_MAC_Tx |
* @arg RCC_AHBPeriph_ETH_MAC_Rx |
* |
* For @b other_STM32_devices, this parameter can be any combination of the |
* following values: |
* @arg RCC_AHBPeriph_DMA1 |
* @arg RCC_AHBPeriph_DMA2 |
* @arg RCC_AHBPeriph_SRAM |
* @arg RCC_AHBPeriph_FLITF |
* @arg RCC_AHBPeriph_CRC |
* @arg RCC_AHBPeriph_FSMC |
* @arg RCC_AHBPeriph_SDIO |
* |
* @note SRAM and FLITF clock can be disabled only during sleep mode. |
* @param NewState: new state of the specified peripheral clock. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
if (NewState != DISABLE) |
{ |
RCC->AHBENR |= RCC_AHBPeriph; |
} |
else |
{ |
RCC->AHBENR &= ~RCC_AHBPeriph; |
} |
} |
/** |
* @brief Enables or disables the High Speed APB (APB2) peripheral clock. |
* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. |
* This parameter can be any combination of the following values: |
* @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, |
* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, |
* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, |
* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, |
* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, |
* RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, |
* RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 |
* @param NewState: new state of the specified peripheral clock. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
if (NewState != DISABLE) |
{ |
RCC->APB2ENR |= RCC_APB2Periph; |
} |
else |
{ |
RCC->APB2ENR &= ~RCC_APB2Periph; |
} |
} |
/** |
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock. |
* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. |
* This parameter can be any combination of the following values: |
* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, |
* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, |
* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, |
* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, |
* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, |
* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, |
* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, |
* RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 |
* @param NewState: new state of the specified peripheral clock. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
if (NewState != DISABLE) |
{ |
RCC->APB1ENR |= RCC_APB1Periph; |
} |
else |
{ |
RCC->APB1ENR &= ~RCC_APB1Periph; |
} |
} |
#ifdef STM32F10X_CL |
/** |
* @brief Forces or releases AHB peripheral reset. |
* @note This function applies only to STM32 Connectivity line devices. |
* @param RCC_AHBPeriph: specifies the AHB peripheral to reset. |
* This parameter can be any combination of the following values: |
* @arg RCC_AHBPeriph_OTG_FS |
* @arg RCC_AHBPeriph_ETH_MAC |
* @param NewState: new state of the specified peripheral reset. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
if (NewState != DISABLE) |
{ |
RCC->AHBRSTR |= RCC_AHBPeriph; |
} |
else |
{ |
RCC->AHBRSTR &= ~RCC_AHBPeriph; |
} |
} |
#endif /* STM32F10X_CL */ |
/** |
* @brief Forces or releases High Speed APB (APB2) peripheral reset. |
* @param RCC_APB2Periph: specifies the APB2 peripheral to reset. |
* This parameter can be any combination of the following values: |
* @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, |
* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, |
* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, |
* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, |
* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, |
* RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, |
* RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 |
* @param NewState: new state of the specified peripheral reset. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
if (NewState != DISABLE) |
{ |
RCC->APB2RSTR |= RCC_APB2Periph; |
} |
else |
{ |
RCC->APB2RSTR &= ~RCC_APB2Periph; |
} |
} |
/** |
* @brief Forces or releases Low Speed APB (APB1) peripheral reset. |
* @param RCC_APB1Periph: specifies the APB1 peripheral to reset. |
* This parameter can be any combination of the following values: |
* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, |
* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, |
* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, |
* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, |
* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, |
* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, |
* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, |
* RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 |
* @param NewState: new state of the specified peripheral clock. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
if (NewState != DISABLE) |
{ |
RCC->APB1RSTR |= RCC_APB1Periph; |
} |
else |
{ |
RCC->APB1RSTR &= ~RCC_APB1Periph; |
} |
} |
/** |
* @brief Forces or releases the Backup domain reset. |
* @param NewState: new state of the Backup domain reset. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_BackupResetCmd(FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
*(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; |
} |
/** |
* @brief Enables or disables the Clock Security System. |
* @param NewState: new state of the Clock Security System.. |
* This parameter can be: ENABLE or DISABLE. |
* @retval None |
*/ |
void RCC_ClockSecuritySystemCmd(FunctionalState NewState) |
{ |
/* Check the parameters */ |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
*(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; |
} |
/** |
* @brief Selects the clock source to output on MCO pin. |
* @param RCC_MCO: specifies the clock source to output. |
* |
* For @b STM32_Connectivity_line_devices, this parameter can be one of the |
* following values: |
* @arg RCC_MCO_NoClock: No clock selected |
* @arg RCC_MCO_SYSCLK: System clock selected |
* @arg RCC_MCO_HSI: HSI oscillator clock selected |
* @arg RCC_MCO_HSE: HSE oscillator clock selected |
* @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected |
* @arg RCC_MCO_PLL2CLK: PLL2 clock selected |
* @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected |
* @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected |
* @arg RCC_MCO_PLL3CLK: PLL3 clock selected |
* |
* For @b other_STM32_devices, this parameter can be one of the following values: |
* @arg RCC_MCO_NoClock: No clock selected |
* @arg RCC_MCO_SYSCLK: System clock selected |
* @arg RCC_MCO_HSI: HSI oscillator clock selected |
* @arg RCC_MCO_HSE: HSE oscillator clock selected |
* @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected |
* |
* @retval None |
*/ |
void RCC_MCOConfig(uint8_t RCC_MCO) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_MCO(RCC_MCO)); |
/* Perform Byte access to MCO bits to select the MCO source */ |
*(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; |
} |
/** |
* @brief Checks whether the specified RCC flag is set or not. |
* @param RCC_FLAG: specifies the flag to check. |
* |
* For @b STM32_Connectivity_line_devices, this parameter can be one of the |
* following values: |
* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready |
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready |
* @arg RCC_FLAG_PLLRDY: PLL clock ready |
* @arg RCC_FLAG_PLL2RDY: PLL2 clock ready |
* @arg RCC_FLAG_PLL3RDY: PLL3 clock ready |
* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready |
* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready |
* @arg RCC_FLAG_PINRST: Pin reset |
* @arg RCC_FLAG_PORRST: POR/PDR reset |
* @arg RCC_FLAG_SFTRST: Software reset |
* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset |
* @arg RCC_FLAG_WWDGRST: Window Watchdog reset |
* @arg RCC_FLAG_LPWRRST: Low Power reset |
* |
* For @b other_STM32_devices, this parameter can be one of the following values: |
* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready |
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready |
* @arg RCC_FLAG_PLLRDY: PLL clock ready |
* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready |
* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready |
* @arg RCC_FLAG_PINRST: Pin reset |
* @arg RCC_FLAG_PORRST: POR/PDR reset |
* @arg RCC_FLAG_SFTRST: Software reset |
* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset |
* @arg RCC_FLAG_WWDGRST: Window Watchdog reset |
* @arg RCC_FLAG_LPWRRST: Low Power reset |
* |
* @retval The new state of RCC_FLAG (SET or RESET). |
*/ |
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) |
{ |
uint32_t tmp = 0; |
uint32_t statusreg = 0; |
FlagStatus bitstatus = RESET; |
/* Check the parameters */ |
assert_param(IS_RCC_FLAG(RCC_FLAG)); |
/* Get the RCC register index */ |
tmp = RCC_FLAG >> 5; |
if (tmp == 1) /* The flag to check is in CR register */ |
{ |
statusreg = RCC->CR; |
} |
else if (tmp == 2) /* The flag to check is in BDCR register */ |
{ |
statusreg = RCC->BDCR; |
} |
else /* The flag to check is in CSR register */ |
{ |
statusreg = RCC->CSR; |
} |
/* Get the flag position */ |
tmp = RCC_FLAG & FLAG_Mask; |
if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) |
{ |
bitstatus = SET; |
} |
else |
{ |
bitstatus = RESET; |
} |
/* Return the flag status */ |
return bitstatus; |
} |
/** |
* @brief Clears the RCC reset flags. |
* @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, |
* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST |
* @param None |
* @retval None |
*/ |
void RCC_ClearFlag(void) |
{ |
/* Set RMVF bit to clear the reset flags */ |
RCC->CSR |= CSR_RMVF_Set; |
} |
/** |
* @brief Checks whether the specified RCC interrupt has occurred or not. |
* @param RCC_IT: specifies the RCC interrupt source to check. |
* |
* For @b STM32_Connectivity_line_devices, this parameter can be one of the |
* following values: |
* @arg RCC_IT_LSIRDY: LSI ready interrupt |
* @arg RCC_IT_LSERDY: LSE ready interrupt |
* @arg RCC_IT_HSIRDY: HSI ready interrupt |
* @arg RCC_IT_HSERDY: HSE ready interrupt |
* @arg RCC_IT_PLLRDY: PLL ready interrupt |
* @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
* @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
* @arg RCC_IT_CSS: Clock Security System interrupt |
* |
* For @b other_STM32_devices, this parameter can be one of the following values: |
* @arg RCC_IT_LSIRDY: LSI ready interrupt |
* @arg RCC_IT_LSERDY: LSE ready interrupt |
* @arg RCC_IT_HSIRDY: HSI ready interrupt |
* @arg RCC_IT_HSERDY: HSE ready interrupt |
* @arg RCC_IT_PLLRDY: PLL ready interrupt |
* @arg RCC_IT_CSS: Clock Security System interrupt |
* |
* @retval The new state of RCC_IT (SET or RESET). |
*/ |
ITStatus RCC_GetITStatus(uint8_t RCC_IT) |
{ |
ITStatus bitstatus = RESET; |
/* Check the parameters */ |
assert_param(IS_RCC_GET_IT(RCC_IT)); |
/* Check the status of the specified RCC interrupt */ |
if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) |
{ |
bitstatus = SET; |
} |
else |
{ |
bitstatus = RESET; |
} |
/* Return the RCC_IT status */ |
return bitstatus; |
} |
/** |
* @brief Clears the RCCs interrupt pending bits. |
* @param RCC_IT: specifies the interrupt pending bit to clear. |
* |
* For @b STM32_Connectivity_line_devices, this parameter can be any combination |
* of the following values: |
* @arg RCC_IT_LSIRDY: LSI ready interrupt |
* @arg RCC_IT_LSERDY: LSE ready interrupt |
* @arg RCC_IT_HSIRDY: HSI ready interrupt |
* @arg RCC_IT_HSERDY: HSE ready interrupt |
* @arg RCC_IT_PLLRDY: PLL ready interrupt |
* @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
* @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
* @arg RCC_IT_CSS: Clock Security System interrupt |
* |
* For @b other_STM32_devices, this parameter can be any combination of the |
* following values: |
* @arg RCC_IT_LSIRDY: LSI ready interrupt |
* @arg RCC_IT_LSERDY: LSE ready interrupt |
* @arg RCC_IT_HSIRDY: HSI ready interrupt |
* @arg RCC_IT_HSERDY: HSE ready interrupt |
* @arg RCC_IT_PLLRDY: PLL ready interrupt |
* |
* @arg RCC_IT_CSS: Clock Security System interrupt |
* @retval None |
*/ |
void RCC_ClearITPendingBit(uint8_t RCC_IT) |
{ |
/* Check the parameters */ |
assert_param(IS_RCC_CLEAR_IT(RCC_IT)); |
/* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt |
pending bits */ |
*(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; |
} |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/stm32f10x_rcc.h |
---|
0,0 → 1,726 |
/** |
****************************************************************************** |
* @file stm32f10x_rcc.h |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief This file contains all the functions prototypes for the RCC firmware |
* library. |
****************************************************************************** |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
/* Define to prevent recursive inclusion -------------------------------------*/ |
#ifndef __STM32F10x_RCC_H |
#define __STM32F10x_RCC_H |
#ifdef __cplusplus |
extern "C" { |
#endif |
/* Includes ------------------------------------------------------------------*/ |
#include "stm32f10x.h" |
/** @addtogroup STM32F10x_StdPeriph_Driver |
* @{ |
*/ |
/** @addtogroup RCC |
* @{ |
*/ |
/** @defgroup RCC_Exported_Types |
* @{ |
*/ |
typedef struct |
{ |
uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ |
uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ |
uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ |
uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ |
uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ |
}RCC_ClocksTypeDef; |
/** |
* @} |
*/ |
/** @defgroup RCC_Exported_Constants |
* @{ |
*/ |
/** @defgroup HSE_configuration |
* @{ |
*/ |
#define RCC_HSE_OFF ((uint32_t)0x00000000) |
#define RCC_HSE_ON ((uint32_t)0x00010000) |
#define RCC_HSE_Bypass ((uint32_t)0x00040000) |
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
((HSE) == RCC_HSE_Bypass)) |
/** |
* @} |
*/ |
/** @defgroup PLL_entry_clock_source |
* @{ |
*/ |
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) |
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) |
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) |
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ |
((SOURCE) == RCC_PLLSource_HSE_Div1) || \ |
((SOURCE) == RCC_PLLSource_HSE_Div2)) |
#else |
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) |
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ |
((SOURCE) == RCC_PLLSource_PREDIV1)) |
#endif /* STM32F10X_CL */ |
/** |
* @} |
*/ |
/** @defgroup PLL_multiplication_factor |
* @{ |
*/ |
#ifndef STM32F10X_CL |
#define RCC_PLLMul_2 ((uint32_t)0x00000000) |
#define RCC_PLLMul_3 ((uint32_t)0x00040000) |
#define RCC_PLLMul_4 ((uint32_t)0x00080000) |
#define RCC_PLLMul_5 ((uint32_t)0x000C0000) |
#define RCC_PLLMul_6 ((uint32_t)0x00100000) |
#define RCC_PLLMul_7 ((uint32_t)0x00140000) |
#define RCC_PLLMul_8 ((uint32_t)0x00180000) |
#define RCC_PLLMul_9 ((uint32_t)0x001C0000) |
#define RCC_PLLMul_10 ((uint32_t)0x00200000) |
#define RCC_PLLMul_11 ((uint32_t)0x00240000) |
#define RCC_PLLMul_12 ((uint32_t)0x00280000) |
#define RCC_PLLMul_13 ((uint32_t)0x002C0000) |
#define RCC_PLLMul_14 ((uint32_t)0x00300000) |
#define RCC_PLLMul_15 ((uint32_t)0x00340000) |
#define RCC_PLLMul_16 ((uint32_t)0x00380000) |
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ |
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ |
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ |
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ |
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ |
((MUL) == RCC_PLLMul_16)) |
#else |
#define RCC_PLLMul_4 ((uint32_t)0x00080000) |
#define RCC_PLLMul_5 ((uint32_t)0x000C0000) |
#define RCC_PLLMul_6 ((uint32_t)0x00100000) |
#define RCC_PLLMul_7 ((uint32_t)0x00140000) |
#define RCC_PLLMul_8 ((uint32_t)0x00180000) |
#define RCC_PLLMul_9 ((uint32_t)0x001C0000) |
#define RCC_PLLMul_6_5 ((uint32_t)0x00340000) |
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ |
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
((MUL) == RCC_PLLMul_6_5)) |
#endif /* STM32F10X_CL */ |
/** |
* @} |
*/ |
/** @defgroup PREDIV1_division_factor |
* @{ |
*/ |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) |
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) |
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) |
#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) |
#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) |
#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) |
#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) |
#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) |
#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) |
#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) |
#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) |
#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) |
#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) |
#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) |
#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) |
#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) |
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ |
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ |
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ |
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ |
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ |
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ |
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ |
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) |
#endif |
/** |
* @} |
*/ |
/** @defgroup PREDIV1_clock_source |
* @{ |
*/ |
#ifdef STM32F10X_CL |
/* PREDIV1 clock source (for STM32 connectivity line devices) */ |
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) |
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) |
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ |
((SOURCE) == RCC_PREDIV1_Source_PLL2)) |
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
/* PREDIV1 clock source (for STM32 Value line devices) */ |
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) |
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) |
#endif |
/** |
* @} |
*/ |
#ifdef STM32F10X_CL |
/** @defgroup PREDIV2_division_factor |
* @{ |
*/ |
#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) |
#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) |
#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) |
#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) |
#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) |
#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) |
#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) |
#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) |
#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) |
#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) |
#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) |
#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) |
#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) |
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) |
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) |
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) |
#define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ |
((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ |
((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ |
((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ |
((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ |
((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ |
((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ |
((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) |
/** |
* @} |
*/ |
/** @defgroup PLL2_multiplication_factor |
* @{ |
*/ |
#define RCC_PLL2Mul_8 ((uint32_t)0x00000600) |
#define RCC_PLL2Mul_9 ((uint32_t)0x00000700) |
#define RCC_PLL2Mul_10 ((uint32_t)0x00000800) |
#define RCC_PLL2Mul_11 ((uint32_t)0x00000900) |
#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) |
#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) |
#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) |
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) |
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) |
#define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ |
((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ |
((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ |
((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ |
((MUL) == RCC_PLL2Mul_20)) |
/** |
* @} |
*/ |
/** @defgroup PLL3_multiplication_factor |
* @{ |
*/ |
#define RCC_PLL3Mul_8 ((uint32_t)0x00006000) |
#define RCC_PLL3Mul_9 ((uint32_t)0x00007000) |
#define RCC_PLL3Mul_10 ((uint32_t)0x00008000) |
#define RCC_PLL3Mul_11 ((uint32_t)0x00009000) |
#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) |
#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) |
#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) |
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) |
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) |
#define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ |
((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ |
((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ |
((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ |
((MUL) == RCC_PLL3Mul_20)) |
/** |
* @} |
*/ |
#endif /* STM32F10X_CL */ |
/** @defgroup System_clock_source |
* @{ |
*/ |
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) |
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) |
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) |
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ |
((SOURCE) == RCC_SYSCLKSource_HSE) || \ |
((SOURCE) == RCC_SYSCLKSource_PLLCLK)) |
/** |
* @} |
*/ |
/** @defgroup AHB_clock_source |
* @{ |
*/ |
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) |
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) |
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) |
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) |
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) |
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) |
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) |
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) |
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) |
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ |
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ |
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ |
((HCLK) == RCC_SYSCLK_Div512)) |
/** |
* @} |
*/ |
/** @defgroup APB1_APB2_clock_source |
* @{ |
*/ |
#define RCC_HCLK_Div1 ((uint32_t)0x00000000) |
#define RCC_HCLK_Div2 ((uint32_t)0x00000400) |
#define RCC_HCLK_Div4 ((uint32_t)0x00000500) |
#define RCC_HCLK_Div8 ((uint32_t)0x00000600) |
#define RCC_HCLK_Div16 ((uint32_t)0x00000700) |
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ |
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ |
((PCLK) == RCC_HCLK_Div16)) |
/** |
* @} |
*/ |
/** @defgroup RCC_Interrupt_source |
* @{ |
*/ |
#define RCC_IT_LSIRDY ((uint8_t)0x01) |
#define RCC_IT_LSERDY ((uint8_t)0x02) |
#define RCC_IT_HSIRDY ((uint8_t)0x04) |
#define RCC_IT_HSERDY ((uint8_t)0x08) |
#define RCC_IT_PLLRDY ((uint8_t)0x10) |
#define RCC_IT_CSS ((uint8_t)0x80) |
#ifndef STM32F10X_CL |
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) |
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) |
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) |
#else |
#define RCC_IT_PLL2RDY ((uint8_t)0x20) |
#define RCC_IT_PLL3RDY ((uint8_t)0x40) |
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) |
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ |
((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) |
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) |
#endif /* STM32F10X_CL */ |
/** |
* @} |
*/ |
#ifndef STM32F10X_CL |
/** @defgroup USB_Device_clock_source |
* @{ |
*/ |
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) |
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) |
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ |
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) |
/** |
* @} |
*/ |
#else |
/** @defgroup USB_OTG_FS_clock_source |
* @{ |
*/ |
#define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) |
#define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) |
#define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ |
((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) |
/** |
* @} |
*/ |
#endif /* STM32F10X_CL */ |
#ifdef STM32F10X_CL |
/** @defgroup I2S2_clock_source |
* @{ |
*/ |
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) |
#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) |
#define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ |
((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) |
/** |
* @} |
*/ |
/** @defgroup I2S3_clock_source |
* @{ |
*/ |
#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) |
#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) |
#define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ |
((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) |
/** |
* @} |
*/ |
#endif /* STM32F10X_CL */ |
/** @defgroup ADC_clock_source |
* @{ |
*/ |
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) |
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) |
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) |
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) |
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ |
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) |
/** |
* @} |
*/ |
/** @defgroup LSE_configuration |
* @{ |
*/ |
#define RCC_LSE_OFF ((uint8_t)0x00) |
#define RCC_LSE_ON ((uint8_t)0x01) |
#define RCC_LSE_Bypass ((uint8_t)0x04) |
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
((LSE) == RCC_LSE_Bypass)) |
/** |
* @} |
*/ |
/** @defgroup RTC_clock_source |
* @{ |
*/ |
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) |
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) |
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) |
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ |
((SOURCE) == RCC_RTCCLKSource_LSI) || \ |
((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) |
/** |
* @} |
*/ |
/** @defgroup AHB_peripheral |
* @{ |
*/ |
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) |
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) |
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) |
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) |
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) |
#ifndef STM32F10X_CL |
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) |
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) |
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) |
#else |
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) |
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) |
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) |
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) |
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) |
#define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) |
#endif /* STM32F10X_CL */ |
/** |
* @} |
*/ |
/** @defgroup APB2_peripheral |
* @{ |
*/ |
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) |
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) |
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) |
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) |
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) |
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) |
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) |
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) |
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) |
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) |
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) |
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) |
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) |
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) |
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) |
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) |
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) |
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) |
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) |
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) |
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) |
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) |
/** |
* @} |
*/ |
/** @defgroup APB1_peripheral |
* @{ |
*/ |
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) |
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) |
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) |
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) |
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) |
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) |
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) |
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) |
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) |
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) |
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) |
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) |
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) |
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) |
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) |
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) |
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) |
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) |
#define RCC_APB1Periph_USB ((uint32_t)0x00800000) |
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) |
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) |
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) |
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) |
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) |
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) |
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) |
/** |
* @} |
*/ |
/** @defgroup Clock_source_to_output_on_MCO_pin |
* @{ |
*/ |
#define RCC_MCO_NoClock ((uint8_t)0x00) |
#define RCC_MCO_SYSCLK ((uint8_t)0x04) |
#define RCC_MCO_HSI ((uint8_t)0x05) |
#define RCC_MCO_HSE ((uint8_t)0x06) |
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) |
#ifndef STM32F10X_CL |
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ |
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ |
((MCO) == RCC_MCO_PLLCLK_Div2)) |
#else |
#define RCC_MCO_PLL2CLK ((uint8_t)0x08) |
#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) |
#define RCC_MCO_XT1 ((uint8_t)0x0A) |
#define RCC_MCO_PLL3CLK ((uint8_t)0x0B) |
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ |
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ |
((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ |
((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ |
((MCO) == RCC_MCO_PLL3CLK)) |
#endif /* STM32F10X_CL */ |
/** |
* @} |
*/ |
/** @defgroup RCC_Flag |
* @{ |
*/ |
#define RCC_FLAG_HSIRDY ((uint8_t)0x21) |
#define RCC_FLAG_HSERDY ((uint8_t)0x31) |
#define RCC_FLAG_PLLRDY ((uint8_t)0x39) |
#define RCC_FLAG_LSERDY ((uint8_t)0x41) |
#define RCC_FLAG_LSIRDY ((uint8_t)0x61) |
#define RCC_FLAG_PINRST ((uint8_t)0x7A) |
#define RCC_FLAG_PORRST ((uint8_t)0x7B) |
#define RCC_FLAG_SFTRST ((uint8_t)0x7C) |
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) |
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) |
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) |
#ifndef STM32F10X_CL |
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ |
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ |
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ |
((FLAG) == RCC_FLAG_LPWRRST)) |
#else |
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) |
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) |
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ |
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ |
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ |
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ |
((FLAG) == RCC_FLAG_LPWRRST)) |
#endif /* STM32F10X_CL */ |
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/** @defgroup RCC_Exported_Macros |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @defgroup RCC_Exported_Functions |
* @{ |
*/ |
void RCC_DeInit(void); |
void RCC_HSEConfig(uint32_t RCC_HSE); |
ErrorStatus RCC_WaitForHSEStartUp(void); |
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); |
void RCC_HSICmd(FunctionalState NewState); |
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); |
void RCC_PLLCmd(FunctionalState NewState); |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); |
#endif |
#ifdef STM32F10X_CL |
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); |
void RCC_PLL2Config(uint32_t RCC_PLL2Mul); |
void RCC_PLL2Cmd(FunctionalState NewState); |
void RCC_PLL3Config(uint32_t RCC_PLL3Mul); |
void RCC_PLL3Cmd(FunctionalState NewState); |
#endif /* STM32F10X_CL */ |
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); |
uint8_t RCC_GetSYSCLKSource(void); |
void RCC_HCLKConfig(uint32_t RCC_SYSCLK); |
void RCC_PCLK1Config(uint32_t RCC_HCLK); |
void RCC_PCLK2Config(uint32_t RCC_HCLK); |
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); |
#ifndef STM32F10X_CL |
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); |
#else |
void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); |
#endif /* STM32F10X_CL */ |
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); |
#ifdef STM32F10X_CL |
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); |
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); |
#endif /* STM32F10X_CL */ |
void RCC_LSEConfig(uint8_t RCC_LSE); |
void RCC_LSICmd(FunctionalState NewState); |
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); |
void RCC_RTCCLKCmd(FunctionalState NewState); |
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); |
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
#ifdef STM32F10X_CL |
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
#endif /* STM32F10X_CL */ |
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
void RCC_BackupResetCmd(FunctionalState NewState); |
void RCC_ClockSecuritySystemCmd(FunctionalState NewState); |
void RCC_MCOConfig(uint8_t RCC_MCO); |
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); |
void RCC_ClearFlag(void); |
ITStatus RCC_GetITStatus(uint8_t RCC_IT); |
void RCC_ClearITPendingBit(uint8_t RCC_IT); |
#ifdef __cplusplus |
} |
#endif |
#endif /* __STM32F10x_RCC_H */ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/lib/system_stm32f10x.h |
---|
0,0 → 1,97 |
/** |
****************************************************************************** |
* @file system_stm32f10x.h |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. |
****************************************************************************** |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
****************************************************************************** |
*/ |
/** @addtogroup CMSIS |
* @{ |
*/ |
/** @addtogroup stm32f10x_system |
* @{ |
*/ |
/** |
* @brief Define to prevent recursive inclusion |
*/ |
#ifndef __SYSTEM_STM32F10X_H |
#define __SYSTEM_STM32F10X_H |
#ifdef __cplusplus |
extern "C" { |
#endif |
/** @addtogroup STM32F10x_System_Includes |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @addtogroup STM32F10x_System_Exported_types |
* @{ |
*/ |
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ |
/** |
* @} |
*/ |
/** @addtogroup STM32F10x_System_Exported_Constants |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @addtogroup STM32F10x_System_Exported_Macros |
* @{ |
*/ |
/** |
* @} |
*/ |
/** @addtogroup STM32F10x_System_Exported_Functions |
* @{ |
*/ |
extern void SystemInit(void); |
extern void SystemCoreClockUpdate(void); |
/** |
* @} |
*/ |
#ifdef __cplusplus |
} |
#endif |
#endif /*__SYSTEM_STM32F10X_H */ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/startup_stm32f10x_md.s |
---|
0,0 → 1,357 |
/** |
****************************************************************************** |
* @file startup_stm32f10x_md.s |
* @author MCD Application Team |
* @version V3.3.0 |
* @date 04/16/2010 |
* @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. |
* This module performs: |
* - Set the initial SP |
* - Set the initial PC == Reset_Handler, |
* - Set the vector table entries with the exceptions ISR address |
* - Configure the clock system |
* - Branches to main in the C library (which eventually |
* calls main()). |
* After Reset the Cortex-M3 processor is in Thread mode, |
* priority is Privileged, and the Stack is set to Main. |
******************************************************************************* |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
.syntax unified |
.cpu cortex-m3 |
.fpu softvfp |
.thumb |
.global g_pfnVectors |
.global Default_Handler |
/* start address for the initialization values of the .data section. |
defined in linker script */ |
.word _sidata |
/* start address for the .data section. defined in linker script */ |
.word _sdata |
/* end address for the .data section. defined in linker script */ |
.word _edata |
/* start address for the .bss section. defined in linker script */ |
.word _sbss |
/* end address for the .bss section. defined in linker script */ |
.word _ebss |
.equ BootRAM, 0xF108F85F |
/** |
* @brief This is the code that gets called when the processor first |
* starts execution following a reset event. Only the absolutely |
* necessary set is performed, after which the application |
* supplied main() routine is called. |
* @param None |
* @retval : None |
*/ |
.section .text.Reset_Handler |
.weak Reset_Handler |
.type Reset_Handler, %function |
Reset_Handler: |
/* Copy the data segment initializers from flash to SRAM */ |
movs r1, #0 |
b LoopCopyDataInit |
CopyDataInit: |
ldr r3, =_sidata |
ldr r3, [r3, r1] |
str r3, [r0, r1] |
adds r1, r1, #4 |
LoopCopyDataInit: |
ldr r0, =_sdata |
ldr r3, =_edata |
adds r2, r0, r1 |
cmp r2, r3 |
bcc CopyDataInit |
ldr r2, =_sbss |
b LoopFillZerobss |
/* Zero fill the bss segment. */ |
FillZerobss: |
movs r3, #0 |
str r3, [r2], #4 |
LoopFillZerobss: |
ldr r3, = _ebss |
cmp r2, r3 |
bcc FillZerobss |
/* Call the clock system intitialization function.*/ |
bl SystemInit |
/* Call the application's entry point.*/ |
bl main |
bx lr |
.size Reset_Handler, .-Reset_Handler |
/** |
* @brief This is the code that gets called when the processor receives an |
* unexpected interrupt. This simply enters an infinite loop, preserving |
* the system state for examination by a debugger. |
* @param None |
* @retval None |
*/ |
.section .text.Default_Handler,"ax",%progbits |
Default_Handler: |
Infinite_Loop: |
b Infinite_Loop |
.size Default_Handler, .-Default_Handler |
/****************************************************************************** |
* |
* The minimal vector table for a Cortex M3. Note that the proper constructs |
* must be placed on this to ensure that it ends up at physical address |
* 0x0000.0000. |
* |
******************************************************************************/ |
.section .isr_vector,"a",%progbits |
.type g_pfnVectors, %object |
.size g_pfnVectors, .-g_pfnVectors |
g_pfnVectors: |
.word _estack |
.word Reset_Handler |
.word NMI_Handler |
.word HardFault_Handler |
.word MemManage_Handler |
.word BusFault_Handler |
.word UsageFault_Handler |
.word 0 |
.word 0 |
.word 0 |
.word 0 |
.word SVC_Handler |
.word DebugMon_Handler |
.word 0 |
.word PendSV_Handler |
.word SysTick_Handler |
.word WWDG_IRQHandler |
.word PVD_IRQHandler |
.word TAMPER_IRQHandler |
.word RTC_IRQHandler |
.word FLASH_IRQHandler |
.word RCC_IRQHandler |
.word EXTI0_IRQHandler |
.word EXTI1_IRQHandler |
.word EXTI2_IRQHandler |
.word EXTI3_IRQHandler |
.word EXTI4_IRQHandler |
.word DMA1_Channel1_IRQHandler |
.word DMA1_Channel2_IRQHandler |
.word DMA1_Channel3_IRQHandler |
.word DMA1_Channel4_IRQHandler |
.word DMA1_Channel5_IRQHandler |
.word DMA1_Channel6_IRQHandler |
.word DMA1_Channel7_IRQHandler |
.word ADC1_2_IRQHandler |
.word USB_HP_CAN1_TX_IRQHandler |
.word USB_LP_CAN1_RX0_IRQHandler |
.word CAN1_RX1_IRQHandler |
.word CAN1_SCE_IRQHandler |
.word EXTI9_5_IRQHandler |
.word TIM1_BRK_IRQHandler |
.word TIM1_UP_IRQHandler |
.word TIM1_TRG_COM_IRQHandler |
.word TIM1_CC_IRQHandler |
.word TIM2_IRQHandler |
.word TIM3_IRQHandler |
.word TIM4_IRQHandler |
.word I2C1_EV_IRQHandler |
.word I2C1_ER_IRQHandler |
.word I2C2_EV_IRQHandler |
.word I2C2_ER_IRQHandler |
.word SPI1_IRQHandler |
.word SPI2_IRQHandler |
.word USART1_IRQHandler |
.word USART2_IRQHandler |
.word USART3_IRQHandler |
.word EXTI15_10_IRQHandler |
.word RTCAlarm_IRQHandler |
.word USBWakeUp_IRQHandler |
.word 0 |
.word 0 |
.word 0 |
.word 0 |
.word 0 |
.word 0 |
.word 0 |
.word BootRAM /* @0x108. This is for boot in RAM mode for |
STM32F10x Medium Density devices. */ |
/******************************************************************************* |
* |
* Provide weak aliases for each Exception handler to the Default_Handler. |
* As they are weak aliases, any function with the same name will override |
* this definition. |
* |
*******************************************************************************/ |
.weak NMI_Handler |
.thumb_set NMI_Handler,Default_Handler |
.weak HardFault_Handler |
.thumb_set HardFault_Handler,Default_Handler |
.weak MemManage_Handler |
.thumb_set MemManage_Handler,Default_Handler |
.weak BusFault_Handler |
.thumb_set BusFault_Handler,Default_Handler |
.weak UsageFault_Handler |
.thumb_set UsageFault_Handler,Default_Handler |
.weak SVC_Handler |
.thumb_set SVC_Handler,Default_Handler |
.weak DebugMon_Handler |
.thumb_set DebugMon_Handler,Default_Handler |
.weak PendSV_Handler |
.thumb_set PendSV_Handler,Default_Handler |
.weak SysTick_Handler |
.thumb_set SysTick_Handler,Default_Handler |
.weak WWDG_IRQHandler |
.thumb_set WWDG_IRQHandler,Default_Handler |
.weak PVD_IRQHandler |
.thumb_set PVD_IRQHandler,Default_Handler |
.weak TAMPER_IRQHandler |
.thumb_set TAMPER_IRQHandler,Default_Handler |
.weak RTC_IRQHandler |
.thumb_set RTC_IRQHandler,Default_Handler |
.weak FLASH_IRQHandler |
.thumb_set FLASH_IRQHandler,Default_Handler |
.weak RCC_IRQHandler |
.thumb_set RCC_IRQHandler,Default_Handler |
.weak EXTI0_IRQHandler |
.thumb_set EXTI0_IRQHandler,Default_Handler |
.weak EXTI1_IRQHandler |
.thumb_set EXTI1_IRQHandler,Default_Handler |
.weak EXTI2_IRQHandler |
.thumb_set EXTI2_IRQHandler,Default_Handler |
.weak EXTI3_IRQHandler |
.thumb_set EXTI3_IRQHandler,Default_Handler |
.weak EXTI4_IRQHandler |
.thumb_set EXTI4_IRQHandler,Default_Handler |
.weak DMA1_Channel1_IRQHandler |
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler |
.weak DMA1_Channel2_IRQHandler |
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler |
.weak DMA1_Channel3_IRQHandler |
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler |
.weak DMA1_Channel4_IRQHandler |
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler |
.weak DMA1_Channel5_IRQHandler |
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler |
.weak DMA1_Channel6_IRQHandler |
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler |
.weak DMA1_Channel7_IRQHandler |
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler |
.weak ADC1_2_IRQHandler |
.thumb_set ADC1_2_IRQHandler,Default_Handler |
.weak USB_HP_CAN1_TX_IRQHandler |
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler |
.weak USB_LP_CAN1_RX0_IRQHandler |
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler |
.weak CAN1_RX1_IRQHandler |
.thumb_set CAN1_RX1_IRQHandler,Default_Handler |
.weak CAN1_SCE_IRQHandler |
.thumb_set CAN1_SCE_IRQHandler,Default_Handler |
.weak EXTI9_5_IRQHandler |
.thumb_set EXTI9_5_IRQHandler,Default_Handler |
.weak TIM1_BRK_IRQHandler |
.thumb_set TIM1_BRK_IRQHandler,Default_Handler |
.weak TIM1_UP_IRQHandler |
.thumb_set TIM1_UP_IRQHandler,Default_Handler |
.weak TIM1_TRG_COM_IRQHandler |
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler |
.weak TIM1_CC_IRQHandler |
.thumb_set TIM1_CC_IRQHandler,Default_Handler |
.weak TIM2_IRQHandler |
.thumb_set TIM2_IRQHandler,Default_Handler |
.weak TIM3_IRQHandler |
.thumb_set TIM3_IRQHandler,Default_Handler |
.weak TIM4_IRQHandler |
.thumb_set TIM4_IRQHandler,Default_Handler |
.weak I2C1_EV_IRQHandler |
.thumb_set I2C1_EV_IRQHandler,Default_Handler |
.weak I2C1_ER_IRQHandler |
.thumb_set I2C1_ER_IRQHandler,Default_Handler |
.weak I2C2_EV_IRQHandler |
.thumb_set I2C2_EV_IRQHandler,Default_Handler |
.weak I2C2_ER_IRQHandler |
.thumb_set I2C2_ER_IRQHandler,Default_Handler |
.weak SPI1_IRQHandler |
.thumb_set SPI1_IRQHandler,Default_Handler |
.weak SPI2_IRQHandler |
.thumb_set SPI2_IRQHandler,Default_Handler |
.weak USART1_IRQHandler |
.thumb_set USART1_IRQHandler,Default_Handler |
.weak USART2_IRQHandler |
.thumb_set USART2_IRQHandler,Default_Handler |
.weak USART3_IRQHandler |
.thumb_set USART3_IRQHandler,Default_Handler |
.weak EXTI15_10_IRQHandler |
.thumb_set EXTI15_10_IRQHandler,Default_Handler |
.weak RTCAlarm_IRQHandler |
.thumb_set RTCAlarm_IRQHandler,Default_Handler |
.weak USBWakeUp_IRQHandler |
.thumb_set USBWakeUp_IRQHandler,Default_Handler |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/stm32_128K_20K.ld |
---|
0,0 → 1,156 |
/* |
***************************************************************************** |
** File : stm32_flash.ld |
** |
** Abstract : Linker script for STM32F103 Device with |
** 128KByte FLASH, 20KByte RAM |
** |
** Set heap size, stack size and stack location according |
** to application requirements. |
** |
** Set memory bank area and size if external memory is used. |
** |
** Target : STMicroelectronics STM32 |
** |
***************************************************************************** |
*/ |
/* Entry Point */ |
ENTRY(Reset_Handler) |
/* Highest address of the user mode stack */ |
_estack = 0x20005000; /* end of 8K RAM */ |
/* Generate a link error if heap and stack don't fit into RAM */ |
_Min_Heap_Size = 0; /* required amount of heap */ |
_Min_Stack_Size = 0x800; /* required amount of stack */ |
/* Specify the memory areas */ |
MEMORY |
{ |
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K |
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K |
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K |
} |
/* Define output sections */ |
SECTIONS |
{ |
/* The startup code goes first into FLASH */ |
.isr_vector : |
{ |
. = ALIGN(4); |
KEEP(*(.isr_vector)) /* Startup code */ |
. = ALIGN(4); |
} >FLASH |
/* The program code and other data goes into FLASH */ |
.text : |
{ |
. = ALIGN(4); |
*(.text) /* .text sections (code) */ |
*(.text*) /* .text* sections (code) */ |
*(.rodata) /* .rodata sections (constants, strings, etc.) */ |
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */ |
*(.glue_7) /* glue arm to thumb code */ |
*(.glue_7t) /* glue thumb to arm code */ |
KEEP (*(.init)) |
KEEP (*(.fini)) |
. = ALIGN(4); |
_etext = .; /* define a global symbols at end of code */ |
} >FLASH |
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH |
.ARM : { |
__exidx_start = .; |
*(.ARM.exidx*) |
__exidx_end = .; |
} >FLASH |
.ARM.attributes 0 : { *(.ARM.attributes) } |
.preinit_array : |
{ |
PROVIDE_HIDDEN (__preinit_array_start = .); |
KEEP (*(.preinit_array*)) |
PROVIDE_HIDDEN (__preinit_array_end = .); |
} >FLASH |
.init_array : |
{ |
PROVIDE_HIDDEN (__init_array_start = .); |
KEEP (*(SORT(.init_array.*))) |
KEEP (*(.init_array*)) |
PROVIDE_HIDDEN (__init_array_end = .); |
} >FLASH |
.fini_array : |
{ |
PROVIDE_HIDDEN (__fini_array_start = .); |
KEEP (*(.fini_array*)) |
KEEP (*(SORT(.fini_array.*))) |
PROVIDE_HIDDEN (__fini_array_end = .); |
} >FLASH |
/* used by the startup to initialize data */ |
_sidata = .; |
/* Initialized data sections goes into RAM, load LMA copy after code */ |
.data : AT ( _sidata ) |
{ |
. = ALIGN(4); |
_sdata = .; /* create a global symbol at data start */ |
*(.data) /* .data sections */ |
*(.data*) /* .data* sections */ |
. = ALIGN(4); |
_edata = .; /* define a global symbol at data end */ |
} >RAM |
/* Uninitialized data section */ |
. = ALIGN(4); |
.bss : |
{ |
/* This is used by the startup in order to initialize the .bss secion */ |
_sbss = .; /* define a global symbol at bss start */ |
__bss_start__ = _sbss; |
*(.bss) |
*(.bss*) |
*(COMMON) |
. = ALIGN(4); |
_ebss = .; /* define a global symbol at bss end */ |
__bss_end__ = _ebss; |
} >RAM |
PROVIDE ( end = _ebss ); |
PROVIDE ( _end = _ebss ); |
/* User_heap_stack section, used to check that there is enough RAM left */ |
._user_heap_stack : |
{ |
. = ALIGN(4); |
. = . + _Min_Heap_Size; |
. = . + _Min_Stack_Size; |
. = ALIGN(4); |
} >RAM |
/* MEMORY_bank1 section, code must be located here explicitly */ |
/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ |
.memory_b1_text : |
{ |
*(.mb1text) /* .mb1text sections (code) */ |
*(.mb1text*) /* .mb1text* sections (code) */ |
*(.mb1rodata) /* read-only data (constants) */ |
*(.mb1rodata*) |
} >MEMORY_B1 |
/* Remove information from the standard libraries */ |
/DISCARD/ : |
{ |
libc.a ( * ) |
libm.a ( * ) |
libgcc.a ( * ) |
} |
} |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/stm32_128K_8K_vl.ld |
---|
0,0 → 1,170 |
/* |
***************************************************************************** |
** |
** File : stm32_flash.ld |
** |
** Abstract : Linker script for STM32F100VB Device with |
** 128KByte FLASH, 8KByte RAM |
** |
** Set heap size, stack size and stack location according |
** to application requirements. |
** |
** Set memory bank area and size if external memory is used. |
** |
** Target : STMicroelectronics STM32 |
** |
** Environment : Atollic TrueSTUDIO(R) |
** |
** Distribution: The file is distributed as is, without any warranty |
** of any kind. |
** |
** (c)Copyright Atollic AB. |
** You may use this file as-is or modify it according to the needs of your |
** project. Distribution of this file (unmodified or modified) is not |
** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the |
** rights to distribute the assembled, compiled & linked contents of this |
** file as part of an application binary file, provided that it is built |
** using the Atollic TrueSTUDIO(R) toolchain. |
** |
***************************************************************************** |
*/ |
/* Entry Point */ |
ENTRY(Reset_Handler) |
/* Highest address of the user mode stack */ |
_estack = 0x20002000; /* end of 8K RAM */ |
/* Generate a link error if heap and stack don't fit into RAM */ |
_Min_Heap_Size = 0; /* required amount of heap */ |
_Min_Stack_Size = 0x800; /* required amount of stack */ |
/* Specify the memory areas */ |
MEMORY |
{ |
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K |
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K |
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K |
} |
/* Define output sections */ |
SECTIONS |
{ |
/* The startup code goes first into FLASH */ |
.isr_vector : |
{ |
. = ALIGN(4); |
KEEP(*(.isr_vector)) /* Startup code */ |
. = ALIGN(4); |
} >FLASH |
/* The program code and other data goes into FLASH */ |
.text : |
{ |
. = ALIGN(4); |
*(.text) /* .text sections (code) */ |
*(.text*) /* .text* sections (code) */ |
*(.rodata) /* .rodata sections (constants, strings, etc.) */ |
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */ |
*(.glue_7) /* glue arm to thumb code */ |
*(.glue_7t) /* glue thumb to arm code */ |
KEEP (*(.init)) |
KEEP (*(.fini)) |
. = ALIGN(4); |
_etext = .; /* define a global symbols at end of code */ |
} >FLASH |
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH |
.ARM : { |
__exidx_start = .; |
*(.ARM.exidx*) |
__exidx_end = .; |
} >FLASH |
.ARM.attributes 0 : { *(.ARM.attributes) } |
.preinit_array : |
{ |
PROVIDE_HIDDEN (__preinit_array_start = .); |
KEEP (*(.preinit_array*)) |
PROVIDE_HIDDEN (__preinit_array_end = .); |
} >FLASH |
.init_array : |
{ |
PROVIDE_HIDDEN (__init_array_start = .); |
KEEP (*(SORT(.init_array.*))) |
KEEP (*(.init_array*)) |
PROVIDE_HIDDEN (__init_array_end = .); |
} >FLASH |
.fini_array : |
{ |
PROVIDE_HIDDEN (__fini_array_start = .); |
KEEP (*(.fini_array*)) |
KEEP (*(SORT(.fini_array.*))) |
PROVIDE_HIDDEN (__fini_array_end = .); |
} >FLASH |
/* used by the startup to initialize data */ |
_sidata = .; |
/* Initialized data sections goes into RAM, load LMA copy after code */ |
.data : AT ( _sidata ) |
{ |
. = ALIGN(4); |
_sdata = .; /* create a global symbol at data start */ |
*(.data) /* .data sections */ |
*(.data*) /* .data* sections */ |
. = ALIGN(4); |
_edata = .; /* define a global symbol at data end */ |
} >RAM |
/* Uninitialized data section */ |
. = ALIGN(4); |
.bss : |
{ |
/* This is used by the startup in order to initialize the .bss secion */ |
_sbss = .; /* define a global symbol at bss start */ |
__bss_start__ = _sbss; |
*(.bss) |
*(.bss*) |
*(COMMON) |
. = ALIGN(4); |
_ebss = .; /* define a global symbol at bss end */ |
__bss_end__ = _ebss; |
} >RAM |
PROVIDE ( end = _ebss ); |
PROVIDE ( _end = _ebss ); |
/* User_heap_stack section, used to check that there is enough RAM left */ |
._user_heap_stack : |
{ |
. = ALIGN(4); |
. = . + _Min_Heap_Size; |
. = . + _Min_Stack_Size; |
. = ALIGN(4); |
} >RAM |
/* MEMORY_bank1 section, code must be located here explicitly */ |
/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ |
.memory_b1_text : |
{ |
*(.mb1text) /* .mb1text sections (code) */ |
*(.mb1text*) /* .mb1text* sections (code) */ |
*(.mb1rodata) /* read-only data (constants) */ |
*(.mb1rodata*) |
} >MEMORY_B1 |
/* Remove information from the standard libraries */ |
/DISCARD/ : |
{ |
libc.a ( * ) |
libm.a ( * ) |
libgcc.a ( * ) |
} |
} |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/stm32_512K_64K.ld |
---|
0,0 → 1,156 |
/* |
***************************************************************************** |
** File : stm32_flash.ld |
** |
** Abstract : Linker script for STM32F103 Device with |
** 512KByte FLASH, 64KByte RAM |
** |
** Set heap size, stack size and stack location according |
** to application requirements. |
** |
** Set memory bank area and size if external memory is used. |
** |
** Target : STMicroelectronics STM32 |
** |
***************************************************************************** |
*/ |
/* Entry Point */ |
ENTRY(Reset_Handler) |
/* Highest address of the user mode stack */ |
_estack = 0x20010000; /* end of 64K RAM */ |
/* Generate a link error if heap and stack don't fit into RAM */ |
_Min_Heap_Size = 0; /* required amount of heap */ |
_Min_Stack_Size = 0x1000; /* required amount of stack */ |
/* Specify the memory areas */ |
MEMORY |
{ |
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K |
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K |
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K |
} |
/* Define output sections */ |
SECTIONS |
{ |
/* The startup code goes first into FLASH */ |
.isr_vector : |
{ |
. = ALIGN(4); |
KEEP(*(.isr_vector)) /* Startup code */ |
. = ALIGN(4); |
} >FLASH |
/* The program code and other data goes into FLASH */ |
.text : |
{ |
. = ALIGN(4); |
*(.text) /* .text sections (code) */ |
*(.text*) /* .text* sections (code) */ |
*(.rodata) /* .rodata sections (constants, strings, etc.) */ |
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */ |
*(.glue_7) /* glue arm to thumb code */ |
*(.glue_7t) /* glue thumb to arm code */ |
KEEP (*(.init)) |
KEEP (*(.fini)) |
. = ALIGN(4); |
_etext = .; /* define a global symbols at end of code */ |
} >FLASH |
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH |
.ARM : { |
__exidx_start = .; |
*(.ARM.exidx*) |
__exidx_end = .; |
} >FLASH |
.ARM.attributes 0 : { *(.ARM.attributes) } |
.preinit_array : |
{ |
PROVIDE_HIDDEN (__preinit_array_start = .); |
KEEP (*(.preinit_array*)) |
PROVIDE_HIDDEN (__preinit_array_end = .); |
} >FLASH |
.init_array : |
{ |
PROVIDE_HIDDEN (__init_array_start = .); |
KEEP (*(SORT(.init_array.*))) |
KEEP (*(.init_array*)) |
PROVIDE_HIDDEN (__init_array_end = .); |
} >FLASH |
.fini_array : |
{ |
PROVIDE_HIDDEN (__fini_array_start = .); |
KEEP (*(.fini_array*)) |
KEEP (*(SORT(.fini_array.*))) |
PROVIDE_HIDDEN (__fini_array_end = .); |
} >FLASH |
/* used by the startup to initialize data */ |
_sidata = .; |
/* Initialized data sections goes into RAM, load LMA copy after code */ |
.data : AT ( _sidata ) |
{ |
. = ALIGN(4); |
_sdata = .; /* create a global symbol at data start */ |
*(.data) /* .data sections */ |
*(.data*) /* .data* sections */ |
. = ALIGN(4); |
_edata = .; /* define a global symbol at data end */ |
} >RAM |
/* Uninitialized data section */ |
. = ALIGN(4); |
.bss : |
{ |
/* This is used by the startup in order to initialize the .bss secion */ |
_sbss = .; /* define a global symbol at bss start */ |
__bss_start__ = _sbss; |
*(.bss) |
*(.bss*) |
*(COMMON) |
. = ALIGN(4); |
_ebss = .; /* define a global symbol at bss end */ |
__bss_end__ = _ebss; |
} >RAM |
PROVIDE ( end = _ebss ); |
PROVIDE ( _end = _ebss ); |
/* User_heap_stack section, used to check that there is enough RAM left */ |
._user_heap_stack : |
{ |
. = ALIGN(4); |
. = . + _Min_Heap_Size; |
. = . + _Min_Stack_Size; |
. = ALIGN(4); |
} >RAM |
/* MEMORY_bank1 section, code must be located here explicitly */ |
/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ |
.memory_b1_text : |
{ |
*(.mb1text) /* .mb1text sections (code) */ |
*(.mb1text*) /* .mb1text* sections (code) */ |
*(.mb1rodata) /* read-only data (constants) */ |
*(.mb1rodata*) |
} >MEMORY_B1 |
/* Remove information from the standard libraries */ |
/DISCARD/ : |
{ |
libc.a ( * ) |
libm.a ( * ) |
libgcc.a ( * ) |
} |
} |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/stm32f10x_conf.h |
---|
0,0 → 1,77 |
/** |
****************************************************************************** |
* @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief Library configuration file. |
****************************************************************************** |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
/* Define to prevent recursive inclusion -------------------------------------*/ |
#ifndef __STM32F10x_CONF_H |
#define __STM32F10x_CONF_H |
/* Includes ------------------------------------------------------------------*/ |
/* Uncomment the line below to enable peripheral header file inclusion */ |
/* #include "stm32f10x_adc.h" */ |
/* #include "stm32f10x_bkp.h" */ |
/* #include "stm32f10x_can.h" */ |
/* #include "stm32f10x_cec.h" */ |
/* #include "stm32f10x_crc.h" */ |
/* #include "stm32f10x_dac.h" */ |
/* #include "stm32f10x_dbgmcu.h" */ |
//!!#include "stm32f10x_dma.h" |
//!!#include "stm32f10x_exti.h" |
//!!#include "stm32f10x_flash.h" |
//!!#include "stm32f10x_fsmc.h" |
#include "stm32f10x_gpio.h" |
/*#include "stm32f10x_i2c.h"*/ |
/* #include "stm32f10x_iwdg.h" */ |
/* #include "stm32f10x_pwr.h" */ |
#include "stm32f10x_rcc.h" |
/* #include "stm32f10x_rtc.h" */ |
/* #include "stm32f10x_sdio.h" */ |
//!!#include "stm32f10x_spi.h" |
/* #include "stm32f10x_tim.h" */ |
//!!#include "stm32f10x_usart.h" |
/* #include "stm32f10x_wwdg.h" */ |
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ |
/* Exported types ------------------------------------------------------------*/ |
/* Exported constants --------------------------------------------------------*/ |
/* Uncomment the line below to expanse the "assert_param" macro in the |
Standard Peripheral Library drivers code */ |
//#define USE_FULL_ASSERT 1 |
/* Exported macro ------------------------------------------------------------*/ |
#ifdef USE_FULL_ASSERT |
/** |
* @brief The assert_param macro is used for function's parameters check. |
* @param expr: If expr is false, it calls assert_failed function |
* which reports the name of the source file and the source |
* line number of the call that failed. |
* If expr is true, it returns no value. |
* @retval None |
*/ |
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) |
/* Exported functions ------------------------------------------------------- */ |
void assert_failed(uint8_t* file, uint32_t line); |
#else |
#define assert_param(expr) ((void)0) |
#endif /* USE_FULL_ASSERT */ |
#endif /* __STM32F10x_CONF_H */ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/stm32f10x_it.c |
---|
0,0 → 1,166 |
/** |
****************************************************************************** |
* @file GPIO/IOToggle/stm32f10x_it.c |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief Main Interrupt Service Routines. |
* This file provides template for all exceptions handler and peripherals |
* interrupt service routine. |
****************************************************************************** |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
/* Includes ------------------------------------------------------------------*/ |
#include "stm32f10x_it.h" |
/** @addtogroup STM32F10x_StdPeriph_Examples |
* @{ |
*/ |
/** @addtogroup GPIO_IOToggle |
* @{ |
*/ |
/* Private typedef -----------------------------------------------------------*/ |
/* Private define ------------------------------------------------------------*/ |
/* Private macro -------------------------------------------------------------*/ |
/* Private variables ---------------------------------------------------------*/ |
/* Private function prototypes -----------------------------------------------*/ |
/* Private functions ---------------------------------------------------------*/ |
/******************************************************************************/ |
/* Cortex-M3 Processor Exceptions Handlers */ |
/******************************************************************************/ |
/** |
* @brief This function handles NMI exception. |
* @param None |
* @retval None |
*/ |
void NMI_Handler(void) |
{ |
} |
/** |
* @brief This function handles Hard Fault exception. |
* @param None |
* @retval None |
*/ |
void HardFault_Handler(void) |
{ |
/* Go to infinite loop when Hard Fault exception occurs */ |
while (1) |
{ |
} |
} |
/** |
* @brief This function handles Memory Manage exception. |
* @param None |
* @retval None |
*/ |
void MemManage_Handler(void) |
{ |
/* Go to infinite loop when Memory Manage exception occurs */ |
while (1) |
{ |
} |
} |
/** |
* @brief This function handles Bus Fault exception. |
* @param None |
* @retval None |
*/ |
void BusFault_Handler(void) |
{ |
/* Go to infinite loop when Bus Fault exception occurs */ |
while (1) |
{ |
} |
} |
/** |
* @brief This function handles Usage Fault exception. |
* @param None |
* @retval None |
*/ |
void UsageFault_Handler(void) |
{ |
/* Go to infinite loop when Usage Fault exception occurs */ |
while (1) |
{ |
} |
} |
/** |
* @brief This function handles SVCall exception. |
* @param None |
* @retval None |
*/ |
void SVC_Handler(void) |
{ |
} |
/** |
* @brief This function handles Debug Monitor exception. |
* @param None |
* @retval None |
*/ |
void DebugMon_Handler(void) |
{ |
} |
/** |
* @brief This function handles PendSV_Handler exception. |
* @param None |
* @retval None |
*/ |
void PendSV_Handler(void) |
{ |
} |
/** |
* @brief This function handles SysTick Handler. |
* @param None |
* @retval None |
*/ |
void SysTick_Handler(void) |
{ |
} |
/******************************************************************************/ |
/* STM32F10x Peripherals Interrupt Handlers */ |
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ |
/* available peripheral interrupt handler's name please refer to the startup */ |
/* file (startup_stm32f10x_xx.s). */ |
/******************************************************************************/ |
/** |
* @brief This function handles PPP interrupt request. |
* @param None |
* @retval None |
*/ |
/*void PPP_IRQHandler(void) |
{ |
}*/ |
/** |
* @} |
*/ |
/** |
* @} |
*/ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/LED_blink/stm32f10x_it.h |
---|
0,0 → 1,45 |
/** |
****************************************************************************** |
* @file GPIO/IOToggle/stm32f10x_it.h |
* @author MCD Application Team |
* @version V3.4.0 |
* @date 10/15/2010 |
* @brief This file contains the headers of the interrupt handlers. |
****************************************************************************** |
* @copy |
* |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
* |
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
*/ |
/* Define to prevent recursive inclusion -------------------------------------*/ |
#ifndef __STM32F10x_IT_H |
#define __STM32F10x_IT_H |
/* Includes ------------------------------------------------------------------*/ |
#include "stm32f10x.h" |
/* Exported types ------------------------------------------------------------*/ |
/* Exported constants --------------------------------------------------------*/ |
/* Exported macro ------------------------------------------------------------*/ |
/* Exported functions ------------------------------------------------------- */ |
void NMI_Handler(void); |
void HardFault_Handler(void); |
void MemManage_Handler(void); |
void BusFault_Handler(void); |
void UsageFault_Handler(void); |
void SVC_Handler(void); |
void DebugMon_Handler(void); |
void PendSV_Handler(void); |
void SysTick_Handler(void); |
#endif /* __STM32F10x_IT_H */ |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STBLLIB.dll |
---|
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+application/octet-stream |
\ No newline at end of property |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STMFlashLoader.exe |
---|
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svn:mime-type = application/octet-stream |
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+application/octet-stream |
\ No newline at end of property |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Conf/Default.conf |
---|
0,0 → 1,75 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : Default.conf |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : Defines the default parameters configuration |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[INTERFACE] |
comm_int=0 |
[Serial] |
PortNumber=0 |
BaudRate=2 |
DataBits=3 |
Parity=2 |
StopBits=0 |
TimeOut=4 |
Echo=0 |
[MCUs] |
f1=STM32F1 |
f2=STR75x |
f3=STM8 |
f4=STR91xFA |
[f1] |
ADDR_RAM_SIZE =1FFFF7E2; |
ADDR_FLASH_SIZE=1FFFF7E0; |
[f2] |
AN=AN2430 |
Title=STR75x System Memory boot mode |
ADDR_RAM_SIZE =FFFFFFFF; |
ADDR_FLASH_SIZE=FFFFFFFF; |
[f3] |
ADDR_RAM_SIZE =FFFFFFFF; |
ADDR_FLASH_SIZE=FFFFFFFF; |
[f4] |
ADDR_RAM_SIZE =FFFFFFFF; |
ADDR_FLASH_SIZE=FFFFFFFF; |
[Operation] |
Index=0 |
Verify=1 |
Run=0 |
Optimize=1 |
EROP=0 |
DisEna=1 |
RW=1 |
RunAddress=8000 |
Family=0 |
ApplyOPB=0 |
EraseDnLoad=2 |
[Files] |
DownloadExt=*.hex |
UploadExt=*.hex |
OPBExt=*.bin |
Download= |
Upload= |
OPBFile= |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Files.dll |
---|
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_Connectivity-line_128K.STmap |
---|
0,0 → 1,475 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_Connectivity-line_128K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_Connectivity-line_128K |
PID=0418 |
FlashSize=0080 ;;ADDR_FLASH_SIZE=1FFFF7E0; |
RAMSize=0020 ;;ADDR_RAM_SIZE =1FFFF7E2; |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Pages |
PagesPerSector=2 |
family = 1; |
[Page0] |
Name=Page0 |
Index=00 |
Address=08000000 |
Size=00000800 |
Type=111 |
UFO=111 |
[Page1] |
Name=Page1 |
Index=01 |
Address=08000800 |
Size=00000800 |
Type=111 |
UFO=111 |
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Index=02 |
Address=08001000 |
Size=00000800 |
Type=111 |
UFO=111 |
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Index=03 |
Address=08001800 |
Size=00000800 |
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UFO=111 |
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Index=05 |
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UFO=111 |
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Index=06 |
Address=08003000 |
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UFO=111 |
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Index=07 |
Address=08003800 |
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UFO=111 |
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Address=08005000 |
Size=00000800 |
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UFO=111 |
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UFO=111 |
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[Page58] |
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UFO=111 |
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UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_Connectivity-line_256K.STmap |
---|
0,0 → 1,922 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_Connectivity-line_256K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_Connectivity-line_256K |
PID=0418 |
FlashSize=0100 ;;ADDR_FLASH_SIZE=1FFFF7E0; |
RAMSize=0040 ;;ADDR_RAM_SIZE =1FFFF7E2; |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Pages |
PagesPerSector=2 |
family = 1; |
[Page0] |
Name=Page0 |
Index=00 |
Address=08000000 |
Size=00000800 |
Type=111 |
UFO=111 |
[Page1] |
Name=Page1 |
Index=01 |
Address=08000800 |
Size=00000800 |
Type=111 |
UFO=111 |
[Page2] |
Name=Page2 |
Index=02 |
Address=08001000 |
Size=00000800 |
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Index=03 |
Address=08001800 |
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Index=04 |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_Connectivity-line_64K.STmap |
---|
0,0 → 1,250 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_Connectivity-line_64K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_Connectivity-line_64K |
PID=0418 |
FlashSize=0040 ;;ADDR_FLASH_SIZE=1FFFF7E0; |
RAMSize=0014 ;;ADDR_RAM_SIZE =1FFFF7E2; |
PacketSize=FF |
ACKVAL=79 |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_High-density_256K.STmap |
---|
0,0 → 1,923 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_High-density_256K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_High-density_256K |
PID=0414 |
FlashSize=0100 ;;ADDR_FLASH_SIZE=1FFFF7E0; |
RAMSize=0030 ;;ADDR_RAM_SIZE =1FFFF7E2; |
PacketSize=FF |
ACKVAL=79 |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_High-density_384K.STmap |
---|
0,0 → 1,1370 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_High-density_384K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_High-density_384K |
PID=0414 |
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RAMSize=0040 ;;ADDR_RAM_SIZE =1FFFF7E2; |
PacketSize=FF |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_High-density_512K.STmap |
---|
0,0 → 1,1818 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_High-density_512K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_High-density_512K |
PID=0414 |
FlashSize=0200 ;;ADDR_FLASH_SIZE=1FFFF7E0; |
RAMSize=0040 ;;ADDR_RAM_SIZE =1FFFF7E2; |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Pages |
PagesPerSector=2 |
family = 1; |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_Low-density_16K.STmap |
---|
0,0 → 1,140 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_Low-density_16K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_Low-density_16K |
PID=0412 |
FlashSize=0010 |
RAMSize=0006 |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Pages |
PagesPerSector = 4 |
family = 1; |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_Low-density_32K.STmap |
---|
0,0 → 1,250 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_Low-density_32K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_Low-density_32K |
PID=0412 |
FlashSize=0020 |
RAMSize=000A |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Pages |
PagesPerSector = 4 |
family = 1; |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_Med-density-value_128K.STmap |
---|
0,0 → 1,923 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_Med-density-value_128K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_Med-density-value_128K |
PID=0420 |
BID=1FFFF7D6 |
FlashSize=0080 |
RAMSize=0008 |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Pages |
PagesPerSector = 4 |
family = 1; |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_Med-density-value_64K.STmap |
---|
0,0 → 1,475 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_Med-density-value_64K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_Med-density-value_64K |
PID=0420 |
BID=1FFFF7D6 |
FlashSize=0040 |
RAMSize=0008 |
PacketSize=FF |
ACKVAL=79 |
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PagesPerSector = 4 |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_Med-density_128K.STmap |
---|
0,0 → 1,922 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_Med-density_128K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_Med-density_128K |
PID=0410 |
FlashSize=0080 |
RAMSize=0014 |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_Med-density_64K.STmap |
---|
0,0 → 1,474 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_Med-density_64K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM32_Med-density_64K.STmap |
PID=0410 |
FlashSize=0040 |
RAMSize=0014 |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Pages |
PagesPerSector = 4 |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_XL-density_1024K.STmap |
---|
0,0 → 1,3611 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_XL-density_1024K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM32_XL-density_768K.STmap |
---|
0,0 → 1,5403 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM32_XL-density_768K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
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[Page759] |
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[Page760] |
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[Page761] |
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[Page763] |
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Size=00000400 |
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UFO=111 |
[Page765] |
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[Page767] |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM8L_32K.STmap |
---|
0,0 → 1,273 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM8L_32K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM8L_32K |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=80 |
ACKVAL=79 |
MAPNAME=sectors |
PagesPerSector=2 |
family = 3 |
;; Erase Write Routines files /* BL_VER = FileName */ |
1.0 = E_W_ROUTINEs_32K_verL_1.0.s19 |
1.1 = E_W_ROUTINEs_32K_verL_1.0.s19 |
;; EEPROM information |
[DataEE] |
Name=DataEE |
Index=20 |
Address=00001000 |
Size=00000400 |
Type=111 |
UFO=111 |
;; OPTION bytes information |
[OptBytes] |
Name=OptBytes |
Address=00004800 |
Size=00000080 |
Type=101 |
UFO=111 |
;; Flash information |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=00008000 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
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[SEC2] |
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[SEC3] |
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[SEC8] |
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[SEC11] |
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[SEC12] |
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[SEC13] |
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[SEC14] |
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[SEC15] |
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[SEC16] |
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[SEC17] |
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[SEC18] |
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[SEC19] |
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UFO=111 |
[SEC20] |
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UFO=111 |
[SEC21] |
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UFO=111 |
[SEC22] |
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UFO=111 |
[SEC23] |
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UFO=111 |
[SEC24] |
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UFO=111 |
[SEC25] |
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UFO=111 |
[SEC26] |
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UFO=111 |
[SEC27] |
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Size=00000400 |
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UFO=111 |
[SEC28] |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC29] |
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UFO=111 |
[SEC30] |
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UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM8L_64K.STmap |
---|
0,0 → 1,505 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM8L_64K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM8L_64K |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=80 |
ACKVAL=79 |
MAPNAME=sectors |
PagesPerSector=2 |
family = 3 |
;; Erase Write Routines files /* BL_VER = FileName */ |
1.0 = E_W_ROUTINEs_32K_verL_1.0.s19 |
;; EEPROM information |
[DataEE0] |
Name=DataEE0 |
Index=40 |
Address=00001000 |
Size=00000400 |
Type=111 |
UFO=111 |
[DataEE1] |
Name=DataEE1 |
Index=41 |
Address=00001400 |
Size=00000400 |
Type=111 |
UFO=111 |
;; OPTION bytes information |
[OptBytes] |
Name=OptBytes |
Address=00004800 |
Size=00000080 |
Type=101 |
UFO=111 |
;; Flash information |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=00008000 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
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[SEC2] |
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[SEC3] |
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[SEC4] |
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[SEC5] |
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[SEC6] |
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UFO=111 |
[SEC7] |
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[SEC8] |
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[SEC9] |
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Type=111 |
UFO=111 |
[SEC10] |
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Size=00000400 |
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UFO=111 |
[SEC11] |
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Address=0000AC00 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC12] |
Name=SEC12 |
Index=0C |
Address=0000B000 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC13] |
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Index=0D |
Address=0000B400 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC14] |
Name=SEC14 |
Index=0E |
Address=0000B800 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC15] |
Name=SEC15 |
Index=0F |
Address=0000BC00 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC16] |
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Index=10 |
Address=0000C000 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC17] |
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Index=11 |
Address=0000C400 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC18] |
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Index=12 |
Address=0000C800 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC19] |
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Address=0000CC00 |
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Type=111 |
UFO=111 |
[SEC20] |
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UFO=111 |
[SEC21] |
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UFO=111 |
[SEC22] |
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UFO=111 |
[SEC23] |
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UFO=111 |
[SEC24] |
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UFO=111 |
[SEC25] |
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UFO=111 |
[SEC26] |
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UFO=111 |
[SEC27] |
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UFO=111 |
[SEC28] |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC29] |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC30] |
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UFO=111 |
[SEC31] |
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Type=111 |
UFO=111 |
[SEC32] |
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UFO=111 |
[SEC33] |
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UFO=111 |
[SEC34] |
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UFO=111 |
[SEC35] |
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UFO=111 |
[SEC36] |
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UFO=111 |
[SEC37] |
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Type=111 |
UFO=111 |
[SEC38] |
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UFO=111 |
[SEC39] |
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UFO=111 |
[SEC40] |
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UFO=111 |
[SEC41] |
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Type=111 |
UFO=111 |
[SEC42] |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC43] |
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Size=00000400 |
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UFO=111 |
[SEC44] |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC45] |
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UFO=111 |
[SEC46] |
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UFO=111 |
[SEC47] |
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UFO=111 |
[SEC48] |
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UFO=111 |
[SEC49] |
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UFO=111 |
[SEC50] |
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UFO=111 |
[SEC51] |
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UFO=111 |
[SEC52] |
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UFO=111 |
[SEC53] |
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UFO=111 |
[SEC54] |
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UFO=111 |
[SEC55] |
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UFO=111 |
[SEC56] |
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UFO=111 |
[SEC57] |
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[SEC58] |
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UFO=111 |
[SEC59] |
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UFO=111 |
[SEC60] |
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UFO=111 |
[SEC61] |
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UFO=111 |
[SEC62] |
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[SEC63] |
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UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM8_128K.STmap |
---|
0,0 → 1,956 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM8_128K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM8_128K |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=80 |
ACKVAL=79 |
MAPNAME=sectors |
PagesPerSector=2 |
family = 3 |
;; Erase Write Routines files /* BL_VER = FileName */ |
2.0 = E_W_ROUTINEs_128K_ver_2.0.s19 |
2.1 = E_W_ROUTINEs_128K_ver_2.1.s19 |
2.2 = E_W_ROUTINEs_128K_ver_2.2.s19 |
;; EEPROM information |
[DataEE0] |
Name=DataEE0 |
Index=80 |
Address=00004000 |
Size=00000400 |
Type=111 |
UFO=111 |
[DataEE1] |
Name=DataEE1 |
Index=81 |
Address=00004400 |
Size=00000400 |
Type=111 |
UFO=111 |
;; OPTION bytes information |
[OptBytes] |
Name=OptBytes |
Address=00004800 |
Size=00000080 |
Type=101 |
UFO=111 |
;; Flash information |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=00008000 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
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Address=00008400 |
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UFO=111 |
[SEC2] |
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UFO=111 |
[SEC3] |
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UFO=111 |
[SEC4] |
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UFO=111 |
[SEC5] |
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UFO=111 |
[SEC6] |
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Type=111 |
UFO=111 |
[SEC7] |
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UFO=111 |
[SEC8] |
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UFO=111 |
[SEC9] |
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Type=111 |
UFO=111 |
[SEC10] |
Name=SEC10 |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC11] |
Name=SEC11 |
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Type=111 |
UFO=111 |
[SEC12] |
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Type=111 |
UFO=111 |
[SEC13] |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC14] |
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Type=111 |
UFO=111 |
[SEC15] |
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Type=111 |
UFO=111 |
[SEC16] |
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UFO=111 |
[SEC17] |
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UFO=111 |
[SEC18] |
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Type=111 |
UFO=111 |
[SEC19] |
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UFO=111 |
[SEC20] |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM8_16K.STmap |
---|
0,0 → 1,161 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM8_16K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM8_16K |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=80 |
ACKVAL=79 |
MAPNAME=sectors |
PagesPerSector=2 |
family = 3 |
;; Erase Write Routines files /* BL_VER = FileName */ |
1.0 = E_W_ROUTINEs_32K_ver_1.0.s19 |
1.2 = E_W_ROUTINEs_32K_ver_1.2.s19 |
;; EEPROM information |
[DataEE] |
Name=DataEE |
Index=20 |
Address=00004000 |
Size=00000400 |
Type=111 |
UFO=111 |
;; OPTION bytes information |
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Size=00000080 |
Type=101 |
UFO=111 |
;; Flash information |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM8_256K.STmap |
---|
0,0 → 1,953 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM8_256K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM8_256K |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=80 |
ACKVAL=79 |
MAPNAME=sectors |
PagesPerSector=2 |
family = 3 |
;; Erase Write Routines files /* BL_VER = FileName */ |
1.0 = E_W_ROUTINEs_256K_ver_1.0.s19 |
;; EEPROM information |
[DataEE0] |
Name=DataEE0 |
Index=80 |
Address=00003800 |
Size=00000800 |
Type=111 |
UFO=111 |
[DataEE1] |
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Index=81 |
Address=00004000 |
Size=00000800 |
Type=111 |
UFO=111 |
;; OPTION bytes information |
[OptBytes] |
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Size=00000080 |
Type=101 |
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;; Flash information |
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[SEC23] |
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[SEC50] |
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[SEC51] |
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[SEC52] |
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[SEC53] |
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[SEC54] |
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[SEC55] |
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[SEC56] |
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[SEC57] |
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[SEC58] |
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[SEC62] |
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[SEC63] |
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[SEC64] |
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[SEC65] |
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[SEC66] |
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[SEC67] |
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[SEC68] |
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[SEC70] |
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[SEC71] |
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[SEC72] |
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[SEC73] |
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[SEC74] |
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[SEC76] |
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[SEC77] |
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[SEC80] |
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[SEC81] |
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[SEC82] |
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[SEC83] |
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[SEC85] |
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[SEC87] |
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[SEC88] |
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[SEC90] |
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[SEC91] |
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[SEC92] |
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[SEC93] |
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[SEC94] |
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[SEC95] |
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[SEC96] |
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[SEC97] |
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[SEC98] |
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[SEC99] |
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[SEC100] |
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[SEC101] |
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[SEC102] |
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[SEC103] |
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[SEC104] |
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[SEC106] |
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[SEC107] |
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[SEC112] |
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[SEC115] |
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[SEC117] |
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[SEC119] |
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[SEC120] |
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[SEC121] |
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[SEC122] |
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[SEC123] |
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[SEC125] |
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[SEC126] |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM8_32K.STmap |
---|
0,0 → 1,275 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM8_32K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM8_32K |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=80 |
ACKVAL=79 |
MAPNAME=sectors |
PagesPerSector=2 |
family = 3 |
;; Erase Write Routines files /* BL_VER = FileName */ |
1.0 = E_W_ROUTINEs_32K_ver_1.0.s19 |
1.2 = E_W_ROUTINEs_32K_ver_1.2.s19 |
1.3 = E_W_ROUTINEs_32K_ver_1.3.s19 |
1.4 = E_W_ROUTINEs_32K_ver_1.4.s19 |
;; EEPROM information |
[DataEE] |
Name=DataEE |
Index=20 |
Address=00004000 |
Size=00000400 |
Type=111 |
UFO=111 |
;; OPTION bytes information |
[OptBytes] |
Name=OptBytes |
Address=00004800 |
Size=00000080 |
Type=101 |
UFO=111 |
;; Flash information |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=00008000 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
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Address=00008400 |
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Type=111 |
UFO=111 |
[SEC2] |
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UFO=111 |
[SEC3] |
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[SEC4] |
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[SEC5] |
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[SEC6] |
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[SEC7] |
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[SEC8] |
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[SEC9] |
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[SEC10] |
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[SEC11] |
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[SEC12] |
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[SEC13] |
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[SEC14] |
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[SEC15] |
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[SEC16] |
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[SEC17] |
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[SEC18] |
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[SEC19] |
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[SEC20] |
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[SEC21] |
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[SEC22] |
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[SEC23] |
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UFO=111 |
[SEC24] |
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UFO=111 |
[SEC25] |
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Type=111 |
UFO=111 |
[SEC26] |
Name=SEC26 |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC27] |
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Type=111 |
UFO=111 |
[SEC28] |
Name=SEC28 |
Index=1C |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC29] |
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UFO=111 |
[SEC30] |
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[SEC31] |
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UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STM8_64K.STmap |
---|
0,0 → 1,507 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STM8_64K.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STM8_64K |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=80 |
ACKVAL=79 |
MAPNAME=sectors |
PagesPerSector=2 |
family = 3 |
;; Erase Write Routines files /* BL_VER = FileName */ |
2.0 = E_W_ROUTINEs_128K_ver_2.0.s19 |
2.1 = E_W_ROUTINEs_128K_ver_2.1.s19 |
;; EEPROM information |
[DataEE0] |
Name=DataEE0 |
Index=80 |
Address=00004000 |
Size=00000400 |
Type=111 |
UFO=111 |
[DataEE1] |
Name=DataEE1 |
Index=81 |
Address=00004400 |
Size=00000400 |
Type=111 |
UFO=111 |
;; OPTION bytes information |
[OptBytes] |
Name=OptBytes |
Address=00004800 |
Size=00000080 |
Type=101 |
UFO=111 |
;; Flash information |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=00008000 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
Index=01 |
Address=00008400 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC2] |
Name=SEC2 |
Index=02 |
Address=00008800 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC3] |
Name=SEC3 |
Index=03 |
Address=00008C00 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC4] |
Name=SEC4 |
Index=04 |
Address=00009000 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC5] |
Name=SEC5 |
Index=05 |
Address=00009400 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC6] |
Name=SEC6 |
Index=06 |
Address=00009800 |
Size=00000400 |
Type=111 |
UFO=111 |
[SEC7] |
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UFO=111 |
[SEC8] |
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[SEC9] |
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[SEC10] |
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[SEC11] |
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[SEC12] |
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[SEC13] |
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[SEC14] |
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[SEC15] |
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[SEC16] |
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[SEC17] |
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[SEC18] |
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[SEC19] |
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UFO=111 |
[SEC20] |
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[SEC21] |
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[SEC22] |
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[SEC23] |
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[SEC24] |
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[SEC25] |
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[SEC26] |
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[SEC27] |
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UFO=111 |
[SEC28] |
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UFO=111 |
[SEC29] |
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Size=00000400 |
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UFO=111 |
[SEC30] |
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UFO=111 |
[SEC31] |
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[SEC32] |
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[SEC33] |
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[SEC34] |
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[SEC35] |
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[SEC36] |
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[SEC37] |
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[SEC38] |
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UFO=111 |
[SEC39] |
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UFO=111 |
[SEC40] |
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[SEC41] |
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UFO=111 |
[SEC42] |
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UFO=111 |
[SEC43] |
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UFO=111 |
[SEC44] |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC45] |
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UFO=111 |
[SEC46] |
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UFO=111 |
[SEC47] |
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UFO=111 |
[SEC48] |
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UFO=111 |
[SEC49] |
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UFO=111 |
[SEC50] |
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UFO=111 |
[SEC51] |
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Size=00000400 |
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UFO=111 |
[SEC52] |
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Address=00015000 |
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UFO=111 |
[SEC53] |
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Index=35 |
Address=00015400 |
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UFO=111 |
[SEC54] |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC55] |
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Size=00000400 |
Type=111 |
UFO=111 |
[SEC56] |
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UFO=111 |
[SEC57] |
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Type=111 |
UFO=111 |
[SEC58] |
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UFO=111 |
[SEC59] |
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UFO=111 |
[SEC60] |
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UFO=111 |
[SEC61] |
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UFO=111 |
[SEC62] |
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UFO=111 |
[SEC63] |
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Size=00000400 |
Type=111 |
UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STR750F.STmap |
---|
0,0 → 1,104 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STR750F.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STR750F |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=FF |
ACKVAL=75 |
MAPNAME=Sectors |
PagesPerSector = 1 |
family = 2; |
[B0F0] |
Name=B0F0 ;; page or sector name |
Index=0 ;; page or sector code |
Address=20000000 ;; start address (hexa format) |
Size=2000 ;; size (hexa format) |
Type=111 ;; reserved |
UFO=1 ;; reserved |
[B0F1] |
Name=B0F1 |
Index=1 |
Address=20002000 |
Size=2000 |
Type=111 |
UFO=1 |
[B0F2] |
Name=B0F2 |
Index=2 |
Address=20004000 |
Size=2000 |
Type=111 |
UFO=1 |
[B0F3] |
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Index=3 |
Address=20006000 |
Size=2000 |
Type=111 |
UFO=1 |
[B0F4] |
Name=B0F4 |
Index=4 |
Address=20008000 |
Size=8000 |
Type=111 |
UFO=1 |
[B0F5] |
Name=B0F5 |
Index=5 |
Address=20010000 |
Size=10000 |
Type=111 |
UFO=1 |
[B0F6] |
Name=B0F6 |
Index=6 |
Address=20020000 |
Size=10000 |
Type=111 |
UFO=1 |
[B0F7] |
Name=B0F7 |
Index=7 |
Address=20030000 |
Size=10000 |
Type=111 |
UFO=1 |
[B1F0] |
Name=B1F0 |
Index=10 |
Address=200C0000 |
Size=2000 |
Type=111 |
UFO=1 |
[B1F1] |
Name=B1F1 |
Index=11 |
Address=200C2000 |
Size=2000 |
Type=111 |
UFO=1 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STR91xFA.STmap |
---|
0,0 → 1,250 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STR91xFA.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STR91xFA |
PID=25966041 |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Sectors |
PagesPerSector = 1 |
family = 4; |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=00200000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
Index=01 |
Address=00210000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC2] |
Name=SEC2 |
Index=02 |
Address=00220000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC3] |
Name=SEC3 |
Index=03 |
Address=00230000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC4] |
Name=SEC4 |
Index=04 |
Address=00240000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC5] |
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Address=00250000 |
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Type=111 |
UFO=111 |
[SEC6] |
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Index=06 |
Address=00260000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC7] |
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Address=00270000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC8] |
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Address=00280000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC9] |
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Address=00290000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC10] |
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Size=00010000 |
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UFO=111 |
[SEC11] |
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Size=00010000 |
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UFO=111 |
[SEC12] |
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Address=002C0000 |
Size=00010000 |
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UFO=111 |
[SEC13] |
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[SEC14] |
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UFO=111 |
[SEC15] |
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UFO=111 |
[SEC16] |
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UFO=111 |
[SEC17] |
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UFO=111 |
[SEC18] |
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UFO=111 |
[SEC19] |
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Size=00010000 |
Type=111 |
UFO=111 |
[SEC20] |
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Type=111 |
UFO=111 |
[SEC21] |
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Size=00010000 |
Type=111 |
UFO=111 |
[SEC22] |
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Address=00360000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC23] |
Name=SEC23 |
Index=17 |
Address=00370000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC24] |
Name=SEC24 |
Index=18 |
Address=00380000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC25] |
Name=SEC25 |
Index=19 |
Address=00390000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC26] |
Name=SEC26 |
Index=1A |
Address=003A0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC27] |
Name=SEC27 |
Index=1B |
Address=003B0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC28] |
Name=SEC28 |
Index=1C |
Address=003C0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC29] |
Name=SEC29 |
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Address=003D0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC30] |
Name=SEC30 |
Index=1E |
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Size=00010000 |
Type=111 |
UFO=111 |
[SEC31] |
Name=SEC31 |
Index=1F |
Address=003F0000 |
Size=00010000 |
Type=111 |
UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STR91xFAWy2.STmap |
---|
0,0 → 1,55 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STR91xFAWy2.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STR91xFAWy2 |
PID=25966041 |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Sectors |
PagesPerSector = 1 |
family = 4; |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=00080000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
Index=01 |
Address=00090000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC2] |
Name=SEC2 |
Index=02 |
Address=000A0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC3] |
Name=SEC3 |
Index=03 |
Address=000B0000 |
Size=00010000 |
Type=111 |
UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STR91xFAWy4.STmap |
---|
0,0 → 1,81 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STR91xFAWy4.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STR91xFAWy4 |
PID=25966041 |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Sectors |
PagesPerSector = 1 |
family = 4; |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=00080000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
Index=01 |
Address=00090000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC2] |
Name=SEC2 |
Index=02 |
Address=000A0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC3] |
Name=SEC3 |
Index=03 |
Address=000B0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC4] |
Name=SEC4 |
Index=04 |
Address=000C0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC5] |
Name=SEC5 |
Index=05 |
Address=000D0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC6] |
Name=SEC6 |
Index=06 |
Address=000E0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC7] |
Name=SEC7 |
Index=07 |
Address=000F0000 |
Size=00010000 |
Type=111 |
UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STR91xFAWy6.STmap |
---|
0,0 → 1,138 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STR91xFAWy6.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STR91xFAWy6 |
PID=25966041 |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Sectors |
PagesPerSector = 1 |
family = 4; |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=0200000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
Index=01 |
Address=0210000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC2] |
Name=SEC2 |
Index=02 |
Address=0220000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC3] |
Name=SEC3 |
Index=03 |
Address=0230000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC4] |
Name=SEC4 |
Index=04 |
Address=0240000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC5] |
Name=SEC5 |
Index=05 |
Address=0250000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC6] |
Name=SEC6 |
Index=06 |
Address=0260000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC7] |
Name=SEC7 |
Index=07 |
Address=0270000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC8] |
Name=SEC8 |
Index=08 |
Address=0280000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC9] |
Name=SEC9 |
Index=09 |
Address=0290000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC10] |
Name=SEC10 |
Index=0A |
Address=02A0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC11] |
Name=SEC11 |
Index=0B |
Address=02B0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC12] |
Name=SEC12 |
Index=0C |
Address=02C0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC13] |
Name=SEC13 |
Index=0D |
Address=02D0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC14] |
Name=SEC14 |
Index=0E |
Address=02E0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC15] |
Name=SEC15 |
Index=0F |
Address=02F0000 |
Size=00010000 |
Type=111 |
UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/Map/STR91xFAWy7.STmap |
---|
0,0 → 1,250 |
;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : STR91xFAWy7.STmap |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : memory mapping |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[Product] |
Name=STR91xFAWy7 |
PID=25966041 |
FlashSize=FFFF |
RAMSize=FFFF |
PacketSize=FF |
ACKVAL=79 |
MAPNAME=Sectors |
PagesPerSector = 1 |
family = 4; |
[SEC0] |
Name=SEC0 |
Index=00 |
Address=00200000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC1] |
Name=SEC1 |
Index=01 |
Address=00210000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC2] |
Name=SEC2 |
Index=02 |
Address=00220000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC3] |
Name=SEC3 |
Index=03 |
Address=00230000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC4] |
Name=SEC4 |
Index=04 |
Address=00240000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC5] |
Name=SEC5 |
Index=05 |
Address=00250000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC6] |
Name=SEC6 |
Index=06 |
Address=00260000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC7] |
Name=SEC7 |
Index=07 |
Address=00270000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC8] |
Name=SEC8 |
Index=08 |
Address=00280000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC9] |
Name=SEC9 |
Index=09 |
Address=00290000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC10] |
Name=SEC10 |
Index=0A |
Address=002A0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC11] |
Name=SEC11 |
Index=0B |
Address=002B0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC12] |
Name=SEC12 |
Index=0C |
Address=002C0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC13] |
Name=SEC13 |
Index=0D |
Address=002D0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC14] |
Name=SEC14 |
Index=0E |
Address=002E0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC15] |
Name=SEC15 |
Index=0F |
Address=002F0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC16] |
Name=SEC16 |
Index=10 |
Address=00300000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC17] |
Name=SEC17 |
Index=11 |
Address=00310000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC18] |
Name=SEC18 |
Index=12 |
Address=00320000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC19] |
Name=SEC19 |
Index=13 |
Address=00330000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC20] |
Name=SEC20 |
Index=14 |
Address=00340000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC21] |
Name=SEC21 |
Index=15 |
Address=00350000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC22] |
Name=SEC22 |
Index=16 |
Address=00360000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC23] |
Name=SEC23 |
Index=17 |
Address=00370000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC24] |
Name=SEC24 |
Index=18 |
Address=00380000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC25] |
Name=SEC25 |
Index=19 |
Address=00390000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC26] |
Name=SEC26 |
Index=1A |
Address=003A0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC27] |
Name=SEC27 |
Index=1B |
Address=003B0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC28] |
Name=SEC28 |
Index=1C |
Address=003C0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC29] |
Name=SEC29 |
Index=1D |
Address=003D0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC30] |
Name=SEC30 |
Index=1E |
Address=003E0000 |
Size=00010000 |
Type=111 |
UFO=111 |
[SEC31] |
Name=SEC31 |
Index=1F |
Address=003F0000 |
Size=00010000 |
Type=111 |
UFO=111 |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_128K_ver_2.0.s19 |
---|
0,0 → 1,19 |
S0090000424C2E736D3723 |
S11300A05F3F907209008E16CD6087B690E7005CC2 |
S11300B04CB790A18226F1A681B7885F3F90E600F5 |
S11300C0A18026073F8AAE4000203FA18126073F3A |
S11300D08AAE44002034A120240E3F8AAE00804220 |
S11300E05858581C80002022A1602411A020AE0082 |
S11300F08042585858A601B78A200F20C1A060AE8C |
S1130100008042585858A602B78A905FCD60879EF7 |
S1130110B78B9FB78CA620C7505B43C7505C4F92E8 |
S1130120BD008A5C9FB78C4F92BD008A5C9FB78CE0 |
S11301304F92BD008A5C9FB78C4F92BD008A7205B6 |
S1130140505FFB90A30007270A905C1D00031C006E |
S11301508020B9B690B18827085F3C90B69097206C |
S11301609A815F720D008E1A720000980BA601C767 |
S1130170505B43C7505C200A3581505B357E505C30 |
S11301803F98CD6087F692A7008A720C008E0572A4 |
S113019005505FFB9FB18827035C20E6720D008E3B |
S10A01A0057205505FFB81AD |
S903FFFFFE |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_128K_ver_2.1.s19 |
---|
0,0 → 1,24 |
S00F000044656275675C424C2E736D38D9 |
S11300A05F3F903F9C7209008E16CD608CB690E73E |
S11300B0005C4CB790A18226F1A681B7885F3F907F |
S11300C0E600A18026073F8AAE4000203DA181269C |
S11300D0073F8AAE44002032A120240E3F8AAE009E |
S11300E080425858581C80002020A160240FA02072 |
S11300F0AE008042585858A601B78A200DA060AEC1 |
S1130100008042585858A602B78A905FCD608C9EF2 |
S1130110B78B9FB78CA620C7505B43C7505C4F92E8 |
S1130120BD008A5C9FB78C4F92BD008A5C9FB78CE0 |
S11301304F92BD008A5C9FB78C4F92BD008A7200BB |
S1130140505F077205505FFB20047210009C90A35F |
S11301500007270A905C1D00031C008020AEB690A7 |
S1130160B188271B5F3C90B69097CC00C09D9D9DA5 |
S11301709D9D9D9D9D9D9D9D9D9D9D9D9D9D9D81C7 |
S1130180CD608C5F3F9D720D008E18720000980B3D |
S1130190A601C7505B43C7505C20083581505B35CE |
S11301A07E505C3F98F692A7008A720C008E137200 |
S11301B000505F077205505FFB20047210009DCD54 |
S11301C0608C9FB18827035C20DB720D008E107257 |
S11301D000505F077205505FFB20247210009D20C1 |
S11301E01E9D9D9D9D9D9D9D9D9D9D9D9D9D9D9DBA |
S11301F09D9D9D9D9D9D9D9D9D9D9D9D9D9D9D8147 |
S903FFFFFE |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_128K_ver_2.2.s19 |
---|
0,0 → 1,12 |
S12300A05F3F903F9B7209008E16CD608AB690E7005C4CB790A18226F1A681B7885F3F9074 |
S12300C0E600A18026073F8AAE4000203DA18126073F8AAE44002032A120240E3F8AAE000E |
S12300E080425858581C80002020A160240FA020AE008042585858A601B78A200DA060AE27 |
S1230100008042585858A602B78A905FCD608A9EB78B9FB78CA620C7505B43C7505C4F92F1 |
S1230120BD008A5C9FB78C4F92BD008A5C9FB78C4F92BD008A5C9FB78C4F92BD008A7200D0 |
S1230140505F077205505FFB20047210009B90A30007270A905C1D00031C008020AEB6905C |
S1230160B188271B5F3C90B69097CC00C09D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D81E1 |
S1230180CD608A5F3F9C720D008E18720000980BA601C7505B43C7505C20083581505B35A3 |
S12301A07E505C3F98F692A7008A720C008E137200505F077205505FFB20047210009CCD0A |
S12301C0608A9FB18827035C20DB720D008E107200505F077205505FFB20247210009C20F0 |
S12301E01E9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D81F6 |
S903FFFFFE |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_256K_ver_1.0.s19 |
---|
0,0 → 1,22 |
S00F000044656275675C626C2E736D3899 |
S11300A05F3F907209008E16CD6097B690E7005CB2 |
S11300B04CB790A18226F1A681B7885F3F90E600F5 |
S11300C0A18026073F8AAE38002068A18126073F19 |
S11300D08AAE4000205DA110240F3F8AAE0080420A |
S11300E0585858581C8000204AA1302410A010AE43 |
S11300F000804258585858A601B78A2036A1502487 |
S113010010A030AE00804258585858A602B78A2032 |
S113011022A1702410A050AE00804258585858A60E |
S113012003B78A200EA070AE00804258585858A6D3 |
S113013004B78A905FCD60979EB78B9FB78CA6203B |
S1130140C7505B43C7505C4F92BD008A5C9FB78C1D |
S11301504F92BD008A5C9FB78C4F92BD008A5C9F12 |
S1130160B78C4F92BD008A7205505FFB90A3000FBD |
S1130170270A905C1D00031C008020B9B690B1884A |
S113018027095F3C90B69097CC00BE815F720D004A |
S11301908E18720000980BA601C7505B43C7505CD1 |
S11301A020083581505B357E505C3F98CD6097F6D2 |
S11301B092A7008A720C008E057205505FFB9FB1F6 |
S11301C08827035C20E6720D008E057205505FFBE4 |
S10401D081A9 |
S903FFFFFE |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_32K_verL_1.0.s19 |
---|
--- SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_32K_ver_1.0.s19 (nonexistent) |
+++ SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_32K_ver_1.0.s19 (revision 2068) |
@@ -0,0 +1,16 @@ |
+S00F000044656275675C626C2E736D3899 |
+S11300A05F3F907209008E16CD605FB690E7005CEA |
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+S1130130720D008E1A720000940BA601C7505B4327 |
+S1130140C7505C200A3581505B357E505C3F94CDAE |
+S1130150605FF692A7008A720C008E057205505FEC |
+S1130160FB9FB18827035C20E6720D008E057205A3 |
+S1070170505FFB815C |
+S903FFFFFE |
\ No newline at end of file |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_32K_ver_1.2.s19 |
---|
0,0 → 1,21 |
S00F000044656275675C626C2E736D3899 |
S11300A05F3F903F977209008E16CD606DB690E762 |
S11300B0005C4CB790A12126F1A620B7885F3F9041 |
S11300C0E600A12026073F8AAE4000200C3F8AAEFE |
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S11300E08B9FB78CA620C7505B43C7505C4F92BD13 |
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S113010092BD008A5C9FB78C4F92BD008A720050EA |
S11301105F077205505FFB20047210009790A300E4 |
S113012007270A905C1D00031C008020AEB690B126 |
S113013088271C5F3C90B69097CC00C09D9D9D9DE8 |
S11301409D9D9D9D9D9D9D9D9D9D9D9D9D9D9D81F7 |
S1130150CD606D5F3F98720D008E18720000940B95 |
S1130160A601C7505B43C7505C20083581505B35FE |
S11301707E505C3F94CD606DF692A7008A720C00AD |
S11301808E137200505F077205505FFB20047210DB |
S11301900098CD606D9FB18827035C20D8720D0054 |
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S11301B00098201B9D9D9D9D9D9D9D9D9D9D9D9D0C |
S11301C09D9D9D9D9D9D9D9D9D9D9D9D9D9D9D8177 |
S903FFFFFE |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_32K_ver_1.3.s19 |
---|
0,0 → 1,21 |
S00F000044656275675C626C2E736D3899 |
S11300A05F3F903F967209008E16CD6065B690E76B |
S11300B0005C4CB790A12126F1A620B7885F3F9041 |
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S113013088271C5F3C90B69097CC00C09D9D9D9DE8 |
S11301409D9D9D9D9D9D9D9D9D9D9D9D9D9D9D81F7 |
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S1130160A601C7505B43C7505C20083581505B35FE |
S11301707E505C3F94F692A7008A720C008E137234 |
S113018000505F077205505FFB200472100097CD8A |
S113019060659FB18827035C20DB720D008E1072AE |
S11301A000505F077205505FFB20247210009720F7 |
S11301B01E9D9D9D9D9D9D9D9D9D9D9D9D9D9D9DEA |
S11301C09D9D9D9D9D9D9D9D9D9D9D9D9D9D9D8177 |
S903FFFFFE |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STM8_Routines/E_W_ROUTINEs_32K_ver_1.4.s19 |
---|
0,0 → 1,20 |
S11300A05F3F903F967209008E16CD6063B690E76D |
S11300B0005C4CB790A12126F1A620B7885F3F9041 |
S11300C0E600A12026073F8AAE4000200C3F8AAEFE |
S11300D00080425858581C8000905FCD60639EB7E2 |
S11300E08B9FB78CA620C7505B43C7505C4F92BD13 |
S11300F0008A5C9FB78C4F92BD008A5C9FB78C4F7F |
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S11301105F077205505FFB20047210009690A300E5 |
S113012007270A905C1D00031C008020AEB690B126 |
S113013088271C5F3C90B6909720859D9D9D9D9D32 |
S11301409D9D9D9D9D9D9D9D9D9D9D9D9D9D9D81F7 |
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S11301707E505C3F94F692A7008A720C008E137234 |
S113018000505F077205505FFB200472100097CD8A |
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S11301A000505F077205505FFB20247210009720F7 |
S11301B01E9D9D9D9D9D9D9D9D9D9D9D9D9D9D9DEA |
S11301C09D9D9D9D9D9D9D9D9D9D9D9D9D9D9D8177 |
S903FFFFFE |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/STUARTBLLIB.dll |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/test1.cmd |
---|
0,0 → 1,2 |
rem STMFlashLoader.exe -c --pn 20 --br 115200 --to 1000 -Auto -i STM32_Connectivity-line_256K -e --all -d --fn LED_Blink.hex --v |
STMFlashLoader.exe -c --pn 20 --br 115200 --to 1000 -Auto -i STM32_Connectivity-line_256K -e --all -o -d --fn test1.hex --v |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/test1.hex |
---|
0,0 → 1,1977 |
:020000040800F2 |
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:100010000572000805720008057200080000000063 |
:100020000000000000000000000000000572000851 |
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:047B1C000000020063 |
:04000005080071C1BD |
:00000001FF |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/test2.cmd |
---|
0,0 → 1,2 |
rem STMFlashLoader.exe -c --pn 20 --br 115200 --to 1000 -Auto -i STM32_Connectivity-line_256K -e --all -d --fn LED_Blink.hex --v |
STMFlashLoader.exe -c --pn 20 --br 115200 --to 1000 -Auto -i STM32_Connectivity-line_256K -e --all -o -d --fn test2.hex |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/BIN/Release/test2.hex |
---|
0,0 → 1,202 |
:020000040800F2 |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMicroelectronics Flash Loader project.sdf |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMicroelectronics Flash Loader project.sln |
---|
0,0 → 1,34 |
|
Microsoft Visual Studio Solution File, Format Version 11.00 |
# Visual Studio 2010 |
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "STBLLIB", "STBLLIB\STBLLIB.vcxproj", "{8077C129-E6D4-0FC8-B319-EF5D1ECBE58A}" |
EndProject |
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "STMFlashLoader", "STMFlashLoader\STMFlashLoader.vcxproj", "{BCF55269-28FE-92E1-E0C1-2F8EECE65A86}" |
ProjectSection(ProjectDependencies) = postProject |
{8077C129-E6D4-0FC8-B319-EF5D1ECBE58A} = {8077C129-E6D4-0FC8-B319-EF5D1ECBE58A} |
EndProjectSection |
EndProject |
Global |
GlobalSection(SolutionConfigurationPlatforms) = preSolution |
Debug|Win32 = Debug|Win32 |
Release|Win32 = Release|Win32 |
Template|Win32 = Template|Win32 |
EndGlobalSection |
GlobalSection(ProjectConfigurationPlatforms) = postSolution |
{8077C129-E6D4-0FC8-B319-EF5D1ECBE58A}.Debug|Win32.ActiveCfg = Debug|Win32 |
{8077C129-E6D4-0FC8-B319-EF5D1ECBE58A}.Debug|Win32.Build.0 = Debug|Win32 |
{8077C129-E6D4-0FC8-B319-EF5D1ECBE58A}.Release|Win32.ActiveCfg = Release|Win32 |
{8077C129-E6D4-0FC8-B319-EF5D1ECBE58A}.Release|Win32.Build.0 = Release|Win32 |
{8077C129-E6D4-0FC8-B319-EF5D1ECBE58A}.Template|Win32.ActiveCfg = Release|Win32 |
{8077C129-E6D4-0FC8-B319-EF5D1ECBE58A}.Template|Win32.Build.0 = Release|Win32 |
{BCF55269-28FE-92E1-E0C1-2F8EECE65A86}.Debug|Win32.ActiveCfg = Debug|Win32 |
{BCF55269-28FE-92E1-E0C1-2F8EECE65A86}.Debug|Win32.Build.0 = Debug|Win32 |
{BCF55269-28FE-92E1-E0C1-2F8EECE65A86}.Release|Win32.ActiveCfg = Release|Win32 |
{BCF55269-28FE-92E1-E0C1-2F8EECE65A86}.Release|Win32.Build.0 = Release|Win32 |
{BCF55269-28FE-92E1-E0C1-2F8EECE65A86}.Template|Win32.ActiveCfg = Template|Win32 |
{BCF55269-28FE-92E1-E0C1-2F8EECE65A86}.Template|Win32.Build.0 = Template|Win32 |
EndGlobalSection |
GlobalSection(SolutionProperties) = preSolution |
HideSolutionNode = FALSE |
EndGlobalSection |
EndGlobal |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMicroelectronics Flash Loader project.suo |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Crs232/rs232.cpp |
---|
0,0 → 1,494 |
/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
* File Name : rs232.cpp |
* Author : MCD Application Team |
* Version : v2.2.0 |
* Date : 05/03/2010 |
* Description : Implements the RS232 class for COM communication |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#include <windows.h> |
#include <stdio.h> |
#include <string.h> |
#include "rs232.h" |
/// set serial communication over COM1 with 115200 Bauds, 8 bitand no parity. |
CRS232::CRS232() |
{ |
hcom = NULL; |
bufferSize = 2048; |
numPort = 1; |
speedInBaud = 115200; |
nbBit = 8; |
parity = 2; |
nbStopBit = 1; |
isConnected = FALSE; |
bEcho =0; |
FlowControl = FALSE; |
} |
CRS232::~CRS232() |
{ |
if(hcom != NULL) |
closeCom(); |
} |
void CRS232::SetComSettings(int _numPort, long _speedInBaud, int _nbBit, int _parity, float _nbStopBit) |
{ |
numPort = _numPort; |
speedInBaud = _speedInBaud; |
nbBit = _nbBit; |
parity = _parity; |
nbStopBit = _nbStopBit; |
} |
bool CRS232::open() |
{ |
char buf[] = "\\\\.\\COM1"; |
if(numPort<1 || numPort>999) |
return false; |
if(speedInBaud<1) |
return false; |
if(nbBit<5 || nbBit > 9) |
return false; |
if(parity<0 || parity > 2) |
return false; |
if(nbStopBit<1 || nbStopBit > 2) |
return false; |
itoa(numPort, &buf[7], 10); |
hcom=CreateFile(buf, GENERIC_READ | GENERIC_WRITE , 0, NULL, OPEN_EXISTING , 0, NULL); |
if (hcom==0 || hcom==INVALID_HANDLE_VALUE) |
return false; |
isConnected = TRUE; |
setTimeOut(5000); |
if ( !SetupComm(hcom, bufferSize, bufferSize) ) |
return false; |
if ( !GetCommState(hcom, &dcb)) |
return false; |
dcb.BaudRate = speedInBaud; |
dcb.ByteSize = nbBit; |
if(nbStopBit == 1) |
dcb.StopBits = ONESTOPBIT; |
if(nbStopBit == 1.5) |
dcb.StopBits = ONE5STOPBITS; |
if(nbStopBit == 2) |
dcb.StopBits = TWOSTOPBITS; |
if(parity == 0) |
dcb.Parity = NOPARITY; |
if(parity == 1) |
dcb.Parity = ODDPARITY; |
if(parity == 2) |
dcb.Parity = EVENPARITY; |
if ( FlowControl == true) |
{ |
dcb.fDtrControl = DTR_CONTROL_ENABLE; |
dcb.fRtsControl = RTS_CONTROL_ENABLE; |
} |
else |
{ |
dcb.fDtrControl = DTR_CONTROL_DISABLE; |
dcb.fRtsControl = RTS_CONTROL_DISABLE; |
} |
if (!SetCommState(hcom, &dcb)) |
return false; |
else |
return true; |
} |
void CRS232::closeCom() |
{ |
CloseHandle(hcom); |
hcom = NULL; |
isConnected = FALSE; |
} |
bool CRS232::setTimeOut(DWORD ms) |
{ |
if( ms<0) |
return false; |
ct.ReadIntervalTimeout = ms; |
ct.ReadTotalTimeoutMultiplier = ms; |
ct.ReadTotalTimeoutConstant = ms; |
ct.WriteTotalTimeoutMultiplier = ms; |
ct.WriteTotalTimeoutConstant = ms; |
if ( !SetCommTimeouts(hcom, &ct) ) |
return false; |
return false; |
//MSDN: The SetCommTimeouts function sets the time-out parameters for all read and write operations on a specified communications device. |
} |
bool CRS232::setSpeed(DWORD baudrate) |
{ |
if( baudrate<1) |
return false; |
if (!GetCommState(hcom, &dcb)) |
return FALSE; |
dcb.BaudRate = baudrate; |
if (!SetCommState(hcom, &dcb)) |
return FALSE; |
else |
return TRUE; |
//MSDN: The SetCommState function configures a communications device according to the specifications in a device-control block (a DCB structure). The function reinitializes all hardware and control settings, but it does not empty output or input queues. |
} |
int CRS232::sendData(string* data) |
{ |
if( data == NULL ) |
return false; |
return sendData((DWORD)data->size(), (LPBYTE)data->data()); |
} |
int CRS232::sendData(DWORD lg, LPBYTE data) |
{ |
DWORD result=0; |
DWORD result1=0; |
DWORD counter =0; |
if( lg<0 || data==NULL) |
return false; |
if ( bEcho == 2) |
{ |
for ( counter =0 ; counter < lg ; counter ++) |
{ |
if ( !WriteFile(hcom, data+counter, 1, &result1, 0) ) |
return -1; |
if( lg<0 || data==NULL) |
return false; |
if (!ReadFile(hcom, data+counter, 1, &result, 0)) |
return -1; |
} |
return (counter); |
} |
else |
{ |
if ( !WriteFile(hcom, data, lg, &result, 0) ) |
return -1; |
else |
return (int)result; |
} |
//MSDN: The WriteFile function writes data to a file and is designed for both synchronous |
// and asynchronous operation. The function starts writing data to the file at the |
// position indicated by the file pointer. After the write operation has been completed |
// , the file pointer is adjusted by the number of bytes actually written, except when |
// the file is opened with FILE_FLAG_OVERLAPPED. If the file handle was created for |
// overlapped input and output (I/O), the application must adjust the position of the |
// file pointer after the write operation is finished. |
// This function is designed for both synchronous and asynchronous operation. |
// The WriteFileEx function is designed solely for asynchronous operation. |
// It lets an application perform other processing during a file write operation. |
} |
int CRS232::receiveData(string* data) |
{ char buffer[1025]; |
int nbChar=0; |
if( data==NULL) |
return false; |
nbChar = receiveData(1024, (LPBYTE)buffer); |
buffer[nbChar] = 0; |
data->assign(buffer); |
return nbChar; |
} |
int CRS232::receiveData(DWORD lg, LPBYTE data) |
{ |
DWORD result=0; |
DWORD result1=0; |
DWORD counter =0; |
if( lg<0 || data==NULL) |
return false; |
if ( bEcho == 0) |
{ |
if (!ReadFile(hcom, data, lg, &result, 0)) |
return -1; |
else |
return (int)result; |
} |
else if ( bEcho == 1) |
{ |
for ( counter =0 ; counter < lg ; counter ++) |
{ |
if (!ReadFile(hcom, data+counter, 1, &result, 0)) |
return -1; |
if( lg<0 || data==NULL) |
return false; |
if ( !WriteFile(hcom, data+counter, 1, &result1, 0) ) |
return -1; |
} |
return (counter); |
} |
else if ( bEcho == 2) |
{ |
if (!ReadFile(hcom, data, lg, &result, 0)) |
return -1; |
else |
return (int)result; |
} |
else |
{ |
/* TODO */ |
return -1; |
} |
//MSDN: The ReadFile function reads data from a file, starting at the position indicated |
// by the file pointer. After the read operation has been completed, the file pointer |
// is adjusted by the number of bytes actually read, unless the file handle is |
// created with the overlapped attribute. If the file handle is created for |
// overlapped input and output (I/O), the application must adjust the position of |
// the file pointer after the read operation. |
// This function is designed for both synchronous and asynchronous operation. |
// The ReadFileEx function is designed solely for asynchronous operation. It lets |
// an application perform other processing during a file read operation. |
} |
/**************************** SetRts(val) **************************************************/ |
bool CRS232::setRts(bool val) |
{ |
if(val) |
{ |
if(EscapeCommFunction(hcom, SETRTS) == TRUE ) |
return true; |
} |
else |
{ |
if(EscapeCommFunction(hcom, CLRRTS) == TRUE ) |
return true; |
} |
return false; |
} |
/**************************** SetTxd(val) ***************************************************/ |
bool CRS232::setTxd(bool val) |
{ |
if(val) |
{ |
if( EscapeCommFunction(hcom, SETBREAK) == TRUE ) |
return true; |
} |
else |
{ |
if( EscapeCommFunction(hcom, CLRBREAK) == TRUE ) |
return true; |
} |
return false; |
} |
/**************************** SetDtr(val) ************************************************** */ |
bool CRS232::setDtr(bool val) |
{ |
if(val) |
{ |
if( EscapeCommFunction(hcom, SETDTR) == TRUE ) |
return true; |
} |
else |
{ |
if( EscapeCommFunction(hcom, CLRDTR) == TRUE ) |
return false; |
} |
return false; |
} |
/********************** GetCts() ***********************/ |
bool CRS232::getCts() |
{ |
DWORD result; |
GetCommModemStatus(hcom, &result); |
if(result & MS_CTS_ON) |
return true; |
else |
return false; |
} |
/********************** GetDtr() ***********************/ |
bool CRS232::getDtr() |
{ |
DWORD result; |
GetCommModemStatus(hcom, &result); |
if(result & MS_DSR_ON) |
return true; |
else |
return false; |
} |
/********************** GetRi() ***********************/ |
bool CRS232::getRi() |
{ |
DWORD result; |
GetCommModemStatus(hcom, &result); |
if(result & MS_RING_ON) |
return true; |
else |
return false; |
} |
/********************** GetCd() ***********************/ |
bool CRS232::getCd() |
{ int err=0; |
DWORD result; |
err = GetCommModemStatus(hcom, &result); |
if(result & MS_RLSD_ON) |
return true; |
else |
return false; |
} |
string CRS232::getErrorMsg() |
{ |
LPVOID lpMsgBuf; |
string sErreur = ""; |
if ( FormatMessage( FORMAT_MESSAGE_ALLOCATE_BUFFER | FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS, |
NULL, GetLastError(), |
MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT), // Default language |
(LPTSTR) &lpMsgBuf, 0, NULL )) |
{ |
sErreur.assign((LPCTSTR)lpMsgBuf); |
} |
return sErreur; |
} |
void CRS232::SetParity(int _parity) |
{ |
if(_parity == 0) |
dcb.Parity = NOPARITY; |
if(_parity == 1) |
dcb.Parity = ODDPARITY; |
if(_parity == 2) |
dcb.Parity = EVENPARITY; |
SetCommState(hcom, &dcb); |
} |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE******/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Crs232/rs232.h |
---|
0,0 → 1,80 |
/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
* File Name : rs232.h |
* Author : MCD Application Team |
* Version : v2.2.0 |
* Date : 05/03/2010 |
* Description : Defines the RS232 class for COM communication |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#ifndef LSERIE_H |
#define LSERIE_H |
#include <string> |
using namespace std; |
class CRS232 |
{ |
public: |
void SetParity(int _parity); |
BOOL isConnected; |
int numPort; |
long speedInBaud; |
int nbBit; |
int parity; |
float nbStopBit; |
int bEcho ; /* Echo back for LIN emulation */ |
/* 0 : Disabled , 1 : Echo Back , 2 : Listen back */ |
bool FlowControl; |
//------ CONSTRUCTOR ------ |
CRS232(); |
virtual ~CRS232(); |
//------ OPEN AND CONFIGURE ------ |
void SetComSettings(int _numPort, long _speedInBaud, int _nbBit, int _parity, float _nbStopBit); |
bool open(); // Open the serial port COM "numPort" at the speed "speedInBaud". |
// bauds with and this adjustement : "nbBit" bit / "nbStopBit" stop bit / "parity"). |
// Return: true if success. |
void closeCom(); //Close the serial port. |
bool setTimeOut(DWORD ms); //Set the time-out for receive data. Return: true if success. |
bool setSpeed(DWORD baudrate); //Set the speed in bauds. Return: true if success. |
//------ SEND AND RECEIVE DATA ------ |
int sendData(DWORD lg, LPBYTE data); //Send table "data" of "lg" bytes. Return: number of bytes really sent. |
int sendData(string* data); //Send string "data". Return: number of bytes really sent. |
int receiveData(DWORD lg, LPBYTE data); //Receive table "data" who is limit at "lg" bytes. Return: number of bytes received. |
int receiveData(string* data); //Receive string "data". Return: number of bytes received. |
//------ READ AND WRITE THE STATE OF THE CONTROL LINE ------ |
bool setRts(bool val); // Set the state of RTS. Return: true if success. |
bool setDtr(bool val); // Set the state of DTR. Return: true if success. |
bool setTxd(bool val); // Set the state of TXD. Return: true if success. |
bool getCts(); // Return: The state of CTS. |
bool getDtr(); // Return: The state of DTR. |
bool getRi(); // Return: The state of RI. |
bool getCd(); // Return: The state of CD. |
string getErrorMsg(); // Return: The error message generated by the last function. |
private: |
HANDLE hcom; //Otput file to the COM port | The file stream use for acces to the serial port. |
_COMMTIMEOUTS ct; //={0,0,0,0,0}; //Config du Time Out | This variable contain the delay of the time-out. |
DCB dcb; //Port configuration struct | This object is use in order to configure the serial port. |
int bufferSize; |
}; |
#endif |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE******/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Files/Debug/Files.lib |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Files/Errors.h |
---|
0,0 → 1,45 |
/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** |
* File Name : Errors.h |
* Author : MCD Application Team |
* Version : v2.1.0 |
* Date : 11/02/2009 |
* Description : Defines the files Input/Output error codes |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#ifndef ERRORS_H |
#define ERRORS_H |
#define FILES_ERROR_OFFSET (0x12340000+0x6000) |
#define FILES_NOERROR (0x12340000+0x0000) |
#define FILES_BADSUFFIX (FILES_ERROR_OFFSET+0x0002) |
#define FILES_UNABLETOOPENFILE (FILES_ERROR_OFFSET+0x0003) |
#define FILES_UNABLETOOPENTEMPFILE (FILES_ERROR_OFFSET+0x0004) |
#define FILES_BADFORMAT (FILES_ERROR_OFFSET+0x0005) |
#define FILES_BADADDRESSRANGE (FILES_ERROR_OFFSET+0x0006) |
#define FILES_BADPARAMETER (FILES_ERROR_OFFSET+0x0008) |
#define FILES_UNEXPECTEDERROR (FILES_ERROR_OFFSET+0x000A) |
#define FILES_FILEGENERALERROR (FILES_ERROR_OFFSET+0x000D) |
#define STPRT_ERROR_OFFSET (0x12340000+0x5000) |
#define STPRT_NOERROR (0x12340000) |
#define STPRT_UNABLETOLAUNCHTHREAD (STPRT_ERROR_OFFSET+0x0001) |
#define STPRT_ALREADYRUNNING (STPRT_ERROR_OFFSET+0x0007) |
#define STPRT_BADPARAMETER (STPRT_ERROR_OFFSET+0x0008) |
#define STPRT_BADFIRMWARESTATEMACHINE (STPRT_ERROR_OFFSET+0x0009) |
#define STPRT_UNEXPECTEDERROR (STPRT_ERROR_OFFSET+0x000A) |
#define STPRT_ERROR (STPRT_ERROR_OFFSET+0x000B) |
#define STPRT_RETRYERROR (STPRT_ERROR_OFFSET+0x000C) |
#define STPRT_UNSUPPORTEDFEATURE (STPRT_ERROR_OFFSET+0x000D) |
#endif |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE******/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Files/Files.h |
---|
0,0 → 1,99 |
/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** |
* File Name : Files.h |
* Author : MCD Application Team |
* Version : v2.1.0 |
* Date : 11/02/2009 |
* Description : Defines the Files DLL interface |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#if !defined(AFX_FILES_H__E07F909F_97B4_4295_8B8F_5EA1A83ECA92__INCLUDED_) |
#define AFX_FILES_H__E07F909F_97B4_4295_8B8F_5EA1A83ECA92__INCLUDED_ |
#if _MSC_VER > 1000 |
#pragma once |
#endif // _MSC_VER > 1000 |
#ifndef __AFXWIN_H__ |
#error include 'stdafx.h' before including this file for PCH |
#endif |
#include "resource.h" // main symbols |
#include "FilesInc.h" |
#include "Image.h" |
#include "Errors.h" |
//#include "IniFile.h" |
///////////////////////////////////////////////////////////////////////////// |
// CFilesApp |
// See Files.cpp for the implementation of this class |
// |
class CFilesApp : public CWinApp |
{ |
public: |
CFilesApp(); |
// Overrides |
// ClassWizard generated virtual function overrides |
//{{AFX_VIRTUAL(CFilesApp) |
//}}AFX_VIRTUAL |
//{{AFX_MSG(CFilesApp) |
// NOTE - the ClassWizard will add and remove member functions here. |
// DO NOT EDIT what you see in these blocks of generated code ! |
//}}AFX_MSG |
DECLARE_MESSAGE_MAP() |
}; |
extern "C" DWORD EXPORT FILES_OpenExistingFile(PSTR pPathFile, PHANDLE phFile, PWORD pVid, PWORD pPid, PWORD pBcd,PBYTE pNbImages); |
extern "C" DWORD EXPORT FILES_CreateNewFile(PSTR pPathFile, PHANDLE phFile, WORD Vid, WORD Pid, WORD Bcd); |
extern "C" DWORD EXPORT FILES_CloseFile(HANDLE hFile); |
extern "C" DWORD EXPORT FILES_AppendImageToFile(HANDLE hFile, HANDLE Image); |
extern "C" DWORD EXPORT FILES_ReadImageFromFile(HANDLE hFile, int Rank, PHANDLE pImage); |
extern "C" DWORD EXPORT FILES_ImageFromFile(PSTR pPathFile, PHANDLE pImage, BYTE nAlternate); |
extern "C" DWORD EXPORT FILES_ImageToFile(PSTR pPathFile, HANDLE Image); |
extern "C" DWORD EXPORT FILES_CreateImage(PHANDLE pHandle, BYTE nAlternate); |
extern "C" DWORD EXPORT FILES_CreateImageFromMapping(PHANDLE pHandle, PMAPPING pMapping); |
extern "C" DWORD EXPORT FILES_DuplicateImage(HANDLE hSource, PHANDLE pDest); |
extern "C" DWORD EXPORT FILES_FilterImageForOperation(HANDLE Handle, PMAPPING pMapping, DWORD Operation, BOOL bTruncateLeadFFForUpgrade); |
extern "C" DWORD EXPORT FILES_DestroyImageElement(HANDLE Handle, DWORD dwRank); |
extern "C" DWORD EXPORT FILES_DestroyImage(PHANDLE pHandle); |
extern "C" DWORD EXPORT FILES_GetImageAlternate(HANDLE Handle, PBYTE pAlternate); |
extern "C" DWORD EXPORT FILES_GetImageNbElement(HANDLE Handle, PDWORD pNbElements); |
extern "C" DWORD EXPORT FILES_GetImageName(HANDLE Handle, PSTR Name); |
extern "C" DWORD EXPORT FILES_SetImageName(HANDLE Handle, PSTR Name); |
extern "C" DWORD EXPORT FILES_SetImageElement(HANDLE Handle, DWORD dwRank, BOOL bInsert, IMAGEELEMENT Element); |
extern "C" DWORD EXPORT FILES_GetImageElement(HANDLE Handle, DWORD dwRank, PIMAGEELEMENT pElement); |
extern "C" DWORD EXPORT FILES_GetMemoryMapping(PSTR pPathFile, PWORD Size, PSTR MapName, PWORD PacketSize, PMAPPING pMapping, PBYTE PagesPerSector); |
/*FILES_OpenExistingFile |
FILES_CreateNewFile |
FILES_CloseFile |
FILES_AppendImageToFile |
FILES_ReadImageFromFile*/ |
///////////////////////////////////////////////////////////////////////////// |
//{{AFX_INSERT_LOCATION}} |
// Microsoft Visual C++ will insert additional declarations immediately before the previous line. |
#endif // !defined(AFX_FILES_H__E07F909F_97B4_4295_8B8F_5EA1A83ECA92__INCLUDED_) |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE******/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Files/FilesInc.h |
---|
0,0 → 1,69 |
/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** |
* File Name : FilesInc.h |
* Author : MCD Application Team |
* Version : v2.1.0 |
* Date : 11/02/2009 |
* Description : Defines the struct types used by Files DLL |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#ifndef FILES_INC_H |
#define FILES_INC_H |
#define OPERATION_DETACH 0 |
#define OPERATION_RETURN 1 |
#define OPERATION_UPLOAD 2 |
#define OPERATION_ERASE 3 |
#define OPERATION_DNLOAD 4 |
#ifndef TYPE_STATUS |
typedef struct |
{ |
UCHAR bStatus; |
UCHAR bwPollTimeout[3]; |
UCHAR bState; |
UCHAR iString; |
} STATUS, *PSTATUS; |
#endif |
#define BIT_READABLE 1 |
#define BIT_ERASABLE 2 |
#define BIT_WRITEABLE 4 |
typedef struct { |
char* Name; |
DWORD dwStartAddress; |
DWORD dwAliasedAddress; |
DWORD dwSectorIndex; |
DWORD dwSectorSize; |
BYTE bSectorType; |
BOOL UseForOperation; |
BOOL UseForErase; |
BOOL UseForUpload; |
BOOL UseForWriteProtect; |
} MAPPINGSECTOR, *PMAPPINGSECTOR; |
typedef struct { |
BYTE nAlternate; |
char Name[MAX_PATH]; |
DWORD NbSectors; |
PMAPPINGSECTOR pSectors; |
} MAPPING, *PMAPPING; |
typedef struct { |
DWORD dwAddress; |
DWORD dwDataLength; |
PBYTE Data; |
} IMAGEELEMENT, *PIMAGEELEMENT; |
#endif |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE******/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Files/Image.h |
---|
0,0 → 1,63 |
/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** |
* File Name : Image.h |
* Author : MCD Application Team |
* Version : v2.1.0 |
* Date : 11/02/2009 |
* Description : Defines the CImage class interface |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#ifndef _IMAGE_H_ |
#define _IMAGE_H_ |
class CImage : public CObject |
{ |
private: |
char m_LastError[1000]; |
BYTE m_bAlternate; |
CPtrArray *m_pElements; |
BOOL m_ImageState; |
BOOL m_bNamed; |
char m_Name[255]; |
BOOL LoadS19(PSTR pFilePath); |
BOOL LoadHEX(PSTR pFilePath); |
BOOL LoadBIN(PSTR pFilePath); |
BOOL SaveS19(PSTR pFilePath); |
BOOL SaveHEX(PSTR pFilePath); |
void LDisplayError(PSTR Str) { lstrcpy(m_LastError, Str); } |
BOOL ExistsElementsAtAddress(DWORD Address); |
void CompactElements(); |
public: |
CImage(CImage *pSource); |
CImage(BYTE bAlternate, BOOL bNamed, PSTR Name); |
CImage(PMAPPING pMapping, BOOL bNamed, PSTR Name); |
CImage(BYTE bAlternate, PSTR pFilePath, BOOL bNamed, PSTR Name); |
virtual ~CImage(); |
BOOL DumpToFile(PSTR pFilePath); |
BYTE GetAlternate() { return m_bAlternate; } |
BOOL GetImageState() { return m_ImageState; } |
BOOL GetName(PSTR Name) { if (m_bNamed) lstrcpy(Name, m_Name); return m_bNamed; } |
void SetName(PSTR Name) { lstrcpy(m_Name, Name); m_bNamed=TRUE; } |
BOOL GetBuffer(DWORD dwAddress, DWORD dwSize, PBYTE pBuffer); |
DWORD GetNbElements() { return m_pElements->GetSize(); } |
BOOL SetImageElement(DWORD dwRank, BOOL bInsert, IMAGEELEMENT Element); |
BOOL GetImageElement(DWORD dwRank, PIMAGEELEMENT pElement); |
BOOL FilterImageForOperation(PMAPPING pMapping, DWORD Operation, BOOL bTruncateLeadFF); |
BOOL DestroyImageElement(DWORD dwRank); |
}; |
#endif |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE******/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Files/Release/Files.lib |
---|
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svn:mime-type = application/octet-stream |
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Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Files/res/Files.rc2 |
---|
0,0 → 1,13 |
// |
// FILES.RC2 - resources Microsoft Visual C++ does not edit directly |
// |
#ifdef APSTUDIO_INVOKED |
#error this file is not editable by Microsoft Visual C++ |
#endif //APSTUDIO_INVOKED |
///////////////////////////////////////////////////////////////////////////// |
// Add manually edited resources here... |
///////////////////////////////////////////////////////////////////////////// |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/Files/resource.h |
---|
0,0 → 1,15 |
//{{NO_DEPENDENCIES}} |
// Microsoft Developer Studio generated include file. |
// Used by Files.rc |
// |
// Next default values for new objects |
// |
#ifdef APSTUDIO_INVOKED |
#ifndef APSTUDIO_READONLY_SYMBOLS |
#define _APS_NEXT_RESOURCE_VALUE 101 |
#define _APS_NEXT_COMMAND_VALUE 40001 |
#define _APS_NEXT_CONTROL_VALUE 1000 |
#define _APS_NEXT_SYMED_VALUE 101 |
#endif |
#endif |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STBLLIB/STBLLIB.cpp |
---|
0,0 → 1,827 |
/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
* File Name : STBLLIB.cpp |
* Author : MCD Application Team |
* Version : v2.2.0 |
* Date : 05/03/2010 |
* Description : Implements the System memory boot loader protocol interface |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#include <malloc.h> |
#include "stdafx.h" |
#include "STBLLIB.h" |
/************************************************************************************/ |
/* Generic BL API types |
/* |
/* |
/************************************************************************************/ |
typedef BYTE virt_GetProgress(LPBYTE progress); |
typedef BYTE virt_GetActivityTime(LPDWORD time); |
typedef BYTE virt_SetActivityTime(DWORD time); |
typedef BYTE virt_TARGET_GetFlashSize(DWORD Addr, LPWORD val); |
typedef BYTE virt_TARGET_GetMemoryAddress(DWORD Addr, LPBYTE val); |
typedef BYTE virt_TARGET_GetRDPOptionByte(LPBYTE RDP); |
typedef BYTE virt_TARGET_GetWRPOptionBytes(LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3); |
typedef BYTE virt_Send_RQ(LPSTBL_Request pRQ); |
typedef BYTE virt_SetCOMSettings(int numPort, long speedInBaud, int nbBit, int parity, float nbStopBit); |
typedef BYTE virt_COM_Open(); |
typedef BYTE virt_COM_Close(); |
typedef BYTE virt_STBL_SetSpeed(DWORD speed); |
typedef BYTE virt_STBL_Init_BL(); |
typedef BYTE virt_STBL_GET(LPBYTE Version, LPCommands pCmds); |
typedef BYTE virt_STBL_GET_VER_ROPS(LPBYTE Version, LPBYTE ROPEnabled, LPBYTE ROPDisabled); |
typedef BYTE virt_STBL_GET_ID(LPBYTE size, LPBYTE pID); |
typedef BYTE virt_STBL_READ(DWORD Address, BYTE Size, LPBYTE pData); |
typedef BYTE virt_STBL_GO(DWORD Address); |
typedef BYTE virt_STBL_WRITE(DWORD address, BYTE size, LPBYTE pData); |
typedef BYTE virt_STBL_ERASE(WORD NbSectors, LPBYTE pSectors); |
typedef BYTE virt_STBL_WRITE_PROTECT(BYTE NbSectors, LPBYTE pSectors); |
typedef BYTE virt_STBL_WRITE_TEMP_UNPROTECT(); |
typedef BYTE virt_STBL_WRITE_PERM_UNPROTECT(); |
typedef BYTE virt_STBL_READOUT_PROTECT(); |
typedef BYTE virt_STBL_READOUT_TEMP_UNPROTECT(); |
typedef BYTE virt_STBL_READOUT_PERM_UNPROTECT(); |
typedef BYTE virt_STBL_UPLOAD(DWORD Address, LPBYTE pData, DWORD Length); |
typedef BYTE virt_STBL_VERIFY(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad); |
typedef BYTE virt_STBL_DNLOAD(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad); |
typedef BYTE virt_SetPaketSize(BYTE size); |
typedef BYTE virt_GetPaketSize(LPBYTE size); |
typedef ACKS virt_GetAckValue(); |
typedef BOOL virt_COM_is_Open(); |
typedef BYTE virt_SetTimeOut(DWORD vms); |
typedef BYTE virt_TARGET_GetUserOptionByte(LPBYTE User); |
typedef BYTE virt_TARGET_GetDataOptionByte(LPBYTE Data0, LPBYTE Data1); |
typedef BYTE virt_TARGET_SetSIFData(BYTE User, BYTE RDP, BYTE Data0, BYTE Data1, BYTE WRP0, BYTE WRP1, BYTE WRP2, BYTE WRP3); |
typedef BYTE virt_TARGET_GetSIFData(LPBYTE User, LPBYTE RDP, LPBYTE Data0, LPBYTE Data1, LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3); |
typedef BYTE virt_STBL_SetRts(BOOL Val); |
typedef BYTE virt_STBL_SetDtr(BOOL Val); |
typedef BYTE virt_STBL_setTxd(BOOL val); |
typedef BYTE virt_STBL_getCts(BOOL* pval); |
typedef BYTE virt_STBL_getDtr(BOOL* pval); |
typedef BYTE virt_STBL_getRi(BOOL* pval); |
typedef BYTE virt_STBL_getCd(BOOL* pval); |
typedef BYTE virt_STBL_SetEcho(int val); |
typedef BYTE virt_STBL_SetFlowControl(int Val); |
/************************************************************************************/ |
/* Generic BL API references |
/* |
/* |
/************************************************************************************/ |
virt_GetProgress *pt_GetProgress; //(LPBYTE progress); |
virt_GetActivityTime *pt_GetActivityTime; //(LPDWORD time); |
virt_SetActivityTime *pt_SetActivityTime; //(DWORD time); |
virt_TARGET_GetFlashSize *pt_TARGET_GetFlashSize; //(DWORD Addr, LPWORD val); |
virt_TARGET_GetMemoryAddress *pt_TARGET_GetMemoryAddress; //(DWORD Addr, LPWORD val); |
virt_TARGET_GetRDPOptionByte *pt_TARGET_GetRDPOptionByte; //(LPBYTE RDP); |
virt_TARGET_GetWRPOptionBytes *pt_TARGET_GetWRPOptionBytes; //(LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3); |
virt_Send_RQ *pt_Send_RQ; //(LPSTBL_Request pRQ); |
virt_SetCOMSettings *pt_SetCOMSettings; //(int numPort, long speedInBaud, int nbBit, int parity, float nbStopBit); |
virt_COM_Open *pt_COM_Open; //(); |
virt_COM_Close *pt_COM_Close; //(); |
virt_STBL_SetSpeed *pt_STBL_SetSpeed; //(DWORD speed); |
virt_STBL_Init_BL *pt_STBL_Init_BL; //(); |
virt_STBL_GET *pt_STBL_GET; //(LPBYTE Version, LPCommands pCmds); |
virt_STBL_GET_VER_ROPS *pt_STBL_GET_VER_ROPS; //(LPBYTE Version, LPBYTE ROPEnabled, LPBYTE ROPDisabled); |
virt_STBL_GET_ID *pt_STBL_GET_ID; //(LPBYTE size, LPBYTE pID); |
virt_STBL_READ *pt_STBL_READ; //(DWORD Address, BYTE Size, LPBYTE pData); |
virt_STBL_GO *pt_STBL_GO; //(DWORD Address); |
virt_STBL_WRITE *pt_STBL_WRITE; //(DWORD address, BYTE size, LPBYTE pData); |
virt_STBL_ERASE *pt_STBL_ERASE; //(BYTE NbSectors, LPBYTE pSectors); |
virt_STBL_WRITE_PROTECT *pt_STBL_WRITE_PROTECT; //(BYTE NbSectors, LPBYTE pSectors); |
virt_STBL_WRITE_TEMP_UNPROTECT *pt_STBL_WRITE_TEMP_UNPROTECT; //(); |
virt_STBL_WRITE_PERM_UNPROTECT *pt_STBL_WRITE_PERM_UNPROTECT; //(); |
virt_STBL_READOUT_PROTECT *pt_STBL_READOUT_PROTECT; //(); |
virt_STBL_READOUT_TEMP_UNPROTECT *pt_STBL_READOUT_TEMP_UNPROTECT; //(); |
virt_STBL_READOUT_PERM_UNPROTECT *pt_STBL_READOUT_PERM_UNPROTECT; //(); |
virt_STBL_UPLOAD *pt_STBL_UPLOAD; //(DWORD Address, LPBYTE pData, DWORD Length); |
virt_STBL_VERIFY *pt_STBL_VERIFY; //(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad); |
virt_STBL_DNLOAD *pt_STBL_DNLOAD; //(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad); |
virt_SetPaketSize *pt_SetPaketSize; //(BYTE size); |
virt_GetPaketSize *pt_GetPaketSize; //(LPBYTE size); |
virt_GetAckValue *pt_GetAckValue; //(); |
virt_COM_is_Open *pt_COM_is_Open; //(); |
virt_SetTimeOut *pt_SetTimeOut; //(DWORD vms); |
virt_TARGET_GetUserOptionByte *pt_TARGET_GetUserOptionByte; //(LPBYTE User); |
virt_TARGET_GetDataOptionByte *pt_TARGET_GetDataOptionByte; //(LPBYTE Data0, LPBYTE Data1); |
virt_TARGET_SetSIFData *pt_TARGET_SetSIFData; //(BYTE User, BYTE RDP, BYTE Data0, BYTE Data1, BYTE WRP0, BYTE WRP1, BYTE WRP2, BYTE WRP3); |
virt_TARGET_GetSIFData *pt_TARGET_GetSIFData; //(LPBYTE User, LPBYTE RDP, LPBYTE Data0, LPBYTE Data1, LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3); |
virt_STBL_SetRts *pt_STBL_SetRts; //(BOOL val); |
virt_STBL_SetDtr *pt_STBL_SetDtr; //(BOOL val); |
virt_STBL_setTxd *pt_STBL_setTxd; //(BOOL val); |
virt_STBL_getCts *pt_STBL_getCts; //(BOOL* pval); |
virt_STBL_getDtr *pt_STBL_getDtr; //(BOOL* pval); |
virt_STBL_getRi *pt_STBL_getRi; //(BOOL* pval); |
virt_STBL_getCd *pt_STBL_getCd; //(BOOL* pval); |
virt_STBL_SetEcho *pt_STBL_SetEcho ; //(int val); |
virt_STBL_SetFlowControl *pt_STBL_SetFlowControl ; //(bool val); |
DWORD MAX_DATA_SIZE = 0xFF; // Packet size(in byte) |
BYTE ACK = 0x79; |
BYTE NACK = 0x1F; |
ACKS ACK_VALUE = ST79; |
LPTARGET_DESCRIPTOR Target; |
CRS232 Cur_COM; |
ACKS McuTarget; |
DWORD Progress; |
DWORD ActivityTime ; |
HINSTANCE ST_BL_Lib_Hdle = NULL; |
BOOL APIENTRY DllMain( HANDLE hModule, |
DWORD ul_reason_for_call, |
LPVOID lpReserved |
) |
{ |
switch (ul_reason_for_call) |
{ |
case DLL_PROCESS_ATTACH :{ |
McuTarget = UNDEFINED; |
Target = (LPTARGET_DESCRIPTOR)malloc(sizeof(TARGET_DESCRIPTOR)); |
Target->Version = 0x00; |
Target->CmdCount = 0x00; |
Target->PIDLen = 0x00; |
Target->PID = (LPBYTE)malloc(1); |
Target->ROPE = 0x00; |
Target->ROPD = 0x00; |
Target->GET_CMD = FALSE ; //Get the version and the allowed commands supported by the current version of the boot loader |
Target->GET_VER_ROPS_CMD = FALSE ; //Get the BL version and the Read Protection status of the NVM |
Target->GET_ID_CMD = FALSE ; //Get the chip ID |
Target->READ_CMD = FALSE ; //Read up to 256 bytes of memory starting from an address specified by the user |
Target->GO_CMD = FALSE ; //Jump to an address specified by the user to execute (a loaded) code |
Target->WRITE_CMD = FALSE ; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
Target->ERASE_CMD = FALSE ; //Erase from one to all the NVM sectors |
Target->ERASE_EXT_CMD = FALSE ; //Erase from one to all the NVM sectors |
Target->WRITE_PROTECT_CMD = FALSE ; //Enable the write protection in a permanent way for some sectors |
Target->WRITE_TEMP_UNPROTECT_CMD = FALSE ; //Disable the write protection in a temporary way for all NVM sectors |
Target->WRITE_PERM_UNPROTECT_CMD = FALSE ; //Disable the write protection in a permanent way for all NVM sectors |
Target->READOUT_PERM_PROTECT_CMD = FALSE ; //Enable the readout protection in a permanent way |
Target->READOUT_TEMP_UNPROTECT_CMD = FALSE ; //Disable the readout protection in a temporary way |
Target->READOUT_PERM_UNPROTECT_CMD = FALSE ; //Disable the readout protection in a permanent way |
}break; |
case DLL_THREAD_ATTACH :{ |
/*McuTarget = UNDEFINED; |
Target = (LPTARGET_DESCRIPTOR)malloc(sizeof(TARGET_DESCRIPTOR)); |
Target->Version = 0x00; |
Target->CmdCount = 0x00; |
Target->PIDLen = 0x00; |
Target->PID = (LPBYTE)malloc(1); |
Target->ROPE = 0x00; |
Target->ROPD = 0x00; |
Target->GET_CMD = FALSE ; //Get the version and the allowed commands supported by the current version of the boot loader |
Target->GET_VER_ROPS_CMD = FALSE ; //Get the BL version and the Read Protection status of the NVM |
Target->GET_ID_CMD = FALSE ; //Get the chip ID |
Target->READ_CMD = FALSE ; //Read up to 256 bytes of memory starting from an address specified by the user |
Target->GO_CMD = FALSE ; //Jump to an address specified by the user to execute (a loaded) code |
Target->WRITE_CMD = FALSE ; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
Target->ERASE_CMD = FALSE ; //Erase from one to all the NVM sectors |
Target->WRITE_PROTECT_CMD = FALSE ; //Enable the write protection in a permanent way for some sectors |
Target->WRITE_TEMP_UNPROTECT_CMD = FALSE ; //Disable the write protection in a temporary way for all NVM sectors |
Target->WRITE_PERM_UNPROTECT_CMD = FALSE ; //Disable the write protection in a permanent way for all NVM sectors |
Target->READOUT_PERM_PROTECT_CMD = FALSE ; //Enable the readout protection in a permanent way |
Target->READOUT_TEMP_UNPROTECT_CMD = FALSE ; //Disable the readout protection in a temporary way |
Target->READOUT_PERM_UNPROTECT_CMD = FALSE ; //Disable the readout protection in a permanent way |
*/}break; |
case DLL_THREAD_DETACH :{}break; |
case DLL_PROCESS_DETACH :{}break; |
} |
return TRUE; |
} |
/************************************************************************************/ |
/* SET COMMUNICATION INTERFACE TYPE |
/* UART - CAN - ... |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_SetComIntType(BYTE com_int_type) |
{ |
//com_int_type = 0; // This is reserved for Future, When the CANtoUSB Bridge will be available |
// The CAN module and DLL should be used in com_int_type =1 |
switch (com_int_type) |
{ |
case 0:{ |
ST_BL_Lib_Hdle = GetModuleHandle("STUARTBLLIB"); |
if ( ST_BL_Lib_Hdle == NULL ) |
{ |
ST_BL_Lib_Hdle = LoadLibrary("STUARTBLLIB") ; |
} |
}break; |
case 1:{ |
ST_BL_Lib_Hdle = GetModuleHandle("STCANBLLIB"); |
if ( ST_BL_Lib_Hdle == NULL ) |
{ |
ST_BL_Lib_Hdle = LoadLibrary("STCANBLLIB") ; |
} |
}break; |
} |
pt_GetProgress = (virt_GetProgress*)GetProcAddress(ST_BL_Lib_Hdle,"GetProgress"); |
pt_GetActivityTime = (virt_GetActivityTime*)GetProcAddress(ST_BL_Lib_Hdle,"GetActivityTime"); //(LPDWORD time); |
pt_SetActivityTime = (virt_SetActivityTime*)GetProcAddress(ST_BL_Lib_Hdle,"SetActivityTime"); //(DWORD time); |
pt_TARGET_GetFlashSize = (virt_TARGET_GetFlashSize*)GetProcAddress(ST_BL_Lib_Hdle,"TARGET_GetFlashSize"); |
pt_TARGET_GetMemoryAddress = (virt_TARGET_GetMemoryAddress*)GetProcAddress(ST_BL_Lib_Hdle,"TARGET_GetMemoryAddress"); |
pt_TARGET_GetRDPOptionByte = (virt_TARGET_GetRDPOptionByte*)GetProcAddress(ST_BL_Lib_Hdle,"TARGET_GetRDPOptionByte"); |
pt_TARGET_GetWRPOptionBytes = (virt_TARGET_GetWRPOptionBytes*)GetProcAddress(ST_BL_Lib_Hdle,"TARGET_GetWRPOptionBytes"); |
pt_Send_RQ = (virt_Send_RQ*)GetProcAddress(ST_BL_Lib_Hdle,"Send_RQ"); |
pt_SetCOMSettings = (virt_SetCOMSettings*)GetProcAddress(ST_BL_Lib_Hdle,"SetCOMSettings"); |
pt_COM_Open = (virt_COM_Open*)GetProcAddress(ST_BL_Lib_Hdle,"COM_Open"); |
pt_COM_Close = (virt_COM_Close*)GetProcAddress(ST_BL_Lib_Hdle,"COM_Close"); |
pt_STBL_SetSpeed = (virt_STBL_SetSpeed*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_SetSpeed"); |
pt_STBL_Init_BL = (virt_STBL_Init_BL*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_Init_BL"); |
pt_STBL_GET = (virt_STBL_GET*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_GET"); |
pt_STBL_GET_VER_ROPS = (virt_STBL_GET_VER_ROPS*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_GET_VER_ROPS"); |
pt_STBL_GET_ID = (virt_STBL_GET_ID*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_GET_ID"); |
pt_STBL_READ = (virt_STBL_READ*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_READ"); |
pt_STBL_GO = (virt_STBL_GO*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_GO"); |
pt_STBL_WRITE = (virt_STBL_WRITE*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_WRITE"); |
pt_STBL_ERASE = (virt_STBL_ERASE*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_ERASE"); |
pt_STBL_WRITE_PROTECT = (virt_STBL_WRITE_PROTECT*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_WRITE_PROTECT"); |
pt_STBL_WRITE_TEMP_UNPROTECT = (virt_STBL_WRITE_TEMP_UNPROTECT*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_WRITE_TEMP_UNPROTECT"); |
pt_STBL_WRITE_PERM_UNPROTECT = (virt_STBL_WRITE_PERM_UNPROTECT*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_WRITE_PERM_UNPROTECT"); |
pt_STBL_READOUT_PROTECT = (virt_STBL_READOUT_PROTECT*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_READOUT_PROTECT"); |
pt_STBL_READOUT_TEMP_UNPROTECT = (virt_STBL_READOUT_TEMP_UNPROTECT*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_READOUT_TEMP_UNPROTECT"); |
pt_STBL_READOUT_PERM_UNPROTECT = (virt_STBL_READOUT_PERM_UNPROTECT*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_READOUT_PERM_UNPROTECT"); |
pt_STBL_UPLOAD = (virt_STBL_UPLOAD*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_UPLOAD"); |
pt_STBL_VERIFY = (virt_STBL_VERIFY*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_VERIFY"); |
pt_STBL_DNLOAD = (virt_STBL_DNLOAD*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_DNLOAD"); |
pt_SetPaketSize = (virt_SetPaketSize*)GetProcAddress(ST_BL_Lib_Hdle,"SetPaketSize"); |
pt_GetPaketSize = (virt_GetPaketSize*)GetProcAddress(ST_BL_Lib_Hdle,"GetPaketSize"); |
pt_GetAckValue = (virt_GetAckValue*)GetProcAddress(ST_BL_Lib_Hdle,"GetAckValue"); |
pt_COM_is_Open = (virt_COM_is_Open*)GetProcAddress(ST_BL_Lib_Hdle,"COM_is_Open"); |
pt_SetTimeOut = (virt_SetTimeOut*)GetProcAddress(ST_BL_Lib_Hdle,"SetTimeOut"); |
pt_TARGET_GetUserOptionByte = (virt_TARGET_GetUserOptionByte*)GetProcAddress(ST_BL_Lib_Hdle,"TARGET_GetUserOptionByte"); |
pt_TARGET_GetDataOptionByte = (virt_TARGET_GetDataOptionByte*)GetProcAddress(ST_BL_Lib_Hdle,"TARGET_GetDataOptionByte"); |
pt_TARGET_SetSIFData = (virt_TARGET_SetSIFData*)GetProcAddress(ST_BL_Lib_Hdle,"TARGET_SetSIFData"); |
pt_TARGET_GetSIFData = (virt_TARGET_GetSIFData*)GetProcAddress(ST_BL_Lib_Hdle,"TARGET_GetSIFData"); |
pt_STBL_SetRts = (virt_STBL_SetRts*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_SetRts"); |
pt_STBL_SetDtr = (virt_STBL_SetDtr*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_SetDtr"); |
pt_STBL_setTxd = (virt_STBL_setTxd*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_setTxd"); |
pt_STBL_getCts = (virt_STBL_getCts*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_getCts"); |
pt_STBL_getDtr = (virt_STBL_getDtr*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_getDtr"); |
pt_STBL_getRi = (virt_STBL_getRi*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_getRi"); |
pt_STBL_getCd = (virt_STBL_getCd*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_getCd"); |
pt_STBL_SetEcho = (virt_STBL_SetEcho*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_SetEcho"); |
pt_STBL_SetFlowControl = (virt_STBL_SetFlowControl*)GetProcAddress(ST_BL_Lib_Hdle,"STBL_SetFlowControl"); |
return 0; |
} |
/************************************************************************************/ |
/*Set the communication settings for UART, CAN, ... |
/* UART - numPort, speedInBaud, nbBit, parity, nbStopBit |
/* CAN - only : speedInBaud |
/************************************************************************************/ |
STBLLIB_API BYTE SetCOMSettings(int numPort, long speedInBaud, int nbBit, |
int parity, float nbStopBit) |
{ |
if(pt_SetCOMSettings) |
return pt_SetCOMSettings(numPort, speedInBaud, nbBit, parity, nbStopBit); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE Send_RQ(LPSTBL_Request pRQ) |
{ |
if(pt_Send_RQ) |
return pt_Send_RQ(pRQ); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE COM_Open() |
{ |
if(pt_COM_Open) |
return pt_COM_Open(); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE COM_Close() |
{ |
if(pt_COM_Close) |
return pt_COM_Close(); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_SetSpeed(DWORD speed) |
{ |
if(pt_STBL_SetSpeed) |
return pt_STBL_SetSpeed(speed); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_Init_BL() |
{ |
if(pt_STBL_Init_BL) |
return pt_STBL_Init_BL(); |
else |
return LIB_LOADING_ERROR; |
} |
/******************************************************************************************/ |
/* Boot Loader commands implementation |
/******************************************************************************************/ |
STBLLIB_API BYTE STBL_GET(LPBYTE Version, LPCommands pCmds) |
{ |
if(pt_STBL_GET) |
return pt_STBL_GET(Version, pCmds); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_GET_VER_ROPS(LPBYTE Version, LPBYTE ROPEnabled, LPBYTE ROPDisabled) |
{ |
if(pt_STBL_GET_VER_ROPS) |
return pt_STBL_GET_VER_ROPS(Version, ROPEnabled, ROPDisabled); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_GET_ID(LPBYTE size, LPBYTE pID) |
{ |
if(pt_STBL_GET_ID) |
return pt_STBL_GET_ID(size, pID); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_READ(DWORD Address, BYTE Size, LPBYTE pData) |
{ |
if(pt_STBL_READ) |
return pt_STBL_READ(Address, Size, pData); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_GO(DWORD Address) |
{ |
if(pt_STBL_GO) |
return pt_STBL_GO(Address); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_WRITE(DWORD address, BYTE size, LPBYTE pData) |
{ |
if(pt_STBL_WRITE) |
return pt_STBL_WRITE(address, size, pData); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_ERASE(WORD NbSectors, LPBYTE pSectors) |
{ |
if(pt_STBL_ERASE) |
return pt_STBL_ERASE(NbSectors, pSectors); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_WRITE_PROTECT(BYTE NbSectors, LPBYTE pSectors) |
{ |
if(pt_STBL_WRITE_PROTECT) |
return pt_STBL_WRITE_PROTECT(NbSectors, pSectors); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_WRITE_TEMP_UNPROTECT() |
{ |
if(pt_STBL_WRITE_TEMP_UNPROTECT) |
return pt_STBL_WRITE_TEMP_UNPROTECT(); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_WRITE_PERM_UNPROTECT() |
{ |
if(pt_STBL_WRITE_PERM_UNPROTECT) |
return pt_STBL_WRITE_PERM_UNPROTECT(); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_READOUT_PROTECT() |
{ |
if(pt_STBL_READOUT_PROTECT) |
return pt_STBL_READOUT_PROTECT(); |
else |
return LIB_LOADING_ERROR; |
} |
STBLLIB_API BYTE STBL_READOUT_TEMP_UNPROTECT() |
{ |
if(pt_STBL_READOUT_TEMP_UNPROTECT) |
return pt_STBL_READOUT_TEMP_UNPROTECT(); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* READOUT_PERM_UNPROTECT |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_READOUT_PERM_UNPROTECT() |
{ |
if(pt_STBL_READOUT_PERM_UNPROTECT) |
return pt_STBL_READOUT_PERM_UNPROTECT(); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* UPLOAD |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_UPLOAD(DWORD Address, LPBYTE pData, DWORD Length) |
{ |
if(pt_STBL_UPLOAD) |
return pt_STBL_UPLOAD(Address, pData, Length); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* VERIFY |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_VERIFY(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad) |
{ |
if(pt_STBL_VERIFY) |
return pt_STBL_VERIFY(Address, pData, Length,bTruncateLeadFFForDnLoad); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* DNLOAD - this command uses the STBL_WRITE function to download a big block of data |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_DNLOAD(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad) |
{ |
if(pt_STBL_DNLOAD) |
return pt_STBL_DNLOAD(Address, pData, Length,bTruncateLeadFFForDnLoad); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* SET PACKET SIZE |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE SetPaketSize(BYTE size) |
{ |
if(pt_SetPaketSize) |
return pt_SetPaketSize(size); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* GET PACKET SIZE |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE GetPaketSize(LPBYTE size) |
{ |
if(pt_GetPaketSize) |
return pt_GetPaketSize(size); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* GetAckValue |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API ACKS GetAckValue() |
{ |
if(pt_GetAckValue) |
return pt_GetAckValue(); |
else |
return UNDEFINED; |
} |
/************************************************************************************/ |
/* IsConnected |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BOOL COM_is_Open() |
{ |
if(pt_COM_is_Open) |
return pt_COM_is_Open(); |
else |
return FALSE; |
} |
/************************************************************************************/ |
/* SetTimeOut |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE SetTimeOut(DWORD vms) |
{ |
if(pt_SetTimeOut) |
return pt_SetTimeOut(vms); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* GetFlashSize |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetFlashSize(DWORD Addr, LPWORD val) |
{ |
if(pt_TARGET_GetFlashSize) |
return pt_TARGET_GetFlashSize(Addr, val); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* GetMemoryAddress |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetMemoryAddress(DWORD Addr, LPBYTE val) |
{ |
if(pt_TARGET_GetMemoryAddress) |
return pt_TARGET_GetMemoryAddress(Addr, val); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* GetRDPOptionByte |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetRDPOptionByte(LPBYTE RDP) |
{ |
if(pt_TARGET_GetRDPOptionByte) |
return pt_TARGET_GetRDPOptionByte(RDP); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* GetWRPOptionBytes |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetWRPOptionBytes(LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3) |
{ |
if(pt_TARGET_GetWRPOptionBytes) |
return pt_TARGET_GetWRPOptionBytes(WRP0, WRP1, WRP2, WRP3); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* GetUserOptionByte |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetUserOptionByte(LPBYTE User) |
{ |
if(pt_TARGET_GetUserOptionByte) |
return pt_TARGET_GetUserOptionByte(User); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* GetDataOptionByte |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetDataOptionByte(LPBYTE Data0, LPBYTE Data1) |
{ |
if(pt_TARGET_GetDataOptionByte) |
return pt_TARGET_GetDataOptionByte(Data0, Data1); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* SetSIFData |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_SetSIFData(BYTE User, BYTE RDP, BYTE Data0, BYTE Data1, |
BYTE WRP0, BYTE WRP1, BYTE WRP2, BYTE WRP3) |
{ |
if(pt_TARGET_SetSIFData) |
return pt_TARGET_SetSIFData(User, RDP, Data0, Data1, WRP0, WRP1, WRP2, WRP3); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* SetSIFData |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetSIFData(LPBYTE User, LPBYTE RDP, LPBYTE Data0, LPBYTE Data1, |
LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3) |
{ |
if(pt_TARGET_GetSIFData) |
return pt_TARGET_GetSIFData(User, RDP, Data0, Data1, WRP0, WRP1, WRP2, WRP3); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* GET PROGRESS STATE |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE GetProgress(LPBYTE progress) |
{ |
if(pt_GetProgress) |
return pt_GetProgress(progress); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Get activity time |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE GetActivityTime(LPDWORD time) |
{ |
if(pt_GetActivityTime) |
return pt_GetActivityTime(time); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Set activity time |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE SetActivityTime(DWORD time) |
{ |
if(pt_SetActivityTime) |
return pt_SetActivityTime(time); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Set Rts Line State |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_SetRts(BOOL Val) |
{ |
if(pt_STBL_SetRts) |
return pt_STBL_SetRts(Val); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Set Dtr Line State |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_SetDtr(BOOL Val) |
{ |
if(pt_Send_RQ) |
return pt_STBL_SetDtr(Val); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Set the state of TXD. Return: true if success. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_setTxd(BOOL val) |
{ |
if(pt_STBL_setTxd) |
return pt_STBL_setTxd(val); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Return: The state of CTS. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_getCts(BOOL* pval) |
{ |
if(pt_STBL_getCts) |
return pt_STBL_getCts(pval); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Return: The state of DTR. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_getDtr(BOOL* pval) |
{ |
if(pt_STBL_getDtr) |
return pt_STBL_getDtr(pval); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Return: The state of RI. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_getRi(BOOL* pval) |
{ |
if(pt_STBL_getRi) |
return pt_STBL_getRi(pval); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Return: The state of DTR. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_getCd(BOOL* pval) |
{ |
if(pt_STBL_getCd) |
return pt_STBL_getCd(pval); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* Set Echo back Mode |
/* 0 = Echo Disabled |
/* 1 = Echo Back Enabled |
/* 2 = Listen Echo Enabled |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_SetEcho(int val) |
{ |
if(pt_STBL_SetEcho) |
return pt_STBL_SetEcho(val); |
else |
return LIB_LOADING_ERROR; |
} |
/************************************************************************************/ |
/* SetFlowControl : Enable/Disable Flow Control of DTR and RTS |
/* FALSE = Disabled |
/* TRUE = Enabled |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_SetFlowControl(bool val) |
{ |
if(pt_STBL_SetFlowControl) |
return pt_STBL_SetFlowControl(val); |
else |
return LIB_LOADING_ERROR; |
} |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE******/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STBLLIB/STBLLIB.dsp |
---|
0,0 → 1,129 |
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!MESSAGE "STBLLIB - Win32 Debug" (based on "Win32 (x86) Dynamic-Link Library") |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STBLLIB/STBLLIB.h |
---|
0,0 → 1,486 |
/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
* File Name : STBLLIB.h |
* Author : MCD Application Team |
* Version : v2.2.0 |
* Date : 05/03/2010 |
* Description : Defines the system memory boot loader protocol interface |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#ifndef STDLIB_H |
#define STDLIB_H |
#include "StdAfx.h" |
#include "../CRs232/rs232.h" |
#ifdef STBLLIB_EXPORTS |
#define STBLLIB_API __declspec(dllexport) |
#else |
#define STBLLIB_API __declspec(dllimport) |
#endif |
const BYTE INIT_CON = 0x7F; |
const BYTE GET_CMD = 0x00; //Get the version and the allowed commands supported by the current version of the boot loader |
const BYTE GET_VER_ROPS_CMD = 0x01; //Get the BL version and the Read Protection status of the NVM |
const BYTE GET_ID_CMD = 0x02; //Get the chip ID |
const BYTE SET_SPEED_CMD = 0x03; //set the new baudrate |
const BYTE READ_CMD = 0x11; //Read up to 256 bytes of memory starting from an address specified by the user |
const BYTE GO_CMD = 0x21; //Jump to an address specified by the user to execute (a loaded) code |
const BYTE WRITE_CMD = 0x31; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
const BYTE ERASE_CMD = 0x43; //Erase from one to all the NVM sectors |
const BYTE ERASE_EXT_CMD = 0x44; //Erase from one to all the NVM sectors |
const BYTE WRITE_PROTECT_CMD = 0x63; //Enable the write protection in a permanent way for some sectors |
const BYTE WRITE_TEMP_UNPROTECT_CMD = 0x71; //Disable the write protection in a temporary way for all NVM sectors |
const BYTE WRITE_PERM_UNPROTECT_CMD = 0x73; //Disable the write protection in a permanent way for all NVM sectors |
const BYTE READOUT_PROTECT_CMD = 0x82; //Enable the readout protection in a permanent way |
const BYTE READOUT_TEMP_UNPROTECT_CMD = 0x91; //Disable the readout protection in a temporary way |
const BYTE READOUT_PERM_UNPROTECT_CMD = 0x92; //Disable the readout protection in a permanent way |
const BYTE SUCCESS = 0x00; // No error |
const BYTE ERROR_OFFSET = 0x00; //error offset |
const BYTE COM_ERROR_OFFSET = ERROR_OFFSET + 0x00; |
const BYTE NO_CON_AVAILABLE = COM_ERROR_OFFSET + 0x01; // No serial port opened |
const BYTE COM_ALREADY_OPENED = COM_ERROR_OFFSET + 0x02; // Serial port already opened |
const BYTE CANT_OPEN_COM = COM_ERROR_OFFSET + 0x03; // Fail to open serial port |
const BYTE SEND_FAIL = COM_ERROR_OFFSET + 0x04; // send over serial port fail |
const BYTE READ_FAIL = COM_ERROR_OFFSET + 0x05; // Read from serial port fail |
const BYTE SYS_MEM_ERROR_OFFSET = ERROR_OFFSET + 0x10; |
const BYTE CANT_INIT_BL = SYS_MEM_ERROR_OFFSET + 0x01; // Fail to start system memory BL |
const BYTE UNREOGNIZED_DEVICE = SYS_MEM_ERROR_OFFSET + 0x02; // Unreconized device |
const BYTE CMD_NOT_ALLOWED = SYS_MEM_ERROR_OFFSET + 0x03; // Command not allowed |
const BYTE CMD_FAIL = SYS_MEM_ERROR_OFFSET + 0x04; // command failed |
const BYTE PROGRAM_ERROR_OFFSET = ERROR_OFFSET + 0x20; |
const BYTE INPUT_PARAMS_ERROR = PROGRAM_ERROR_OFFSET + 0x01; |
const BYTE INPUT_PARAMS_MEMORY_ALLOCATION_ERROR = PROGRAM_ERROR_OFFSET + 0x02; |
const BYTE LIB_LOADING_ERROR = PROGRAM_ERROR_OFFSET + 0x03; |
enum ACKS {UNDEFINED=0x00, ST75=0x75, ST79=0x79}; |
enum INTERFACE_TYPE {UART, CAN}; |
enum EBaudRate { brCustom,br110, br300, br600, br1200, br2400, br4800, br9600, br14400, br19200, br38400, |
br56000, br57600, br115200, br128000, br256000 };// Port Numbers ( custom or COM1..COM16 } |
enum EPortNumber { pnCustom,pnCOM1, pnCOM2, pnCOM3, pnCOM4, pnCOM5, pnCOM6, pnCOM7,pnCOM8, pnCOM9, pnCOM10, |
pnCOM11, pnCOM12, pnCOM13,pnCOM14, pnCOM15, pnCOM16 };// Data bits ( 5, 6, 7, 8 } |
enum EDataBits { db5BITS, db6BITS, db7BITS, db8BITS }; |
// Stop bits ( 1, 1.5, 2 } |
enum EStopBits { sb1BITS, sb1HALFBITS, sb2BITS }; |
// Parity ( None, odd, even, mark, space } |
enum EParity { ptNONE, ptODD, ptEVEN, ptMARK, ptSPACE }; |
// Hardware Flow Control ( None, None + RTS always on, RTS/CTS } |
enum EHwFlowControl { hfNONE, hfNONERTSON, hfRTSCTS }; |
// Software Flow Control ( None, XON/XOFF } |
enum ESwFlowControl { sfNONE, sfXONXOFF }; |
// What to do with incomplete (incoming} packets ( Discard, Pass } |
enum EPacketMode { pmDiscard, pmPass }; |
enum OPERATION {NONE, ERASE, UPLOAD, DNLOAD, DIS_R_PROT, DIS_W_PROT, ENA_R_PROT, ENA_W_PROT}; |
typedef struct RESULT |
{ |
OPERATION operation; |
char* filename; |
HANDLE Image; |
}* LPRESULT; |
typedef struct Commands |
{ |
BOOL GET_CMD ; //Get the version and the allowed commands supported by the current version of the boot loader |
BOOL GET_VER_ROPS_CMD ; //Get the BL version and the Read Protection status of the NVM |
BOOL GET_ID_CMD ; //Get the chip ID |
BOOL SET_SPEED_CMD ; //Change the CAN baudrate |
BOOL READ_CMD ; //Read up to 256 bytes of memory starting from an address specified by the user |
BOOL GO_CMD ; //Jump to an address specified by the user to execute (a loaded) code |
BOOL WRITE_CMD ; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
BOOL ERASE_CMD ; //Erase from one to all the NVM sectors |
BOOL ERASE_EXT_CMD ; //Erase from one to all the NVM sectors |
BOOL WRITE_PROTECT_CMD ; //Enable the write protection in a permanent way for some sectors |
BOOL WRITE_TEMP_UNPROTECT_CMD ; //Disable the write protection in a temporary way for all NVM sectors |
BOOL WRITE_PERM_UNPROTECT_CMD ; //Disable the write protection in a permanent way for all NVM sectors |
BOOL READOUT_PROTECT_CMD ; //Enable the readout protection in a permanent way |
BOOL READOUT_TEMP_UNPROTECT_CMD ; //Disable the readout protection in a temporary way |
BOOL READOUT_PERM_UNPROTECT_CMD ; //Disable the readout protection in a permanent way |
}* LPCommands; |
typedef struct TARGET_DESCRIPTOR |
{ |
BYTE Version ; |
BYTE CmdCount ; |
BYTE PIDLen ; |
BYTE* PID ; |
BYTE ROPE ; |
BYTE ROPD ; |
BOOL GET_CMD ; //Get the version and the allowed commands supported by the current version of the boot loader |
BOOL GET_VER_ROPS_CMD ; //Get the BL version and the Read Protection status of the NVM |
BOOL GET_ID_CMD ; //Get the chip ID |
BOOL SET_SPEED_CMD ; |
BOOL READ_CMD ; //Read up to 256 bytes of memory starting from an address specified by the user |
BOOL GO_CMD ; //Jump to an address specified by the user to execute (a loaded) code |
BOOL WRITE_CMD ; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
BOOL ERASE_CMD ; //Erase from one to all the NVM sectors |
BOOL ERASE_EXT_CMD ; //Erase from one to all the NVM sectors |
BOOL WRITE_PROTECT_CMD ; //Enable the write protection in a permanent way for some sectors |
BOOL WRITE_TEMP_UNPROTECT_CMD ; //Disable the write protection in a temporary way for all NVM sectors |
BOOL WRITE_PERM_UNPROTECT_CMD ; //Disable the write protection in a permanent way for all NVM sectors |
BOOL READOUT_PERM_PROTECT_CMD ; //Enable the readout protection in a permanent way |
BOOL READOUT_TEMP_UNPROTECT_CMD ; //Disable the readout protection in a temporary way |
BOOL READOUT_PERM_UNPROTECT_CMD ; //Disable the readout protection in a permanent way |
}* LPTARGET_DESCRIPTOR; |
typedef struct STBL_Request |
{ |
BYTE _cmd; |
DWORD _address; |
WORD _length; |
BYTE _nbSectors; |
LPTARGET_DESCRIPTOR _target; |
LPBYTE _data; |
WORD _wbSectors; |
}* LPSTBL_Request; |
extern "C" |
{ |
/************************************************************************************/ |
/* GET PROGRESS STATE |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE GetProgress(LPBYTE progress); |
/************************************************************************************/ |
/* GET ACTIVITY TIME |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE GetActivityTime(LPDWORD time); |
/************************************************************************************/ |
/* SET ACTIVITY TIME |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE SetActivityTime(DWORD time); |
/************************************************************************************/ |
/* SET COMMUNICATION INTERFACE TYPE |
/* UART - CAN - ... |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_SetComIntType(BYTE com_int_type); |
/************************************************************************************/ |
/* GetFlashSize |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetFlashSize(DWORD Addr, LPWORD val); |
/************************************************************************************/ |
/* GetMemoryAddress |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetMemoryAddress(DWORD Addr, LPBYTE val); |
/************************************************************************************/ |
/* GetRDPOptionByte |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetRDPOptionByte(LPBYTE RDP); |
/************************************************************************************/ |
/* GetWRPOptionBytes |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetWRPOptionBytes(LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3); |
/************************************************************************************/ |
/* Basic function to send a request |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE Send_RQ(LPSTBL_Request pRQ); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE SetCOMSettings(int numPort, long speedInBaud, int nbBit, |
int parity, float nbStopBit); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
/*STBLLIB_API BYTE ESetCOMSettings(EPortNumber numPort, EBaudRate speedInBaud, EDataBits nbBit, |
EParity parity, EStopBits nbStopBit);*/ |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE COM_Open(); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE COM_Close(); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_SetSpeed(DWORD speed); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_Init_BL(); |
/************************************************************************************/ |
/* 0x00; //Get the version and the allowed commands supported by the current version of the boot loader |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_GET(LPBYTE Version, LPCommands pCmds); |
/************************************************************************************/ |
/* 0x01; //Get the BL version and the Read Protection status of the NVM |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_GET_VER_ROPS(LPBYTE Version, LPBYTE ROPEnabled, LPBYTE ROPDisabled); |
/************************************************************************************/ |
/* 0x02; //Get the chip ID |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_GET_ID(LPBYTE size, LPBYTE pID); |
/************************************************************************************/ |
/* 0x11; //Read up to 256 bytes of memory starting from an address specified by the user |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_READ(DWORD Address, BYTE Size, LPBYTE pData); |
/************************************************************************************/ |
/* 0x21; //Jump to an address specified by the user to execute (a loaded) code |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_GO(DWORD Address); |
/************************************************************************************/ |
/* 0x31; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_WRITE(DWORD address, BYTE size, LPBYTE pData); |
/************************************************************************************/ |
/* 0x43; //Erase from one to all the NVM sectors |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_ERASE(WORD NbSectors, LPBYTE pSectors); |
/************************************************************************************/ |
/* 0x63; //Enable the write protection in a permanent way for some sectors |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_WRITE_PROTECT(BYTE NbSectors, LPBYTE pSectors); |
/************************************************************************************/ |
/* 0x71; //Disable the write protection in a temporary way for all NVM sectors |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_WRITE_TEMP_UNPROTECT(); |
/************************************************************************************/ |
/* 0x73; //Disable the write protection in a permanent way for all NVM sectors |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_WRITE_PERM_UNPROTECT(); |
/************************************************************************************/ |
/* 0x82; //Enable the readout protection in a permanent way |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_READOUT_PROTECT(); |
/************************************************************************************/ |
/* 0x91; //Disable the readout protection in a temporary way |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_READOUT_TEMP_UNPROTECT(); |
/************************************************************************************/ |
/* 0x92; //Disable the readout protection in a permanent way |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_READOUT_PERM_UNPROTECT(); |
/************************************************************************************/ |
/* UPLOAD |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_UPLOAD(DWORD Address, LPBYTE pData, DWORD Length); |
/************************************************************************************/ |
/* VERIFY |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_VERIFY(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad); |
/************************************************************************************/ |
/* DNLOAD |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_DNLOAD(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad); |
/************************************************************************************/ |
/* SET PACKET SIZE |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE SetPaketSize(BYTE WORD); |
/************************************************************************************/ |
/* GET PACKET SIZE |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE GetPaketSize(LPBYTE size); |
/************************************************************************************/ |
/* GetAckValue |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API ACKS GetAckValue(); |
/************************************************************************************/ |
/* IsConnected |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BOOL COM_is_Open(); |
/************************************************************************************/ |
/* SetTimeOut |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE SetTimeOut(DWORD vms); |
/************************************************************************************/ |
/* GetUserOptionByte |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetUserOptionByte(LPBYTE User); |
/************************************************************************************/ |
/* GetDataOptionByte |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetDataOptionByte(LPBYTE Data0, LPBYTE Data1); |
/************************************************************************************/ |
/* SetSIFData |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_SetSIFData(BYTE User, BYTE RDP, BYTE Data0, BYTE Data1, |
BYTE WRP0, BYTE WRP1, BYTE WRP2, BYTE WRP3); |
/************************************************************************************/ |
/* GetSIFData |
/* |
/* |
/************************************************************************************/ |
STBLLIB_API BYTE TARGET_GetSIFData(LPBYTE User, LPBYTE RDP, LPBYTE Data0, LPBYTE Data1, |
LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3); |
/************************************************************************************/ |
/* Set Rts Line State |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_SetRts(BOOL Val); |
/************************************************************************************/ |
/* Set Dtr Line State |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_SetDtr(BOOL Val); |
/************************************************************************************/ |
/* Set the state of TXD. Return: true if success. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_setTxd(BOOL val); |
/************************************************************************************/ |
/* Return: The state of CTS. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_getCts(BOOL* pval); |
/************************************************************************************/ |
/* Return: The state of DTR. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_getDtr(BOOL* pval); |
/************************************************************************************/ |
/* Return: The state of RI. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_getRi(BOOL* pval); |
/************************************************************************************/ |
/* Return: The state of DTR. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_getCd(BOOL* pval); |
/************************************************************************************/ |
/* Set Echo back Mode |
/* 0 = Echo Disabled |
/* 1 = Echo Back Enabled |
/* 2 = Listen Echo Enabled |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_SetEcho(int val); |
/************************************************************************************/ |
/* SetFlowControl : Enable/Disable Flow Control of DTR and RTS |
/* FALSE = Disabled |
/* TRUE = Enabled |
/************************************************************************************/ |
STBLLIB_API BYTE STBL_SetFlowControl(bool val); |
} |
#endif |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE******/ |
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VS_VERSION_INFO VERSIONINFO |
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<Link> |
<SuppressStartupBanner>true</SuppressStartupBanner> |
<LinkDLL>true</LinkDLL> |
<GenerateDebugInformation>true</GenerateDebugInformation> |
<SubSystem>Console</SubSystem> |
<OutputFile>..\BIN\Debug\STBLLIB.dll</OutputFile> |
<ImportLibrary>.\Debug\STBLLIB.lib</ImportLibrary> |
</Link> |
</ItemDefinitionGroup> |
<ItemGroup> |
<ClCompile Include="..\Crs232\rs232.cpp" /> |
<ClCompile Include="STBLLIB.cpp" /> |
</ItemGroup> |
<ItemGroup> |
<ResourceCompile Include="STBLLIB.rc" /> |
</ItemGroup> |
<ItemGroup> |
<ClInclude Include="..\Crs232\rs232.h" /> |
<ClInclude Include="STBLLIB.h" /> |
<ClInclude Include="StdAfx.h" /> |
</ItemGroup> |
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" /> |
<ImportGroup Label="ExtensionTargets"> |
</ImportGroup> |
</Project> |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STBLLIB/STBLLIB.vcxproj.filters |
---|
0,0 → 1,41 |
<?xml version="1.0" encoding="utf-8"?> |
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003"> |
<ItemGroup> |
<Filter Include="Source Files"> |
<UniqueIdentifier>{f02c9ef7-81f7-4a3c-bba5-cbd8a7793ff7}</UniqueIdentifier> |
<Extensions>cpp;c;cxx;rc;def;r;odl;idl;hpj;bat</Extensions> |
</Filter> |
<Filter Include="Header Files"> |
<UniqueIdentifier>{5fa88289-9f8f-49f7-a8e6-bd8c704b257d}</UniqueIdentifier> |
<Extensions>h;hpp;hxx;hm;inl</Extensions> |
</Filter> |
<Filter Include="Resource Files"> |
<UniqueIdentifier>{2186d3c8-01e7-4b41-9322-45da004618c8}</UniqueIdentifier> |
<Extensions>ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe</Extensions> |
</Filter> |
</ItemGroup> |
<ItemGroup> |
<ClCompile Include="..\Crs232\rs232.cpp"> |
<Filter>Source Files</Filter> |
</ClCompile> |
<ClCompile Include="STBLLIB.cpp"> |
<Filter>Source Files</Filter> |
</ClCompile> |
</ItemGroup> |
<ItemGroup> |
<ResourceCompile Include="STBLLIB.rc"> |
<Filter>Source Files</Filter> |
</ResourceCompile> |
</ItemGroup> |
<ItemGroup> |
<ClInclude Include="..\Crs232\rs232.h"> |
<Filter>Header Files</Filter> |
</ClInclude> |
<ClInclude Include="STBLLIB.h"> |
<Filter>Header Files</Filter> |
</ClInclude> |
<ClInclude Include="StdAfx.h"> |
<Filter>Header Files</Filter> |
</ClInclude> |
</ItemGroup> |
</Project> |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STBLLIB/STBLLIB.vcxproj.user |
---|
0,0 → 1,3 |
<?xml version="1.0" encoding="utf-8"?> |
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003"> |
</Project> |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STBLLIB/StdAfx.cpp |
---|
0,0 → 1,10 |
// stdafx.cpp : source file that includes just the standard includes |
// STBLLIB.pch will be the pre-compiled header |
// stdafx.obj will contain the pre-compiled type information |
#include "stdafx.h" |
// TODO: reference any additional headers you need in STDAFX.H |
// and not in this file |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STBLLIB/StdAfx.h |
---|
0,0 → 1,23 |
#if !defined(AFX_STDAFX_H__5756AFC7_1A09_4C0E_B6E8_BA86A975A687__INCLUDED_) |
#define AFX_STDAFX_H__5756AFC7_1A09_4C0E_B6E8_BA86A975A687__INCLUDED_ |
#if _MSC_VER > 1000 |
#pragma once |
#endif // _MSC_VER > 1000 |
// Insert your headers here |
#define WIN32_LEAN_AND_MEAN // Exclude rarely-used stuff from Windows headers |
#include <windows.h> |
//#include "../Files/Files.h" |
// TODO: reference additional headers your program requires here |
//{{AFX_INSERT_LOCATION}} |
// Microsoft Visual C++ will insert additional declarations immediately before the previous line. |
#endif // !defined(AFX_STDAFX_H__5756AFC7_1A09_4C0E_B6E8_BA86A975A687__INCLUDED_) |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STBLLIB/resource.h |
---|
0,0 → 1,15 |
//{{NO_DEPENDENCIES}} |
// Microsoft Developer Studio generated include file. |
// Used by STBLLIB.rc |
// |
// Next default values for new objects |
// |
#ifdef APSTUDIO_INVOKED |
#ifndef APSTUDIO_READONLY_SYMBOLS |
#define _APS_NEXT_RESOURCE_VALUE 101 |
#define _APS_NEXT_COMMAND_VALUE 40001 |
#define _APS_NEXT_CONTROL_VALUE 1000 |
#define _APS_NEXT_SYMED_VALUE 101 |
#endif |
#endif |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/Ini.cpp |
---|
0,0 → 1,1064 |
///////////////////////////////////////////////////////////////////////////////// |
// Cini Class Implementation |
///////////////////////////////////////////////////////////////////////////////// |
#include "stdafx.h" // include if you got "fatal error C1010: unexpected end of file..." |
#include "Ini.h" |
#include <string.h> |
#include <stdio.h> |
#include <assert.h> |
#define DEF_PROFILE_NUM_LEN 64 // numeric string length, could be quite long for binary format |
#define DEF_PROFILE_THRESHOLD 512 // temporary string length |
#define DEF_PROFILE_DELIMITER _T(",") // default string delimiter |
#define DEF_PROFILE_TESTSTRING _T("{63788286-AE30-4D6B-95DF-3B451C1C79F9}") // Uuid for internal use |
// struct used to be passed to __KeyPairProc as a LPVOID parameter |
struct STR_LIMIT |
{ |
LPTSTR lpTarget; |
DWORD dwRemain; |
DWORD dwTotalCopied; |
}; |
///////////////////////////////////////////////////////////////////////////////// |
// Constructors & Destructor |
///////////////////////////////////////////////////////////////////////////////// |
CIni::CIni() |
{ |
m_pszPathName = NULL; |
} |
CIni::CIni(LPCTSTR lpPathName) |
{ |
m_pszPathName = NULL; |
SetPathName(lpPathName); |
} |
CIni::~CIni() |
{ |
if (m_pszPathName != NULL) |
delete [] m_pszPathName; |
} |
///////////////////////////////////////////////////////////////////////////////// |
// Ini File Path Access |
///////////////////////////////////////////////////////////////////////////////// |
// Assign ini file path name |
void CIni::SetPathName(LPCTSTR lpPathName) |
{ |
if (lpPathName == NULL) |
{ |
if (m_pszPathName != NULL) |
*m_pszPathName = _T('\0'); |
} |
else |
{ |
if (m_pszPathName != NULL) |
delete [] m_pszPathName; |
m_pszPathName = _tcsdup(lpPathName); |
} |
} |
// Retrieve ini file path name |
DWORD CIni::GetPathName(LPTSTR lpBuffer, DWORD dwBufSize) const |
{ |
*lpBuffer = _T('\0'); |
DWORD dwLen = 0; |
if (lpBuffer != NULL) |
{ |
_tcsncpy(lpBuffer, m_pszPathName, dwBufSize); |
dwLen = _tcslen(lpBuffer); |
} |
else |
{ |
// just calculate the required buffer size |
dwLen = _tcslen(m_pszPathName); |
} |
return dwLen; |
} |
#ifdef __AFXWIN_H__ |
CString CIni::GetPathName() const |
{ |
return CString(m_pszPathName); |
} |
#endif |
///////////////////////////////////////////////////////////////////////////////// |
// Raw String Access |
///////////////////////////////////////////////////////////////////////////////// |
// Get a profile string value, if the buffer size is not large enough, the result |
// may be truncated. |
DWORD CIni::GetString(LPCTSTR lpSection, LPCTSTR lpKey, LPTSTR lpBuffer, DWORD dwBufSize, LPCTSTR lpDefault) const |
{ |
if (lpBuffer != NULL) |
*lpBuffer = _T('\0'); |
LPTSTR psz = __GetStringDynamic(lpSection, lpKey, lpDefault); |
DWORD dwLen = _tcslen(psz); |
if (lpBuffer != NULL) |
{ |
_tcsncpy(lpBuffer, psz, dwBufSize); |
dwLen = min(dwLen, dwBufSize); |
} |
delete [] psz; |
return dwLen; |
} |
#ifdef __AFXWIN_H__ |
CString CIni::GetString(LPCTSTR lpSection, LPCTSTR lpKey, LPCTSTR lpDefault) const |
{ |
LPTSTR psz = __GetStringDynamic(lpSection, lpKey, lpDefault); |
CString str(psz); |
delete [] psz; |
return str; |
} |
#endif |
// Write a string value to the ini file |
BOOL CIni::WriteString(LPCTSTR lpSection, LPCTSTR lpKey, LPCTSTR lpValue) const |
{ |
if (lpSection == NULL || lpKey == NULL) |
return FALSE; |
return ::WritePrivateProfileString(lpSection, lpKey, lpValue == NULL ? _T("") : lpValue, m_pszPathName); |
} |
// Read a string value from the ini file, append another string after it and then write it |
// back to the ini file |
BOOL CIni::AppendString(LPCTSTR lpSection, LPCTSTR lpKey, LPCTSTR lpString) const |
{ |
if (lpString == NULL) |
return FALSE; |
TCHAR* psz = __GetStringDynamic(lpSection, lpKey); |
TCHAR* pNewString = new TCHAR[_tcslen(psz) + _tcslen(lpString) + 1]; |
_stprintf(pNewString, _T("%s%s"), psz, lpString); |
const BOOL RES = WriteString(lpSection, lpKey, pNewString); |
delete [] pNewString; |
delete [] psz; |
return RES; |
} |
///////////////////////////////////////////////////////////////////////////////// |
// Ini File String Array Access |
///////////////////////////////////////////////////////////////////////////////// |
// Get an array of string |
DWORD CIni::GetArray(LPCTSTR lpSection, LPCTSTR lpKey, LPTSTR lpBuffer, DWORD dwBufSize, LPCTSTR lpDelimiter, BOOL bTrimString) const |
{ |
if (lpBuffer != NULL) |
*lpBuffer = _T('\0'); |
if (lpSection == NULL || lpKey == NULL) |
return 0; |
LPTSTR psz = __GetStringDynamic(lpSection, lpKey); |
DWORD dwCopied = 0; |
if (*psz != _T('\0')) |
{ |
if (lpBuffer == NULL) |
{ |
// just calculate the required buffer size |
const DWORD MAX_LEN = _tcslen(psz) + 2; |
LPTSTR p = new TCHAR[MAX_LEN + 1]; |
dwCopied = __StringSplit(psz, p, MAX_LEN, lpDelimiter, bTrimString); |
delete [] p; |
} |
else |
{ |
dwCopied = __StringSplit(psz, lpBuffer, dwBufSize, lpDelimiter, bTrimString); |
} |
} |
delete [] psz; |
return dwCopied; |
} |
#ifdef __AFXWIN_H__ |
void CIni::GetArray(LPCTSTR lpSection, LPCTSTR lpKey, CStringArray *pArray, LPCTSTR lpDelimiter, BOOL bTrimString) const |
{ |
if (pArray != NULL) |
pArray->RemoveAll(); |
const DWORD LEN = GetArray(lpSection, lpKey, NULL, 0, lpDelimiter); |
if (LEN == 0) |
return; |
LPTSTR psz = new TCHAR[LEN + 3]; |
GetArray(lpSection, lpKey, psz, LEN + 2, lpDelimiter); |
ParseDNTString(psz, __SubStrAdd, (LPVOID)pArray); |
delete [] psz; |
} |
#endif |
#ifdef __AFXWIN_H__ |
BOOL CIni::WriteArray(LPCTSTR lpSection, LPCTSTR lpKey, const CStringArray *pArray, int nWriteCount, LPCTSTR lpDelimiter) const |
{ |
if (pArray == NULL) |
return FALSE; |
if (nWriteCount < 0) |
nWriteCount = pArray->GetSize(); |
else |
nWriteCount = min(nWriteCount, pArray->GetSize()); |
const CString DELIMITER = (lpDelimiter == NULL || *lpDelimiter == _T('\0')) ? _T(",") : lpDelimiter; |
CString sLine; |
for (int i = 0; i < nWriteCount; i++) |
{ |
sLine += pArray->GetAt(i); |
if (i != nWriteCount - 1) |
sLine += DELIMITER; |
} |
return WriteString(lpSection, lpKey, sLine); |
} |
#endif |
///////////////////////////////////////////////////////////////////////////////// |
// Primitive Data Type Access |
///////////////////////////////////////////////////////////////////////////////// |
// Get a signed integral value |
int CIni::GetInt(LPCTSTR lpSection, LPCTSTR lpKey, int nDefault, int nBase) const |
{ |
TCHAR sz[DEF_PROFILE_NUM_LEN + 1] = _T(""); |
GetString(lpSection, lpKey, sz, DEF_PROFILE_NUM_LEN); |
return *sz == _T('\0') ? nDefault : int(_tcstoul(sz, NULL, __ValidateBase(nBase))); |
} |
// Get an unsigned integral value |
UINT CIni::GetUInt(LPCTSTR lpSection, LPCTSTR lpKey, UINT nDefault, int nBase) const |
{ |
TCHAR sz[DEF_PROFILE_NUM_LEN + 1] = _T(""); |
GetString(lpSection, lpKey, sz, DEF_PROFILE_NUM_LEN); |
return *sz == _T('\0') ? nDefault : UINT(_tcstoul(sz, NULL, __ValidateBase(nBase))); |
} |
// Get a boolean value |
BOOL CIni::GetBool(LPCTSTR lpSection, LPCTSTR lpKey, BOOL bDefault) const |
{ |
TCHAR sz[DEF_PROFILE_NUM_LEN + 1] = _T(""); |
GetString(lpSection, lpKey, sz, DEF_PROFILE_NUM_LEN); |
return StringToBool(sz, bDefault); |
} |
// Get a double floating value |
double CIni::GetDouble(LPCTSTR lpSection, LPCTSTR lpKey, double fDefault) const |
{ |
TCHAR sz[DEF_PROFILE_NUM_LEN + 1] = _T(""); |
GetString(lpSection, lpKey, sz, DEF_PROFILE_NUM_LEN); |
return *sz == _T('\0') ? fDefault : _tcstod(sz, NULL); |
} |
// Write a signed integral value to the ini file |
BOOL CIni::WriteInt(LPCTSTR lpSection, LPCTSTR lpKey, int nValue, int nBase) const |
{ |
TCHAR szValue[DEF_PROFILE_NUM_LEN + 1] = _T(""); |
__IntToString(nValue, szValue, nBase); |
return WriteString(lpSection, lpKey, szValue); |
} |
// Write an unsigned value to the ini file |
BOOL CIni::WriteUInt(LPCTSTR lpSection, LPCTSTR lpKey, UINT nValue, int nBase) const |
{ |
TCHAR szValue[DEF_PROFILE_NUM_LEN + 1] = _T(""); |
__UIntToString(nValue, szValue, nBase); |
return WriteString(lpSection, lpKey, szValue); |
} |
// Write a double floating value to the ini file |
BOOL CIni::WriteDouble(LPCTSTR lpSection, LPCTSTR lpKey, double fValue, int nPrecision) const |
{ |
TCHAR szFmt[16] = _T("%f"); |
if (nPrecision > 0) |
_stprintf(szFmt, _T("%%.%df"), nPrecision); |
TCHAR szValue[DEF_PROFILE_NUM_LEN + 1] = _T(""); |
_stprintf(szValue, szFmt, fValue); |
return WriteString(lpSection, lpKey, szValue); |
} |
// Read a double value from the ini file, increase it then write it back |
BOOL CIni::IncreaseDouble(LPCTSTR lpSection, LPCTSTR lpKey, double fIncrease, int nPrecision) const |
{ |
double f = GetDouble(lpSection, lpKey, 0.0); |
f += fIncrease; |
return WriteDouble(lpSection, lpKey, f, nPrecision); |
} |
// Write a boolean value to the ini file |
BOOL CIni::WriteBool(LPCTSTR lpSection, LPCTSTR lpKey, BOOL bValue) const |
{ |
return WriteInt(lpSection, lpKey, bValue ? 1 : 0, BASE_DECIMAL); |
} |
// Read a boolean value from the ini file, invert it(true becomes false, false becomes true), |
// then write it back |
BOOL CIni::InvertBool(LPCTSTR lpSection, LPCTSTR lpKey) const |
{ |
return WriteBool(lpSection, lpKey, !GetBool(lpSection, lpKey, FALSE)); |
} |
// Read a int from the ini file, increase it and then write it back to the ini file |
BOOL CIni::IncreaseInt(LPCTSTR lpSection, LPCTSTR lpKey, int nIncrease, int nBase) const |
{ |
int nVal = GetInt(lpSection, lpKey, 0, nBase); |
nVal += nIncrease; |
return WriteInt(lpSection, lpKey, nVal, nBase); |
} |
// Read an UINT from the ini file, increase it and then write it back to the ini file |
BOOL CIni::IncreaseUInt(LPCTSTR lpSection, LPCTSTR lpKey, UINT nIncrease, int nBase) const |
{ |
UINT nVal = GetUInt(lpSection, lpKey, 0, nBase); |
nVal += nIncrease; |
return WriteUInt(lpSection, lpKey, nVal, nBase); |
} |
TCHAR CIni::GetChar(LPCTSTR lpSection, LPCTSTR lpKey, TCHAR cDefault) const |
{ |
TCHAR sz[2] = _T(""); |
GetString(lpSection, lpKey, sz, 1); |
return *sz == _T('\0') ? cDefault : sz[0]; |
} |
BOOL CIni::WriteChar(LPCTSTR lpSection, LPCTSTR lpKey, TCHAR c) const |
{ |
TCHAR sz[2] = { c, _T('\0') }; |
return WriteString(lpSection, lpKey, sz); |
} |
///////////////////////////////////////////////////////////////////////////////// |
// User-Defined Data Type Access |
///////////////////////////////////////////////////////////////////////////////// |
// Get a block of raw data from the ini file |
DWORD CIni::GetDataBlock(LPCTSTR lpSection, LPCTSTR lpKey, LPVOID lpBuffer, DWORD dwBufSize, DWORD dwOffset) const |
{ |
LPTSTR psz = __GetStringDynamic(lpSection, lpKey); |
DWORD dwLen = _tcslen(psz) / 2; |
if (dwLen <= dwOffset) |
{ |
delete [] psz; |
return 0; |
} |
// verify psz, must be all in hex format |
for (int i = 0; psz[i] != _T('\0'); i++) |
{ |
TCHAR c = psz[i]; |
if ((c >= _T('0') && c <= _T('9')) |
|| (c >= _T('a') && c <= _T('f')) |
|| (c >= _T('A') && c <= _T('F'))) |
{ |
// valid |
} |
else |
{ |
delete [] psz; |
return 0; |
} |
} |
DWORD dwProcLen = 0; |
LPBYTE lpb = (LPBYTE)lpBuffer; |
if (lpb != NULL) |
{ |
dwProcLen = min(dwLen - dwOffset, dwBufSize); |
LPCTSTR p = &psz[dwOffset * 2]; |
for (DWORD i = 0; i < dwProcLen; i++) |
{ |
TCHAR sz[3] = _T(""); |
_tcsncpy(sz, p, 2); |
lpb[i] = BYTE(_tcstoul(sz, NULL, 16)); |
p = &p[2]; |
} |
} |
else |
{ |
dwProcLen = dwLen - dwOffset; |
} |
delete [] psz; |
return dwProcLen; |
} |
// Write a block of raw data to the ini file |
BOOL CIni::WriteDataBlock(LPCTSTR lpSection, LPCTSTR lpKey, LPCVOID lpData, DWORD dwDataSize) const |
{ |
const BYTE* lpb = (const BYTE*)lpData; |
if (lpb == NULL) |
return FALSE; |
LPTSTR psz = new TCHAR[dwDataSize * 2 + 1]; |
for (DWORD i = 0, j = 0; i < dwDataSize; i++, j += 2) |
_stprintf(&psz[j], _T("%02X"), lpb[i]); |
const BOOL RES = WriteString(lpSection, lpKey, psz); |
delete [] psz; |
return RES; |
} |
// Append a block of raw data to a specified key in the ini file |
BOOL CIni::AppendDataBlock(LPCTSTR lpSection, LPCTSTR lpKey, LPCVOID lpData, DWORD dwDataSize) const |
{ |
const BYTE* lpb = (const BYTE*)lpData; |
if (lpb == NULL) |
return FALSE; |
LPTSTR psz = new TCHAR[dwDataSize * 2 + 1]; |
for (DWORD i = 0, j = 0; i < dwDataSize; i++, j += 2) |
_stprintf(&psz[j], _T("%02X"), lpb[i]); |
const BOOL RES = AppendString(lpSection, lpKey, psz); |
delete [] psz; |
return RES; |
} |
// Get a POINT value |
POINT CIni::GetPoint(LPCTSTR lpSection, LPCTSTR lpKey, POINT ptDefault) const |
{ |
POINT pt; |
if (GetDataBlock(lpSection, lpKey, &pt, sizeof(POINT)) != sizeof(POINT)) |
pt = ptDefault; |
return pt; |
} |
// Get a RECT value |
RECT CIni::GetRect(LPCTSTR lpSection, LPCTSTR lpKey, RECT rcDefault) const |
{ |
RECT rc; |
if (GetDataBlock(lpSection, lpKey, &rc, sizeof(RECT)) != sizeof(RECT)) |
rc = rcDefault; |
return rc; |
} |
// Write a POINT to the ini file |
BOOL CIni::WritePoint(LPCTSTR lpSection, LPCTSTR lpKey, POINT pt) const |
{ |
return WriteDataBlock(lpSection, lpKey, &pt, sizeof(POINT)); |
} |
// Write a RECT to the ini file |
BOOL CIni::WriteRect(LPCTSTR lpSection, LPCTSTR lpKey, RECT rc) const |
{ |
return WriteDataBlock(lpSection, lpKey, &rc, sizeof(RECT)); |
} |
///////////////////////////////////////////////////////////////////////////////// |
// Sections & Keys Access |
///////////////////////////////////////////////////////////////////////////////// |
// Retrieve a list of key-lines(key-pairs) of the specified section |
DWORD CIni::GetKeyLines(LPCTSTR lpSection, LPTSTR lpBuffer, DWORD dwBufSize) const |
{ |
if (lpBuffer != NULL) |
*lpBuffer = _T('\0'); |
if (lpSection == NULL) |
return 0; |
if (lpBuffer == NULL) |
{ |
// just calculate the required buffer size |
DWORD dwLen = DEF_PROFILE_THRESHOLD; |
LPTSTR psz = new TCHAR[dwLen + 1]; |
DWORD dwCopied = ::GetPrivateProfileSection(lpSection, psz, dwLen, m_pszPathName); |
while (dwCopied + 2 >= dwLen) |
{ |
dwLen += DEF_PROFILE_THRESHOLD; |
delete [] psz; |
psz = new TCHAR[dwLen + 1]; |
dwCopied = ::GetPrivateProfileSection(lpSection, psz, dwLen, m_pszPathName); |
} |
delete [] psz; |
return dwCopied + 2; |
} |
else |
{ |
return ::GetPrivateProfileSection(lpSection, lpBuffer, dwBufSize, m_pszPathName); |
} |
} |
// Retrieve a list of key names of the specified section |
DWORD CIni::GetKeyNames(LPCTSTR lpSection, LPTSTR lpBuffer, DWORD dwBufSize) const |
{ |
if (lpBuffer != NULL) |
*lpBuffer = _T('\0'); |
if (lpSection == NULL) |
return 0; |
STR_LIMIT sl; |
sl.lpTarget = lpBuffer; |
sl.dwRemain = dwBufSize; |
sl.dwTotalCopied = 0; |
const DWORD LEN = GetKeyLines(lpSection, NULL, 0); |
if (LEN == 0) |
return 0; |
LPTSTR psz = new TCHAR[LEN + 1]; |
GetKeyLines(lpSection, psz, LEN); |
ParseDNTString(psz, __KeyPairProc, (LPVOID)(&sl)); |
delete [] psz; |
if (lpBuffer != NULL) |
lpBuffer[sl.dwTotalCopied] = _T('\0'); |
return sl.dwTotalCopied; |
} |
// Get all section names from an ini file |
DWORD CIni::GetSectionNames(LPTSTR lpBuffer, DWORD dwBufSize) const |
{ |
if (lpBuffer == NULL) |
{ |
// just calculate the required buffer size |
DWORD dwLen = DEF_PROFILE_THRESHOLD; |
LPTSTR psz = new TCHAR[dwLen + 1]; |
DWORD dwCopied = ::GetPrivateProfileSectionNames(psz, dwLen, m_pszPathName); |
while (dwCopied + 2 >= dwLen) |
{ |
dwLen += DEF_PROFILE_THRESHOLD; |
delete [] psz; |
psz = new TCHAR[dwLen + 1]; |
dwCopied = ::GetPrivateProfileSectionNames(psz, dwLen, m_pszPathName); |
} |
delete [] psz; |
return dwCopied + 2; |
} |
else |
{ |
return ::GetPrivateProfileSectionNames(lpBuffer, dwBufSize, m_pszPathName); |
} |
} |
#ifdef __AFXWIN_H__ |
void CIni::GetSectionNames(CStringArray *pArray) const |
{ |
if (pArray != NULL) |
pArray->RemoveAll(); |
const DWORD LEN = GetSectionNames(NULL, 0); |
if (LEN == 0) |
return; |
LPTSTR psz = new TCHAR[LEN + 1]; |
GetSectionNames(psz, LEN); |
ParseDNTString(psz, __SubStrAdd, pArray); |
delete [] psz; |
} |
#endif |
#ifdef __AFXWIN_H__ |
// Retrieve a list of key-lines(key-pairs) of the specified section |
void CIni::GetKeyLines(LPCTSTR lpSection, CStringArray *pArray) const |
{ |
if (pArray != NULL) |
pArray->RemoveAll(); |
const DWORD LEN = GetKeyLines(lpSection, NULL, 0); |
if (LEN == 0) |
return; |
LPTSTR psz = new TCHAR[LEN + 1]; |
GetKeyLines(lpSection, psz, LEN); |
ParseDNTString(psz, __SubStrAdd, pArray); |
delete [] psz; |
} |
#endif |
#ifdef __AFXWIN_H__ |
// Retrieve a list of key names of the specified section |
void CIni::GetKeyNames(LPCTSTR lpSection, CStringArray *pArray) const |
{ |
if (pArray == NULL) |
return; |
pArray->RemoveAll(); |
#ifndef _VS_USED |
const int LEN = GetKeyNames(lpSection, NULL, 0); |
#else |
const LEN = GetKeyNames(lpSection, NULL, 0); |
#endif |
LPTSTR psz = new TCHAR[LEN + 1]; |
GetKeyNames(lpSection, psz, LEN); |
ParseDNTString(psz, __SubStrAdd, (LPVOID)pArray); |
delete [] psz; |
} |
#endif |
// Remove whole section from the ini file |
BOOL CIni::DeleteSection(LPCTSTR lpSection) const |
{ |
return ::WritePrivateProfileString(lpSection, NULL, _T(""), m_pszPathName); |
} |
// Remove a key from a section |
BOOL CIni::DeleteKey(LPCTSTR lpSection, LPCTSTR lpKey) const |
{ |
return ::WritePrivateProfileString(lpSection, lpKey, NULL, m_pszPathName); |
} |
BOOL CIni::IsSectionExist(LPCTSTR lpSection) const |
{ |
if (lpSection == NULL) |
return FALSE; |
// first get the section name list, then check if lpSection exists |
// in the list. |
const DWORD LEN = GetSectionNames(NULL, 0); |
if (LEN == 0) |
return FALSE; |
LPTSTR psz = new TCHAR[LEN + 1]; |
GetSectionNames(psz, LEN); |
BOOL RES = !ParseDNTString(psz, __SubStrCompare, (LPVOID)lpSection); |
delete [] psz; |
return RES; |
} |
BOOL CIni::IsKeyExist(LPCTSTR lpSection, LPCTSTR lpKey) const |
{ |
if (lpSection == NULL || lpKey == NULL) |
return FALSE; |
// Test it with the default unique string |
LPTSTR psz = __GetStringDynamic(lpSection, lpKey, DEF_PROFILE_TESTSTRING); |
const BOOL RES = (_tcscmp(psz, DEF_PROFILE_TESTSTRING) != 0); |
delete [] psz; |
return RES; |
} |
BOOL CIni::CopySection(LPCTSTR lpSrcSection, LPCTSTR lpDestSection, BOOL bFailIfExist) const |
{ |
if (lpSrcSection == NULL || lpDestSection == NULL) |
return FALSE; |
if (_tcsicmp(lpSrcSection, lpDestSection) == 0) |
return FALSE; |
if (!IsSectionExist(lpSrcSection)) |
return FALSE; |
if (bFailIfExist && IsSectionExist(lpDestSection)) |
return FALSE; |
DeleteSection(lpDestSection); |
const DWORD SRC_LEN = GetKeyLines(lpSrcSection, NULL, 0); |
LPTSTR psz = new TCHAR[SRC_LEN + 2]; |
//memset(psz, 0, sizeof(TCHAR) * (SRC_LEN + 2)); |
GetKeyLines(lpSrcSection, psz, SRC_LEN); |
const BOOL RES = ::WritePrivateProfileSection(lpDestSection, psz, m_pszPathName); |
delete [] psz; |
return RES; |
} |
BOOL CIni::CopyKey(LPCTSTR lpSrcSection, LPCTSTR lpSrcKey, LPCTSTR lpDestSection, LPCTSTR lpDestKey, BOOL bFailIfExist) const |
{ |
if (lpSrcSection == NULL || lpSrcKey == NULL || lpDestKey == NULL) |
return FALSE; |
if (_tcsicmp(lpSrcSection, lpDestSection) == 0 |
&& _tcsicmp(lpSrcKey, lpDestKey) == 0) |
return FALSE; |
if (!IsKeyExist(lpSrcSection, lpSrcKey)) |
return FALSE; |
if (bFailIfExist && IsKeyExist(lpDestSection, lpDestKey)) |
return FALSE; |
LPTSTR psz = __GetStringDynamic(lpSrcSection, lpSrcKey); |
const BOOL RES = WriteString(lpDestSection, lpDestKey, psz); |
delete [] psz; |
return RES; |
} |
BOOL CIni::MoveSection(LPCTSTR lpSrcSection, LPCTSTR lpDestSection, BOOL bFailIfExist) const |
{ |
return CopySection(lpSrcSection, lpDestSection, bFailIfExist) |
&& DeleteSection(lpSrcSection); |
} |
BOOL CIni::MoveKey(LPCTSTR lpSrcSection, LPCTSTR lpSrcKey, LPCTSTR lpDestSection, LPCTSTR lpDestKey, BOOL bFailIfExist) const |
{ |
return CopyKey(lpSrcSection, lpSrcKey, lpDestSection, lpDestKey, bFailIfExist) |
&& DeleteKey(lpSrcSection, lpSrcKey); |
} |
///////////////////////////////////////////////////////////////////////////////// |
// Helper Functions |
///////////////////////////////////////////////////////////////////////////////// |
// Get a profile string value, return a heap pointer so we do not have to worry |
// about the buffer size, however, this function requires the caller to manually |
// free the memory. |
// This function is the back-bone of all "Getxxx" functions of this class. |
LPTSTR CIni::__GetStringDynamic(LPCTSTR lpSection, LPCTSTR lpKey, LPCTSTR lpDefault) const |
{ |
TCHAR* psz = NULL; |
if (lpSection == NULL || lpKey == NULL) |
{ |
// Invalid section or key name, just return the default string |
if (lpDefault == NULL) |
{ |
// Empty string |
psz = new TCHAR[1]; |
*psz = _T('\0'); |
} |
else |
{ |
psz = new TCHAR[_tcslen(lpDefault) + 1]; |
_tcscpy(psz, lpDefault); |
} |
return psz; |
} |
// Keep enlarging the buffer size until being certain on that the string we |
// retrieved was original(not truncated). |
DWORD dwLen = DEF_PROFILE_THRESHOLD; |
psz = new TCHAR[dwLen + 1]; |
DWORD dwCopied = ::GetPrivateProfileString(lpSection, lpKey, lpDefault == NULL ? _T("") : lpDefault, psz, dwLen, m_pszPathName); |
while (dwCopied + 1 >= dwLen) |
{ |
dwLen += DEF_PROFILE_THRESHOLD; |
delete [] psz; |
psz = new TCHAR[dwLen + 1]; |
dwCopied = ::GetPrivateProfileString(lpSection, lpKey, lpDefault == NULL ? _T("") : lpDefault, psz, dwLen, m_pszPathName); |
} |
return psz; // !!! Requires the caller to free this memory !!! |
} |
// Split a string usinf a particular delimiter, split result are copied into lpBuffer |
// in the "double null terminated string" format as the following figure shows: |
// xxx\0xxxx\0xx\0xxx\0\0 |
// |
// For example, if the delimiter is ",", then string "ab,cd,e" will be |
// splitted into "ab\0cd\0e\0\0", this string format can be parsed into an array |
// of sub strings easily using user defined functions or CIni::ParseStringArray. |
DWORD CIni::__StringSplit(LPCTSTR lpString, LPTSTR lpBuffer, DWORD dwBufSize, LPCTSTR lpDelimiter, BOOL bTrimString) |
{ |
if (lpString == NULL || lpBuffer == NULL || dwBufSize == 0) |
return 0; |
DWORD dwCopied = 0; |
*lpBuffer = _T('\0'); |
if (*lpString == _T('\0')) |
return 0; |
// If lpDelimiter is NULL, use the default delimiter ",", if delimiter length |
// is 0, then return whole string |
if (lpDelimiter != NULL && *lpDelimiter == _T('\0')) |
{ |
_tcsncpy(lpBuffer, lpString, dwBufSize - 1); |
return _tcslen(lpBuffer); |
} |
LPTSTR pszDel = (lpDelimiter == NULL) ? _tcsdup(DEF_PROFILE_DELIMITER) : _tcsdup(lpDelimiter); |
const DWORD DEL_LEN = _tcslen(pszDel); |
LPTSTR lpTarget = lpBuffer; |
// Search through lpString for delimiter matches, and extract sub strings out |
LPCTSTR lpPos = lpString; |
LPCTSTR lpEnd = _tcsstr(lpPos, pszDel); |
while (lpEnd != NULL) |
{ |
LPTSTR pszSeg = __StrDupEx(lpPos, lpEnd); |
if (bTrimString) |
__TrimString(pszSeg); |
const DWORD SEG_LEN = _tcslen(pszSeg); |
const DWORD COPY_LEN = min(SEG_LEN, dwBufSize - dwCopied); |
// Need to avoid buffer overflow |
if (COPY_LEN > 0) |
{ |
dwCopied += COPY_LEN + 1; |
_tcsncpy(lpTarget, pszSeg, COPY_LEN); |
lpTarget[COPY_LEN] = _T('\0'); |
lpTarget = &lpTarget[SEG_LEN + 1]; |
} |
delete [] pszSeg; |
lpPos = &lpEnd[DEL_LEN]; // Advance the pointer for next search |
lpEnd = _tcsstr(lpPos, pszDel); |
} |
// The last part of string, there may not be the trailing delimiter, so we |
// need to take care of this part, too |
LPTSTR pszSeg = _tcsdup(lpPos); |
if (bTrimString) |
__TrimString(pszSeg); |
const DWORD SEG_LEN = _tcslen(pszSeg); |
const DWORD COPY_LEN = min(SEG_LEN, dwBufSize - dwCopied); |
if (COPY_LEN > 0) |
{ |
dwCopied += COPY_LEN + 1; |
_tcsncpy(lpTarget, pszSeg, COPY_LEN); |
lpTarget[COPY_LEN] = _T('\0'); |
} |
delete [] pszSeg; |
lpBuffer[dwCopied] = _T('\0'); |
delete [] pszDel; |
return dwCopied; |
} |
// Parse a "double null terminated string", pass each sub string to a user-defined |
// callback function |
BOOL CIni::ParseDNTString(LPCTSTR lpString, SUBSTRPROC lpFnStrProc, LPVOID lpParam) |
{ |
if (lpString == NULL || lpFnStrProc == NULL) |
return FALSE; |
LPCTSTR p = lpString; |
DWORD dwLen = _tcslen(p); |
while (dwLen > 0) |
{ |
if (!lpFnStrProc(p, lpParam)) |
return FALSE; |
p = &p[dwLen + 1]; |
dwLen = _tcslen(p); |
} |
return TRUE; |
} |
// Callback function used to compare elements inside of a |
// "double null terminated string" with a given string. Useful for |
// searching in the section names list. |
BOOL CALLBACK CIni::__SubStrCompare(LPCTSTR lpString1, LPVOID lpParam) |
{ |
assert(lpString1 != NULL); |
LPCTSTR lpString2 = (LPCTSTR)lpParam; |
assert(lpString2 != NULL); |
// if two string matches, return zero to stop the parsing |
return _tcsicmp(lpString1, lpString2) != 0; |
} |
// Callback function used to process a key-pair, it extracts the |
// key name from the key-pair string |
BOOL CALLBACK CIni:: __KeyPairProc(LPCTSTR lpString, LPVOID lpParam) |
{ |
STR_LIMIT* psl = (STR_LIMIT*)lpParam; |
if (lpString == NULL || psl== NULL) |
return FALSE; |
LPCTSTR p = _tcschr(lpString, _T('=')); |
if (p == NULL || p == lpString) |
return TRUE; |
// extract the sub-string on left side of the '=' |
LPTSTR psz = new TCHAR[_tcslen(lpString) + 1]; |
#ifndef _VS6_USED |
int i; |
#endif |
for (int i = 0; &lpString[i] < p; i++) |
psz[i] = lpString[i]; |
psz[i] = _T('\0'); |
// trim |
__TrimString(psz); |
DWORD dwNameLen = _tcslen(psz); |
DWORD dwCopyLen = 0; |
//copy to the buffer |
if (psl->lpTarget != NULL) |
{ |
dwCopyLen = (psl->dwRemain > 1) ? min(dwNameLen, psl->dwRemain - 1) : 0; |
_tcsncpy(psl->lpTarget, psz, dwCopyLen); |
psl->lpTarget[dwCopyLen] = _T('\0'); |
psl->lpTarget = &(psl->lpTarget[dwCopyLen + 1]); |
psl->dwRemain -= dwCopyLen + 1; |
} |
else |
{ |
dwCopyLen = dwNameLen; |
} |
delete [] psz; |
psl->dwTotalCopied += dwCopyLen + 1; |
return TRUE; |
} |
#ifdef __AFXWIN_H__ |
// Callback function used to add elements that are extracted from a |
// "double null terminated string" to an MFC CStringArray. |
BOOL CALLBACK CIni::__SubStrAdd(LPCTSTR lpString, LPVOID lpParam) |
{ |
CStringArray* pArray = (CStringArray*)lpParam; |
if (pArray == NULL || lpString == NULL) |
return FALSE; |
pArray->Add(lpString); |
return TRUE; |
} |
#endif |
// Convert an integer into binary string format |
void CIni::__ToBinaryString(UINT nNumber, LPTSTR lpBuffer, DWORD dwBufSize) |
{ |
if (dwBufSize == 0) |
return; |
DWORD dwIndex = 0; |
do |
{ |
lpBuffer[dwIndex++] = (nNumber % 2) ? _T('1') : _T('0'); |
nNumber /= 2; |
} while (nNumber > 0 && dwIndex < dwBufSize); |
lpBuffer[dwIndex] = _T('\0'); |
_tcsrev(lpBuffer); |
} |
// Make sure the base will be expected value |
int CIni::__ValidateBase(int nBase) |
{ |
switch (nBase) |
{ |
case BASE_BINARY: |
case BASE_OCTAL: |
case BASE_HEXADECIMAL: |
break; |
default: |
nBase = BASE_DECIMAL; |
} |
return nBase; |
} |
// Convert a signed integer into string representation, based on its base |
void CIni::__IntToString(int nNumber, LPTSTR lpBuffer, int nBase) |
{ |
switch (nBase) |
{ |
case BASE_BINARY: |
case BASE_OCTAL: |
case BASE_HEXADECIMAL: |
__UIntToString((UINT)nNumber, lpBuffer, nBase); |
break; |
default: |
_stprintf(lpBuffer, _T("%d"), nNumber); |
break; |
} |
} |
// Convert an unsigned integer into string representation, based on its base |
void CIni::__UIntToString(UINT nNumber, LPTSTR lpBuffer, int nBase) |
{ |
switch (nBase) |
{ |
case BASE_BINARY: |
__ToBinaryString(nNumber, lpBuffer, DEF_PROFILE_NUM_LEN); |
break; |
case BASE_OCTAL: |
_stprintf(lpBuffer, _T("%o"), nNumber); |
break; |
case BASE_HEXADECIMAL: |
_stprintf(lpBuffer, _T("%X"), nNumber); |
break; |
default: |
_stprintf(lpBuffer, _T("%u"), nNumber); |
break; |
} |
} |
BOOL CIni::StringToBool(LPCTSTR lpString, BOOL bDefault) |
{ |
// Default: empty string |
// TRUE: "true", "yes", non-zero decimal numner |
// FALSE: all other cases |
if (lpString == NULL || *lpString == _T('\0')) |
return bDefault; |
return (_tcsicmp(lpString, _T("true")) == 0 |
|| _tcsicmp(lpString, _T("yes")) == 0 |
|| _tcstol(lpString, NULL, BASE_DECIMAL) != 0); |
} |
BOOL CIni::__TrimString(LPTSTR lpString) |
{ |
if (lpString == NULL) |
return FALSE; |
BOOL bTrimmed = FALSE; |
int nLen = _tcslen(lpString); |
// '\n' and '\r' are actually not possible in this case, but anyway... |
// Trim right side |
while (nLen >= 0 |
&& (lpString[nLen - 1] == _T(' ') |
|| lpString[nLen - 1] == _T('\t') |
|| lpString[nLen - 1] == _T('\r') |
|| lpString[nLen - 1] == _T('\n'))) |
{ |
lpString[--nLen] = _T('\0'); |
bTrimmed = TRUE; |
} |
// Trim left side |
LPCTSTR p = lpString; |
while (*p == _T(' ') |
|| *p == _T('\t') |
|| *p == _T('\r') |
|| *p == _T('\n')) |
{ |
p = &p[1]; |
bTrimmed = TRUE; |
} |
if (p != lpString) |
{ |
LPTSTR psz = _tcsdup(p); |
_tcscpy(lpString, psz); |
delete [] psz; |
} |
return bTrimmed; |
} |
LPTSTR CIni::__StrDupEx(LPCTSTR lpStart, LPCTSTR lpEnd) |
{ |
const DWORD LEN = ((DWORD)lpEnd - (DWORD)lpStart) / sizeof(TCHAR); |
LPTSTR psz = new TCHAR[LEN + 1]; |
_tcsncpy(psz, lpStart, LEN); |
psz[LEN] = _T('\0'); |
return psz; // !!! Requires the caller to free this memory !!! |
} |
///////////////////////////////////////////////////////////////////////////////// |
// End of Cini Class Implementation |
///////////////////////////////////////////////////////////////////////////////// |
// If you are getting this error: |
// ---------------------------------------------------------------------------- |
// "fatal error C1010: unexpected end of file while looking for precompiled |
// header directive" |
//----------------------------------------------------------------------------- |
// Please scroll all the way up and uncomment '#include "stdafx.h"' |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/Ini.h |
---|
0,0 → 1,169 |
#ifndef __INI_H__ |
#define __INI_H__ |
#include <windows.h> |
#include <tchar.h> |
// If MFC is linked, we will use CStringArray for great convenience |
#ifdef __AFXWIN_H__ |
#include <afxtempl.h> |
#endif |
// Number bases |
#define BASE_BINARY 2 |
#define BASE_OCTAL 8 |
#define BASE_DECIMAL 10 |
#define BASE_HEXADECIMAL 16 |
//--------------------------------------------------------------- |
// Callback Function Type Definition |
//--------------------------------------------------------------- |
// The callback function used for parsing a "double-null terminated string". |
// When called, the 1st parameter passed in will store the newly extracted sub |
// string, the 2nd parameter is a 32-bit user defined data, this parameter can |
// be NULL. The parsing will terminate if this function returns zero. To use |
// the callback, function pointer needs to be passed to "CIni::ParseDNTString". |
typedef BOOL (CALLBACK *SUBSTRPROC)(LPCTSTR, LPVOID); |
class CIni |
{ |
public: |
//----------------------------------------------------------- |
// Constructors & Destructor |
//----------------------------------------------------------- |
CIni(); // Default constructor |
CIni(LPCTSTR lpPathName); // Construct with a given file name |
virtual ~CIni(); |
//----------------------------------------------------------- |
// Ini File Path Name Access |
//----------------------------------------------------------- |
void SetPathName(LPCTSTR lpPathName); // Specify a new file name |
DWORD GetPathName(LPTSTR lpBuffer, DWORD dwBufSize) const; // Retrieve current file name |
#ifdef __AFXWIN_H__ |
CString GetPathName() const; |
#endif |
//------------------------------------------------------------ |
// String Access |
//------------------------------------------------------------ |
DWORD GetString(LPCTSTR lpSection, LPCTSTR lpKey, LPTSTR lpBuffer, DWORD dwBufSize, LPCTSTR lpDefault = NULL) const; |
#ifdef __AFXWIN_H__ |
CString GetString(LPCTSTR lpSection, LPCTSTR lpKey, LPCTSTR lpDefault = NULL) const; |
#endif |
BOOL WriteString(LPCTSTR lpSection, LPCTSTR lpKey, LPCTSTR lpValue) const; |
// Read a string from the ini file, append it with another string then write it |
// back to the ini file. |
BOOL AppendString(LPCTSTR Section, LPCTSTR lpKey, LPCTSTR lpString) const; |
//------------------------------------------------------------ |
// Ini File String Array Access |
//------------------------------------------------------------ |
// Parse the string retrieved from the ini file and split it into a set of sub strings. |
DWORD GetArray(LPCTSTR lpSection, LPCTSTR lpKey, LPTSTR lpBuffer, DWORD dwBufSize, LPCTSTR lpDelimiter = NULL, BOOL bTrimString = TRUE) const; |
#ifdef __AFXWIN_H__ |
void GetArray(LPCTSTR lpSection, LPCTSTR lpKey, CStringArray* pArray, LPCTSTR lpDelimiter = NULL, BOOL bTrimString = TRUE) const; |
BOOL WriteArray(LPCTSTR lpSection, LPCTSTR lpKey, const CStringArray* pArray, int nWriteCount = -1, LPCTSTR lpDelimiter = NULL) const; |
#endif |
//------------------------------------------------------------ |
// Primitive Data Type Access |
//------------------------------------------------------------ |
int GetInt(LPCTSTR lpSection, LPCTSTR lpKey, int nDefault, int nBase = BASE_DECIMAL) const; |
BOOL WriteInt(LPCTSTR lpSection, LPCTSTR lpKey, int nValue, int nBase = BASE_DECIMAL) const; |
BOOL IncreaseInt(LPCTSTR lpSection, LPCTSTR lpKey, int nIncrease = 1, int nBase = BASE_DECIMAL) const; |
UINT GetUInt(LPCTSTR lpSection, LPCTSTR lpKey, UINT nDefault, int nBase = BASE_DECIMAL) const; |
BOOL WriteUInt(LPCTSTR lpSection, LPCTSTR lpKey, UINT nValue, int nBase = BASE_DECIMAL) const; |
BOOL IncreaseUInt(LPCTSTR lpSection, LPCTSTR lpKey, UINT nIncrease = 1, int nBase = BASE_DECIMAL) const; |
BOOL GetBool(LPCTSTR lpSection, LPCTSTR lpKey, BOOL bDefault) const; |
BOOL WriteBool(LPCTSTR lpSection, LPCTSTR lpKey, BOOL bValue) const; |
BOOL InvertBool(LPCTSTR lpSection, LPCTSTR lpKey) const; |
double GetDouble(LPCTSTR lpSection, LPCTSTR lpKey, double fDefault) const; |
BOOL WriteDouble(LPCTSTR lpSection, LPCTSTR lpKey, double fValue, int nPrecision = -1) const; |
BOOL IncreaseDouble(LPCTSTR lpSection, LPCTSTR lpKey, double fIncrease, int nPrecision = -1) const; |
TCHAR GetChar(LPCTSTR lpSection, LPCTSTR lpKey, TCHAR cDefault) const; |
BOOL WriteChar(LPCTSTR lpSection, LPCTSTR lpKey, TCHAR c) const; |
//------------------------------------------------------------ |
// User-Defined Data Type & Data Block Access |
//------------------------------------------------------------ |
POINT GetPoint(LPCTSTR lpSection, LPCTSTR lpKey, POINT ptDefault) const; |
BOOL WritePoint(LPCTSTR lpSection, LPCTSTR lpKey, POINT pt) const; |
RECT GetRect(LPCTSTR lpSection, LPCTSTR lpKey, RECT rcDefault) const; |
BOOL WriteRect(LPCTSTR lpSection, LPCTSTR lpKey, RECT rc) const; |
DWORD GetDataBlock(LPCTSTR lpSection, LPCTSTR lpKey, LPVOID lpBuffer, DWORD dwBufSize, DWORD dwOffset = 0) const; |
BOOL WriteDataBlock(LPCTSTR lpSection, LPCTSTR lpKey, LPCVOID lpData, DWORD dwDataSize) const; |
BOOL AppendDataBlock(LPCTSTR lpSection, LPCTSTR lpKey, LPCVOID lpData, DWORD dwDataSize) const; |
//------------------------------------------------------------ |
// Section Operations |
//------------------------------------------------------------ |
BOOL IsSectionExist(LPCTSTR lpSection) const; |
DWORD GetSectionNames(LPTSTR lpBuffer, DWORD dwBufSize) const; |
#ifdef __AFXWIN_H__ |
void GetSectionNames(CStringArray* pArray) const; |
#endif |
BOOL CopySection(LPCTSTR lpSrcSection, LPCTSTR lpDestSection, BOOL bFailIfExist) const; |
BOOL MoveSection(LPCTSTR lpSrcSection, LPCTSTR lpDestSection, BOOL bFailIfExist = TRUE) const; |
BOOL DeleteSection(LPCTSTR lpSection) const; |
//------------------------------------------------------------ |
// Key Operations |
//------------------------------------------------------------ |
BOOL IsKeyExist(LPCTSTR lpSection, LPCTSTR lpKey) const; |
DWORD GetKeyLines(LPCTSTR lpSection, LPTSTR lpBuffer, DWORD dwBufSize) const; |
#ifdef __AFXWIN_H__ |
void GetKeyLines(LPCTSTR lpSection, CStringArray* pArray) const; |
#endif |
DWORD GetKeyNames(LPCTSTR lpSection, LPTSTR lpBuffer, DWORD dwBufSize) const; |
#ifdef __AFXWIN_H__ |
void GetKeyNames(LPCTSTR lpSection, CStringArray* pArray) const; |
#endif |
BOOL CopyKey(LPCTSTR lpSrcSection, LPCTSTR lpSrcKey, LPCTSTR lpDestSection, LPCTSTR lpDestKey, BOOL bFailIfExist) const; |
BOOL MoveKey(LPCTSTR lpSrcSection, LPCTSTR lpSrcKey, LPCTSTR lpDestSection, LPCTSTR lpDestKey, BOOL bFailIfExist = TRUE) const; |
BOOL DeleteKey(LPCTSTR lpSection, LPCTSTR lpKey) const; |
//------------------------------------------------------------ |
// Parse a "Double-Null Terminated String" |
//------------------------------------------------------------ |
static BOOL ParseDNTString(LPCTSTR lpString, SUBSTRPROC lpFnStrProc, LPVOID lpParam = NULL); |
//------------------------------------------------------------ |
// Check for Whether a String Representing TRUE or FALSE |
//------------------------------------------------------------ |
static BOOL StringToBool(LPCTSTR lpString, BOOL bDefault = FALSE); |
protected: |
//------------------------------------------------------------ |
// Helper Functions |
//------------------------------------------------------------ |
static LPTSTR __StrDupEx(LPCTSTR lpStart, LPCTSTR lpEnd); |
static BOOL __TrimString(LPTSTR lpBuffer); |
LPTSTR __GetStringDynamic(LPCTSTR lpSection, LPCTSTR lpKey, LPCTSTR lpDefault = NULL) const; |
static DWORD __StringSplit(LPCTSTR lpString, LPTSTR lpBuffer, DWORD dwBufSize, LPCTSTR lpDelimiter = NULL, BOOL bTrimString = TRUE); |
static void __ToBinaryString(UINT nNumber, LPTSTR lpBuffer, DWORD dwBufSize); |
static int __ValidateBase(int nBase); |
static void __IntToString(int nNumber, LPTSTR lpBuffer, int nBase); |
static void __UIntToString(UINT nNumber, LPTSTR lpBuffer, int nBase); |
static BOOL CALLBACK __SubStrCompare(LPCTSTR lpString1, LPVOID lpParam); |
static BOOL CALLBACK __KeyPairProc(LPCTSTR lpString, LPVOID lpParam); |
#ifdef __AFXWIN_H__ |
static BOOL CALLBACK __SubStrAdd(LPCTSTR lpString, LPVOID lpParam); |
#endif |
//------------------------------------------------------------ |
// Member Data |
//------------------------------------------------------------ |
LPTSTR m_pszPathName; // Stores path of the associated ini file |
}; |
#endif // #ifndef __INI_H__ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/STMFlashLoader.cpp |
---|
0,0 → 1,1743 |
/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
* File Name : STMFlashLoader.cpp |
* Author : MCD Application Team |
* Version : v2.2.0 |
* Date : 05/03/2010 |
* Description : STM Flash Loader command line version |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#include "stdafx.h" |
#include "string.h" |
#include <stdio.h> |
#include <string.h> |
#include <stdlib.h> |
#include <errno.h> |
#include <dos.h> |
#include "../STBLLIB/STBLLIB.h" |
#include "../Files/Files.h" |
#include "ini.h" |
#define NONE = 0; |
#define ODD = 1; |
#define EVEN = 2; |
typedef enum STATE {OK,KO}; |
char MapFile[256]; |
PMAPPING pmMapping; |
int TimeBO = 100; |
BOOL SHOW_OK = TRUE; // Set to TRUE/FALSE to show/hide OK status messages |
BOOL SHOW_KO = TRUE; // Set to TRUE/FALSE to show/hide KO status messages |
/*******************************************************************************************/ |
/* Function : FileExist */ |
/* IN : file name */ |
/* OUT : boolean */ |
/* Description : verify if the given file exists */ |
/*******************************************************************************************/ |
BOOL FileExist(LPCTSTR filename) |
{ |
// Data structure for FindFirstFile |
WIN32_FIND_DATA findData; |
// Clear find structure |
ZeroMemory(&findData, sizeof(findData)); |
// Search the file |
HANDLE hFind = FindFirstFile( filename, &findData ); |
if ( hFind == INVALID_HANDLE_VALUE ) |
{ |
// File not found |
return false; |
} |
// File found |
// Release find handle |
FindClose( hFind ); |
hFind = NULL; |
// The file exists |
return true; |
} |
/*******************************************************************************************/ |
/* Function : void man() */ |
/* IN : */ |
/* OUT : */ |
/* Description : print the manual on the standard output */ |
/*******************************************************************************************/ |
void man() |
{ |
printf("STMicroelectronics UART Flash Loader command line v2.2.0.MLAB \n\n"); |
printf(" Usage : \n\n"); |
printf(" STMFlashLoader.exe [options] [Agrument][[options] [Agrument]...] \n\n"); |
printf(" -? (Show this help) \n"); |
printf(" -c (Establish connection to the COM port) \n"); |
printf(" --pn port_nb : e.g: 1, 2 ..., default 1 \n"); |
printf(" --br baud_rate : e.g: 115200, 57600 ..., default 57600 \n"); |
printf(" --db data_bits : value in {5,6,7,8} ..., default 8 \n"); |
printf(" --pr parity : value in {NONE,ODD,EVEN} ..., default EVEN \n"); |
printf(" --sb stop_bits : value in {1,1.5,2} ..., default 1 \n"); |
printf(" --ec echo : value OFF or ECHO or LISTEN ..., default is OFF \n"); |
printf(" --co control : Enable or Disable RTS and DTR outputs control \n"); |
printf(" : value OFF or ON ..., default is OFF \n"); |
printf(" --to time_out : (ms) e.g 1000, 2000, 3000 ..., default 5000 \n"); |
printf(" -Rts (set Rts line to Hi, Lo)\n"); |
printf(" --State : State in {Hi, Lo} \n"); |
printf(" -Dtr (Set Rts line to Hi, Lo)\n"); |
printf(" --State : State in {Hi, Lo}\n"); |
printf(" -Auto (Set Rts and Dtr line Automatically)\n"); |
printf(" -i device_name (e.g STM32_Low-density_16K, [See the Map directory]) \n"); |
printf(" -e (erase flash pages\n"); |
printf(" --all all pages : erase all pages\n"); |
printf(" --sec number_of_pages_group pages_group_codes : erase specified group pages \n"); |
printf(" -u (Upload flash contents to a .bin, .hex or .s19 file )\n"); |
printf(" --fn file_name : full path name of the file \n"); |
printf(" -d (Download the content of a file into MCU flash) \n"); |
printf(" --a address(hex): start @ in hex ; ignored if it is not a binary file \n"); |
printf(" --fn file_name : full path name (.bin, .hex or .s19 file) \n"); |
printf(" --v : verify after download \n"); |
printf(" --o : optimize; removes FFs data \n"); |
printf(" -r (Run the flash code at the specified address \n"); |
printf(" --a address(hex) : address in hexadecimal) \n"); |
printf(" -p (Enable or Disable protections) \n"); |
printf(" --ewp : enable write protection for sector codes (e.g 1,2,etc.) \n"); |
printf(" --dwp : disable write protection \n"); |
printf(" --drp : disable read protection \n"); |
printf(" --erp : enable read protection, all arguments following this one will fail \n"); |
printf(" -o (Get or Set STM32 option bytes: use -d command for STM8!) \n"); |
printf(" --get --fn file_name : get option bytes from the device \n"); |
printf(" and write it in the specified file \n"); |
printf(" --set --fn file_name : load option bytes from the specified file \n"); |
printf(" and write it to the device \n"); |
printf(" --set --vals --OPB hex_val : set the specified option byte; OPB in: User, \n"); |
printf(" RDP, Data0, Data1, WRP0, WRP1, WRP2, WRP3 \n"); |
} |
/*******************************************************************************************/ |
/* Function : ParityToInt */ |
/* IN : parity as string (NONE, ODD, EVEN) */ |
/* OUT : integer */ |
/* Description : Get the integer representation of the given parity */ |
/*******************************************************************************************/ |
int ParityToInt(char* parity) |
{ |
if (strcmp(parity,"NONE")==0) return 0; |
else if(strcmp(parity,"ODD")==0) return 1; |
else if(strcmp(parity,"EVEN")==0) return 2; |
else return 2; |
} |
/*******************************************************************************************/ |
/* Function : ModeToInt */ |
/* IN : Mode as string (OFF, ECHO, LISTEN) */ |
/* OUT : int */ |
/* Description : Get the int representation of the given string Mode */ |
/*******************************************************************************************/ |
int ModeToInt(char* status) |
{ |
if (strcmp(status,"OFF")==0) return 0; |
else if(strcmp(status,"ECHO")==0) return 1; |
else if(strcmp(status,"LISTEN")==0) return 2; |
else return 0; |
} |
/*******************************************************************************************/ |
/* Function : StatusToBool */ |
/* IN : Status as string (ON, OFF) */ |
/* OUT : Bool */ |
/* Description : Get the boolean representation of the given string ON/OFF */ |
/*******************************************************************************************/ |
bool StatusToBool(char* status) |
{ |
if (strcmp(status,"OFF")==0) return false; |
else if(strcmp(status,"ON")==0) return true; |
else return false; |
} |
/*******************************************************************************************/ |
/* Function : Is_Option */ |
/* IN : option as string */ |
/* OUT : boolean */ |
/* Description : Verify if the given string present an option */ |
/*******************************************************************************************/ |
bool Is_Option(char* option) |
{ |
if (strcmp(option,"-?")==0) return true; |
else if (strcmp(option,"-c")==0) return true; |
else if (strcmp(option,"-i")==0) return true; |
else if (strcmp(option,"-e")==0) return true; |
else if (strcmp(option,"-u")==0) return true; |
else if (strcmp(option,"-d")==0) return true; |
else if (strcmp(option,"-v")==0) return true; |
else if (strcmp(option,"-p")==0) return true; |
else if (strcmp(option,"-r")==0) return true; |
else if (strcmp(option,"-o")==0) return true; |
else if (strcmp(option,"-Rts")==0) return true; |
else if (strcmp(option,"-Dtr")==0) return true; |
else if (strcmp(option,"-Auto")==0) return true; |
else return false; |
} |
/*******************************************************************************************/ |
/* Function : Is_SubOption */ |
/* IN : sub-option as string */ |
/* OUT : boolean */ |
/* Description : Verify if the given string present a sub-option */ |
/*******************************************************************************************/ |
bool Is_SubOption(char* suboption) |
{ |
if (strcmp(suboption,"--pn")==0) return true; |
else if (strcmp(suboption,"--br")==0) return true; |
else if (strcmp(suboption,"--db")==0) return true; |
else if (strcmp(suboption,"--pr")==0) return true; |
else if (strcmp(suboption,"--sb")==0) return true; |
else if (strcmp(suboption,"--ec")==0) return true; |
else if (strcmp(suboption,"--co")==0) return true; |
else if (strcmp(suboption,"--to")==0) return true; |
else if (strcmp(suboption,"--lcs")==0) return true; |
else if (strcmp(suboption,"--all")==0) return true; |
else if (strcmp(suboption,"--sec")==0) return true; |
else if (strcmp(suboption,"--a")==0) return true; |
else if (strcmp(suboption,"--s")==0) return true; |
else if (strcmp(suboption,"--fn")==0) return true; |
else if (strcmp(suboption,"--v")==0) return true; |
else if (strcmp(suboption,"--o")==0) return true; |
else if (strcmp(suboption,"--erp")==0) return true; |
else if (strcmp(suboption,"--drp")==0) return true; |
else if (strcmp(suboption,"--ewp")==0) return true; |
else if (strcmp(suboption,"--dwp")==0) return true; |
else if (strcmp(suboption,"--get")==0) return true; |
else if (strcmp(suboption,"--set")==0) return true; |
else if (strcmp(suboption,"--vals")==0) return true; |
else if (strcmp(suboption,"--RDP")==0) return true; |
else if (strcmp(suboption,"--User")==0) return true; |
else if (strcmp(suboption,"--Data0")==0) return true; |
else if (strcmp(suboption,"--Data1")==0) return true; |
else if (strcmp(suboption,"--WRP0")==0) return true; |
else if (strcmp(suboption,"--WRP1")==0) return true; |
else if (strcmp(suboption,"--WRP2")==0) return true; |
else if (strcmp(suboption,"--WRP3")==0) return true; |
else if (strcmp(suboption,"--Hi")==0) return true; |
else if (strcmp(suboption,"--Lo")==0) return true; |
else return false; |
} |
/*******************************************************************************************/ |
/* Function : write_debug_info */ |
/* IN : */ |
/* OUT : */ |
/* Description : print the output messages on the standart output */ |
/*******************************************************************************************/ |
void write_debug_info(char *msg, int page, DWORD addr, float size, STATE status) |
{ |
char d_info[256]; |
if((page==0) && (addr==0) && (size==0)) |
{ |
if(status == OK) |
sprintf(d_info, "%s \t\t\t\t [OK] \n", msg); |
else |
sprintf(d_info, "%s \t\t\t\t [KO] \n", msg); |
} |
else if(status == OK) |
sprintf(d_info, "%s \t page %i \t @0x %8X \t size %.2f(KB) \t [OK] \n", msg, page, addr, (float)size); |
else |
sprintf(d_info, "%s \t page %i \t @0x %8X \t size %.2f(KB) \t [KO] \n", msg, page, addr, (float)size); |
if((SHOW_OK && (status == OK)) || (SHOW_KO && (status == KO))) printf(d_info); |
} |
/*******************************************************************************************/ |
/* Function : main */ |
/* IN : */ |
/* OUT : */ |
/* Description : */ |
/*******************************************************************************************/ |
int main(int argc, char* argv[]) |
{ |
START: |
BYTE Res = SUCCESS; |
BYTE User, RDP, Data0, Data1, WRP0, WRP1, WRP2, WRP3; |
bool WaitForMoreSubOpt = TRUE; |
//Initializing default serial connection parameters |
int portname = 1; |
long BaudRate = 57600 ; |
int DataBits = 8; |
int parity = ParityToInt("EVEN"); |
double nbStopBit = 1; |
int timeout = 5000; |
bool control = false; |
int nsec = 0; |
DWORD address = 0x00000000; |
DWORD size = 0x00000000; |
char* filename; |
char devname[256] = "STM32_Low-density_32K.STmap"; |
bool Verify = FALSE; |
bool optimize = FALSE; |
int becho = 0; |
char Drive[3], Dir[256], Fname[256], Ext[256]; |
char *ptr; |
bool bAuto = false; |
if (argc == 1) // wrong parameters |
man(); |
else |
{ |
int arg_index = 1; |
while(arg_index < argc) |
{ |
if(!Is_Option(argv[arg_index])) |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
if (bAuto) |
goto Done_Success; |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
//============================ Show the man ========================================= |
if (strcmp(argv[arg_index],"-?")==0) |
{ |
man(); |
return 0; |
} |
//=============================== connect ============================================ |
else if (strcmp(argv[arg_index],"-c")==0) |
{ |
while(arg_index < argc) |
{ |
if (arg_index< argc-1) |
arg_index++; |
else |
break; |
if(Is_Option(argv[arg_index])) // Set default connection settings and continue with the next option |
break; |
else if(Is_SubOption(argv[arg_index])) // Get connection settings |
{ |
if (arg_index< argc-1) |
arg_index++; |
else |
break; |
if (strcmp(argv[arg_index-1],"--pn")==0) portname = atoi(argv[arg_index]);//port name (e.g COM1, COM2 ..., default COM1) \n"); |
else if (strcmp(argv[arg_index-1],"--br")==0) BaudRate = atoi(argv[arg_index]);//baud reate (e.g 115200, 128000 ..., default 57600) \n"); |
else if (strcmp(argv[arg_index-1],"--db")==0) DataBits = atoi(argv[arg_index]);//data bits (in {5,6,7,8} ..., default 8) \n"); |
else if (strcmp(argv[arg_index-1],"--pr")==0) parity = ParityToInt(argv[arg_index]); //parity (in {NONE,ODD,EVEN} ..., default EVEN) \n"); |
else if (strcmp(argv[arg_index-1],"--sb")==0) nbStopBit= atof(argv[arg_index]);//stop bits (in {1,1.5,2} ..., default 1) \n"); |
else if (strcmp(argv[arg_index-1],"--to")==0) timeout = atoi(argv[arg_index]);//time out (e.g 1000, 2000, 3000 ..., default 5) \n"); |
else if (strcmp(argv[arg_index-1],"--ec")==0) becho = ModeToInt(argv[arg_index]); // Echo back mode, default is OFF \n"); |
else if (strcmp(argv[arg_index-1],"--co")==0) control = StatusToBool(argv[arg_index]); // Outputs Control ON/OFF, default is OFF \n"); |
} |
else |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
// Apply serial connection settings |
TARGET_SetComIntType(0); |
SetCOMSettings(portname, BaudRate, DataBits, parity, nbStopBit); |
STBL_SetFlowControl(control); |
// Opening serial connection |
Res = COM_Open(); |
SetTimeOut(1000); |
if ((Res != SUCCESS) && (Res != COM_ALREADY_OPENED)) |
{ |
write_debug_info("Opening Port", 0 ,0, 0, KO); |
printf("Cannot open the com port, the port may \n be used by another application \n"); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
else write_debug_info("Opening Port", 0 ,0, 0, OK); |
STBL_SetEcho(becho); // Setting Echo back mode |
} |
//============================ Auto option ======================================= |
else if (strcmp(argv[arg_index],"-Auto")==0) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
bAuto = true; |
// BOOT0 = High |
STBL_SetDtr(TRUE); |
Sleep(100); |
// Reset = Low |
STBL_SetRts(TRUE); |
Sleep(100); |
// Reset = High |
STBL_SetRts(FALSE); |
Sleep(100); |
STBL_SetDtr(FALSE); |
Sleep(100); |
COM_Close(); |
COM_Open(); |
STBL_SetDtr(TRUE); |
Sleep(100); |
// Reset = Low |
STBL_SetRts(TRUE); |
Sleep(100); |
// Reset = High |
STBL_SetRts(FALSE); |
Sleep(100); |
STBL_SetDtr(FALSE); |
Sleep(500); |
write_debug_info("Setting device to BOOT0", 0 ,0, 0, OK); |
} |
//============================ command RTS pin ======================================= |
else if (strcmp(argv[arg_index],"-Rts")==0) |
{ |
//_sleep(1000); |
while(arg_index < argc) |
{ |
if (arg_index< argc-1) arg_index++; |
else break; |
if(Is_Option(argv[arg_index])) break; |
else if(Is_SubOption(argv[arg_index])) |
{ |
if (strcmp(argv[arg_index],"--Hi")==0) |
{ |
write_debug_info("Set Rts line", 0 ,0, 0,OK); |
STBL_SetRts(TRUE); |
} |
else if (strcmp(argv[arg_index],"--Lo")==0) |
{ |
write_debug_info("Reset Rts line", 0 ,0, 0,OK); |
STBL_SetRts(FALSE); |
} |
else |
{ |
write_debug_info("bad parameter [Set Rts line] should be Hi or Lo ", 0 ,0, 0,KO); |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
else |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
} |
//============================ command DTR pin ======================================= |
else if (strcmp(argv[arg_index],"-Dtr")==0) |
{ |
while(arg_index < argc) |
{ |
if (arg_index< argc-1) |
arg_index++; |
else |
break; |
if(Is_Option(argv[arg_index])) |
break; |
else if(Is_SubOption(argv[arg_index])) |
{ |
if (strcmp(argv[arg_index],"--Hi")==0) |
{ |
write_debug_info("Set Dtr line", 0 ,0, 0,OK); |
STBL_SetDtr(TRUE); |
} |
else if (strcmp(argv[arg_index],"--Lo")==0) |
{ |
write_debug_info("Reset Dtr line", 0 ,0, 0,OK); |
STBL_SetDtr(FALSE); |
} |
else |
{ |
write_debug_info("bad parameter [Set Dtr line] should be Hi or Lo ", 0 ,0, 0,KO); |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
else |
{ |
if (arg_index < argc - 1) printf("bad parameter [%s] \n", argv[arg_index]); |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
} |
//============================ ERASE ================================================= |
else if (strcmp(argv[arg_index],"-e")==0) |
{ |
while(arg_index < argc) |
{ |
if (!WaitForMoreSubOpt) |
break; |
if (arg_index< argc-1) |
arg_index++; |
else |
break; |
if(Is_Option(argv[arg_index])) |
break; |
else if(Is_SubOption(argv[arg_index])) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
//******************** This section is only for STM8 boot loader ******************* |
BYTE Version; |
Commands pCmds; |
CString m_Version; |
if (STBL_GET(&Version, &pCmds) == SUCCESS) |
{ |
m_Version.Format("%x.%x",Version/16, Version & 0x0F) ; |
} |
CIni Ini((LPCSTR)MapFile); |
if(Ini.IsKeyExist((LPCTSTR)"Product",(LPCTSTR)m_Version)) |
{ |
CString E_W_ROUTINEs = Ini.GetString((LPCTSTR)"Product",(LPCTSTR)m_Version, ""); |
CString Path(*__argv); |
char fullPath [MAX_PATH]; |
GetModuleFileName(0, fullPath, (MAX_PATH)); |
Path=fullPath; |
int j=Path.ReverseFind('\\')+1; |
if(j) Path=Path.Left(j); |
CString ToFind; |
ToFind.Format("%s%s%s", Path, "STM8_Routines\\", E_W_ROUTINEs); |
if(!E_W_ROUTINEs.IsEmpty()) |
{ |
if(!FileExist((LPCTSTR)ToFind)) |
{ |
printf("\n!WARNING the erase or download operation may fail \n EW routines file is missing [%s]\n", ToFind); |
} |
else |
{ |
HANDLE Image; |
if (FILES_ImageFromFile((LPSTR)(LPCSTR)ToFind,&Image, 1)== FILES_NOERROR) |
{ |
FILES_SetImageName(Image,(LPSTR)(LPCSTR)ToFind); |
DWORD NbElements; |
if (FILES_GetImageNbElement(Image, &NbElements) == FILES_NOERROR) |
{ |
for (int el=0; el< (int)NbElements;el++) |
{ |
IMAGEELEMENT Element={0}; |
if (FILES_GetImageElement(Image, el, &Element) == FILES_NOERROR) |
{ |
Element.Data=new BYTE[Element.dwDataLength]; |
if (FILES_GetImageElement(Image, el, &Element) == FILES_NOERROR) |
{ |
if (STBL_DNLOAD(Element.dwAddress, Element.Data, Element.dwDataLength, FALSE) != SUCCESS) |
{ |
} |
} |
} |
} |
// Verify writen data |
BOOL VerifySuccess = TRUE; |
_sleep(100);; |
#ifndef _VS6_USED |
int el; |
#endif |
for (el=0; el< (int)NbElements;el++) |
{ |
IMAGEELEMENT Element={0}; |
if (FILES_GetImageElement(Image, el, &Element) == FILES_NOERROR) |
{ |
Element.Data=new BYTE[Element.dwDataLength]; |
if (FILES_GetImageElement(Image, el, &Element) == FILES_NOERROR) |
{ |
if (STBL_VERIFY(Element.dwAddress, Element.Data, Element.dwDataLength, FALSE) != SUCCESS) |
{ |
VerifySuccess = FALSE; |
char str[255]; |
sprintf(str, "%s at address :0x%X. \n%s \nPlease disable the write protection then try agin.", "Data not matching ", Element.dwAddress, "The page may be write protected."); |
AfxMessageBox(str, MB_OK|MB_ICONEXCLAMATION); |
return 1; |
} |
} |
} |
} |
} |
} |
else |
{ |
AfxMessageBox("Unable to load data from this file " + ToFind + " ..."); |
return -1; |
} |
} |
} |
} |
else |
{ |
int family = Ini.GetInt((LPCTSTR)"Product",(LPCTSTR)"family", 0); |
if(family == 3) |
{ |
printf("\n!WARNING the erase or download operation may fail \n EW routines file is missing\n"); |
} |
} |
//End****************** This section is only for STM8 boot loader ******************* |
//End****************** This section is only for STM8 boot loader ******************* |
printf("\n ERASING ... \n"); |
if (strcmp(argv[arg_index-1],"--all")==0) |
{ |
WaitForMoreSubOpt = false; |
Res = STBL_ERASE(0xFFFF, NULL); |
if (Res != SUCCESS) |
write_debug_info("erasing all pages", 0 ,0, 0, KO); |
else |
write_debug_info("erasing all pages", 0 ,0, 0, OK); |
} |
else if (strcmp(argv[arg_index-1],"--sec")==0) |
{ |
WaitForMoreSubOpt = true; |
nsec = atoi(argv[arg_index]); |
LPWORD sectors = (LPWORD)malloc(nsec *2 + 2); |
sectors[0] = 0; |
for(int i = 1; i<= nsec; i++) |
{ |
sectors[0]++; |
arg_index++; |
sectors[sectors[0]] = atoi(argv[arg_index]); |
} |
WaitForMoreSubOpt = false; |
printf("\nerasing %i sectors : ", sectors[0]); |
#ifndef _VS6_USED |
int i; |
#endif |
for(i = 1; i<= nsec; i++) |
{ |
printf("<%i>", sectors[i]); |
} |
printf("\n"); |
Res = STBL_ERASE(nsec, (LPBYTE)sectors+2); |
if (Res != SUCCESS) |
{ |
write_debug_info("erasing", 0 ,0, 0, KO); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
else |
write_debug_info("erasing", 0 ,0, 0, OK); |
arg_index++; |
} |
} |
else |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
} |
//============================ UPLOAD =============================================== |
else if (strcmp(argv[arg_index],"-u")==0) |
{ |
while(arg_index < argc) |
{ |
if (arg_index< argc-1) |
arg_index++; |
else |
break; |
if(Is_Option(argv[arg_index])) |
break; |
else if(Is_SubOption(argv[arg_index])) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
/*if (strcmp(argv[arg_index-1],"--a")==0) |
{ |
address = _tcstoul(argv[arg_index], 0, 16) ; |
} |
else if (strcmp(argv[arg_index-1],"--s")==0) |
{ |
size = _tcstoul(argv[arg_index], 0, 16) ; |
} |
else */if (strcmp(argv[arg_index-1],"--fn")==0) |
{ |
filename = argv[arg_index]; |
} |
} |
else |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
printf("\n UPLOADING ... \n\n"); |
HANDLE Handle; |
FILES_CreateImage(&Handle, 0); |
FILES_CreateImageFromMapping(&Handle,pmMapping); |
DWORD NbElements = 0; |
if (FILES_GetImageNbElement(Handle, &NbElements) == FILES_NOERROR) |
{ |
if (NbElements > 0) |
{ |
for(int i = 0; i< (int)NbElements; i++) |
{ |
IMAGEELEMENT Element={0}; |
// Get element data size |
if (FILES_GetImageElement(Handle, i, &Element) == FILES_NOERROR) |
{ |
//Upload element data |
Element.Data = (LPBYTE)malloc(Element.dwDataLength); |
if (STBL_UPLOAD(Element.dwAddress, Element.Data, Element.dwDataLength) == SUCCESS) |
{ |
//Insert elment in the Image |
write_debug_info("Uploading", i ,Element.dwAddress, (float)Element.dwDataLength/(float)1024, OK); |
FILES_SetImageElement(Handle,i,FALSE,Element); |
} |
else |
{ |
write_debug_info("Uploading", i ,Element.dwAddress, (float)Element.dwDataLength/(float)1024, KO); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
} |
} |
} |
if(!FileExist((LPCTSTR)filename)) |
{ |
printf( "file %s does not exist .. Creating file\n", filename); |
FILE* fp = fopen((LPCTSTR)filename, "a+"); |
fclose(fp); |
} |
printf( "Writing data ...\n"); |
if (FILES_ImageToFile((LPSTR)(LPCSTR)filename,Handle) != FILES_NOERROR) |
{ |
printf( "cannot write to file %s \n", filename); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
else |
printf("\n Uploaded data is dumped on %s", filename); |
} |
//============================ Get Device map file name ============================== |
else if (strcmp(argv[arg_index],"-i")==0) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
sprintf(devname,"%s.STmap", argv[arg_index]); |
char Drive[3], Dir[256], Fname[256], Ext[256]; |
_splitpath(argv[0],Drive,Dir,Fname,Ext); |
sprintf(MapFile, "%s%s%s%s", Drive, Dir , "Map\\", devname); |
pmMapping = NULL; |
WORD size = 0; |
WORD PacketSize = 0; |
pmMapping = NULL; |
WORD Size = 0; |
char MapName[256]; |
// Get the number of sectors in the flash target: pmMapping should be NULL |
// number of sectors is returned in the Size value |
BYTE PagePerSector = 0; |
if (!FileExist((LPCTSTR)MapFile)) |
{ |
printf("This version is not intended to support the <%s> target\n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
FILES_GetMemoryMapping((LPSTR)(LPCTSTR)MapFile, &Size, (LPSTR)MapName, &PacketSize, pmMapping, &PagePerSector); |
// Allocate the mapping structure memory |
pmMapping = (PMAPPING)malloc(sizeof(MAPPING)); |
pmMapping->NbSectors = 0; |
pmMapping->pSectors = (PMAPPINGSECTOR) malloc((Size) * sizeof(MAPPINGSECTOR)); |
// Get the mapping info |
FILES_GetMemoryMapping((LPSTR)(LPCTSTR)MapFile, &Size, (LPSTR)(LPCTSTR)MapName, &PacketSize, pmMapping, &PagePerSector); |
SetPaketSize(PacketSize); |
//sending BL config byte (0x7F) & identifing target |
Res = STBL_Init_BL(); |
if (Res == UNREOGNIZED_DEVICE) |
{ |
write_debug_info("Activating device", 0 ,0, 0, KO); |
if(COM_is_Open()) |
COM_Close(); |
printf("Unrecognized device... Please, reset your device then try again \n"); |
if(COM_is_Open()) |
COM_Close(); |
printf("Please, reset your device then press any key to continue \n"); |
printf("\n Press any key to continue ..."); |
getchar(); |
goto START; |
} |
else if (Res != SUCCESS) |
{ |
write_debug_info("Activating device", 0 ,0, 0, KO); |
printf("No response from the target, the Boot loader can not be started. \nPlease, verify the boot mode configuration, reset your device then try again. \n"); |
if(COM_is_Open()) |
COM_Close(); |
printf("Please, reset your device then then press any key to continue \n"); |
printf("\n Press any key to continue ..."); |
getchar(); |
goto START; |
} |
_sleep(TimeBO); |
write_debug_info("Activating device", 0 ,0, 0, OK); |
//Getting Target informations (version, available commands) |
BYTE Version ; |
Commands pCmds; |
Res = STBL_GET(&Version, &pCmds); |
if (Res != SUCCESS) |
{ |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
SetTimeOut(timeout); |
if (arg_index< argc) |
arg_index++; |
else |
break; |
} |
//============================ DOWNLOAD ============================================== |
else if (strcmp(argv[arg_index],"-d")==0) |
{ |
while(arg_index < argc) |
{ |
if (arg_index< argc-1) |
arg_index++; |
else |
break; |
if(Is_Option(argv[arg_index])) |
break; |
else if(Is_SubOption(argv[arg_index])) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
if (strcmp(argv[arg_index-1],"--a")==0) |
{ |
address = _tcstoul(argv[arg_index], 0, 16) ; |
} |
else if (strcmp(argv[arg_index-1],"--v")==0) |
{ |
Verify = true; |
arg_index--; |
} |
else if (strcmp(argv[arg_index-1],"--o")==0) |
{ |
optimize = TRUE; |
arg_index--; |
} |
else if (strcmp(argv[arg_index-1],"--fn")==0) |
{ |
filename = argv[arg_index]; |
_splitpath(filename,Drive,Dir,Fname,Ext); |
ptr=strupr(Ext); |
strcpy(Ext, ptr); |
} |
} |
else |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
PMAPPINGSECTOR pSector = pmMapping->pSectors; |
for(int i = 1; i<= (int)pmMapping->NbSectors; i++) |
{ |
if ((strcmp(Ext, ".BIN")!=0) && (i==0)) |
address = pSector->dwStartAddress; |
pSector->UseForOperation = TRUE; |
pSector++; |
} |
if(!FileExist((LPCTSTR)filename)) |
{ |
printf( "file does not exist %s \n", filename); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
//****************** This section is only for STM8 boot loader ******************* |
BYTE Version; |
Commands pCmds; |
CString m_Version; |
if (STBL_GET(&Version, &pCmds) == SUCCESS) |
{ |
m_Version.Format("%x.%x",Version/16, Version & 0x0F) ; |
} |
CIni Ini((LPCSTR)MapFile); |
if(Ini.IsKeyExist((LPCTSTR)"Product",(LPCTSTR)m_Version)) |
{ |
CString E_W_ROUTINEs = Ini.GetString((LPCTSTR)"Product",(LPCTSTR)m_Version, ""); |
CString Path(*__argv); |
int j=Path.ReverseFind('\\')+1; |
if(j) Path=Path.Left(j); |
CString ToFind; |
ToFind.Format("%s%s%s", Path, "STM8_Routines\\", E_W_ROUTINEs); |
if(!E_W_ROUTINEs.IsEmpty()) |
{ |
if(!FileExist((LPCTSTR)ToFind)) |
{ |
printf("\n!WARNING the erase or download operation may fail \n EW routines file is missing [%s]\n", ToFind); |
} |
else |
{ |
HANDLE Image; |
if (FILES_ImageFromFile((LPSTR)(LPCSTR)ToFind,&Image, 1)== FILES_NOERROR) |
{ |
FILES_SetImageName(Image,(LPSTR)(LPCSTR)ToFind); |
DWORD NbElements; |
if (FILES_GetImageNbElement(Image, &NbElements) == FILES_NOERROR) |
{ |
for (int el=0; el< (int)NbElements;el++) |
{ |
IMAGEELEMENT Element={0}; |
if (FILES_GetImageElement(Image, el, &Element) == FILES_NOERROR) |
{ |
Element.Data=new BYTE[Element.dwDataLength]; |
if (FILES_GetImageElement(Image, el, &Element) == FILES_NOERROR) |
{ |
if (STBL_DNLOAD(Element.dwAddress, Element.Data, Element.dwDataLength, FALSE) != SUCCESS) |
{ |
} |
} |
} |
} |
// Verify writen data |
BOOL VerifySuccess = TRUE; |
_sleep(100); |
#ifndef _VS6_USED |
int el; |
#endif |
for (el=0; el< (int)NbElements;el++) |
{ |
IMAGEELEMENT Element={0}; |
if (FILES_GetImageElement(Image, el, &Element) == FILES_NOERROR) |
{ |
Element.Data=new BYTE[Element.dwDataLength]; |
if (FILES_GetImageElement(Image, el, &Element) == FILES_NOERROR) |
{ |
if (STBL_VERIFY(Element.dwAddress, Element.Data, Element.dwDataLength, FALSE) != SUCCESS) |
{ |
VerifySuccess = FALSE; |
char str[255]; |
sprintf(str, "%s at address :0x%X. \n%s \nPlease disable the write protection then try agin.", "Data not matching ", Element.dwAddress, "The page may be write protected."); |
AfxMessageBox(str, MB_OK|MB_ICONEXCLAMATION); |
return 1; |
} |
} |
} |
} |
} |
} |
else |
{ |
AfxMessageBox("Unable to load data from this file " + ToFind + " ..."); |
return -1; |
} |
} |
} |
} |
else |
{ |
int family = Ini.GetInt((LPCTSTR)"Product",(LPCTSTR)"family", 0); |
if(family == 3) |
{ |
printf("\n!WARNING the erase or download operation may fail \n EW routines file is missing\n"); |
} |
} |
//End****************** This section is only for STM8 boot loader ******************* |
printf("\n DOWNLOADING ... \n\n"); |
HANDLE Handle; |
if (FILES_ImageFromFile((LPSTR)(LPCSTR)filename,&Handle, 1) == FILES_NOERROR) |
{ |
FILES_SetImageName(Handle,(LPSTR)(LPCSTR)filename); |
DWORD NbElements = 0; |
if (FILES_GetImageNbElement(Handle, &NbElements) == FILES_NOERROR) |
{ |
if ( NbElements > 0 ) |
{ // if binary file -> change the elemnts address |
if (strcmp(Ext, ".BIN")==0) |
{ |
for (int i=0;i< (int)NbElements;i++) |
{ |
IMAGEELEMENT Element={0}; |
if (FILES_GetImageElement(Handle, i, &Element) == FILES_NOERROR) |
{ |
Element.Data= (LPBYTE)malloc(Element.dwDataLength); |
if (FILES_GetImageElement(Handle, i, &Element) == FILES_NOERROR) |
{ |
Element.dwAddress = Element.dwAddress + address; |
FILES_SetImageElement(Handle, i, FALSE, Element); |
} |
} |
} |
} |
} |
} |
FILES_FilterImageForOperation(Handle, pmMapping, OPERATION_UPLOAD, optimize); |
} |
else |
{ |
printf("cannot open file %s \n", filename); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
DWORD NbElements = 0; |
if (FILES_GetImageNbElement(Handle, &NbElements) == FILES_NOERROR) |
{ |
for (int el=0; el< (int)NbElements;el++) |
{ |
IMAGEELEMENT Element={0}; |
if (FILES_GetImageElement(Handle, el, &Element) == FILES_NOERROR) |
{ |
Element.Data= (LPBYTE)malloc(Element.dwDataLength); |
if (FILES_GetImageElement(Handle, el, &Element) == FILES_NOERROR) |
{ |
if ((strcmp(Ext, ".BIN")==0) && (el==0)) |
Element.dwAddress = address; |
if (STBL_DNLOAD(Element.dwAddress, Element.Data, Element.dwDataLength, optimize) != SUCCESS) |
{ |
write_debug_info( "downloading", el ,Element.dwAddress, (float)Element.dwDataLength/(float)1024, KO); |
write_debug_info("The flash may be read protected; use -p --drp to disable write protection." , 0, 0, 0, KO); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
write_debug_info( "downloading", el ,Element.dwAddress, (float)Element.dwDataLength/(float)1024, OK); |
} |
} |
} |
} |
bool VerifySuccess = true; |
if (Verify) |
{ |
printf("\n VERIFYING ... \n\n"); |
for (int el=0; el< (int)NbElements;el++) |
{ |
IMAGEELEMENT Element={0}; |
if (FILES_GetImageElement(Handle, el, &Element) == FILES_NOERROR) |
{ |
Element.Data=(LPBYTE)malloc(Element.dwDataLength); |
if (FILES_GetImageElement(Handle, el, &Element) == FILES_NOERROR) |
{ |
if ((strcmp(Ext, ".BIN")==0) && (el==0)) |
Element.dwAddress = address; |
if (STBL_VERIFY(Element.dwAddress, Element.Data, Element.dwDataLength, optimize) != SUCCESS) |
{ |
VerifySuccess = false; |
write_debug_info("verifying" ,el ,Element.dwAddress, (float)Element.dwDataLength/(float)1024, KO); |
write_debug_info("some pages may be write protected; use -p --dwp to disable write protection." , 0, 0, 0, KO); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
write_debug_info("verifying" ,el ,Element.dwAddress, (float)Element.dwDataLength/(float)1024, OK); |
} |
} |
} |
} |
} |
//============================ VERIFY ================================================ |
else if (strcmp(argv[arg_index],"-v")==0) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
} |
//============================ Program option bytes ================================== |
else if (strcmp(argv[arg_index],"-o")==0) |
{ |
while(arg_index < argc) |
{ |
if (arg_index< argc-1) |
arg_index++; |
else |
break; |
if(Is_Option(argv[arg_index])) |
break; |
else if(Is_SubOption(argv[arg_index])) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
if (strcmp(argv[arg_index-1],"--get")==0) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
if (strcmp(argv[arg_index-1],"--fn")==0) |
filename = argv[arg_index]; |
if(TARGET_GetSIFData(&User, &RDP, &Data0, &Data1, &WRP0, &WRP1, &WRP2, &WRP3) == SUCCESS) |
{ |
write_debug_info("Getting Option bytes data" ,0 ,0, 0, OK); |
HANDLE Image; |
if (FILES_CreateImage(&Image, 1) == FILES_NOERROR) |
{ |
IMAGEELEMENT Element={0}; |
Element.dwAddress = 0x1FFFF800; |
Element.dwDataLength = 16; |
Element.Data = (LPBYTE)malloc(Element.dwDataLength); |
{ |
Element.Data[0] = RDP; |
Element.Data[1] = ~RDP; |
Element.Data[2] = User; |
Element.Data[3] = ~User; |
Element.Data[4] = Data0; |
Element.Data[5] = ~Data0; |
Element.Data[6] = Data1; |
Element.Data[7] = ~Data1; |
Element.Data[8] = WRP0; |
Element.Data[9] = ~WRP0; |
Element.Data[10] = WRP1; |
Element.Data[11] = ~WRP1; |
Element.Data[12] = WRP2; |
Element.Data[13] = ~WRP2; |
Element.Data[14] = WRP3; |
Element.Data[15] = ~WRP3; |
} |
FILES_SetImageElement(Image,0,TRUE,Element); |
if (FILES_ImageToFile((LPSTR)(LPCSTR)filename,Image) != FILES_NOERROR) |
{ |
write_debug_info("Saving Option bytes data",0 ,0, 0, KO); |
} |
else write_debug_info("Saving Option bytes data",0 ,0, 0, OK); |
} |
} |
else write_debug_info("Getting Option bytes data" ,0 ,0, 0, KO); |
} |
else if (strcmp(argv[arg_index-1],"--set")==0) |
{ |
if (arg_index< argc) arg_index++; |
else break; |
if (strcmp(argv[arg_index-1],"--fn")==0) |
{ |
filename = argv[arg_index]; |
HANDLE OPBImage; |
if(!FileExist((LPCTSTR)filename)) |
{ |
printf( "file does not exist %s \n", filename); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
if (FILES_ImageFromFile((LPSTR)(LPCSTR)filename, &OPBImage, 0) == FILES_NOERROR) |
{ |
DWORD NbElements = 0; |
if (FILES_GetImageNbElement(OPBImage, &NbElements) == FILES_NOERROR) |
{ |
if ( NbElements == 1 ) |
{ |
IMAGEELEMENT Element={0}; |
if (FILES_GetImageElement(OPBImage, 0, &Element) == FILES_NOERROR) |
{ |
Element.Data= (LPBYTE)malloc(Element.dwDataLength); |
if (FILES_GetImageElement(OPBImage, 0, &Element) == FILES_NOERROR) |
{ |
RDP = Element.Data[0] ; |
User = Element.Data[2] ; |
Data0 = Element.Data[4] ; |
Data1 = Element.Data[6] ; |
WRP0 = Element.Data[8] ; |
WRP1 = Element.Data[10]; |
WRP2 = Element.Data[12]; |
WRP3 = Element.Data[14]; |
if (TARGET_SetSIFData(User, RDP, Data0, Data1, WRP0, WRP1, WRP2, WRP3) == SUCCESS) |
{ |
write_debug_info("Setting Option bytes data" ,0 ,0, 0, OK); |
if(COM_is_Open()) |
COM_Close(); |
COM_Open(); |
if(STBL_Init_BL() != SUCCESS) |
write_debug_info("Resetting device" ,0 ,0, 0, KO); |
else |
write_debug_info("Resetting device" ,0 ,0, 0, OK); |
} |
else |
write_debug_info("Setting Option bytes data" ,0 ,0, 0, KO); |
} |
} |
} |
} |
} |
} |
else if (strcmp(argv[arg_index-1],"--vals")==0) |
{ |
TARGET_GetSIFData(&User, &RDP, &Data0, &Data1, &WRP0, &WRP1, &WRP2, &WRP3); |
while(arg_index< argc) |
{ |
if(Is_Option(argv[arg_index])) |
break; |
else if(Is_SubOption(argv[arg_index])) |
{ |
arg_index++; |
if(strcmp(argv[arg_index-1],"--RDP")==0) { RDP = _tcstoul(argv[arg_index], 0, 16);arg_index++;} |
else if(strcmp(argv[arg_index-1],"--User")==0) { User = _tcstoul(argv[arg_index], 0, 16);arg_index++;} |
else if(strcmp(argv[arg_index-1],"--data0")==0){ Data0 = _tcstoul(argv[arg_index], 0, 16);arg_index++;} |
else if(strcmp(argv[arg_index-1],"--data1")==0){ Data1 = _tcstoul(argv[arg_index], 0, 16);arg_index++;} |
else if(strcmp(argv[arg_index-1],"--WRP0")==0) { WRP0 = _tcstoul(argv[arg_index], 0, 16);arg_index++;} |
else if(strcmp(argv[arg_index-1],"--WRP1")==0) { WRP1 = _tcstoul(argv[arg_index], 0, 16);arg_index++;} |
else if(strcmp(argv[arg_index-1],"--WRP2")==0) { WRP2 = _tcstoul(argv[arg_index], 0, 16);arg_index++;} |
else if(strcmp(argv[arg_index-1],"--WRP3")==0) { WRP3 = _tcstoul(argv[arg_index], 0, 16);arg_index++;} |
} |
} |
if (TARGET_SetSIFData(User, RDP, Data0, Data1, WRP0, WRP1, WRP2, WRP3) != SUCCESS) |
write_debug_info("Setting Option bytes data" ,0 ,0, 0, KO); |
else |
{ |
write_debug_info("Setting Option bytes data" ,0 ,0, 0, OK); |
if(COM_is_Open()) |
COM_Close(); |
COM_Open(); |
if(STBL_Init_BL() != SUCCESS) |
write_debug_info("Resetting device" ,0 ,0, 0, KO); |
else |
write_debug_info("Resetting device" ,0 ,0, 0, OK); |
} |
arg_index--; |
} |
} |
} |
else |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
} |
//============================ Set/Unset R/W protection ========================== |
else if (strcmp(argv[arg_index],"-p")==0) |
{ |
while(arg_index < argc) |
{ |
if (arg_index< argc-1) |
arg_index++; |
else |
break; |
if(Is_Option(argv[arg_index])) |
break; |
else if(Is_SubOption(argv[arg_index])) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
if (strcmp(argv[arg_index-1],"--erp")==0) |
{ |
if(STBL_READOUT_PROTECT() != SUCCESS) |
write_debug_info( "enabling read protection", 0 , 0, 0, KO); |
else |
write_debug_info( "enabling read protection", 0 , 0, 0, OK); |
_sleep(TimeBO); |
if(STBL_Init_BL() != SUCCESS) |
write_debug_info( "reseting device", 0 , 0, 0, KO); |
else |
write_debug_info( "reseting device", 0 , 0, 0, OK); |
arg_index--; |
} |
else if (strcmp(argv[arg_index-1],"--drp")==0) |
{ |
if(STBL_READOUT_PERM_UNPROTECT() == SUCCESS) |
{ |
write_debug_info( "disabling read protection", 0 , 0, 0, OK); |
_sleep(TimeBO); |
if(STBL_Init_BL() != SUCCESS) |
write_debug_info( "reseting device", 0 , 0, 0, KO); |
else |
write_debug_info( "reseting device", 0 , 0, 0, OK); |
} |
else |
write_debug_info( "disabling read protection", 0 , 0, 0, KO); |
arg_index--; |
} |
else if (strcmp(argv[arg_index-1],"--ewp")==0) |
{ |
LPBYTE sectors; |
if(Is_Option(argv[arg_index])) break; |
nsec = atoi(argv[arg_index]); |
sectors = (LPBYTE)malloc(nsec + 1); |
sectors[0] = 0; |
for(int i = 1; i<= nsec; i++) |
{ |
sectors[0]++; |
arg_index++; |
sectors[sectors[0]] = atoi(argv[arg_index]); |
} |
printf("\nenabling write protection %i sectors : ", sectors[0]); |
#ifndef _VS6_USED |
int i; |
#endif |
for(i = 1; i<= nsec; i++) |
{ |
printf("<%i>", sectors[i]); |
} |
printf("\n"); |
if(STBL_WRITE_PROTECT(((LPBYTE)sectors)[0],&((LPBYTE)sectors)[1]) != SUCCESS) |
write_debug_info( "enabling write protection", 0 , 0, 0, KO); |
else |
write_debug_info( "enabling write protection", 0 , 0, 0, OK); |
_sleep(TimeBO); |
if(STBL_Init_BL() != SUCCESS) |
write_debug_info( "reseting device", 0 , 0, 0, KO); |
else |
write_debug_info( "reseting device", 0 , 0, 0, OK); |
} |
else if (strcmp(argv[arg_index-1],"--dwp")==0) |
{ |
if(STBL_WRITE_PERM_UNPROTECT() != SUCCESS) |
write_debug_info( "disabling write protection", 0 , 0, 0, KO); |
else |
write_debug_info( "disabling write protection", 0 , 0, 0, OK); |
_sleep(TimeBO); |
if(STBL_Init_BL() != SUCCESS) |
write_debug_info( "reseting device", 0 , 0, 0, KO); |
else |
write_debug_info( "reseting device", 0 , 0, 0, OK); |
arg_index--; |
} |
} |
else |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
} |
//============================ Run at address ======================================== |
else if (strcmp(argv[arg_index],"-r")==0) |
{ |
while(arg_index < argc) |
{ |
if (arg_index< argc-1) |
arg_index++; |
else |
break; |
if(Is_Option(argv[arg_index])) |
break; |
else if(Is_SubOption(argv[arg_index])) |
{ |
if (arg_index< argc) |
arg_index++; |
else |
break; |
PMAPPINGSECTOR pSector = pmMapping->pSectors; |
address = pSector->dwStartAddress; |
if (strcmp(argv[arg_index-1],"--a")==0) |
{ |
address = _tcstoul(argv[arg_index], 0, 16) ; |
} |
} |
else |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
if (STBL_GO(address) == SUCCESS) |
{ |
printf("Your code is running...\n"); |
} |
else |
{ |
printf( "run fails \n"); |
} |
} |
} |
else |
{ |
if (arg_index < argc - 1) |
printf("bad parameter [%s] \n", argv[arg_index]); |
if(COM_is_Open()) |
COM_Close(); |
printf("\n Press any key to continue ..."); |
getchar(); |
return 1; |
} |
} |
} |
Done_Success: |
if (bAuto) |
{ |
// commented |
STBL_SetDtr(FALSE); |
Sleep(50); |
if(COM_is_Open()) |
COM_Close(); |
COM_Open(); |
// Reset = Low |
STBL_SetRts(TRUE); |
Sleep(50); |
write_debug_info("Unset BOOT0 & RESET ", 0 ,0, 0, OK); |
// Reset = High |
STBL_SetRts(FALSE); |
} |
printf("\nFlashing done. Enjoy ... \n"); |
if(COM_is_Open()) |
COM_Close(); |
return 0; |
} |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE******/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/STMFlashLoader.dsp |
---|
0,0 → 1,116 |
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/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/STMFlashLoader.vcproj |
---|
0,0 → 1,281 |
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ProjectType="Visual C++" |
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Name="STMFlashLoader" |
ProjectGUID="{5DED8251-B239-46C2-B2EE-087FF8D46398}" |
Keyword="MFCProj" |
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IntermediateDirectory=".\Release" |
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InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC60.vsprops" |
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---|
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</ClCompile> |
<ClCompile Include="STMFlashLoader.cpp" /> |
</ItemGroup> |
<ItemGroup> |
<ClInclude Include="StdAfx.h" /> |
</ItemGroup> |
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" /> |
<ImportGroup Label="ExtensionTargets"> |
</ImportGroup> |
</Project> |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/STMFlashLoader.vcxproj.filters |
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0,0 → 1,33 |
<?xml version="1.0" encoding="utf-8"?> |
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003"> |
<ItemGroup> |
<Filter Include="Source Files"> |
<UniqueIdentifier>{ac980f17-2122-4126-9ae5-5592b88d1599}</UniqueIdentifier> |
<Extensions>cpp;c;cxx;rc;def;r;odl;idl;hpj;bat</Extensions> |
</Filter> |
<Filter Include="Header Files"> |
<UniqueIdentifier>{fc26f28a-0bb7-4eef-beb8-e5048a0bf5c0}</UniqueIdentifier> |
<Extensions>h;hpp;hxx;hm;inl</Extensions> |
</Filter> |
<Filter Include="Resource Files"> |
<UniqueIdentifier>{fe09c62c-5ad9-49f3-95e7-210be25edff9}</UniqueIdentifier> |
<Extensions>ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe</Extensions> |
</Filter> |
</ItemGroup> |
<ItemGroup> |
<ClCompile Include="Ini.cpp"> |
<Filter>Source Files</Filter> |
</ClCompile> |
<ClCompile Include="StdAfx.cpp"> |
<Filter>Source Files</Filter> |
</ClCompile> |
<ClCompile Include="STMFlashLoader.cpp"> |
<Filter>Source Files</Filter> |
</ClCompile> |
</ItemGroup> |
<ItemGroup> |
<ClInclude Include="StdAfx.h"> |
<Filter>Header Files</Filter> |
</ClInclude> |
</ItemGroup> |
</Project> |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/STMFlashLoader.vcxproj.user |
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0,0 → 1,3 |
<?xml version="1.0" encoding="utf-8"?> |
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003"> |
</Project> |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/StdAfx.cpp |
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0,0 → 1,9 |
// stdafx.cpp : source file that includes just the standard includes |
// STMFlashLoader.pch will be the pre-compiled header |
// stdafx.obj will contain the pre-compiled type information |
#include "stdafx.h" |
// TODO: reference any additional headers you need in STDAFX.H |
// and not in this file |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/StdAfx.h |
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0,0 → 1,22 |
#if !defined(AFX_STDAFX_H__0581A7FA_DEC6_4D61_B47A_826059363FA9__INCLUDED_) |
#define AFX_STDAFX_H__0581A7FA_DEC6_4D61_B47A_826059363FA9__INCLUDED_ |
#if _MSC_VER > 1000 |
#pragma once |
#endif // _MSC_VER > 1000 |
#define WIN32_LEAN_AND_MEAN // Exclude rarely-used stuff from Windows headers |
#include <stdio.h> |
#include <afxcmn.h> // MFC support for Windows Common Controls |
#include "../Files/Files.h" |
// TODO: reference additional headers your program requires here |
//{{AFX_INSERT_LOCATION}} |
// Microsoft Visual C++ will insert additional declarations immediately before the previous line. |
#endif // !defined(AFX_STDAFX_H__0581A7FA_DEC6_4D61_B47A_826059363FA9__INCLUDED_) |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMFlashLoader/resource.h |
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0,0 → 1,15 |
//{{NO_DEPENDENCIES}} |
// Microsoft Developer Studio generated include file. |
// Used by STMFlashLoader.rc |
// |
// Next default values for new objects |
// |
#ifdef APSTUDIO_INVOKED |
#ifndef APSTUDIO_READONLY_SYMBOLS |
#define _APS_NEXT_RESOURCE_VALUE 101 |
#define _APS_NEXT_COMMAND_VALUE 40001 |
#define _APS_NEXT_CONTROL_VALUE 1000 |
#define _APS_NEXT_SYMED_VALUE 101 |
#endif |
#endif |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMicroelectronics Flash Loader project.dsw |
---|
0,0 → 1,52 |
Microsoft Developer Studio Workspace File, Format Version 6.00 |
# WARNING: DO NOT EDIT OR DELETE THIS WORKSPACE FILE! |
############################################################################### |
Project: "STBLLIB"=".\STBLLIB\STBLLIB.dsp" - Package Owner=<4> |
Package=<5> |
{{{ |
begin source code control |
"$/PC/ST Generic Boot Loader/SOFTWARE", UBQAAAAA |
. |
end source code control |
}}} |
Package=<4> |
{{{ |
}}} |
############################################################################### |
Project: "STMFlashLoader"=".\STMFlashLoader\STMFlashLoader.dsp" - Package Owner=<4> |
Package=<5> |
{{{ |
begin source code control |
"$/PC/ST Generic Boot Loader/SOFTWARE", UBQAAAAA |
. |
end source code control |
}}} |
Package=<4> |
{{{ |
Begin Project Dependency |
Project_Dep_Name STBLLIB |
End Project Dependency |
}}} |
############################################################################### |
Global: |
Package=<5> |
{{{ |
}}} |
Package=<3> |
{{{ |
}}} |
############################################################################### |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STMicroelectronics Flash Loader project.opensdf |
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Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STUARTBLLIB/STUARTBLLIB.h |
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0,0 → 1,486 |
/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
* File Name : STUARTBLLIB.h |
* Author : MCD Application Team |
* Version : v2.2.0 |
* Date : 05/03/2010 |
* Description : Defines the system memory boot loader protocol interface |
******************************************************************************** |
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
*******************************************************************************/ |
#ifndef STDLIB_H |
#define STDLIB_H |
#include "StdAfx.h" |
#include "../CRs232/rs232.h" |
#ifdef STUARTBLLIB_EXPORTS |
#define STUARTBLLIB_API __declspec(dllexport) |
#else |
#define STUARTBLLIB_API __declspec(dllimport) |
#endif |
const BYTE INIT_CON = 0x7F; |
const BYTE GET_CMD = 0x00; //Get the version and the allowed commands supported by the current version of the boot loader |
const BYTE GET_VER_ROPS_CMD = 0x01; //Get the BL version and the Read Protection status of the NVM |
const BYTE GET_ID_CMD = 0x02; //Get the chip ID |
const BYTE SET_SPEED_CMD = 0x03; //set the new baudrate |
const BYTE READ_CMD = 0x11; //Read up to 256 bytes of memory starting from an address specified by the user |
const BYTE GO_CMD = 0x21; //Jump to an address specified by the user to execute (a loaded) code |
const BYTE WRITE_CMD = 0x31; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
const BYTE ERASE_CMD = 0x43; //Erase from one to all the NVM sectors |
const BYTE ERASE_EXT_CMD = 0x44; //Erase from one to all the NVM sectors |
const BYTE WRITE_PROTECT_CMD = 0x63; //Enable the write protection in a permanent way for some sectors |
const BYTE WRITE_TEMP_UNPROTECT_CMD = 0x71; //Disable the write protection in a temporary way for all NVM sectors |
const BYTE WRITE_PERM_UNPROTECT_CMD = 0x73; //Disable the write protection in a permanent way for all NVM sectors |
const BYTE READOUT_PROTECT_CMD = 0x82; //Enable the readout protection in a permanent way |
const BYTE READOUT_TEMP_UNPROTECT_CMD = 0x91; //Disable the readout protection in a temporary way |
const BYTE READOUT_PERM_UNPROTECT_CMD = 0x92; //Disable the readout protection in a permanent way |
const BYTE SUCCESS = 0x00; // No error |
const BYTE ERROR_OFFSET = 0x00; //error offset |
const BYTE COM_ERROR_OFFSET = ERROR_OFFSET + 0x00; |
const BYTE NO_CON_AVAILABLE = COM_ERROR_OFFSET + 0x01; // No serial port opened |
const BYTE COM_ALREADY_OPENED = COM_ERROR_OFFSET + 0x02; // Serial port already opened |
const BYTE CANT_OPEN_COM = COM_ERROR_OFFSET + 0x03; // Fail to open serial port |
const BYTE SEND_FAIL = COM_ERROR_OFFSET + 0x04; // send over serial port fail |
const BYTE READ_FAIL = COM_ERROR_OFFSET + 0x05; // Read from serial port fail |
const BYTE SYS_MEM_ERROR_OFFSET = ERROR_OFFSET + 0x10; |
const BYTE CANT_INIT_BL = SYS_MEM_ERROR_OFFSET + 0x01; // Fail to start system memory BL |
const BYTE UNREOGNIZED_DEVICE = SYS_MEM_ERROR_OFFSET + 0x02; // Unreconized device |
const BYTE CMD_NOT_ALLOWED = SYS_MEM_ERROR_OFFSET + 0x03; // Command not allowed |
const BYTE CMD_FAIL = SYS_MEM_ERROR_OFFSET + 0x04; // command failed |
const BYTE PROGRAM_ERROR_OFFSET = ERROR_OFFSET + 0x20; |
const BYTE INPUT_PARAMS_ERROR = PROGRAM_ERROR_OFFSET + 0x01; |
const BYTE INPUT_PARAMS_MEMORY_ALLOCATION_ERROR = PROGRAM_ERROR_OFFSET + 0x02; |
enum ACKS {UNDEFINED=0x00, ST75=0x75, ST79=0x79}; |
enum INTERFACE_TYPE {UART, CAN}; |
enum EBaudRate { brCustom,br110, br300, br600, br1200, br2400, br4800, br9600, br14400, br19200, br38400, |
br56000, br57600, br115200, br128000, br256000 };// Port Numbers ( custom or COM1..COM16 } |
enum EPortNumber { pnCustom,pnCOM1, pnCOM2, pnCOM3, pnCOM4, pnCOM5, pnCOM6, pnCOM7,pnCOM8, pnCOM9, pnCOM10, |
pnCOM11, pnCOM12, pnCOM13,pnCOM14, pnCOM15, pnCOM16 };// Data bits ( 5, 6, 7, 8 } |
enum EDataBits { db5BITS, db6BITS, db7BITS, db8BITS }; |
// Stop bits ( 1, 1.5, 2 } |
enum EStopBits { sb1BITS, sb1HALFBITS, sb2BITS }; |
// Parity ( None, odd, even, mark, space } |
enum EParity { ptNONE, ptODD, ptEVEN, ptMARK, ptSPACE }; |
// Hardware Flow Control ( None, None + RTS always on, RTS/CTS } |
enum EHwFlowControl { hfNONE, hfNONERTSON, hfRTSCTS }; |
// Software Flow Control ( None, XON/XOFF } |
enum ESwFlowControl { sfNONE, sfXONXOFF }; |
// What to do with incomplete (incoming} packets ( Discard, Pass } |
enum EPacketMode { pmDiscard, pmPass }; |
enum OPERATION {NONE, ERASE, UPLOAD, DNLOAD, DIS_R_PROT, DIS_W_PROT, ENA_R_PROT, ENA_W_PROT}; |
typedef struct RESULT |
{ |
OPERATION operation; |
char* filename; |
HANDLE Image; |
}* LPRESULT; |
typedef struct Commands |
{ |
BOOL GET_CMD ; //Get the version and the allowed commands supported by the current version of the boot loader |
BOOL GET_VER_ROPS_CMD ; //Get the BL version and the Read Protection status of the NVM |
BOOL GET_ID_CMD ; //Get the chip ID |
BOOL SET_SPEED_CMD ; //Change the CAN baudrate |
BOOL READ_CMD ; //Read up to 256 bytes of memory starting from an address specified by the user |
BOOL GO_CMD ; //Jump to an address specified by the user to execute (a loaded) code |
BOOL WRITE_CMD ; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
BOOL ERASE_CMD ; //Erase from one to all the NVM sectors |
BOOL ERASE_EXT_CMD ; //Erase from one to all the NVM sectors |
BOOL WRITE_PROTECT_CMD ; //Enable the write protection in a permanent way for some sectors |
BOOL WRITE_TEMP_UNPROTECT_CMD ; //Disable the write protection in a temporary way for all NVM sectors |
BOOL WRITE_PERM_UNPROTECT_CMD ; //Disable the write protection in a permanent way for all NVM sectors |
BOOL READOUT_PROTECT_CMD ; //Enable the readout protection in a permanent way |
BOOL READOUT_TEMP_UNPROTECT_CMD ; //Disable the readout protection in a temporary way |
BOOL READOUT_PERM_UNPROTECT_CMD ; //Disable the readout protection in a permanent way |
}* LPCommands; |
typedef struct TARGET_DESCRIPTOR |
{ |
BYTE Version ; |
BYTE CmdCount ; |
BYTE PIDLen ; |
BYTE* PID ; |
BYTE ROPE ; |
BYTE ROPD ; |
BOOL GET_CMD ; //Get the version and the allowed commands supported by the current version of the boot loader |
BOOL GET_VER_ROPS_CMD ; //Get the BL version and the Read Protection status of the NVM |
BOOL GET_ID_CMD ; //Get the chip ID |
BOOL SET_SPEED_CMD ; |
BOOL READ_CMD ; //Read up to 256 bytes of memory starting from an address specified by the user |
BOOL GO_CMD ; //Jump to an address specified by the user to execute (a loaded) code |
BOOL WRITE_CMD ; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
BOOL ERASE_CMD ; //Erase from one to all the NVM sectors |
BOOL ERASE_EXT_CMD ; //Erase from one to all the NVM sectors |
BOOL WRITE_PROTECT_CMD ; //Enable the write protection in a permanent way for some sectors |
BOOL WRITE_TEMP_UNPROTECT_CMD ; //Disable the write protection in a temporary way for all NVM sectors |
BOOL WRITE_PERM_UNPROTECT_CMD ; //Disable the write protection in a permanent way for all NVM sectors |
BOOL READOUT_PERM_PROTECT_CMD ; //Enable the readout protection in a permanent way |
BOOL READOUT_TEMP_UNPROTECT_CMD ; //Disable the readout protection in a temporary way |
BOOL READOUT_PERM_UNPROTECT_CMD ; //Disable the readout protection in a permanent way |
}* LPTARGET_DESCRIPTOR; |
typedef struct STBL_Request |
{ |
BYTE _cmd; |
DWORD _address; |
WORD _length; |
BYTE _nbSectors; |
LPTARGET_DESCRIPTOR _target; |
LPBYTE _data; |
WORD _wbSectors; |
}* LPSTBL_Request; |
extern "C" |
{ |
/************************************************************************************/ |
/* SET COMMUNICATION INTERFACE TYPE |
/* UART - ... |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE TARGET_SetComIntType(BYTE com_int_type); |
/************************************************************************************/ |
/* GET PROGRESS STATE |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE GetProgress(LPBYTE progress); |
/************************************************************************************/ |
/* GET ACTIVITY TIME |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE GetActivityTime(LPDWORD time); |
/************************************************************************************/ |
/* SET ACTIVITY TIME |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE SetActivityTime(DWORD time); |
/************************************************************************************/ |
/* GetFlashSize |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE TARGET_GetFlashSize(DWORD Addr, LPWORD val); |
/************************************************************************************/ |
/* GetRAMSize |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE TARGET_GetMemoryAddress(DWORD Addr, LPBYTE val); |
/************************************************************************************/ |
/* GetRDPOptionByte |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE TARGET_GetRDPOptionByte(LPBYTE RDP); |
/************************************************************************************/ |
/* GetWRPOptionBytes |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE TARGET_GetWRPOptionBytes(LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3); |
/************************************************************************************/ |
/* Basic function to send a request |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE Send_RQ(LPSTBL_Request pRQ); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE SetCOMSettings(int numPort, long speedInBaud, int nbBit, |
int parity, float nbStopBit); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
/*STUARTBLLIB_API BYTE ESetCOMSettings(EPortNumber numPort, EBaudRate speedInBaud, EDataBits nbBit, |
EParity parity, EStopBits nbStopBit);*/ |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE COM_Open(); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE COM_Close(); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_SetSpeed(DWORD speed); |
/************************************************************************************/ |
/* |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_Init_BL(); |
/************************************************************************************/ |
/* 0x00; //Get the version and the allowed commands supported by the current version of the boot loader |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_GET(LPBYTE Version, LPCommands pCmds); |
/************************************************************************************/ |
/* 0x01; //Get the BL version and the Read Protection status of the NVM |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_GET_VER_ROPS(LPBYTE Version, LPBYTE ROPEnabled, LPBYTE ROPDisabled); |
/************************************************************************************/ |
/* 0x02; //Get the chip ID |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_GET_ID(LPBYTE size, LPBYTE pID); |
/************************************************************************************/ |
/* 0x11; //Read up to 256 bytes of memory starting from an address specified by the user |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_READ(DWORD Address, BYTE Size, LPBYTE pData); |
/************************************************************************************/ |
/* 0x21; //Jump to an address specified by the user to execute (a loaded) code |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_GO(DWORD Address); |
/************************************************************************************/ |
/* 0x31; //Write maximum 256 bytes to the RAM or the NVM starting from an address specified by the user |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_WRITE(DWORD address, BYTE size, LPBYTE pData); |
/************************************************************************************/ |
/* 0x43; //Erase from one to all the NVM sectors |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_ERASE(WORD NbSectors, LPBYTE pSectors); |
/************************************************************************************/ |
/* 0x63; //Enable the write protection in a permanent way for some sectors |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_WRITE_PROTECT(BYTE NbSectors, LPBYTE pSectors); |
/************************************************************************************/ |
/* 0x71; //Disable the write protection in a temporary way for all NVM sectors |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_WRITE_TEMP_UNPROTECT(); |
/************************************************************************************/ |
/* 0x73; //Disable the write protection in a permanent way for all NVM sectors |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_WRITE_PERM_UNPROTECT(); |
/************************************************************************************/ |
/* 0x82; //Enable the readout protection in a permanent way |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_READOUT_PROTECT(); |
/************************************************************************************/ |
/* 0x91; //Disable the readout protection in a temporary way |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_READOUT_TEMP_UNPROTECT(); |
/************************************************************************************/ |
/* 0x92; //Disable the readout protection in a permanent way |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_READOUT_PERM_UNPROTECT(); |
/************************************************************************************/ |
/* UPLOAD |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_UPLOAD(DWORD Address, LPBYTE pData, DWORD Length); |
/************************************************************************************/ |
/* VERIFY |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_VERIFY(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad); |
/************************************************************************************/ |
/* DNLOAD |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_DNLOAD(DWORD Address, LPBYTE pData, DWORD Length,BOOL bTruncateLeadFFForDnLoad); |
/************************************************************************************/ |
/* SET PACKET SIZE |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE SetPaketSize(BYTE size); |
/************************************************************************************/ |
/* GET PACKET SIZE |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE GetPaketSize(LPBYTE size); |
/************************************************************************************/ |
/* GetAckValue |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API ACKS GetAckValue(); |
/************************************************************************************/ |
/* IsConnected |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BOOL COM_is_Open(); |
/************************************************************************************/ |
/* SetTimeOut |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE SetTimeOut(DWORD vms); |
/************************************************************************************/ |
/* GetUserOptionByte |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE TARGET_GetUserOptionByte(LPBYTE User); |
/************************************************************************************/ |
/* GetDataOptionByte |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE TARGET_GetDataOptionByte(LPBYTE Data0, LPBYTE Data1); |
/************************************************************************************/ |
/* SetSIFData |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE TARGET_SetSIFData(BYTE User, BYTE RDP, BYTE Data0, BYTE Data1, |
BYTE WRP0, BYTE WRP1, BYTE WRP2, BYTE WRP3); |
/************************************************************************************/ |
/* GetSIFData |
/* |
/* |
/************************************************************************************/ |
STUARTBLLIB_API BYTE TARGET_GetSIFData(LPBYTE User, LPBYTE RDP, LPBYTE Data0, LPBYTE Data1, |
LPBYTE WRP0, LPBYTE WRP1, LPBYTE WRP2, LPBYTE WRP3); |
/************************************************************************************/ |
/* Set Rts Line State |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_SetRts(BOOL Val); |
/************************************************************************************/ |
/* Set Dtr Line State |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_SetDtr(BOOL Val); |
/************************************************************************************/ |
/* Set the state of TXD. Return: true if success. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_setTxd(BOOL val); |
/************************************************************************************/ |
/* Return: The state of CTS. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_getCts(BOOL* pval); |
/************************************************************************************/ |
/* Return: The state of DTR. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_getDtr(BOOL* pval); |
/************************************************************************************/ |
/* Return: The state of RI. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_getRi(BOOL* pval); |
/************************************************************************************/ |
/* Return: The state of DTR. |
/* High = TRUE |
/* Low = FALSE |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_getCd(BOOL* pval); |
/************************************************************************************/ |
/* Set Echo Mode |
/* 0 = Echo Disabled |
/* 1 = Echo Back Enabled |
/* 2 = Listen Echo Enabled |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_SetEcho(int val); |
/************************************************************************************/ |
/* SetFlowControl : Enable/Disable Flow Control of DTR and RTS |
/* FALSE = Disabled |
/* TRUE = Enabled |
/************************************************************************************/ |
STUARTBLLIB_API BYTE STBL_SetFlowControl(bool val); |
} |
#endif |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE******/ |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/STUARTBLLIB/resource.h |
---|
0,0 → 1,15 |
//{{NO_DEPENDENCIES}} |
// Microsoft Developer Studio generated include file. |
// Used by STUARTBLLIB.rc |
// |
// Next default values for new objects |
// |
#ifdef APSTUDIO_INVOKED |
#ifndef APSTUDIO_READONLY_SYMBOLS |
#define _APS_NEXT_RESOURCE_VALUE 101 |
#define _APS_NEXT_COMMAND_VALUE 40001 |
#define _APS_NEXT_CONTROL_VALUE 1000 |
#define _APS_NEXT_SYMED_VALUE 101 |
#endif |
#endif |
/Modules/ARM/STM32F10xRxT/SW/RS232_bootloader/Src/ipch/stmflashloader-15f8c9e3/stmflashloader-56063049.ipch |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
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;;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** |
;;* File Name : Default.conf |
;;* Author : MCD Application Team |
;;* Version : V2.2.0 |
;;* Date : 05/03/2010 |
;;* Description : Defines the default parameters configuration |
;;******************************************************************************** |
;;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
;;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
;;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
;;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
;;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
;;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
;;******************************************************************************** |
[INTERFACE] |
comm_int=0 |
[Serial] |
PortNumber=2 |
BaudRate=0 |
DataBits=3 |
Parity=2 |
StopBits=0 |
TimeOut=4 |
Echo=0 |
[MCUs] |
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[f2] |
AN=AN2430 |
Title=STR75x System Memory boot mode |
ADDR_RAM_SIZE =FFFFFFFF; |
ADDR_FLASH_SIZE=FFFFFFFF; |
[f3] |
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[f4] |
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RW=1 |
RunAddress=8000000 |
Family=0 |
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UploadExt=*.hex |
OPBExt=*.bin |
Download=C:\Users\kakl\Documents\ARM\KAKL\LED_Blink\bin\LED_Blink.hex |
Upload= |
OPBFile= |
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