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/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/src/PulseGen.vhd
0,0 → 1,466
----------------------------------------------------------------------------------
-- Company: www.mlab.cz
-- Based on code written by MIHO.
--
-- Design Name: S3AN01A
-- Project Name: PulseGen
-- Target Devices: XC3S50AN-4
-- Tool versions: ISE 13.3
-- Description: Sample of Pulse Generator at S3AN01A MLAB board.
--
-- Dependencies: External PS/2 Keyboard has to be connected.
--
-- Version: $Id$
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use WORK.PS2_pkg.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity PulseGen is
generic (
-- Top Value for 100MHz Clock Counter
MAXCOUNT: integer := 30_000_000;
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
);
port (
-- Main Clock
CLK100MHz: in std_logic;
-- Mode Signals (usualy not used)
M: in std_logic_vector(2 downto 0);
VS: in std_logic_vector(2 downto 0);
-- Dipswitch Inputs
DIPSW: in std_logic_vector(7 downto 0);
-- Push Buttons
PB: in std_logic_vector(3 downto 0);
-- LED Bar Outputs
LED: out std_logic_vector(7 downto 0);
-- LED Display (8 digit with 7 segments and ddecimal point)
LD_A_n: out std_logic;
LD_B_n: out std_logic;
LD_C_n: out std_logic;
LD_D_n: out std_logic;
LD_E_n: out std_logic;
LD_F_n: out std_logic;
LD_G_n: out std_logic;
LD_DP_n: out std_logic;
LD_0_n: out std_logic;
LD_1_n: out std_logic;
LD_2_n: out std_logic;
LD_3_n: out std_logic;
LD_4_n: out std_logic;
LD_5_n: out std_logic;
LD_6_n: out std_logic;
LD_7_n: out std_logic;
-- VGA Video Out Port
VGA_R: out std_logic_vector(1 downto 0);
VGA_G: out std_logic_vector(1 downto 0);
VGA_B: out std_logic_vector(1 downto 0);
VGA_VS: out std_logic;
VGA_HS: out std_logic;
-- Bank 1 Pins - Inputs for this Test
B: inout std_logic_vector(24 downto 0);
-- PS/2 Bidirectional Port (open collector, J31 and J32)
-- PS2_CLK1: inout std_logic;
-- PS2_DATA1: inout std_logic;
PS2_CLK2: inout std_logic;
PS2_DATA2: inout std_logic;
-- Diferencial Signals on 4 pin header (J7)
DIF1P: inout std_logic;
DIF1N: inout std_logic;
DIF2P: inout std_logic;
DIF2N: inout std_logic;
-- I2C Signals (on connector J30)
I2C_SCL: inout std_logic;
I2C_SDA: inout std_logic;
-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
SD1AP: inout std_logic;
SD1AN: inout std_logic;
SD1BP: inout std_logic;
SD1BN: inout std_logic;
SD2AP: inout std_logic;
SD2AN: inout std_logic;
SD2BP: inout std_logic;
SD2BN: inout std_logic;
-- Analog In Out
ANA_OUTD: out std_logic;
ANA_REFD: out std_logic;
ANA_IND: in std_logic;
-- SPI Memory Interface
SPI_CS_n: inout std_logic;
SPI_DO: inout std_logic;
SPI_DI: inout std_logic;
SPI_CLK: inout std_logic;
SPI_WP_n: inout std_logic
);
end entity PulseGen;
architecture PulseGen_a of PulseGen is
function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable mybcd : std_logic_vector(11 downto 0) := (others => '0');
variable bint : std_logic_vector(7 downto 0) := bin;
begin
for i in 0 to 7 loop -- repeating 8 times.
mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits.
mybcd(0) := bint(7);
bint(7 downto 1) := bint(6 downto 0);
bint(0) :='0';
if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
end if;
if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
end if;
if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
end if;
end loop;
return mybcd;
end to_bcd;
-- O1: ____|^^^^^^^|______
-- O2: _________|^^|______
-- t1 t2
-- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz
signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2
signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2
signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer
signal O1: std_logic := '0'; -- Output 1
signal O2: std_logic := '0'; -- Output 2
signal CTburst: unsigned(15 downto 0) := X"0000"; -- Pulse counter
-- LED Demo Signals
-- ----------------
signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary)
signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary)
signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz)
-- LED Display
-- -----------
signal Number: std_logic_vector(32 downto 0); -- LED Display Input
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
signal Enable: std_logic;
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
-- PS/2 Port
-- ---------
-- Interface Signals
signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code
signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code
signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock)
signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code
-- Result
signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory)
-- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese
-- VGA Demo Signals
-- ----------------
signal CLK: std_logic; -- Main Clock - global distribution network
signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG
signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network
signal VGA_Blank: boolean; -- Blank
signal VGA_Hsync: boolean; -- Horisontal Synchronisation
signal VGA_Vsync: boolean; -- Vertical Synchronisation
signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter
signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter
signal PinState: std_logic; -- For IB1 Port Test
signal Red: std_logic_vector(1 downto 0);
signal Green: std_logic_vector(1 downto 0);
signal Blue: std_logic_vector(1 downto 0);
-- ADDA
signal ADDA_DataIn: std_logic_vector(7 downto 0);
begin
-- Basic LED Blinking Test
-- =======================
-- LED Bar Counter
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if Counter < MAXCOUNT-1 then
Counter <= Counter + 1;
else
Counter <= (others => '0');
Bar <= Bar + 1;
end if;
end if;
end process;
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
-- LED Display (multiplexed)
-- =========================
-- Connect LED Display Output Ports (negative outputs)
LD_A_n <= not (Segments(0) and Enable);
LD_B_n <= not (Segments(1) and Enable);
LD_C_n <= not (Segments(2) and Enable);
LD_D_n <= not (Segments(3) and Enable);
LD_E_n <= not (Segments(4) and Enable);
LD_F_n <= not (Segments(5) and Enable);
LD_G_n <= not (Segments(6) and Enable);
LD_DP_n <= not (Segments(7) and Enable);
LD_0_n <= not Digits(0);
LD_1_n <= not Digits(1);
LD_2_n <= not Digits(2);
LD_3_n <= not Digits(3);
LD_4_n <= not Digits(4);
LD_5_n <= not Digits(5);
LD_6_n <= not Digits(6);
LD_7_n <= not Digits(7);
-- Time Multiplex
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if MuxCounter < MUXCOUNT-1 then
MuxCounter <= MuxCounter + 1;
else
MuxCounter <= (others => '0');
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
Enable <= '0';
end if;
if MuxCounter > (MUXCOUNT-4) then
Enable <= '1';
end if;
end if;
end process;
-- BCD to 7 Segmet Decoder
-- -- A
-- | | F B
-- -- G
-- | | E C
-- -- D H
-- ABCDEFGH
Segments <= "11111100" when Code="0000" else -- Digit 0
"01100000" when Code="0001" else -- Digit 1
"11011010" when Code="0010" else -- Digit 2
"11110010" when Code="0011" else -- Digit 3
"01100110" when Code="0100" else -- Digit 4
"10110110" when Code="0101" else -- Digit 5
"10111110" when Code="0110" else -- Digit 6
"11100000" when Code="0111" else -- Digit 7
"11111110" when Code="1000" else -- Digit 8
"11110110" when Code="1001" else -- Digit 9
"11101110" when Code="1010" else -- Digit A
"00111110" when Code="1011" else -- Digit b
"10011100" when Code="1100" else -- Digit C
"01111010" when Code="1101" else -- Digit d
"10011110" when Code="1110" else -- Digit E
"10001110" when Code="1111" else -- Digit F
"00000000";
Code <= Number( 3 downto 0) when Digits="00000001" else
Number( 7 downto 4) when Digits="00000010" else
Number(11 downto 8) when Digits="00000100" else
Number(15 downto 12) when Digits="00001000" else
Number(19 downto 16) when Digits="00010000" else
Number(23 downto 20) when Digits="00100000" else
Number(27 downto 24) when Digits="01000000" else
Number(31 downto 28) when Digits="10000000" else
"0000";
-- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0
-- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1
-- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2
-- "11111111";
-- Number(31 downto 28) <= Key(3 downto 0);
-- Number( 7 downto 0) <= std_logic_vector(BAR);
-- Number(31 downto 24) <= DIPSW;
-- PS/2 Port
-- =========
-- Instantiate PS/2 Keyboard Interface Handler
PS2_Keyboard: PS2 generic map(
CLKFREQ => 100_000_000
)
port map(
-- Main Clock
Clk => CLK100MHz,
-- PS/2 Port
PS2_Clk => PS2_CLK2,
PS2_Data => PS2_DATA2,
-- Result - valid when PS2_Valid
PS2_Code => PS2_Code,
PS2_Attribs => PS2_Attribs,
PS2_Valid => PS2_Valid,
-- Immediate State of Shifts
PS2_Shifts => PS2_Shifts
); -- PS2
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if PS2_Valid and PS2_Attribs(7)='0' then
-- Valid Scan Code with no Break Attribute
PS2_Result( 7 downto 0) <= PS2_Code;
PS2_Result(15 downto 8) <= PS2_Attribs;
end if;
if PS2_Valid and PS2_Attribs(7)='0' then
if PS2_Code = X"74" and T1<2000 then T1<=T1+1; end if;
if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if;
if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if;
if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if;
CT0<=X"0000";
O1<='0';
O2<='0';
CTburst<=X"0000";
end if;
if PB(0)='1' then
T1<=X"0000";
T2<=X"0000";
end if;
if DIPSW(0)='1' then
if CT0>X"F000" then
CT0<=X"0000";
else
CT0<=CT0+1;
end if;
else
if CT0>X"0200" then
CT0<=X"0000";
else
CT0<=CT0+1;
end if;
end if;
if CTburst>2000 then
CTburst<=X"0000";
end if;
if (CTburst<1000) or (DIPSW(1)='0') then
if CT0=X"0000" then
O1<='1';
end if;
if CT0=T1+X"0000" then
O2<='1';
end if;
end if;
if CT0=T2+T1+X"0000" then
O1<='0';
O2<='0';
CTburst<=CTburst+1;
end if;
end if;
end process;
-- Display Result on LED
Number(3 downto 0) <= (others=>'0');
Number(15 downto 4) <= to_bcd(std_logic_vector(T2));
Number(19 downto 16) <= (others=>'0');
Number(31 downto 20) <= to_bcd(std_logic_vector(T1));
-- Test Diferencial In/Outs
-- ========================
-- Output Signal on SATA Connector
SD1AP <= Bar(0);
SD1AN <= Bar(1);
SD1BP <= Bar(2);
SD1BN <= Bar(3);
-- Input Here via SATA Cable
SD2AP <= 'Z';
SD2AN <= 'Z';
SD2BP <= 'Z';
SD2BN <= 'Z';
-- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them
-- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!!
DIF1P <= O1;
B(0) <= O1;
DIF1N <= not O1;
B(1) <= not O1;
DIF2P <= O2;
B(2) <= O2;
DIF2N <= not O2;
B(3) <= not O2;
VGA_R(0) <= O1;
VGA_R(1) <= O2;
-- Unused Signals
-- ==============
-- I2C Signals (on connector J30)
I2C_SCL <= 'Z';
I2C_SDA <= 'Z';
-- SPI Memory Interface
SPI_CS_n <= 'Z';
SPI_DO <= 'Z';
SPI_DI <= 'Z';
SPI_CLK <= 'Z';
SPI_WP_n <= 'Z';
ANA_OUTD <= 'Z';
ANA_REFD <= 'Z';
VGA_R <= "ZZ";
VGA_G <= "ZZ";
VGA_B <= "ZZ";
VGA_VS <= 'Z';
VGA_HS <= 'Z';
end architecture PulseGen_a;
Property changes:
Added: svn:keywords
+Id
\ No newline at end of property

/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/src/LIB/PS2.vhd
0,0 → 1,520
----------------------------------------------------------------------------------
-- Company: www.mlab.cz
-- Engineer: miho
--
-- Create Date: 19:31:10 02/20/2011
-- Design Name: S3AN01A Test Design
-- Module Name: PS2
-- Project Name: S3AN01A Test Design
-- Target Devices: XILINX FPGA (Spartan3A/3AN)
-- Tool versions: ISE 12.4 / 13.1 / 13.3
-- Description: Test design for PCB verification
--
-- Dependencies: None
--
-- Revision: 0.01 File Created
--
----------------------------------------------------------------------------------
--
-- PS/2 Keyboard Driver
-- ====================
--
-- PS2_Code
-- --------
--
-- Standard PS/2 Scan Code
--
--
-- PS2_Attribs
-- -----------
--
-- Bit 0 - Shift
-- Bit 1 - Ctrl
-- Bit 2 - Alt
-- Bit 3 - Ext0 (arrows, ...)
-- Bit 4 - Ext1
-- Bit 5 - Shift Num (arrows with NumLock)
-- Bit 6
-- Bit 7 - Break (key release)
--
--
-- PS2_Shifts
-- ----------
--
-- Bit 0 - Shift Left
-- Bit 1 - Shift Right
-- Bit 2 - Ctrl Left
-- Bit 3 - Ctrl Right
-- Bit 4 - Alt Left
-- Bit 5 - Alt Right
-- Bit 6 - Num Lock
-- Bit 7 - Caps Lock
-- Bit 8 - Scroll Lock
-- Bit 9 - Shift Num (virtual state) - Not to be used
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PS2 is
generic (
-- Top Value for 100MHz Clock Counter
CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000)
);
port (
-- Main Clock
Clk: in std_logic;
-- PS/2 Port
PS2_Clk: inout std_logic;
PS2_Data: inout std_logic;
-- Result - valid when PS2_Valid
PS2_Valid: out boolean; -- Valid Data (synchronous with Clk)
PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code
PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code
-- Immediate State of Shifts
PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc.
);
end entity PS2;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package PS2_pkg is
component PS2
generic (
-- Top Value for 100MHz Clock Counter
CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000)
);
port (
-- Main Clock
Clk: in std_logic;
-- PS/2 Port
PS2_Clk: inout std_logic;
PS2_Data: inout std_logic;
-- Result - valid when PS2_Valid
PS2_Valid: out boolean; -- Valid Data (synchronous with Main Clock)
PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code
PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code
-- Immediate State of Shifts
PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc.
);
end component PS2;
end package;
architecture PS2_a of PS2 is
function to_std_logic(State: boolean) return std_logic is
begin
if State then
return '1';
else
return '0';
end if;
end function to_std_logic;
-- Sampled PS/2 Clock and Data
signal PS2_Clk_d: std_logic := '0'; -- For sync with systerm clock
signal PS2_Clk_dd: std_logic := '0'; -- For falling edge detection
signal PS2_Data_d: std_logic := '0'; -- For sync with systerm clock
-- Level 0 - Read Byte from PS/2 Interface
type ReadByte_t is ( -- Read Byte FSM State Type
Idle, -- Inactive State
D0, D1, D2, D3, D4, D5, D6, D7, -- Receiving Bits
Parity, -- Receiving Parity
Final -- Receiving Stop Bit and Sending ReadByte_rdy
);
signal ReadByteState: ReadByte_t := Idle; -- Read Byte FSM State
signal ReadByte: std_logic_vector(7 downto 0) := (others => '0'); -- Read Byte (Raw Scan Code Byte)
signal ReadByte_rdy: boolean := false; -- Read Byte Ready (synchronous with Clk)
-- Level 1 - Process Raw Scan Codes E0,F1 and F0 - valid only when Level1_rdy
signal FlagE0: boolean := false; -- E0 - Ext0 Key
signal FlagE1: boolean := false; -- E1 - Ext1 Key
signal FlagF0: boolean := false; -- F0 - Break (release) Key
signal Level1_rdy: boolean := false; -- Send Data and Flags to the next level
-- Level 2 - Process Raw Scan Codes and Shift-Like Atributes E0, E1 and F0 - valid only when Level2_rdy
signal FlagBreak: boolean := false; -- F0 - Break (depress) Key
signal FlagAltR: boolean := false; -- E0 11 - State of Right Alt Key
signal FlagAltL: boolean := false; -- 11 - State of Left Alt Key
signal FlagShiftNum: boolean := false; -- E0 12 - State of Ext Left Shift (pseudo key)
signal FlagShiftL: boolean := false; -- 12
signal FlagShiftR: boolean := false; -- 59
signal FlagCtrlR: boolean := false; -- E0 14
signal FlagCtrlL: boolean := false; -- 14
signal FlagExt0: boolean := false; -- E0 Keys (extended keys)
signal FlagExt1: boolean := false; -- E1 Keys (extended keys - Prt_Scr and Pause_Brk)
signal FlagNumLock: boolean := false; -- 77 Num Lock State
signal FlagScrollLock: boolean := false; -- 7E Scroll Lock State
signal FlagCapsLock: boolean := false; -- 58 Caps Lock State
signal Level2_rdy: boolean := false; -- Send Data and Flags to the next level
signal Level2a_rdy: boolean := false; -- Send Read Ack for Write Byte
-- Write Byte
type WriteByteState_t is ( -- Write Byte FSM State Type
Idle, -- Idle State
WriteStart, -- Start (pull PS2_Clk down)
WaitStart, -- Wait
SendBits, -- Send Data Bits
WriteParity, -- Send Parity
WriteStop, -- Send Stop Bit
AckBit, -- Wait for Ack Bit from Keyboard
Final, -- Wait for Idle on PS2_Clk and PS2_Data
WaitAckByte -- Wait for Ack Byte from Keyboard
);
signal WriteByteState: WriteByteState_t := Idle; -- Write Byte FSM State
signal WriteCode: std_logic_vector(7 downto 0) := (others =>'0'); -- What to Write
signal WriteByte: boolean := false; -- Init Write Byte Sequence
signal SendingData: boolean := false; -- Block Receiver when Sending Data
signal WriteByte_ack: boolean := false; -- Ack Writen Byte
signal WriteReg: std_logic_vector(7 downto 0) := (others =>'0'); -- Transmit Shift Register
signal ParityBit: std_logic := '0'; -- Parity Bit
signal StartTime: unsigned(31 downto 0) := (others =>'0'); -- Timer for Start of Write (PS2_Clk low)
signal WriteBits: unsigned(3 downto 0) := (others =>'0'); -- Bit Counter
-- Update LED Indicators
type UpdState_t is ( -- Update Led Indicators FSM State Type
Idle, -- Inactive State
SendReset, -- For Debug - Reset Keyboard
SendLed1, -- Send FD
SendLed2, -- Send New LED State
SendFinal --
);
signal UpdState: UpdState_t := Idle; -- Update Led Indicators FSM State
signal UpdateLed: boolean := false; -- Send new LED State to the Keyboard
signal UpdateLed_ack: boolean := false; -- Ack (1 clock pulse)
begin
-- Sync External Signals with Clock
process (Clk)
begin
if rising_edge(Clk) then
-- Sync
PS2_Clk_d <= PS2_Clk;
PS2_Data_d <= PS2_Data;
-- For Falling Edge Detection
PS2_Clk_dd <= PS2_Clk_d;
end if;
end process;
-- Level 0 - Read Byte from PS/2 Interface
process (Clk)
begin
if rising_edge(Clk) then
ReadByte_rdy <= false;
if PS2_Clk_dd='1' and PS2_Clk_d='0' and not SendingData then
-- Falling Edge of PS2_Clk
case ReadByteState is
when Idle =>
-- Test Start Bit
if PS2_Data='0' then
ReadByteState <= D0;
end if;
when D0 =>
-- Bit 0
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D1;
when D1 =>
-- Bit 1
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D2;
when D2 =>
-- Bit 2
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D3;
when D3 =>
-- Bit 3
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D4;
when D4 =>
-- Bit 4
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D5;
when D5 =>
-- Bit 5
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D6;
when D6 =>
-- Bit 6
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D7;
when D7 =>
-- Bit 7
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= Parity;
when Parity =>
-- Check Parity Here...
ReadByteState <= Final;
when Final =>
-- End of Byte
ReadByteState <= Idle;
ReadByte_rdy <= true; -- Scan Code Ready (8 bit word)
end case;
end if;
end if;
end process;
-- Level 1 - Process Raw Scan Codes and ESC Atributes E0, E1 and F0
process (Clk)
begin
if rising_edge(Clk) then
if Level1_rdy then
-- Clean State when Sent Data from Level1 processing
Level1_rdy <= false;
FlagE0 <= false;
FlagE1 <= false;
FlagF0 <= false;
else
if ReadByte_rdy then
-- Process Scan Code Byte from Level 0
if ReadByte=X"E0" then
-- Ext Code
FlagE0 <= true;
elsif ReadByte=X"E1" then
-- Special Ext Code
FlagE1 <= true;
elsif ReadByte=X"F0" then
-- Break Flag
FlagF0 <= true;
else
-- Scan Code
Level1_rdy <= true;
end if;
end if;
end if;
end if;
end process;
-- Level 2 - Process Shift (left and right shift, alt and ctrl) and Num Lock (numeric virtual shift)
process (Clk)
begin
if rising_edge(Clk) then
-- Clear Comands to Higher Level
UpdateLed <= false;
Level2a_rdy <= false;
Level2_rdy <= false;
-- Process Read Byte
if Level1_rdy then
if ReadByte=X"11" then
-- Alt Key
if FlagE0 then
FlagAltR <= not FlagF0;
else
FlagAltL <= not FlagF0;
end if;
elsif ReadByte=X"12" then
-- Left Shift
if FlagE0 then
FlagShiftNum <= not FlagF0;
else
FlagShiftL <= not FlagF0;
end if;
elsif ReadByte=X"59" then
-- Right Shift
FlagShiftR <= not FlagF0;
elsif ReadByte=X"14" then
-- Ctrl
if FlagE0 then
FlagCtrlR <= not FlagF0;
else
FlagCtrlL <= not FlagF0;
end if;
elsif ReadByte=X"77" and not FlagCtrlL and not FlagCtrlR and not FlagAltL and not FlagAltR then
-- Num Lock On/Off
if not FlagF0 then
FlagNumLock <= not FlagNumLock;
UpdateLed <= true; -- Set UpdateLed Request
end if;
elsif ReadByte=X"58" then
-- Caps Lock
if not FlagF0 then
FlagCapsLock <= not FlagCapsLock;
UpdateLed <= true; -- Set UpdateLed Request
end if;
elsif ReadByte=X"7E" then
if not FlagF0 then
FlagScrollLock <= not FlagScrollLock;
UpdateLed <= true; -- Set UpdateLed Request
end if;
else
-- Send Data to the next Level
FlagExt0 <= FlagE0;
FlagExt1 <= FlagE1;
FlagBreak <= FlagF0;
if WriteByteState=WaitAckByte then
-- Send Data (Ack Byte) to WriteByte
Level2a_rdy <= true;
else
-- Send Scan Code to the next Level
Level2_rdy <= true;
end if;
end if;
end if;
end if;
end process;
-- Send Data
PS2_Valid <= Level2_rdy;
-- Scan COde
PS2_Code(7 downto 0) <= ReadByte;
-- Attribs
PS2_Attribs(0) <= '1' when FlagShiftL or FlagShiftR else '0'; -- Bit 0 - Shift
PS2_Attribs(1) <= '1' when FlagCtrlL or FlagCtrlR else '0'; -- Bit 1 - Ctrl
PS2_Attribs(2) <= '1' when FlagAltL or FlagAltR else '0'; -- Bit 2 - Alt
PS2_Attribs(3) <= '1' when FlagExt0 else '0'; -- Bit 3 - Ext Code E0
PS2_Attribs(4) <= '1' when FlagExt1 else '0'; -- Bit 4 - Ext Code E1
PS2_Attribs(5) <= '1' when FlagShiftNum else '0'; -- Bit 5 - Shift Num (Arrows,...) - only if NumLock Led is Off
PS2_Attribs(6) <= '0';
PS2_Attribs(7) <= '1' when FlagBreak else '0'; -- Bit 7 - Break (release) Key
-- Immediate State of Shift Like Keys
PS2_Shifts(0) <= '1' when FlagShiftL else '0'; -- Bit 0 - Shift Left
PS2_Shifts(1) <= '1' when FlagShiftR else '0'; -- Bit 1 - Shift Right
PS2_Shifts(2) <= '1' when FlagCtrlL else '0'; -- Bit 2 - Ctrl Left
PS2_Shifts(3) <= '1' when FlagCtrlR else '0'; -- Bit 3 - Ctrl Right
PS2_Shifts(4) <= '1' when FlagAltL else '0'; -- Bit 4 - Alt Left
PS2_Shifts(5) <= '1' when FlagAltR else '0'; -- Bit 5 - Alt Right
PS2_Shifts(6) <= '1' when FlagNumLock else '0'; -- Bit 7 - Num Lock
PS2_Shifts(7) <= '1' when FlagCapsLock else '0'; -- Bit 8 - Caps Lock
PS2_Shifts(8) <= '1' when FlagScrollLock else '0'; -- Bit 9 - Scroll Lock
PS2_Shifts(9) <= '1' when FlagShiftNum else '0'; -- Bit 6 - Shift Num (virtual state) - Not to be used
-- Write Byte to PS/2 Interface
-- Init By: WriteByte
-- Finish Indication: WriteByte_ack
process (Clk)
begin
if rising_edge(Clk) then
WriteByte_ack <= false;
case WriteByteState is
when Idle =>
PS2_Clk <= 'Z';
PS2_Data <= 'Z';
if WriteByte then
WriteByteState <= WriteStart;
WriteReg <= WriteCode;
end if;
when WriteStart =>
if PS2_Data_d='1' and PS2_Clk_d='1' then
-- PS2 Interface in Idle State
PS2_Clk <= '0'; -- Start of Write (PS2_Clk=L)
StartTime <= to_unsigned(CLKFREQ/16000, StartTime'length); -- cca 60us Start
WriteBits <= to_unsigned(7, WriteBits'length); -- 8 bits
WriteByteState <= WaitStart;
SendingData <= true;
end if;
when WaitStart =>
if StartTime>0 then
StartTime <= StartTime - 1;
else
PS2_Data <= '0'; -- Start Bit
PS2_Clk <= 'Z'; -- Release Clk
ParityBit <= '1'; -- Init Parity Generator (code 1111_1111 has parity 1)
WriteByteState <= SendBits;
end if;
when SendBits =>
if PS2_Clk_dd='1' and PS2_Clk_d='0' then
PS2_Data <= WriteReg(0);
ParityBit <= ParityBit xor WriteReg(0);
WriteReg <= '1' & WriteReg(7 downto 1);
if WriteBits>0 then
WriteBits <= WriteBits - 1;
else
WriteByteState <= WriteParity;
end if;
end if;
when WriteParity =>
if PS2_Clk_dd='1' and PS2_Clk_d='0' then
PS2_Data <= ParityBit;
WriteByteState <= WriteStop;
end if;
when WriteStop =>
if PS2_Clk_dd='1' and PS2_Clk_d='0' then
PS2_Data <= '1';
WriteByteState <= AckBit;
end if;
when AckBit =>
PS2_Data <= 'Z';
if PS2_Clk_dd='1' and PS2_Clk_d='0' then
WriteByteState <= Final;
end if;
when Final =>
if PS2_Clk_d='1' then
WriteByteState <= WaitAckByte;
SendingData <= false;
end if;
when WaitAckByte =>
if Level2a_rdy then
WriteByteState <= Idle;
WriteByte_ack <= true;
end if;
end case;
end if;
end process;
-- Level 3 - Update LED Indicators
-- Init By: UpdateLed or Level2_rdy(with scan code and attrib)
-- Finish Indication: UpdateLed_ack (not used)
process (Clk)
begin
if rising_edge(Clk) then
UpdateLed_ack <= false; -- 1 Clock Pulse
WriteByte <= false;
case UpdState is
when Idle =>
-- Register the request
if Level2_rdy and ReadByte=X"07" and not FlagBreak then
WriteCode <= X"FF";
WriteByte <= true;
elsif UpdateLed then
UpdateLed_ack <= true;
UpdState <= SendLed1;
end if;
when SendReset =>
if WriteByteState=Idle then
-- Send Keyborad Reset
WriteCode <= X"FF";
WriteByte <= true;
UpdState <= SendFinal;
end if;
when SendLed1 =>
if WriteByteState=Idle then
-- Send LED Command
WriteCode <= X"ED";
WriteByte <= true;
UpdState <= SendLed2;
end if;
when SendLed2 =>
if WriteByte_ack then
-- Send LED State
WriteCode <= "00000" & to_std_logic(FlagCapsLock)
& to_std_logic(FlagNumLock)
& to_std_logic(FlagScrollLock);
WriteByte <= true;
UpdState <= SendFinal;
end if;
when SendFinal =>
if WriteByte_ack then ---WriteByteState=Idle then
-- Last Data has been Send
UpdState <= Idle;
end if;
end case;
end if;
end process;
end architecture PS2_a;

/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/src/S3AN01B.ucf
0,0 → 1,152
# Board: www.mlab.cz S3AN01A
# Device: XC3S50AN-4C
# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes
# Main Clock (Embedded 100MHz board oscillator)
NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33;
#NET "CLK100MHz" LOC = P125 | IOSTANDARD = LVCMOS33;
NET "CLK100MHz" TNM_NET = CLK100MHz;
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;
# For DCM connection across the whole chip
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;
NET "PS2_CLK2" CLOCK_DEDICATED_ROUTE = FALSE;
# Mode signals
NET "M[0]" LOC = P38 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "M[1]" LOC = P37 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M1 and M2 for boot from external SPI Flash Memory
NET "M[2]" LOC = P39 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M2 for boot from internal Flash memory
# SPI Flash Vendor Mode Select (for external SPI boot Flash)
NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# DIP Switches (positive signals with pull-down)
NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# Push Buttons (positive signals with pull-down)
NET "PB[0]" LOC = P121 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "PB[1]" LOC = P120 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "PB[2]" LOC = P117 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "PB[3]" LOC = P116 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# LED String (positive output signals)
NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33;
NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33;
NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33;
NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33;
NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33;
NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33;
NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33;
NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33;
# LED Display Output Signals (negative, multiplexed)
NET "LD_A_n" LOC = P15 |IOSTANDARD = LVCMOS33;
NET "LD_B_n" LOC = P30 |IOSTANDARD = LVCMOS33;
NET "LD_C_n" LOC = P21 |IOSTANDARD = LVCMOS33;
NET "LD_D_n" LOC = P19 |IOSTANDARD = LVCMOS33;
NET "LD_E_n" LOC = P18 |IOSTANDARD = LVCMOS33;
NET "LD_F_n" LOC = P16 |IOSTANDARD = LVCMOS33;
NET "LD_G_n" LOC = P24 |IOSTANDARD = LVCMOS33;
NET "LD_DP_n" LOC = P20 |IOSTANDARD = LVCMOS33;
NET "LD_0_n" LOC = P25 |IOSTANDARD = LVCMOS33;
NET "LD_1_n" LOC = P31 |IOSTANDARD = LVCMOS33;
NET "LD_2_n" LOC = P32 |IOSTANDARD = LVCMOS33;
NET "LD_3_n" LOC = P13 |IOSTANDARD = LVCMOS33; # !!! Connect U1.13 with U1.33
NET "LD_4_n" LOC = P27 |IOSTANDARD = LVCMOS33;
NET "LD_5_n" LOC = P29 |IOSTANDARD = LVCMOS33;
NET "LD_6_n" LOC = P28 |IOSTANDARD = LVCMOS33;
NET "LD_7_n" LOC = P12 |IOSTANDARD = LVCMOS33; # !!! Connect U1.12 with U1.35
# VGA Analog Display Connection (outputs)
NET "VGA_R[0]" LOC = P3 |IOSTANDARD = LVCMOS33;
NET "VGA_R[1]" LOC = P4 |IOSTANDARD = LVCMOS33;
NET "VGA_G[0]" LOC = P5 |IOSTANDARD = LVCMOS33;
NET "VGA_G[1]" LOC = P6 |IOSTANDARD = LVCMOS33;
NET "VGA_B[0]" LOC = P7 |IOSTANDARD = LVCMOS33;
NET "VGA_B[1]" LOC = P8 |IOSTANDARD = LVCMOS33;
NET "VGA_VS" LOC = P10 |IOSTANDARD = LVCMOS33;
NET "VGA_HS" LOC = P11 |IOSTANDARD = LVCMOS33;
# Bank 1 Port (input for tests, pull-up)
NET "B[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[24]" LOC = P97 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Connected with B[23] on PCB
# PS/2 Bidirectional Port (open collector, J31 and J32)
#NET "PS2_CLK1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # S3AN01A PCB Design has bug so these pins
#NET "PS2_DATA1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # will be assinged after PCB redesign
NET "PS2_CLK2" LOC = P42 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "PS2_DATA2" LOC = P58 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# Diferencial Signals on 4 pin header (J7)
NET "DIF1P" LOC = P110 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIF1N" LOC = P111 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIF2P" LOC = P112 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIF2N" LOC = P113 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# I2C Signals (on connector J30)
NET "I2C_SCL" LOC = P115 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "I2C_SDA" LOC = P114 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
NET "SD1AP" LOC = P54 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD1AN" LOC = P55 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD1BP" LOC = P59 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD1BN" LOC = P57 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD2AP" LOC = P124 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD2AN" LOC = P126 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD2BP" LOC = P131 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD2BN" LOC = P129 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# SPI Memory Interface
NET "SPI_CS_n" LOC = P41 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "SPI_DO" LOC = P71 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SPI_DI" LOC = P62 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SPI_CLK" LOC = P72 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SPI_WP_n" LOC = P70 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# Analog In Out
NET "ANA_OUTD" LOC = P67 |IOSTANDARD = LVCMOS33;
NET "ANA_REFD" LOC = P68 |IOSTANDARD = LVCMOS33;
NET "ANA_IND" LOC = P69 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
/*
# Used Signals (test points)
NET "TPS1" LOC = P53 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS2" LOC = P125 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS3" LOC = P127 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS4" LOC = P130 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS5" LOC = P141 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS6" LOC = P123 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "XXX1" LOC = P33 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only
NET "XXX2" LOC = P35 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only
*/

/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/PulseGen.xise
0,0 → 1,350
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<!-- ISE source project file created by Project Navigator. -->
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<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
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<file xil_pn:name="src/PulseGen.vhd" xil_pn:type="FILE_VHDL">
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<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|PulseGen|PulseGen_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="src/PulseGen.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PulseGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="PulseGen" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="PulseGen_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="PulseGen_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="PulseGen_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="PulseGen_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="Pulse Generator from 10ns to 2us." xil_pn:valueState="non-default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="PulseGen" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
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<title> S3AN01B HW Reference </title>
<meta name="keywords" content="stavebnice MLAB univerzální moduly FPGA XILINX Spartan3AN development board LED VGA">
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<div class="Text">
<p class="Title">
Vývojová deska s&nbsp;obvodem FPGA XILINX Spartan&nbsp;3AN
</p>
<p class="Autor">
Milan Horkel
</p>
<p class="Subtitle">
Před časem mne kluci na kroužku ukecali, abych udělal jednoduchou
vývojovou desku s&nbsp;nějakým programovatelným obvodem. Nakonec jsem
zvolil obvod FPGA od firmy XILINX z&nbsp;řady Spartan3AN, protože
poskytuje rozumné možnosti za rozumnou cenu. Deska je osazena obvodem
XC3S50AN v&nbsp;pouzdru TQFP&nbsp;144.
</p>
<p class="Subtitle">
Tento dokument popisuje hardware desky, její testování a použití
naleznete v&nbsp;dalších dokumentech.
</p>
<p class="Subtitle">
<img width="453" height="517"
src="S3AN01B_HW_Reference.cs_soubory/image001.jpg"
alt="Deska S3AN01B, pohled shora">
</p>
<p>
<a href="../S3AN01B_HW_Reference.cs.pdf"><img class="NoBorder"
src="../../../../../Web/PIC/FileIco_PDF.ico"
alt="Acrobat">&nbsp;PDF verze</a>
</p>
<h1> Technické parametry </h1>
<table>
<tr>
<th> Parametr </th>
<th> Hodnota </th>
<th> Poznámka </th>
</tr>
<tr>
<td> Použitý obvod </td>
<td> XC3S50AN, TQFP144 </td>
<td> XILINX FPGA Spartan 3AN </td>
</tr>
<tr>
<td> Napájení desky </td>
<td> +5V </td>
<td> Cca. 250mA (závisí na funkci) </td>
</tr>
<tr>
<td> Vnitřní napájení </td>
<td> +3.3V (napájení logiky) </td>
<td> Vlastní stabilizátor </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> +1.2V (napájení jádra FPGA) </td>
<td> Vlastní stabilizátor </td>
</tr>
<tr>
<td> Periferie na desce </td>
<td> LED displej 8 míst </td>
<td> Zapojený multiplexně </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> LED indikátory 8 bitů </td>
<td> Zapojené na samostatné výstupy </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> DIP spínače 8 bitů </td>
<td> Zapojené na samostatné vstupy </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> Tlačítka 4 bity </td>
<td> Zapojené na samostatné vstupy </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> VGA výstup </td>
<td> 2 bity na barvu </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> PS/2 rozhraní 2 kusy </td>
<td> 5V tolerantní </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> I2C rozhraní </td>
<td> 5V tolerantní </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> Obvod 5V tolerantních vstupů </td>
<td> Celkem 32 vstupů </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> Jednoduchý A/D a D/A </td>
<td> Pomocí PWM </td>
</tr>
<tr>
<td> Konfigurace </td>
<td> Interní paměť obvodu FPGA </td>
<td> Platí pro obvody řady AN </td>
</tr>
<tr>
<td> &nbsp; </td>
<td> Volitelně paměť SPI FLASH </td>
<td> Pro obvody řady A i AN </td>
</tr>
<tr>
<td> Rozměry </td>
<td> Cca 112x122x20mm </td>
<td> Výška nad základnou </td>
</tr>
</table>
<p>
<i class="Big">Důrazně</i> <i>připomínám hned na začátku, že obvod FPGA
není 5V tolerantní! Znamená to, že se na jeho vstupy smí připojit pouze
signály do velikosti +3.3V (absolutní maximum je +4.6V).</i>
</p>
<p>
<i>Stejně důrazně musím upozornit na to, že na vstupech obvodu nejsou
ochranné diody mezi vstupem a kladným napájecím napětím! To je zásadní
rozdíl od většiny jednočipových mikroprocesorů. Nelze se tedy spoléhat
na to, že když budeme vstupy budit přes velký sériový odpor, že se nic
nestane. Stane! Při zvýšeném napětí na vstupech může být životnost
vstupních tranzistorů v&nbsp;řádu minut nebo hodin.</i>
</p>
<h1> Popis konstrukce </h1>
<h2> Úvodem </h2>
<p>
Školní deska pro práci s obvody FPGA XILINX řady Spartan 3AN vznikla na
popud kluků v kroužku radiotechniky. Protože s obvody FPGA firmy XILINX
pracuji, ujal jsem se tohoto úkolu. Nejdřív jsem uvažoval, že bychom
začali s&nbsp;deskou s&nbsp;některým obvodem CPLD, ale po prozkoumání
ceníku, jsem se přiklonil k&nbsp;obvodu FPGA řady Spartan3AN.
</p>
<p>
Obvody FPGA mají mnohem propracovanější vnitřní architekturu a obsahují
mnohem víc logiky než obvody CPLD. Obvod samotný stojí pouhých 210Kč
včetně DPH (podzim 2010).
</p>
<p>
Je to vlastně nejpokročilejší obvod FPGA v&nbsp;pouzdru TQFP, tedy
v&nbsp;pouzdru, které si dokážeme sami připájet a v&nbsp;nouzi si
dokonce dokážeme sami vyrobit i plošný spoj. Viz dokumentace od první
verze této desky na adrese
<a href="http://www.mlab.cz/PermaLink/S3AN01A">http://www.mlab.cz/PermaLink/S3AN01A</a>
</p>
<p>
Snad by měl existovat i obvod z&nbsp;řady Spartan6 v&nbsp;pouzdru TQFP,
ale nikde jsem ho neviděl na skladě. Až ho uvidím, tak z&nbsp;něj možná
taky něco udělám, pokud čas dovolí.
</p>
<h2> Zapojení modulu </h2>
<p>
Zapojení desky odpovídá účelu desky. Jako vývojová a školní deska je
vybavena obvody pro snadnou práci s&nbsp;obvodem FPGA. Na desce
nalezneme LED displej, skupinu LED diod, několik tlačítek a DIP
přepínačů. Vstupy a výstupy jsou vyvedeny na propojovací hřebínky.
</p>
<h3> Napájení </h3>
<p>
Celá deska se napájí napětím +5V přivedeným na konektor J1. Opět
důrazně připomínám, že použitý obvod FPGA vydrží na vývodech napětí
3.3V, ale ne 5V!
</p>
<p>
<img width="697" height="308"
src="S3AN01B_HW_Reference.cs_soubory/image002.png"
alt="Schéma napájecí části">
</p>
<p>
Z&nbsp;napětí +5V se lineárním stabilizátorem U2 vytváří napětí +3.3V
pro napájení vstupů a výstupů obvodu FPGA. Přítomnost napětí +3.3V
indikuje dioda D10 umístěná v&nbsp;rohu desky. Napětí +3.3V je vyvedeno
na konektor J2 k&nbsp;dalšímu použití. <i>Pozor, nezapojit sem napájení
+5V, došlo by ke zničení obvodu FPGA!</i> Abych na tento konektor
omylem nepřipojil +5V, dávám si ta prostřední vývody zkratovací
propojku. Dioda D9 slouží jako ochrana před přepólováním napájení.
</p>
<p>
Z&nbsp;napětí +3.3V se&nbsp;lineárním stabilizátorem vytváří napětí
+1.2V pro napájení jádra obvodu FPGA.
</p>
<h3> Konfigurace obvodu FPGA </h3>
<p>
Po zapnutí napájení je obvod FPGA potřeba naplnit obsahem, tedy
definovat, jak bude uvnitř zapojen. Toto vnitřní zapojení se nahrává do
vnitřní konfigurační paměti RAM a lze to udělat několika způsoby:
</p>
<ul>
<li> Prostřednictvím JTAG rozhraní přímo z&nbsp;návrhového systému </li>
<li> Z&nbsp;interní paměti obvodu FPGA </li>
<li> Z&nbsp;vnější SPI paměti FLASH (obvod U5/U6/U7 nebo U8) – volitelná možnost </li>
<li> Z&nbsp;nadřazeného procesoru (paralelně nebo sériově) – zde se tento způsob neužívá </li>
</ul>
<p>
Při úspěšném nahrání konfigurace obvodu FPGA se rozsvítí LED D8
s&nbsp;nápisem DONE. Při vypnutí napájení se samozřejmě obsah vnitřní
konfigurační paměti RAM ztratí.
</p>
<p>
Pro JTAG programování slouží konektor J3, který je zapojen obvyklým
způsobem (jako například na programátoru XILINX Parallel Cable III).
Jeho prostřednictví lze nahrát obsah do konfigurační paměti RAM obvodu
FPGA, naprogramovat vnitřní paměť FLASH obvodu FPGA (jen obvod AN),
nebo provádět další činnosti, které tento port umožňuje (pokud
k&nbsp;tomu máte příslušné nástroje). JTAG rozhraní lze použít vždy.
</p>
<p>
<img width="240" height="176"
src="S3AN01B_HW_Reference.cs_soubory/image003.png"
alt="JTAG programovací konektor">
</p>
<p>
Další způsoby načítání konfigurace se volí prostřednictvím signálů M0
M1 a M2 dle tabulky na schématu. Pro defaultní způsob konfigurace
z&nbsp;interní FLASH paměti FPGA musí být zkratován signál M0 na zem
prostřednictvím propojky mezi vývody J4.1 a J4.2. V&nbsp;takovém
případě, pokud je nahraný platný obsah interní FLASH paměti obvodu FPGA
dojde k&nbsp;automatické konfiguraci součástky při každém zapnutí
napájení (konfigurace trvá řádově milisekundy).
</p>
<p>
<img width="250" height="260"
src="S3AN01B_HW_Reference.cs_soubory/image004.png"
alt="Konfigurace (mode)">
<img width="258" height="230"
src="S3AN01B_HW_Reference.cs_soubory/image005.png"
alt="Konfigurace (SPI režim)">
</p>
<p>
Při načítání konfigurace z&nbsp;vnější SPI paměti FLASH je třeba podle
použitého typu paměti nastavit propojky na konektoru J5 aby se použil
správný příkaz pro čtení dat. Externí paměť SPI osazujeme samozřejmě
jen jednu podle zapojení osazované paměti a velikosti jejího pouzdra.
Tuto možnost využijeme zejména pokud osadíme obvod Spartan3A (nemá
interní FLASH paměť) místo obvodu Spartan3AN (má interní FLASH paměť).
</p>
<p>
V&nbsp;případě potřeby lze konfigurovat obvod FPGA i z&nbsp;nadřazeného
systému, ale jen v&nbsp;režimu sériového přenosu (režim slave serial).
K&nbsp;tomu slouží konektory J33 až J38.
</p>
<h3> Oscilátor </h3>
<p>
Jako zdroj hodinového signálu je na desce osazen obvod U4, oscilátor
s&nbsp;kmitočtem 100MHz. Pokud potřebuje aplikace jiný kmitočet, lze
osadit oscilátor s&nbsp;odlišným kmitočtem, nebo využít vnitřních
programovatelných obvodů (blok DCM) pro generování potřebného kmitočtu.
Vnitřními obvody lze generovat kmitočty odvozené od externích hodin
v&nbsp;dosti širokém rozmezí.
</p>
<h3> Řada LED indikátorů </h3>
<p>
Asi první školní aplikací je blikání LED indikátory. Proto tu je
osazeno 8 LED diod s&nbsp;příslušnými rezistory. Výstupy jsou dále
vyvedeny na konektor J26.
</p>
<p>
<img width="640" height="306"
src="S3AN01B_HW_Reference.cs_soubory/image006.png"
alt="Schéma LED indikátorů">
</p>
<h3> Display LED </h3>
<p>
Pro sofistikovanější výpisy je zde umístěn osmimístný LED displej,
který je zapojený v&nbsp;multiplexním režimu, abychom nespotřebovali
zbytečně mnoho vývodů.
</p>
<p>
<img width="714" height="368"
src="S3AN01B_HW_Reference.cs_soubory/image007.png"
alt="Schéma LED displeje">
</p>
<h3> Vstupní tlačítka a přepínače </h3>
<p>
Pro jednoduché vstupy jsou na desce umístěna 4 tlačítka a jeden
osminásobný DIP přepínač. Vstupy jsou dále opatřeny hřebínky pro další
využití vývodů. Protože se jedná o školní desku, jsou zde osazeny
ochranné sériové rezistory. Použití tlačítek a přepínačů předpokládá,
že jsou vstupy nakonfigurovány s pull-down odpory.
</p>
<p>
<img width="359" height="216"
src="S3AN01B_HW_Reference.cs_soubory/image008.png"
alt="Schéma tlačítek">
<img width="366" height="406"
src="S3AN01B_HW_Reference.cs_soubory/image009.png"
alt="Schéma DIP přepínačů">
</p>
<h3> Rozhraní PS/2 a I²C </h3>
<p>
Deska je osazena dvěma porty PS/2 a jedním portem I²C.
</p>
<p>
Rozhraní PS/2 se používá pro připojení klávesnice a/nebo myši. Obě tyto
periferie se liší pouze protokolem. Rozhraní I²C je určeno pro
připojení periferií pro toto rozhraní.
</p>
<p>
Obě rozhraní jsou po hardwarové stránce triviální, neboť se jedná vždy
o dva vodiče (hodiny a data) buzené výstupy s&nbsp;otevřeným
kolektorem. Komunikace je obousměrná. Protože signalizační napětí
těchto rozhraní může být větší, než je +3.3V, je zde osazen omezovací
obvod s&nbsp;tranzistorem FET, který zajistí, že napětí na vstupu FPGA
nikdy nepřekročí napájecí napětí.
</p>
<p>
<img width="334" height="296"
src="S3AN01B_HW_Reference.cs_soubory/image010.png"
alt="Schéma ochrannýcj obvodů pro PS/2 port">
<img width="318" height="296"
src="S3AN01B_HW_Reference.cs_soubory/image011.png"
alt="Schéma ochranných obvodů pro I2C port">
</p>
<h3> VGA port </h3>
<p>
Pro připojení VGA monitoru k&nbsp;desce je zde realizováno triviální
VGA rozhraní. Využívá se jen 4 úrovní (2 bity) pro každou základní
barvu (tedy celkem 64 barev). Převod na analogové úrovně je realizován
pomocí rezistorové sítě. Deska je osazena standardním VGA konektorem
DB15.
</p>
<p>
<img width="348" height="516"
src="S3AN01B_HW_Reference.cs_soubory/image012.png"
alt="Schéma VGA portu">
</p>
<h3> Diferenciální signály </h3>
<p>
Protože obvod FPGA řady Spartan3A/3AN podporuje diferenciální signály,
je několik těchto signálů vyvedeno na konektor. Hledal jsem vhodný
konektor a na konec jsem použil konektor SATA, protože jej lze snadno
získat ze šrotu. Standardně se tyto konektory neosazují. Signály
z&nbsp;těchto konektorů jsou připojeny na vývody obvodu FPGA, které
mohou sloužit i jako hodinové vstupy.
</p>
<p>
<img width="332" height="196"
src="S3AN01B_HW_Reference.cs_soubory/image013.png"
alt="Konektory pro diferenciální signály">
<img width="158" height="110"
src="S3AN01B_HW_Reference.cs_soubory/image014.png"
alt="Hřebínek pro diferenciální signály">
</p>
<p>
Další diferenciální signály jsou vyvedeny na hřebínek J7 k&nbsp;volnému
použití.
</p>
<p>
Protože jsou pro diferenciální signály využity banky 0 a 2, mohou být
použity jako vstupní i výstupní. Banky 1 a 3 mají naproti tomu silnější
výstupní budiče ale nepodporují diferenciální výstupy. Něco za něco.
</p>
<h3> 5V tolerantní vstupy </h3>
<p>
Protože obvod FPGA samotný (stejně jako všechny novější a rychlejší
obvody) nesnese na svých vstupech 5V signály, použili jsme na desce
vstupní budiče SN74LVC16244, které poskytují 2x16 vstupů. Jsou to
obvody U11 a U12 a prvních 22 signálů je připojeno rovnou na vstupy
FPGA (zbývajících 10 signálů je vyvedeno na hřebínky). Kdo nepotřebuje
5V tolerantní vstupy, nemusí tyto obvody vůbec osazovat.
</p>
<p>
Vstupní budiče je možné po čtveřicích (nibble) aktivovat propojkami J13
až J20. Zkratovací propojka povoluje příslušnou čtveřici budičů
(otevírá třístavový výstup obvodu SN74LVC16244).
</p>
<p>
<i>Použité budiče nemají na vstupu ochranné diody do
plusu! Nesmějí se tedy budit signály většími než 5V a to ani přes velký
sériová rezistor.</i>
</p>
<p>
Aby byla definována logická úroveň na vstupu budičů, jsou na všech
vstupech rezistory 100KΩ do země.
</p>
<p>
<img width="642" height="690"
src="S3AN01B_HW_Reference.cs_soubory/image015.png"
alt="Schéma převodníku 5V signálů - první část">
</p>
<p>
<img width="642" height="672"
src="S3AN01B_HW_Reference.cs_soubory/image016.png"
alt="Schéma převodníku 5V signálů - druhá část">
</p>
<h3> Analogové obvody </h3>
<p>
Pro pokusy s&nbsp;analogovými obvody je na desce osazen zesilovač
s&nbsp;dolní propustí a komparátor. Lze tak realizovat jednoduchý D/A i
A/D převodník. Viz aplikační poznámky XILINX XAPP154 a XAPP155. Nicméně
neočekávejte zázraky, poctivý převodník tím nenhradíte.
</p>
<p>
<img width="669" height="279"
src="S3AN01B_HW_Reference.cs_soubory/image017.png"
alt="Schéma A/D a D/A analogových obvodů">
</p>
<h2> Mechanická konstrukce </h2>
<p>
Vývojová deska má standardní rozměry a upevňovací šrouby v&nbsp;rozích
jako ostatní desky stavebnice MLAB.
</p>
<h1> Osazení a oživení </h1>
<h2> Osazení </h2>
<p>
Pro osazování je vhodné použít mikropáječku a postupovat obezřetně
z&nbsp;hlediska elektrostatického náboje. Dále je potřeba jemná pinzeta
a další obvyklé nářadí.
</p>
<p>
Při osazování je vhodné nejprve osadit obvody napájecích zdrojů U2 a U3
a SMD součástky okolo nich. Poté je vhodné připojit +5V na vstup a
zkontrolovat výstupní napětí +3.3V a +1.2V dokud nemáme osazeny další
obvody.
</p>
<p>
Poté osadíme obvod FPGA U1 a obvody budičů U11 a U12. Tyto obvody
osazujeme s&nbsp;velkou pečlivostí, protože mají hodně vývodů
s&nbsp;malou roztečí. Používáme minimální množství pájky a vhodné
pastovité tavidlo. Obvod vždy nejprve připájíme za 2 protilehlé nožičky
a teprve poté, co se ujistíme, že jsou obvody umístěny na všech
stranách správně postupně zapájíme všechny vývody. Po osazení
zkontrolujeme pod lupou kvalitu pájení a zda nejsou zkraty mezi vývody.
</p>
<p>
Pak osadíme zbývající SMD součástky podle schématu a osazovacího plánu.
Pak následují klasické součástky. Začínáme LED displejem, všemi
hřebínky a nakonec konektory pro PS/2 a VGA port.
</p>
<p>
Na závěr desku opticky zkontrolujeme (orientace součástek, zkraty,
zapomenuté spoje a podobně) a přišroubujeme rohové šrouby se sloupky.
Poslední operací je umytí zbytků tavidla, vysušení a finální optická
kontrola.
</p>
<h3> Osazovací plán, horní strana </h3>
<p>
<img width="676" height="737"
src="S3AN01B_HW_Reference.cs_soubory/image018.jpg"
alt="Osazení - strana součástek">
</p>
<h3> Osazovací plán, spodní strana </h3>
<p>
<img width="677" height="737"
src="S3AN01B_HW_Reference.cs_soubory/image019.jpg"
alt="Osazení - strana spojů">
</p>
<h3> Seznam součástek </h3>
<table class="Soupiska">
<tr>
<th> Počet </th>
<th> Reference </th>
<th> Hodnota </th>
<th> Pouzdro </th>
<th> Poznámka </th>
</tr>
<tr>
<th colspan="5"> Rezistory </th>
</tr>
<tr>
<td> 1 </td>
<td> R28 </td>
<td> 0R </td>
<td> &nbsp; </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 20 </td>
<td> R1-R10, R66, R67, R81-R88 </td>
<td> 100 </td>
<td> R0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 3 </td>
<td> R59, R62, R65 </td>
<td> 120 </td>
<td> R0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 3 </td>
<td> R58, R61, R64 </td>
<td> 270 </td>
<td> R0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 22 </td>
<td> R12, R14, R29, R30-R40, R49-R56 </td>
<td> 390 </td>
<td> R0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 3 </td>
<td> R57, R60, R63 </td>
<td> 510 </td>
<td> R0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 9 </td>
<td> R11, R41-R48 </td>
<td> 820 </td>
<td> R0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 1 </td>
<td> R80 </td>
<td> 1k2 </td>
<td> R0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 4 </td>
<td> R16, R17, R18, R19 </td>
<td> 3k3 </td>
<td> R0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 21 </td>
<td> R13, R15, R20-R27, R68, R70, R72-R79, R89 </td>
<td> 4k7 </td>
<td> R0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 2 </td>
<td> R69, R71 </td>
<td> #4k7 </td>
<td> R0805 </td>
<td> Neosazuje se </td>
</tr>
<tr>
<td> 32 </td>
<td> R100-R131 </td>
<td> 100k </td>
<td> R0603 </td>
<td> &nbsp; </td>
</tr>
<tr>
<th colspan="5"> Kondenzátory keramické </th>
</tr>
<tr>
<td> 3 </td>
<td> C20-C22 </td>
<td> 4n7 </td>
<td> C0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 1 </td>
<td> C34 </td>
<td> 10nF </td>
<td> C0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 27 </td>
<td> C4-C19, C23-C33 </td>
<td> 100nF </td>
<td> C0805 </td>
<td> &nbsp; </td>
</tr>
<tr>
<th colspan="5"> Kondenzátory tantalové </th>
</tr>
<tr>
<td> 3 </td>
<td> C1, C2, C3 </td>
<td> 22uF/6.3V </td>
<td> ELYTB </td>
<td> &nbsp; </td>
</tr>
<tr>
<th colspan="5"> Diody </th>
</tr>
<tr>
<td> 1 </td>
<td> D9 </td>
<td> 1N5820 </td>
<td> DO201 </td>
<td> &nbsp; </td>
</tr>
<tr>
<th colspan="5"> Diody LED a displeje LED </th>
</tr>
<tr>
<td> 10 </td>
<td> D0-D8, D10 </td>
<td> LED3mm_RED </td>
<td> LED3 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 2 </td>
<td> LD0, LD1 </td>
<td> FT-M514RD </td>
<td> 4LED7_12PIN_14_2 </td>
<td> &nbsp; </td>
</tr>
<tr>
<th colspan="5"> Tranzistory </th>
</tr>
<tr>
<td> 8 </td>
<td> Q0-Q7 </td>
<td> BC856 </td>
<td> SOT23 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 6 </td>
<td> Q8-Q13 </td>
<td> BS170SMD </td>
<td> SOT23 </td>
<td> &nbsp; </td>
</tr>
<tr>
<th colspan="5"> Integrované obvody </th>
</tr>
<tr>
<td> 1 </td>
<td> U1 </td>
<td> XC3S50AN-4TQG144C </td>
<td> TQFP144 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 1 </td>
<td> U2 </td>
<td> AP1086K33G-13 </td>
<td> TO263 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 1 </td>
<td> U3 </td>
<td> TS1117BCP12R0 </td>
<td> TO252 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 1 </td>
<td> U4 </td>
<td> CFPS-73-100M </td>
<td> SG8002 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 1 </td>
<td> U5 </td>
<td> AT45DB011D-SSH-B </td>
<td> SO8_150 </td>
<td> Volitelné </td>
</tr>
<tr>
<td> 1 </td>
<td> U6 </td>
<td> AT45DB011D-SH-B </td>
<td> SO8_210 </td>
<td> Volitelné </td>
</tr>
<tr>
<td> 1 </td>
<td> U7 </td>
<td> AT25DF0xxA-SSH </td>
<td> SO8_150 </td>
<td> Volitelné </td>
</tr>
<tr>
<td> 1 </td>
<td> U8 </td>
<td> SST24LF040A-33-4C-S2AE </td>
<td> SO8_210 </td>
<td> Volitelné </td>
</tr>
<tr>
<td> 1 </td>
<td> U9 </td>
<td> MCP6001T-I/OT </td>
<td> SOT23-5 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 1 </td>
<td> U10 </td>
<td> MCP6546T-E/OT </td>
<td> SOT23-5 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 2 </td>
<td> U11, U12 </td>
<td> SN74LVC16244ADL </td>
<td> SSOIII_48_300 </td>
<td> &nbsp; </td>
</tr>
<tr>
<th colspan="5"> Mechanické součástky </th>
</tr>
<tr>
<td> 4 </td>
<td> SW0-SW3 </td>
<td> PUSH050x050 </td>
<td> PUSH050x050 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 1 </td>
<td> SW4 </td>
<td> DIPSW8 </td>
<td> DIPSW8 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 12 </td>
<td> Propojka </td>
<td> &nbsp; </td>
<td> &nbsp; </td>
<td> &nbsp; </td>
</tr>
<tr>
<th colspan="5"> Konektory </th>
</tr>
<tr>
<td> 1 </td>
<td> J27 </td>
<td> DB15F_3L_90 </td>
<td> DB15F_3L_90 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 2 </td>
<td> J31, J32 </td>
<td> MINIDIN6_PS2 </td>
<td> MINIDIN6 </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 2 </td>
<td> J28, J29 </td>
<td> #SATA_DATA </td>
<td> SATA_DATA </td>
<td> Neosazuje se </td>
</tr>
<tr>
<th colspan="5"> Jednořadé hřebínky </th>
</tr>
<tr>
<td> 1 </td>
<td> J33+J34+J35+J36+J37+J38 </td>
<td> JUMP9 </td>
<td> JUMP9 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 1 </td>
<td> J22 </td>
<td> #JUMP1 </td>
<td> JUMP1 </td>
<td> Neosazuje se </td>
</tr>
<tr>
<td> 9 </td>
<td> J6, J13, J14, J15, J16, J17, J18, J19, J20 </td>
<td> JUMP2 </td>
<td> JUMP2 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 1 </td>
<td> J30 </td>
<td> JUMP4 </td>
<td> JUMP4 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 3 </td>
<td> J12, J21, J100 </td>
<td> JUMP10 </td>
<td> JUMP10 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 1 </td>
<td> J10 </td>
<td> JUMP22 </td>
<td> JUMP22 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 1 </td>
<td> J3 </td>
<td> JUMP9_X3_X5_X8</td>
<td> JUMP9_X3_X5_X8</td>
<td> Nalámat </td>
</tr>
<tr>
<th colspan="5"> Douřadé hřebínky </th>
</tr>
<tr>
<td> 1 </td>
<td> J24 </td>
<td> JUMP2X2 </td>
<td> JUMP2X2 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 5 </td>
<td> J1, J2, J4, J5, J8 </td>
<td> JUMP2X3 </td>
<td> JUMP2X3 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 1 </td>
<td> J7 </td>
<td> JUMP2X4 </td>
<td> JUMP2X4 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 2 </td>
<td> J25, J26 </td>
<td> JUMP2X8 </td>
<td> JUMP2X8 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 1 </td>
<td> J11 </td>
<td> JUMP2X10 </td>
<td> JUMP2X10 </td>
<td> Nalámat </td>
</tr>
<tr>
<td> 2 </td>
<td> J9, J23 </td>
<td> JUMP2X22 </td>
<td> JUMP2X22 </td>
<td> Nalámat </td>
</tr>
<tr>
<th colspan="5"> Konstrukční součástky </th>
</tr>
<tr>
<td> 1 </td>
<td> Plošný spoj </td>
<td> PCB S3AN01B </td>
<td> &nbsp; </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 4 </td>
<td> Šroub M3x12mm křížový, válcová hlava, pozinkovaný </td>
<td> &nbsp; </td>
<td> &nbsp; </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 4 </td>
<td> Matice M3, pozinkovaná </td>
<td> &nbsp; /td>
<td> &nbsp; </td>
<td> &nbsp; </td>
</tr>
<tr>
<td> 4 </td>
<td> Podložka M3, pozinkovaná </td>
<td> &nbsp; </td>
<td> &nbsp; </td>
<td> &nbsp; </td>
</tr>
</table>
<h2> Oživení </h2>
<h3> První zapnutí </h3>
<p>
Prvním krokem je připojení k&nbsp;laboratornímu zdroji a kontrola
funkčnosti napájecích zdrojů. Postupně zvyšujeme napájecí napětí až
k&nbsp;hranici +5V a měříme spotřebu (orientačně) a napětí na vnitřních
stabilizátorech U2 a U3. Vnitřní napájecí napětí jsou +3.3V a +1.2V
(mohou se lišit řekněme o desítky milivoltů). Spotřeba desky bez
nahrané konfigurace je cca 50-60mA.
</p>
<p>
Nyní je třeba ověřit, zda pracují ochranné obvody na PS/2 portech.
Měříme napětí na Q10.D, které má být cca +5V a Q10.S, které má být o
něco menší, než +3.3V. Toto měření opakujeme pro všechny 4 tranzistory,
tedy pro Q10 až Q13.
</p>
<p>
Podobně zkontrolujeme i ochranné obvody I²C portu. Jen je třeba
z&nbsp;vnějšku připojit +4V na hřebínek J30.2 a J30.3 a měřit na
tranzistorech Q8 a Q9. Opět se nesmí směrem k&nbsp;FPGA dostávat napětí
větší, než je napájení +3.3V.
</p>
<h3> Testovací obsah </h3>
<p>
Protože samotný obvod FPGA bez nahrané konfigurace je „mrtvým broukem“
je pro další oživování a testování potřeba použít nějaký vhodný obsah,
aby bylo možno otestovat celou funkčnost desky. Testování desky je
popsáno v&nbsp;dokumentu S3AN01B_HW_Test.
</p>
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M2 PAD,HOLE_M3@HOLE_M3
M3 PAD,HOLE_M3@HOLE_M3
M4 PAD,HOLE_M3@HOLE_M3
M5 FIDU,FIDU@FIDU
M6 FIDU,FIDU@FIDU
M7 FIDU,FIDU@FIDU
M8 FIDU,FIDU@FIDU
M9 FIDU_PASTE,FIDU_PASTE@FIDU_PASTE
Q0 T-BEC,BC856@SOT23
Q1 T-BEC,BC856@SOT23
Q10 T-FET-GSD,BS170SMD@SOT23
Q11 T-FET-GSD,BS170SMD@SOT23
Q12 T-FET-GSD,BS170SMD@SOT23
Q13 T-FET-GSD,BS170SMD@SOT23
Q2 T-BEC,BC856@SOT23
Q3 T-BEC,BC856@SOT23
Q4 T-BEC,BC856@SOT23
Q5 T-BEC,BC856@SOT23
Q6 T-BEC,BC856@SOT23
Q7 T-BEC,BC856@SOT23
Q8 T-FET-GSD,BS170SMD@SOT23
Q9 T-FET-GSD,BS170SMD@SOT23
R1 R,100@R0805
R10 R,100@R0805
R100 R,100k@R0603
R101 R,100k@R0603
R102 R,100k@R0603
R103 R,100k@R0603
R104 R,100k@R0603
R105 R,100k@R0603
R106 R,100k@R0603
R107 R,100k@R0603
R108 R,100k@R0603
R109 R,100k@R0603
R11 R,820@R0805
R110 R,100k@R0603
R111 R,100k@R0603
R112 R,100k@R0603
R113 R,100k@R0603
R114 R,100k@R0603
R115 R,100k@R0603
R116 R,100k@R0603
R117 R,100k@R0603
R118 R,100k@R0603
R119 R,100k@R0603
R12 R,390@R0805
R120 R,100k@R0603
R121 R,100k@R0603
R122 R,100k@R0603
R123 R,100k@R0603
R124 R,100k@R0603
R125 R,100k@R0603
R126 R,100k@R0603
R127 R,100k@R0603
R128 R,100k@R0603
R129 R,100k@R0603
R13 R,4k7@R0805
R130 R,100k@R0603
R131 R,100k@R0603
R14 R,390@R0805
R15 R,4k7@R0805
R16 R,3k3@R0805
R17 R,3k3@R0805
R18 R,3k3@R0805
R19 R,3k3@R0805
R2 R,100@R0805
R20 R,4k7@R0805
R21 R,4k7@R0805
R22 R,4k7@R0805
R23 R,4k7@R0805
R24 R,4k7@R0805
R25 R,4k7@R0805
R26 R,4k7@R0805
R27 R,4k7@R0805
R28 R,0R@R0805
R29 R,390@R0805
R3 R,100@R0805
R30 R,390@R0805
R31 R,390@R0805
R32 R,390@R0805
R33 R,390@R0805
R34 R,390@R0805
R35 R,390@R0805
R36 R,390@R0805
R37 R,390@R0805
R38 R,390@R0805
R39 R,390@R0805
R4 R,100@R0805
R40 R,390@R0805
R41 R,820@R0805
R42 R,820@R0805
R43 R,820@R0805
R44 R,820@R0805
R45 R,820@R0805
R46 R,820@R0805
R47 R,820@R0805
R48 R,820@R0805
R49 R,390@R0805
R5 R,100@R0805
R50 R,390@R0805
R51 R,390@R0805
R52 R,390@R0805
R53 R,390@R0805
R54 R,390@R0805
R55 R,390@R0805
R56 R,390@R0805
R57 R,510@R0805
R58 R,270@R0805
R59 R,120@R0805
R6 R,100@R0805
R60 R,510@R0805
R61 R,270@R0805
R62 R,120@R0805
R63 R,510@R0805
R64 R,270@R0805
R65 R,120@R0805
R66 R,100@R0805
R67 R,100@R0805
R68 R,4k7@R0805
R69 R,#4k7@R0805
R7 R,100@R0805
R70 R,4k7@R0805
R71 R,#4k7@R0805
R72 R,4k7@R0805
R73 R,4k7@R0805
R74 R,4k7@R0805
R75 R,4k7@R0805
R76 R,4k7@R0805
R77 R,4k7@R0805
R78 R,4k7@R0805
R79 R,4k7@R0805
R8 R,100@R0805
R80 R,1k2@R0805
R81 R,100@R0805
R82 R,100@R0805
R83 R,100@R0805
R84 R,100@R0805
R85 R,100@R0805
R86 R,100@R0805
R87 R,100@R0805
R88 R,100@R0805
R89 R,4k7@R0805
R9 R,100@R0805
SW0 PB4PIN,PUSH050x050@PUSH050x050
SW1 PB4PIN,PUSH050x050@PUSH050x050
SW2 PB4PIN,PUSH050x050@PUSH050x050
SW3 PB4PIN,PUSH050x050@PUSH050x050
SW4 DIPSW8,DIPSW8@DIPSW8
TPS1 TP,TPS@TPS
TPS2 TP,TPS@TPS
TPS3 TP,TPS@TPS
TPS4 TP,TPS@TPS
TPS5 TP,TPS@TPS
TPS6 TP,TPS@TPS
U1 TQFP144,XC3S50AN-4TQG144C@TQFP144
U10 SOT23-5,MCP6546T-E/OT@SOT23-5
U11 SSOIII_48_300,SN74LVC16244ADL@SSOIII_48_300
U12 SSOIII_48_300,SN74LVC16244ADL@SSOIII_48_300
U2 TO263,AP1086K33G-13@TO263
U3 TO252,TS1117BCP12R0@TO252
U4 XOSC,CFPS-73-100M@SG8002
U5 SO8_150,AT45DB011D-SSH-B@SO8_150
U6 SO8_210,AT45DB011D-SH-B@SO8_210
U7 SO8_150,AT25DF0xxA-SSH@SO8_150
U8 SO8_210,SST24LF040A-33-4C-S2AE@SO8_210
U9 SOT23-5,MCP6001T-I/OT@SOT23-5
*NET*
*SIGNAL* IP12
U11.43 J9.25 J9.26 R112.2
*SIGNAL* DIF1N
U1.111 J7.3
*SIGNAL* N24251
SW2.1 R31.2
*SIGNAL* IP13
J9.27 J9.28 U11.44 R113.2
*SIGNAL* DIF2P
U1.112 J7.5
*SIGNAL* N24231
SW0.1 R29.2
*SIGNAL* IP14
J9.29 J9.30 U11.46 R114.2
*SIGNAL* DIF1P
U1.110 J7.1
*SIGNAL* N24253
SW3.1 R32.2
*SIGNAL* IP15
U11.47 J9.31 J9.32 R115.2
*SIGNAL* DIF2N
U1.113 J7.7
*SIGNAL* N24249
SW1.1 R30.2
*SIGNAL* IP16
U12.26 J9.33 J9.34 R116.2
*SIGNAL* N07427
SW4.5 R36.2
*SIGNAL* IP17
J9.35 J9.36 U12.27 R117.2
*SIGNAL* N07433
SW4.4 R37.2
*SIGNAL* IP18
J9.37 J9.38 U12.29 R118.2
*SIGNAL* N07415
SW4.7 R34.2
*SIGNAL* IP19
U12.30 J9.39 J9.40 R119.2
*SIGNAL* N07409
SW4.8 R33.2
*SIGNAL* IP20
J9.41 J9.42 U12.32 R120.2
*SIGNAL* N07451
R40.2 SW4.1
*SIGNAL* IP21
U12.33 J9.43 J9.44 R121.2
*SIGNAL* N07445
SW4.2 R39.2
*SIGNAL* IX22
J11.1 J11.2 U12.35 R122.2
*SIGNAL* N07421
R35.2 SW4.6
*SIGNAL* IX23
U12.36 J11.3 J11.4 R123.2
*SIGNAL* N07439
R38.2 SW4.3
*SIGNAL* IX24
U12.37 J11.5 J11.6 R124.2
*SIGNAL* IX25
J11.7 J11.8 U12.38 R125.2
*SIGNAL* IX26
U12.40 J11.9 J11.10 R126.2
*SIGNAL* IX27
J11.11 J11.12 U12.41 R127.2
*SIGNAL* IX28
J11.13 J11.14 U12.43 R128.2
*SIGNAL* IX29
U12.44 J11.15 J11.16 R129.2
*SIGNAL* IX30
J11.17 J11.18 U12.46 R130.2
*SIGNAL* N51046
R14.1 D10.A
*SIGNAL* VGA_HS
U1.11 R66.2
*SIGNAL* IX31
J11.19 J11.20 U12.47 R131.2
*SIGNAL* VGA_G0
U1.5 R60.2
*SIGNAL* PB1
U1.120 R30.1
*SIGNAL* X31
U12.2 J21.10
*SIGNAL* VGA_G1
U1.6 R61.2
*SIGNAL* PB2
U1.117 R31.1
*SIGNAL* X30
J21.9 U12.3
*SIGNAL* VGA_B0
U1.7 R63.2
*SIGNAL* PB0
U1.121 R29.1
*SIGNAL* X29
J21.8 U12.5
*SIGNAL* VGA_R0
U1.3 R57.2
*SIGNAL* PB3
U1.116 R32.1
*SIGNAL* X28
J21.7 U12.6
*SIGNAL* VGA_R1
U1.4 R58.2
*SIGNAL* X27
J21.6 U12.8
*SIGNAL* VGA_B1
U1.8 R64.2
*SIGNAL* X26
J21.5 U12.9
*SIGNAL* VGA_VS
U1.10 R67.2
*SIGNAL* X25
J21.4 U12.11
*SIGNAL* VGA_RED
J27.1 R57.1 R58.1 R59.2
*SIGNAL* X24
J21.3 U12.12
*SIGNAL* VGA_GREEN
J27.2 R60.1 R62.2 R61.1
*SIGNAL* X23
J21.2 U12.13
*SIGNAL* VGA_BLUE
J27.3 R63.1 R64.1 R65.2
*SIGNAL* X22
J21.1 U12.14
*SIGNAL* P0
U1.75 U11.23 J23.1 J23.2
*SIGNAL* P2
U1.77 J23.5 J23.6 U11.20
*SIGNAL* P1
J23.3 J23.4 U11.22 U1.76
*SIGNAL* P3
U11.19 J23.7 J23.8 U1.78
*SIGNAL* P4
U1.82 J23.9 J23.10 U11.17
*SIGNAL* P5
U1.83 J23.11 J23.12 U11.16
*SIGNAL* P6
U11.14 U1.84 J23.13 J23.14
*SIGNAL* P7
U11.13 U1.85 J23.15 J23.16
*SIGNAL* P8
U1.87 U11.12 J23.17 J23.18
*SIGNAL* P9
U1.88 J23.19 J23.20 U11.11
*SIGNAL* P10
U1.90 U11.9 J23.21 J23.22
*SIGNAL* N10957
J27.13 R66.1
*SIGNAL* P11
U11.8 J23.23 J23.24 U1.91
*SIGNAL* N10968
J27.14 R67.1
*SIGNAL* P12
U1.92 U11.6 J23.25 J23.26
*SIGNAL* P13
J23.27 J23.28 U11.5 U1.93
*SIGNAL* P14
U11.3 J23.29 J23.30 U1.96
*SIGNAL* P15
U1.98 U11.2 J23.31 J23.32
*SIGNAL* N05189
R56.1 D7.A
*SIGNAL* P16
J23.33 J23.34 U12.23 U1.99
*SIGNAL* N06136
R55.1 D6.A
*SIGNAL* P17
U1.101 J23.35 J23.36 U12.22
*SIGNAL* N06223
R54.1 D5.A
*SIGNAL* P18
U1.102 U12.20 J23.37 J23.38
*SIGNAL* N02505
J3.9 R4.1
*SIGNAL* N06313
R53.1 D4.A
*SIGNAL* P19
J23.39 J23.40 U1.103 U12.19
*SIGNAL* N02508
J3.7 R3.1
*SIGNAL* N06394
R52.1 D3.A
*SIGNAL* P20
U12.17 J23.41 J23.42 U1.104
*SIGNAL* N02511
J3.6 R2.1
*SIGNAL* N06476
R51.1 D2.A
*SIGNAL* P21
U12.16 U1.105 J23.43 J23.44
*SIGNAL* N02521
J3.4 R1.1
*SIGNAL* DONE
J36.1 R12.2 U1.73
*SIGNAL* N06557
R50.1 D1.A
*SIGNAL* P22
U1.79 J24.1 J24.2
*SIGNAL* TMS
U1.1 R4.2
*SIGNAL* N06657
R49.1 D0.A
*SIGNAL* P23
U1.80 U1.97 J24.3 J24.4
*SIGNAL* TCK
U1.109 R1.2
*SIGNAL* LED7
U1.46 J26.15 J26.16 R56.2
*SIGNAL* TDO
U1.107 R2.2
*SIGNAL* LED5
U1.48 R54.2 J26.11 J26.12
*SIGNAL* TDI
U1.2 R3.2
*SIGNAL* LED6
U1.47 J26.13 J26.14 R55.2
*SIGNAL* PROG
J6.1 U1.144
*SIGNAL* LED4
U1.49 J26.9 J26.10 R53.2
*SIGNAL* LED3
U1.50 J26.7 J26.8 R52.2
*SIGNAL* LED2
U1.51 J26.5 J26.6 R51.2
*SIGNAL* LED0
U1.64 J26.1 J26.2 R49.2
*SIGNAL* LED1
U1.63 R50.2 J26.3 J26.4
*SIGNAL* N03324
R13.2 U1.74
*SIGNAL* N30971
Q1.C LD0.8
*SIGNAL* N58963
R73.1 J31.1 Q10.D
*SIGNAL* N31019
Q2.C LD0.9
*SIGNAL* N58687
J31.5 R75.1 Q11.D
*SIGNAL* N30951
Q0.C LD0.6
*SIGNAL* N59441
Q12.D R77.1 J32.1
*SIGNAL* N31013
R43.1 Q2.B
*SIGNAL* N59451
R79.1 Q13.D J32.5
*SIGNAL* PS2_DATA1
U1.130 Q10.S R72.1
*SIGNAL* N30989
R42.1 Q1.B
*SIGNAL* PS2_CLK1
U1.127 R74.1 Q11.S
*SIGNAL* N31009
Q3.C LD0.12
*SIGNAL* PS2_CLK2
U1.42 R78.1 Q13.S
*SIGNAL* PS2_DATA2
U1.58 R76.1 Q12.S
*SIGNAL* N30985
R41.1 Q0.B
*SIGNAL* I2C_SCL
U1.115 R68.1 Q8.S
*SIGNAL* N61543
Q8.D R69.1 J30.2
*SIGNAL* I2C_SDA
U1.114 R70.1 Q9.S
*SIGNAL* N61555
J30.3 Q9.D R71.1
*SIGNAL* N128209
J6.2 R11.2
*SIGNAL* ANA_IND
U1.69 R19.2 U10.1
*SIGNAL* N03524
R12.1 D8.A
*SIGNAL* N118416
R18.1 U10.3 C22.2
*SIGNAL* ANA_IN
R18.2 J8.5
*SIGNAL* ANA_REF
U10.4 C21.2 R17.1 J8.3
*SIGNAL* ANA_OUTD
U1.67 J37.1 R80.2
*SIGNAL* SPI_WP#
U6.5 U5.5 U8.3 U7.3 R15.1 U1.70
*SIGNAL* ANA_OUT
J8.1 C34.1 U9.1 U9.4
*SIGNAL* N09709
J5.2 R8.1
*SIGNAL* ANA_REFD
U1.68 R17.2
*SIGNAL* N09715
J5.4 R9.1
*SIGNAL* N09721
J5.6 R10.1
*SIGNAL* N0
U11.24 J13.1 R20.2
*SIGNAL* N1
J14.1 U11.25 R21.2
*SIGNAL* N2
J15.1 U11.48 R22.2
*SIGNAL* N3
U11.1 J16.1 R23.2
*SIGNAL* N4
U12.24 J17.1 R24.2
*SIGNAL* N5
U12.25 J18.1 R25.2
*SIGNAL* N6
J19.1 U12.48 R26.2
*SIGNAL* N7
U12.1 J20.1 R27.2
*SIGNAL* N119011
R16.1 U9.3 C20.2
*SIGNAL* LD_CA0#
U1.25 R41.2
*SIGNAL* LD_CA4#
U1.27 R45.2
*SIGNAL* LD_CA5#
U1.29 R46.2
*SIGNAL* LD_CA6#
U1.28 R47.2
*SIGNAL* LD_CA1#
U1.31 R42.2
*SIGNAL* LD_CA2#
U1.32 R43.2
*SIGNAL* LD_CA3#
U1.13 R44.2
*SIGNAL* LD_CA7#
U1.12 R48.2
*SIGNAL* LD_SEG0#
R81.2 U1.15
*SIGNAL* DIPSW3
U1.139 J25.7 J25.8 R36.1
*SIGNAL* LD_SEG5#
R86.2 U1.16
*SIGNAL* DIPSW2
U1.140 R35.1 J25.5 J25.6
*SIGNAL* LD_SEG4#
U1.18 R85.2
*SIGNAL* DIPSW5
U1.135 R38.1 J25.11 J25.12
*SIGNAL* LD_SEG7#
U1.20 R88.2
*SIGNAL* DIPSW4
U1.138 R37.1 J25.9 J25.10
*SIGNAL* LD_SEG3#
U1.19 R84.2
*SIGNAL* DIPSW7
U1.132 R40.1 J25.15 J25.16
*SIGNAL* VDD_5V
U2.2 C1.A D9.C J1.3 J1.4 J32.4 J30.1 R69.2
R79.2 R75.2 R71.2 J31.4 R73.2 R77.2
*SIGNAL* LD_SEG6#
R87.2 U1.24
*SIGNAL* DIPSW1
U1.142 R34.1 J25.3 J25.4
*SIGNAL* VDD_1V2
U1.122 U1.22 U1.52 U1.94 C8.2 C5.2 C7.2 C6.2
C3.A U3.3
*SIGNAL* LD_SEG2#
U1.21 R83.2
*SIGNAL* DIPSW6
U1.134 R39.1 J25.13 J25.14
*SIGNAL* VDD_3V3
U7.7 U8.7 U8.8 C10.2 U5.3 U6.3 C15.1 U7.8
U6.6 R14.2 U3.2 J2.3 J2.4 C9.2 J100.10 C2.A
J3.1 U5.6 J33.1 C12.2 C11.2 C13.2 U1.40 C14.2
U1.36 U1.108 U1.66 U2.3 U1.133 U4.1 U4.4 C4.2
U2.4 R15.2 U1.61 R89.2 U9.5 C18.2 C19.2 U1.14
U1.23 U1.136 C17.2 U1.119 C16.2 C23.1 U10.5 R19.1
C24.2 U12.7 C31.2 C30.2 R23.1 U11.18 C27.2 C25.2
U11.42 C28.2 C29.2 C26.2 R25.1 R27.1 R21.1 R26.1
U11.31 R24.1 R22.1 U12.18 U12.42 U12.31 U11.7 R20.1
R28.2 Q4.E Q2.E Q3.E Q1.E Q7.E Q6.E Q5.E
SW4.16 SW4.15 SW4.9 R72.2 Q11.G R74.2 R76.2 Q12.G
SW4.14 SW4.13 SW4.12 SW4.11 SW4.10 R70.2 Q9.G Q10.G
Q0.E Q13.G R78.2 SW1.2 SW0.2 SW2.2 SW3.2 Q8.G
R68.2
*SIGNAL* LD_SEG1#
R82.2 U1.30
*SIGNAL* DIPSW0
U1.143 R33.1 J25.1 J25.2
*SIGNAL* GND
U1.9 U1.17 U1.26 U1.34 M1.1 U1.56 U1.65 U1.81
U1.89 U1.100 U1.106 J5.3 J5.5 U1.118 J5.1 M3.1
U1.137 C15.2 U1.128 J2.5 J2.6 J2.1 J2.2 R13.1
U3.1 C1.C J100.1 J4.1 J4.3 J4.5 D9.A U6.7
C13.1 C14.1 U5.7 J3.2 D8.C C6.1 C7.1 C8.1
C5.1 U4.2 U2.1 U7.4 U8.4 M4.1 M2.1 J38.1
J1.1 J1.2 J1.5 J1.6 C2.C D10.C C4.1 C3.C
R11.1 C9.1 C12.1 C11.1 C10.1 C16.1 J8.2 J8.4
J8.6 C17.1 C22.1 U10.2 J7.2 J7.4 J7.6 J7.8
C20.1 C18.1 C19.1 C23.2 U9.2 C21.1 U12.10 J12.8
C25.1 J13.2 U12.4 J12.5 J10.21 J10.4 J10.3 J12.1
J12.4 J12.10 J10.5 J18.2 C32.1 R116.1 R117.1 R118.1
R119.1 R120.1 R121.1 R122.1 R123.1 R110.1 R115.1 R108.1
R113.1 R112.1 R109.1 R114.1 R111.1 R105.1 R100.1 R103.1
R102.1 R106.1 R104.1 R101.1 R107.1 R126.1 R131.1 R124.1
R129.1 R128.1 R125.1 R130.1 R127.1 U12.45 C33.1 C28.1
J12.9 J17.2 J10.9 J10.8 J10.16 J19.2 J14.2 U11.39
J15.2 U11.28 C24.1 C31.1 U11.34 U12.15 U11.4 J10.18
J10.2 J10.1 J12.3 J10.12 J10.22 C27.1 J20.2 J10.13
U12.28 U11.21 U11.45 J12.2 J10.20 C26.1 J10.6 U11.10
U12.39 J10.14 J10.11 J12.6 J10.10 J10.15 J10.7 J12.7
U12.34 J10.19 U11.15 U12.21 J10.17 J16.2 C30.1 C29.1
D4.C D3.C D1.C D5.C J30.4 J28.4 J28.8 J28.7
J28.1 J28.9 J31.3 J29.9 J29.1 J29.4 J29.7 J29.8
J27.10 J27.8 J27.6 J27.7 J27.5 D7.C R59.1 R65.1
R62.1 D6.C D0.C D2.C J27.16 J27.17 J32.3
*SIGNAL* N01338
R7.1 J4.6
*SIGNAL* N01352
J4.4 R6.1
*SIGNAL* N01358
J4.2 R5.1
*SIGNAL* M2
R7.2 U1.39
*SIGNAL* M1
R6.2 U1.37
*SIGNAL* M0
R5.2 U1.38
*SIGNAL* CLK100MHZ
U1.60 U4.3
*SIGNAL* VS2
R10.2 U1.43
*SIGNAL* VS1
R9.2 U1.44
*SIGNAL* VS0
R8.2 U1.45
*SIGNAL* N197552
R48.1 Q7.B
*SIGNAL* N197801
R44.1 Q3.B
*SIGNAL* LD_SEG5#R
R86.1 LD1.10 LD0.10
*SIGNAL* LD_SEG2#R
R83.1 LD0.4 LD1.4
*SIGNAL* LD_SEG7#R
R88.1 LD1.3 LD0.3
*SIGNAL* LD_SEG6#R
R87.1 LD1.5 LD0.5
*SIGNAL* LD_SEG1#R
R82.1 LD0.7 LD1.7
*SIGNAL* LD_SEG0#R
R81.1 LD0.11 LD1.11
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/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/!____!.txt
0,0 → 1,27
Deska: S3AN01B
Rozmìr: cca 112x122mm
Poèet vrstev: 2 (35um) prokov
Materiál: FR4 1.6mm
Nepájivá maska: 2x
Potisk: 1x
Povrchová úprava: HAL
Podklady Gerber/Excellon. Míry v MILS, vše v pohledu ze strany souèástí.
BOARD.PHO Obrys desky (na støed èáry)
DRILL.DRL Excellon vrtání, jednotkou jsou MILS (1/1000 inch)
DRILL.rep Rozmìry vrtání v MILS (nekritické, prùmìry po prokovení)
T1.PHO Potisk na stranì souèástí
M1.PHO Maska na stranì souèástí
V1.PHO Motiv mìdi na stranì souèástí (standard, 35um po prokovení)
V2.PHO Motiv mìdi na starnì spojù (standard, 35um po prokovení)
M2.PHO Maska na stranì spojù (obsahuje SMD souèástky)
P2.PHO Planžeta pro tisk cínové pasty pro SMD souèásti
Motiv byl navrhován s izolaèními mezerami 7 MILS (0.178mm).
Na celkem 6 místech je izolaèní mezera menší (vesmìs konektory),
styk 2 kulatých ploch. Možno ponechat nebo oøíznout.

/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/BOARD.PHO
0,0 → 1,344
*
*
G04 PADS 9.2 Build Number: 414666 generated Gerber (RS-274-X) file*
G04 PC Version=2.1*
*
%IN "S3AN01A.pcb"*%
*
%MOIN*%
*
%FSLAX35Y35*%
*
*
*
*
G04 PC Standard Apertures*
*
*
G04 Thermal Relief Aperture macro.*
%AMTER*
1,1,$1,0,0*
1,0,$1-$2,0,0*
21,0,$3,$4,0,0,45*
21,0,$3,$4,0,0,135*
%
*
*
G04 Annular Aperture macro.*
%AMANN*
1,1,$1,0,0*
1,0,$2,0,0*
%
*
*
G04 Odd Aperture macro.*
%AMODD*
1,1,$1,0,0*
1,0,$1-0.005,0,0*
%
*
*
G04 PC Custom Aperture Macros*
*
*
*
*
*
*
G04 PC Aperture Table*
*
%ADD024C,0.001*%
%ADD025C,0.01*%
*
*
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
*
G04 PC Custom Flashes*
G04 Layer Name S3AN01A.pcb - flashes*
%LPD*%
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
G54D24*
G01X111000Y111000D02*
X111003D01*
X549000D02*
X549003D01*
X549000D02*
X549003D01*
X549000Y589000D02*
X549003D01*
G54D25*
X111000Y111000D02*
X549000D01*
Y589000*
X111000*
Y111000*
Y100000D02*
X311205D01*
X111000D02*
X121000Y102500D01*
Y97500*
X111000Y100000*
X549000D02*
X348795D01*
X549000D02*
X539000Y97500D01*
Y102500*
X549000Y100000*
X111000Y106000D02*
Y95000D01*
X549000Y106000D02*
Y95000D01*
X316477Y102813D02*
X314205Y98438D01*
X314205D02*
X317614D01*
X316477Y102813D02*
Y96250D01*
X320114Y102813D02*
X322614D01*
X322614D02*
X321250Y100313D01*
X321250D02*
X321932D01*
X321932D02*
X322386Y100000D01*
X322614Y99688*
X322614D02*
X322841Y98750D01*
Y98125*
X322614Y97188*
X322614D02*
X322159Y96563D01*
X322159D02*
X321477Y96250D01*
X320795*
X320114Y96563*
X320114D02*
X319886Y96875D01*
X319659Y97500*
X326023Y102813D02*
X325341Y102500D01*
X325114Y101875*
Y101250*
X325341Y100625*
X325795Y100313*
X325795D02*
X326705Y100000D01*
X327386Y99688*
X327386D02*
X327841Y99063D01*
X327841D02*
X328068Y98438D01*
X328068D02*
Y97500D01*
X327841Y96875*
X327614Y96563*
X327614D02*
X326932Y96250D01*
X326023*
X325341Y96563*
X325341D02*
X325114Y96875D01*
X324886Y97500*
Y98438*
X324886D02*
X325114Y99063D01*
X325114D02*
X325568Y99688D01*
X325568D02*
X326250Y100000D01*
X327159Y100313*
X327159D02*
X327614Y100625D01*
X327841Y101250*
Y101875*
X327614Y102500*
X326932Y102813*
X326932D02*
X326023D01*
X331477D02*
X330795Y102500D01*
X330341Y101563*
X330341D02*
X330114Y100000D01*
Y99063*
X330114D02*
X330341Y97500D01*
X330795Y96563*
X330795D02*
X331477Y96250D01*
X331932*
X332614Y96563*
X332614D02*
X333068Y97500D01*
X333295Y99063*
X333295D02*
Y100000D01*
X333068Y101563*
X333068D02*
X332614Y102500D01*
X331932Y102813*
X331932D02*
X331477D01*
X335341Y100625D02*
Y96250D01*
Y99375D02*
X336023Y100313D01*
X336023D02*
X336477Y100625D01*
X337159*
X337614Y100313*
X337614D02*
X337841Y99375D01*
Y96250*
Y99375D02*
X338523Y100313D01*
X338523D02*
X338977Y100625D01*
X339659*
X340114Y100313*
X340114D02*
X340341Y99375D01*
Y96250*
X342386Y102813D02*
X342614Y102500D01*
X342841Y102813*
X342841D02*
X342614Y103125D01*
X342386Y102813*
X342614Y100625D02*
Y96250D01*
X344886Y102813D02*
Y96250D01*
X560000Y111000D02*
Y331205D01*
Y111000D02*
X557500Y121000D01*
X562500*
X560000Y111000*
Y589000D02*
Y368795D01*
Y589000D02*
X562500Y579000D01*
X557500*
X560000Y589000*
X554000Y111000D02*
X565000D01*
X554000Y589000D02*
X565000D01*
X557187Y336477D02*
X561562Y334205D01*
X561562D02*
Y337614D01*
X557187Y336477D02*
X563750D01*
X557187Y342841D02*
X563750Y340568D01*
X557187Y339659D02*
Y342841D01*
Y346023D02*
X557500Y345341D01*
X558125Y345114*
X558750*
X559375Y345341*
X559687Y345795*
X559687D02*
X560000Y346705D01*
X560312Y347386*
X560312D02*
X560937Y347841D01*
X560937D02*
X561562Y348068D01*
X561562D02*
X562500D01*
X563125Y347841*
X563437Y347614*
X563437D02*
X563750Y346932D01*
Y346023*
X563437Y345341*
X563437D02*
X563125Y345114D01*
X562500Y344886*
X561562*
X561562D02*
X560937Y345114D01*
X560937D02*
X560312Y345568D01*
X560312D02*
X560000Y346250D01*
X559687Y347159*
X559687D02*
X559375Y347614D01*
X558750Y347841*
X558125*
X557500Y347614*
X557187Y346932*
X557187D02*
Y346023D01*
Y351477D02*
X557500Y350795D01*
X558437Y350341*
X558437D02*
X560000Y350114D01*
X560937*
X560937D02*
X562500Y350341D01*
X563437Y350795*
X563437D02*
X563750Y351477D01*
Y351932*
X563437Y352614*
X563437D02*
X562500Y353068D01*
X560937Y353295*
X560937D02*
X560000D01*
X558437Y353068*
X558437D02*
X557500Y352614D01*
X557187Y351932*
X557187D02*
Y351477D01*
X559375Y355341D02*
X563750D01*
X560625D02*
X559687Y356023D01*
X559687D02*
X559375Y356477D01*
Y357159*
X559687Y357614*
X559687D02*
X560625Y357841D01*
X563750*
X560625D02*
X559687Y358523D01*
X559687D02*
X559375Y358977D01*
Y359659*
X559687Y360114*
X559687D02*
X560625Y360341D01*
X563750*
X557187Y362386D02*
X557500Y362614D01*
X557187Y362841*
X557187D02*
X556875Y362614D01*
X557187Y362386*
X559375Y362614D02*
X563750D01*
X557187Y364886D02*
X563750D01*
X0Y0D02*
M02*

/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.DRL
0,0 → 1,526
%
T1C.025F197S55
X01978Y01509
X01965Y02251
X0155Y0258
X0128Y0258
X0155Y0265
X0128Y0265
X01359Y04991
X01539Y04993
X01719Y04994
X01404Y0557
X02259Y03822
X02375Y03375
X02017Y02
X02168Y02
X02442Y02
X02292Y02
X02293Y0176
X02018Y0176
X02168Y0176
X02442Y0176
X02513Y01545
X02483Y02251
X02922Y02881
X02794Y02915
X02608Y03128
X02598Y03285
X02714Y03422
X02796Y0345
X02608Y03544
X02604Y03696
X02796Y03872
X02714Y03893
X0305Y0518
X0305Y0489
X03152Y04644
X03441Y04575
X0305Y0454
X03441Y04175
X0305Y0413
X03145Y04123
X03389Y04104
X03151Y03727
X03308Y03727
X03383Y03727
X03383Y03632
X02995Y03601
X02989Y0341
X03095Y0331
X0299Y0331
X02993Y03192
X03291Y03141
X03291Y03033
X03033Y03031
X0315Y03031
X03368Y03031
X03083Y0272
X03259Y0271
X03473Y02655
X03169Y02644
X03567Y01509
X03607Y0176
X03882Y0176
X03758Y0176
X03607Y02
X03882Y02
X03758Y02
X03556Y02238
X03502Y03034
X03686Y03199
X03686Y03297
X03591Y03297
X03686Y03369
X03586Y03434
X03686Y03434
X03633Y03727
X03486Y03727
X0378Y0402
X03481Y04123
X04159Y05376
X04009Y0371
X04147Y03692
X04147Y03434
X04077Y03434
X04105Y03122
X03989Y03049
X04072Y02251
X04033Y02
X04033Y0176
X04074Y01508
X0476Y0145
X0493Y0186
X047Y02544
X0464Y0278
X04714Y0278
X0455Y02787
X0455Y02977
X04714Y0306
X0464Y0306
X04482Y03124
X0503Y0519
X0515Y0519
X0503Y0511
X0515Y0511
X05018Y033
X05142Y0306
X05142Y0278
X04991Y02002
X051Y0185
T2C.02913F197S55
X024603Y03226
X024997Y03276
X024997Y03326
X024603Y03376
X024997Y03426
X024997Y03476
X024603Y03526
X049327Y0345
X048933Y034
X048933Y0335
X049327Y033
X048933Y0325
X048933Y032
X049327Y0315
T3C.03F197S55
X0204Y045
X0214Y045
X0224Y045
X0234Y045
X0244Y045
X0204Y051
X0214Y051
X0244Y051
X0234Y051
X0224Y051
X0254Y051
X0415Y051
X0405Y051
X0415Y045
X0254Y045
X0405Y045
X0445Y045
X0425Y045
X0435Y045
X0455Y045
X0445Y051
X0435Y051
X0425Y051
X0455Y051
T4C.035F197S55
X0165Y012
X0155Y012
X0165Y013
X0155Y013
X0165Y014
X0155Y014
X0133Y0173
X0143Y0173
X0123Y0173
X0153Y0173
X0166Y0175
X0166Y0199
X01397Y02374
X01697Y02374
X01597Y02374
X01497Y02374
X0146Y0251
X0136Y0251
X0166Y0251
X01318Y02741
X01578Y02741
X01488Y02741
X01578Y02993
X01488Y02993
X01318Y02993
X0158Y034
X0148Y034
X0138Y034
X0168Y034
X0138Y035
X0148Y035
X0168Y035
X0158Y035
X0138Y0371
X0148Y0371
X0158Y0371
X0168Y0371
X0138Y0401
X0168Y0401
X0158Y0401
X0148Y0401
X0188Y0401
X0178Y0401
X0178Y0371
X0188Y0371
X0188Y035
X0178Y035
X0188Y034
X0178Y034
X01838Y02993
X01748Y02993
X01838Y02741
X01748Y02741
X0186Y0251
X0196Y0251
X01797Y02374
X01897Y02374
X0176Y0199
X0176Y0175
X0175Y014
X0185Y014
X0195Y014
X0175Y013
X0185Y013
X0195Y013
X0195Y012
X0185Y012
X0175Y012
X0215Y012
X0205Y012
X0215Y013
X0205Y013
X0215Y014
X0205Y014
X01997Y02374
X02197Y02374
X02097Y02374
X0216Y0251
X02098Y02741
X02008Y02741
X02008Y02993
X02098Y02993
X0208Y034
X0198Y034
X0208Y035
X0198Y035
X0198Y0371
X0208Y0371
X0208Y0401
X0198Y0401
X02427Y03881
X02527Y03881
X02268Y02993
X02456Y02762
X02656Y02762
X02556Y02762
X02268Y02741
X02456Y02662
X02656Y02662
X02556Y02662
X02726Y02447
X02626Y02447
X02526Y02447
X02426Y02447
X02297Y02374
X02726Y02347
X02626Y02347
X02526Y02347
X02426Y02347
X027Y0199
X027Y0175
X0235Y014
X0225Y014
X0245Y014
X0265Y014
X0255Y014
X0245Y013
X0235Y013
X0265Y013
X0255Y013
X0225Y013
X0265Y012
X0235Y012
X0225Y012
X0245Y012
X0255Y012
X0275Y012
X0285Y012
X0295Y012
X0305Y012
X0315Y012
X0295Y013
X0285Y013
X0275Y013
X0315Y013
X0305Y013
X0295Y014
X0285Y014
X0275Y014
X0315Y014
X0305Y014
X028Y0175
X028Y0199
X03226Y02347
X03126Y02347
X03026Y02347
X02926Y02347
X02826Y02347
X03126Y02447
X02826Y02447
X03226Y02447
X03026Y02447
X02926Y02447
X02756Y02662
X02756Y02762
X03513Y02711
X03326Y02447
X03426Y02447
X03726Y02447
X03626Y02447
X03526Y02447
X03326Y02347
X03426Y02347
X03726Y02347
X03626Y02347
X03526Y02347
X0336Y0199
X0326Y0199
X0336Y0175
X0326Y0175
X0365Y014
X0355Y014
X0335Y014
X0325Y014
X0345Y014
X0355Y013
X0335Y013
X0365Y013
X0325Y013
X0345Y013
X0335Y012
X0345Y012
X0325Y012
X0355Y012
X0365Y012
X0375Y012
X0385Y012
X0395Y012
X0395Y013
X0385Y013
X0375Y013
X0385Y014
X0375Y014
X0395Y014
X03926Y02347
X03826Y02347
X03826Y02447
X03926Y02447
X03811Y02621
X03911Y02621
X03911Y02721
X03811Y02721
X03942Y03865
X03942Y03965
X0408Y041774
X04257Y041774
X04433Y041774
X0408Y040786
X04257Y040786
X04433Y040786
X04042Y03965
X04142Y03965
X04456Y0396
X04356Y0396
X04256Y0396
X04142Y03865
X04042Y03865
X04256Y0386
X04456Y0386
X04356Y0386
X042836Y02717
X043824Y02717
X04226Y02447
X04426Y02447
X04326Y02447
X04026Y02447
X04126Y02447
X04126Y02347
X04026Y02347
X04426Y02347
X04326Y02347
X04226Y02347
X0428Y0199
X0438Y0199
X0438Y0175
X0428Y0175
X0425Y014
X0445Y014
X0415Y014
X0405Y014
X0435Y014
X0425Y013
X0415Y013
X0405Y013
X0445Y013
X0435Y013
X0445Y012
X0405Y012
X0435Y012
X0425Y012
X0415Y012
X0455Y012
X0465Y012
X0465Y013
X0455Y013
X0495Y0135
X0485Y0135
X0465Y014
X0455Y014
X0495Y0145
X0485Y0145
X04526Y02347
X04526Y02447
X0448Y0265
X0488Y0265
X0478Y0265
X0477Y03728
X0497Y03728
X0457Y03728
X0487Y03728
X0467Y03728
X0487Y03828
X0457Y03828
X0467Y03828
X0477Y03828
X0497Y03828
X0496Y040786
X04785Y040786
X04608Y040786
X04785Y041774
X0496Y041774
X04608Y041774
X0494Y0529
X0494Y0539
X0494Y0549
X0494Y0561
X0494Y0571
X0494Y0581
X0504Y0581
X0504Y0571
X0504Y0561
X0504Y0549
X0535Y054894
X0535Y053906
X0504Y0539
X0504Y0529
X05135Y041774
X05311Y041774
X05135Y040786
X05311Y040786
X0507Y03828
X0527Y03828
X0517Y03828
X0527Y03728
X0517Y03728
X0507Y03728
X0508Y0265
X0498Y0265
X0528Y0265
X0537Y0251
X0537Y0241
X0537Y0231
X0537Y0221
X0537Y0211
X0537Y0201
X0537Y0191
X0537Y0181
X0537Y0171
X0537Y0161
X0505Y0145
X0505Y0135
T5C.037F197S55
X019097Y0534
X019998Y0534
X0209Y0534
X021802Y0534
X018646Y0544
X019548Y0544
X020449Y0544
X021351Y0544
X022252Y0544
X019097Y0554
X019998Y0554
X0209Y0554
X021802Y0554
X022703Y0554
X022703Y0534
T6C.04F139S55
X029261Y054535
X031939Y054535
X030088Y055519
X031939Y055519
X031112Y055519
X029261Y055519
X036788Y055519
X035961Y055519
X038639Y055519
X037812Y055519
X035961Y054535
X038639Y054535
T7C.052F107S55
X04269Y05783
X04819Y05783
T8C.05315F107S55
X0248Y031209
X0248Y036311
X04913Y035551
X04913Y030449
T9C.09F066S55
X027943Y0567
X033257Y0567
X034643Y0567
X039957Y0567
T10C.098F066S55
X0306Y057015
X0373Y057015
T11C.12F035S794
X015979Y0544
X025821Y0544
T12C.12598F035S794
X013Y013
X013Y057
X053Y057
X053Y013
M30

/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.rep
0,0 → 1,23
Drill Sizes Report
==================
Tool Size Pltd Feed Speed Qty
==== ==== ==== ==== ===== ===
1 25 x 197 550 108
2 29.13 x 197 550 14
3 30 x 197 550 24
4 35 x 197 550 321
5 37 x 197 550 15
6 40 x 139 550 12
7 52 x 107 550 2
8 53.15 x 107 550 4
9 90 x 66 550 4
10 98 x 66 550 2
11 120 x 35 794 2
12 125.98 x 35 794 4

/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M1.PHO
0,0 → 1,503
*
*
G04 PADS 9.2 Build Number: 414666 generated Gerber (RS-274-X) file*
G04 PC Version=2.1*
*
%IN "S3AN01A.pcb"*%
*
%MOIN*%
*
%FSLAX35Y35*%
*
*
*
*
G04 PC Standard Apertures*
*
*
G04 Thermal Relief Aperture macro.*
%AMTER*
1,1,$1,0,0*
1,0,$1-$2,0,0*
21,0,$3,$4,0,0,45*
21,0,$3,$4,0,0,135*
%
*
*
G04 Annular Aperture macro.*
%AMANN*
1,1,$1,0,0*
1,0,$2,0,0*
%
*
*
G04 Odd Aperture macro.*
%AMODD*
1,1,$1,0,0*
1,0,$1-0.005,0,0*
%
*
*
G04 PC Custom Aperture Macros*
*
*
*
*
*
*
G04 PC Aperture Table*
*
%ADD011C,0.06*%
%ADD012R,0.07X0.07*%
%ADD024C,0.001*%
%ADD031C,0.07*%
%ADD032R,0.08X0.08*%
%ADD033C,0.24622*%
%ADD041C,0.08*%
%ADD078C,0.113*%
%ADD079C,0.187*%
%ADD080C,0.05331*%
%ADD081C,0.08874*%
%ADD082C,0.13*%
%ADD083C,0.128*%
%ADD084R,0.09X0.09*%
*
*
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
*
G04 PC Custom Flashes*
G04 Layer Name S3AN01A.pcb - flashes*
%LPD*%
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
G54D11*
G01X130000Y540000D03*
X521000Y170000D03*
G54D12*
X405000Y450000D03*
X204000D03*
G54D24*
G54D31*
X255000Y120000D03*
X265000D03*
X275000D03*
X285000D03*
X295000D03*
X305000D03*
X315000D03*
X325000D03*
X335000D03*
X345000D03*
X355000D03*
X365000D03*
X375000D03*
X385000D03*
X395000D03*
X405000D03*
X415000D03*
X425000D03*
X435000D03*
X445000D03*
X455000D03*
X465000D03*
X245000Y140000D03*
Y130000D03*
X235000Y140000D03*
Y130000D03*
X225000Y140000D03*
Y130000D03*
X215000Y140000D03*
Y130000D03*
X205000Y140000D03*
Y130000D03*
X195000Y140000D03*
Y130000D03*
X185000Y140000D03*
Y130000D03*
X175000Y140000D03*
Y130000D03*
X165000Y140000D03*
Y130000D03*
X155000Y140000D03*
Y130000D03*
X245000Y120000D03*
X235000D03*
X225000D03*
X215000D03*
X205000D03*
X195000D03*
X185000D03*
X175000D03*
X165000D03*
X155000D03*
X351300Y271100D03*
X452600Y244700D03*
Y234700D03*
X442600Y244700D03*
Y234700D03*
X432600Y244700D03*
Y234700D03*
X422600Y244700D03*
Y234700D03*
X412600Y244700D03*
Y234700D03*
X402600Y244700D03*
Y234700D03*
X392600Y244700D03*
Y234700D03*
X382600Y244700D03*
Y234700D03*
X372600Y244700D03*
Y234700D03*
X362600Y244700D03*
Y234700D03*
X352600Y244700D03*
Y234700D03*
X342600Y244700D03*
Y234700D03*
X332600Y244700D03*
Y234700D03*
X322600Y244700D03*
Y234700D03*
X312600Y244700D03*
Y234700D03*
X302600Y244700D03*
Y234700D03*
X292600Y244700D03*
Y234700D03*
X282600Y244700D03*
Y234700D03*
X272600Y244700D03*
Y234700D03*
X262600Y244700D03*
Y234700D03*
X252600Y244700D03*
Y234700D03*
X242600Y244700D03*
Y234700D03*
X465000Y140000D03*
Y130000D03*
X455000Y140000D03*
Y130000D03*
X445000Y140000D03*
Y130000D03*
X435000Y140000D03*
Y130000D03*
X425000Y140000D03*
Y130000D03*
X415000Y140000D03*
Y130000D03*
X405000Y140000D03*
Y130000D03*
X395000Y140000D03*
Y130000D03*
X385000Y140000D03*
Y130000D03*
X375000Y140000D03*
Y130000D03*
X365000Y140000D03*
Y130000D03*
X355000Y140000D03*
Y130000D03*
X345000Y140000D03*
Y130000D03*
X335000Y140000D03*
Y130000D03*
X325000Y140000D03*
Y130000D03*
X315000Y140000D03*
Y130000D03*
X305000Y140000D03*
Y130000D03*
X295000Y140000D03*
Y130000D03*
X285000Y140000D03*
Y130000D03*
X275000Y140000D03*
Y130000D03*
X265000Y140000D03*
Y130000D03*
X255000Y140000D03*
Y130000D03*
X415000Y450000D03*
X425000D03*
X435000D03*
X445000D03*
X455000D03*
Y510000D03*
X445000D03*
X435000D03*
X425000D03*
X415000D03*
X405000D03*
X214000Y450000D03*
X224000D03*
X234000D03*
X244000D03*
X254000D03*
Y510000D03*
X244000D03*
X234000D03*
X224000D03*
X214000D03*
X204000D03*
G54D32*
X531100Y417737D03*
X513500D03*
X535000Y548937D03*
X496000Y417737D03*
X478500D03*
X460800D03*
X443300D03*
X425700D03*
X408000D03*
X438237Y271700D03*
X494000Y581000D03*
X504000D03*
X494000Y571000D03*
X504000D03*
X494000Y561000D03*
X504000D03*
X537000Y161000D03*
Y171000D03*
Y181000D03*
Y191000D03*
Y201000D03*
Y211000D03*
Y221000D03*
Y231000D03*
Y241000D03*
Y251000D03*
X428000Y199000D03*
X438000D03*
X428000Y175000D03*
X438000D03*
X336000D03*
X326000D03*
X336000Y199000D03*
X326000D03*
X270000D03*
X280000D03*
X270000Y175000D03*
X280000D03*
X176000D03*
X166000D03*
X494000Y549000D03*
X504000D03*
X494000Y539000D03*
X504000D03*
X494000Y529000D03*
X504000D03*
X176000Y199000D03*
X166000D03*
X229700Y237400D03*
X219700D03*
X209700D03*
X199700D03*
X189700D03*
X179700D03*
X169700D03*
X159700D03*
X149700D03*
X139700D03*
X391100Y272100D03*
Y262100D03*
X381100Y272100D03*
Y262100D03*
X208000Y350000D03*
Y340000D03*
X198000Y350000D03*
Y340000D03*
X188000Y350000D03*
Y340000D03*
X178000Y350000D03*
Y340000D03*
X168000Y350000D03*
Y340000D03*
X158000Y350000D03*
Y340000D03*
X148000Y350000D03*
Y340000D03*
X138000Y350000D03*
Y340000D03*
X527000Y382800D03*
Y372800D03*
X517000Y382800D03*
Y372800D03*
X507000Y382800D03*
Y372800D03*
X497000Y382800D03*
Y372800D03*
X487000Y382800D03*
Y372800D03*
X477000Y382800D03*
Y372800D03*
X467000Y382800D03*
Y372800D03*
X457000Y382800D03*
Y372800D03*
X136000Y251000D03*
X123000Y173000D03*
X133000D03*
X143000D03*
X153000D03*
X414200Y396500D03*
Y386500D03*
X404200Y396500D03*
Y386500D03*
X394200Y396500D03*
Y386500D03*
X445600Y396000D03*
Y386000D03*
X435600Y396000D03*
Y386000D03*
X425600Y396000D03*
Y386000D03*
X252700Y388100D03*
X242700D03*
X275600Y276200D03*
Y266200D03*
X265600Y276200D03*
Y266200D03*
X255600Y276200D03*
Y266200D03*
X245600Y276200D03*
Y266200D03*
X505000Y145000D03*
Y135000D03*
X495000Y145000D03*
Y135000D03*
X485000Y145000D03*
Y135000D03*
X138000Y371000D03*
X148000D03*
X158000D03*
X168000D03*
X178000D03*
X188000D03*
X198000D03*
X208000D03*
Y401000D03*
X198000D03*
X188000D03*
X178000D03*
X168000D03*
X158000D03*
X148000D03*
X138000D03*
X488000Y265000D03*
X508000D03*
X498000D03*
X448000D03*
X528000D03*
X478000D03*
G54D33*
X130000Y570000D03*
X530000D03*
Y130000D03*
X130000D03*
G54D41*
X531100Y407863D03*
X513500D03*
X535000Y539063D03*
X496000Y407863D03*
X478500D03*
X460800D03*
X443300D03*
X425700D03*
X408000D03*
X428363Y271700D03*
X190969Y534000D03*
X199984D03*
X209000D03*
X218016D03*
X227031D03*
X186461Y544000D03*
X195476D03*
X204492D03*
X213508D03*
X222524D03*
X190969Y554000D03*
X199984D03*
X209000D03*
X218016D03*
X227031D03*
X146000Y251000D03*
X166000D03*
X186000D03*
X196000D03*
X216000D03*
X300882Y555189D03*
X311118D03*
X292614D03*
X319386D03*
X292614Y545346D03*
X319386D03*
X367882Y555189D03*
X378118D03*
X359614D03*
X386386D03*
X359614Y545346D03*
X386386D03*
G54D78*
X481900Y578300D03*
X426900D03*
G54D79*
X258213Y544000D03*
X159787D03*
G54D80*
X493269Y345000D03*
X489331Y340000D03*
Y335000D03*
X493269Y330000D03*
X489331Y325000D03*
Y320000D03*
X493269Y315000D03*
X246031Y322600D03*
X249969Y327600D03*
Y332600D03*
X246031Y337600D03*
X249969Y342600D03*
Y347600D03*
X246031Y352600D03*
G54D81*
X491300Y304488D03*
Y355512D03*
X248000Y363112D03*
Y312088D03*
G54D82*
X332575Y567000D03*
X279425D03*
X399575D03*
X346425D03*
G54D83*
X306000Y570150D03*
X373000D03*
G54D84*
X226800Y299300D03*
X209800D03*
Y274100D03*
X226800D03*
X200800Y299300D03*
X183800D03*
Y274100D03*
X200800D03*
X174800Y299300D03*
X157800D03*
Y274100D03*
X174800D03*
X148800Y299300D03*
X131800D03*
Y274100D03*
X148800D03*
X0Y0D02*
M02*

/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M2.PHO
0,0 → 1,3784
*
*
G04 PADS 9.2 Build Number: 414666 generated Gerber (RS-274-X) file*
G04 PC Version=2.1*
*
%IN "S3AN01A.pcb"*%
*
%MOIN*%
*
%FSLAX35Y35*%
*
*
*
*
G04 PC Standard Apertures*
*
*
G04 Thermal Relief Aperture macro.*
%AMTER*
1,1,$1,0,0*
1,0,$1-$2,0,0*
21,0,$3,$4,0,0,45*
21,0,$3,$4,0,0,135*
%
*
*
G04 Annular Aperture macro.*
%AMANN*
1,1,$1,0,0*
1,0,$2,0,0*
%
*
*
G04 Odd Aperture macro.*
%AMODD*
1,1,$1,0,0*
1,0,$1-0.005,0,0*
%
*
*
G04 PC Custom Aperture Macros*
*
*
*
*
*
*
G04 PC Aperture Table*
*
%ADD024C,0.001*%
%ADD025C,0.01*%
%ADD035C,0.065*%
%ADD085R,0.116X0.071*%
%ADD086R,0.055X0.072*%
%ADD087R,0.072X0.055*%
%ADD088R,0.071X0.116*%
%ADD089R,0.086X0.086*%
%ADD090C,0.086*%
%ADD091C,0.119*%
%ADD092C,0.07591*%
%ADD093C,0.193*%
%ADD094C,0.05921*%
%ADD095C,0.09465*%
%ADD096C,0.136*%
%ADD097C,0.134*%
%ADD098R,0.076X0.076*%
%ADD099C,0.076*%
%ADD100C,0.25213*%
%ADD101C,0.21*%
%ADD102R,0.056X0.056*%
%ADD103R,0.055X0.067*%
%ADD104R,0.067X0.055*%
%ADD105R,0.096X0.096*%
%ADD106C,0.046*%
%ADD107O,0.032X0.096*%
%ADD108O,0.096X0.032*%
%ADD109R,0.061X0.04*%
%ADD110O,0.028X0.068*%
%ADD111R,0.12X0.081*%
%ADD112R,0.426X0.44*%
%ADD113R,0.088X0.076*%
%ADD114R,0.216X0.216*%
%ADD115R,0.086X0.096*%
%ADD116O,0.086X0.041*%
*
*
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
*
G04 PC Custom Flashes*
G04 Layer Name S3AN01A.pcb - flashes*
%LPD*%
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
G54D24*
G54D25*
G01X395288Y312896D02*
X390904Y308512D01*
X394086Y305330*
X398470Y309714*
X395288Y312896*
X393416Y306000D02*
X394756D01*
X392416Y307000D02*
X395756D01*
X391416Y308000D02*
X396756D01*
X391392Y309000D02*
X397756D01*
X392392Y310000D02*
X398184D01*
X393392Y311000D02*
X397184D01*
X394392Y312000D02*
X396184D01*
X391000Y308416D02*
Y308608D01*
X392000Y307416D02*
Y309608D01*
X393000Y306416D02*
Y310608D01*
X394000Y305416D02*
Y311608D01*
X395000Y306244D02*
Y312608D01*
X396000Y307244D02*
Y312184D01*
X397000Y308244D02*
Y311184D01*
X398000Y309244D02*
Y310184D01*
X389914Y318270D02*
X385530Y313886D01*
X388712Y310704*
X393096Y315088*
X389914Y318270*
X388416Y311000D02*
X389008D01*
X387416Y312000D02*
X390008D01*
X386416Y313000D02*
X391008D01*
X385644Y314000D02*
X392008D01*
X386644Y315000D02*
X393008D01*
X387644Y316000D02*
X392184D01*
X388644Y317000D02*
X391184D01*
X389644Y318000D02*
X390184D01*
X386000Y313416D02*
Y314356D01*
X387000Y312416D02*
Y315356D01*
X388000Y311416D02*
Y316356D01*
X389000Y310992D02*
Y317356D01*
X390000Y311992D02*
Y318184D01*
X391000Y312992D02*
Y317184D01*
X392000Y313992D02*
Y316184D01*
X393000Y314992D02*
Y315184D01*
X406488Y320996D02*
X402104Y316612D01*
X405286Y313430*
X409670Y317814*
X406488Y320996*
X404716Y314000D02*
X405856D01*
X403716Y315000D02*
X406856D01*
X402716Y316000D02*
X407856D01*
X402492Y317000D02*
X408856D01*
X403492Y318000D02*
X409484D01*
X404492Y319000D02*
X408484D01*
X405492Y320000D02*
X407484D01*
X403000Y315716D02*
Y317508D01*
X404000Y314716D02*
Y318508D01*
X405000Y313716D02*
Y319508D01*
X406000Y314144D02*
Y320508D01*
X407000Y315144D02*
Y320484D01*
X408000Y316144D02*
Y319484D01*
X409000Y317144D02*
Y318484D01*
X401114Y326370D02*
X396730Y321986D01*
X399912Y318804*
X404296Y323188*
X401114Y326370*
X399716Y319000D02*
X400108D01*
X398716Y320000D02*
X401108D01*
X397716Y321000D02*
X402108D01*
X396744Y322000D02*
X403108D01*
X397744Y323000D02*
X404108D01*
X398744Y324000D02*
X403484D01*
X399744Y325000D02*
X402484D01*
X400744Y326000D02*
X401484D01*
X397000Y321716D02*
Y322256D01*
X398000Y320716D02*
Y323256D01*
X399000Y319716D02*
Y324256D01*
X400000Y318892D02*
Y325256D01*
X401000Y319892D02*
Y326256D01*
X402000Y320892D02*
Y325484D01*
X403000Y321892D02*
Y324484D01*
X404000Y322892D02*
Y323484D01*
X199712Y217504D02*
X204096Y221888D01*
X200914Y225070*
X196530Y220686*
X199712Y217504*
X199216Y218000D02*
X200208D01*
X198216Y219000D02*
X201208D01*
X197216Y220000D02*
X202208D01*
X196844Y221000D02*
X203208D01*
X197844Y222000D02*
X203984D01*
X198844Y223000D02*
X202984D01*
X199844Y224000D02*
X201984D01*
X200844Y225000D02*
X200984D01*
X197000Y220216D02*
Y221156D01*
X198000Y219216D02*
Y222156D01*
X199000Y218216D02*
Y223156D01*
X200000Y217792D02*
Y224156D01*
X201000Y218792D02*
Y224984D01*
X202000Y219792D02*
Y223984D01*
X203000Y220792D02*
Y222984D01*
X204000Y221792D02*
Y221984D01*
X205086Y212130D02*
X209470Y216514D01*
X206288Y219696*
X201904Y215312*
X205086Y212130*
X204216Y213000D02*
X205956D01*
X203216Y214000D02*
X206956D01*
X202216Y215000D02*
X207956D01*
X202592Y216000D02*
X208956D01*
X203592Y217000D02*
X208984D01*
X204592Y218000D02*
X207984D01*
X205592Y219000D02*
X206984D01*
X202000Y215216D02*
Y215408D01*
X203000Y214216D02*
Y216408D01*
X204000Y213216D02*
Y217408D01*
X205000Y212216D02*
Y218408D01*
X206000Y213044D02*
Y219408D01*
X207000Y214044D02*
Y218984D01*
X208000Y215044D02*
Y217984D01*
X209000Y216044D02*
Y216984D01*
X240704Y221888D02*
X245088Y217504D01*
X248270Y220686*
X243886Y225070*
X240704Y221888*
X244592Y218000D02*
X245584D01*
X243592Y219000D02*
X246584D01*
X242592Y220000D02*
X247584D01*
X241592Y221000D02*
X247956D01*
X240816Y222000D02*
X246956D01*
X241816Y223000D02*
X245956D01*
X242816Y224000D02*
X244956D01*
X243816Y225000D02*
X243956D01*
X241000Y221592D02*
Y222184D01*
X242000Y220592D02*
Y223184D01*
X243000Y219592D02*
Y224184D01*
X244000Y218592D02*
Y224956D01*
X245000Y217592D02*
Y223956D01*
X246000Y218416D02*
Y222956D01*
X247000Y219416D02*
Y221956D01*
X248000Y220416D02*
Y220956D01*
X235330Y216514D02*
X239714Y212130D01*
X242896Y215312*
X238512Y219696*
X235330Y216514*
X238844Y213000D02*
X240584D01*
X237844Y214000D02*
X241584D01*
X236844Y215000D02*
X242584D01*
X235844Y216000D02*
X242208D01*
X235816Y217000D02*
X241208D01*
X236816Y218000D02*
X240208D01*
X237816Y219000D02*
X239208D01*
X236000Y215844D02*
Y217184D01*
X237000Y214844D02*
Y218184D01*
X238000Y213844D02*
Y219184D01*
X239000Y212844D02*
Y219208D01*
X240000Y212416D02*
Y218208D01*
X241000Y213416D02*
Y217208D01*
X242000Y214416D02*
Y216208D01*
X205396Y154112D02*
X201012Y158496D01*
X197830Y155314*
X202214Y150930*
X205396Y154112*
X202144Y151000D02*
X202284D01*
X201144Y152000D02*
X203284D01*
X200144Y153000D02*
X204284D01*
X199144Y154000D02*
X205284D01*
X198144Y155000D02*
X204508D01*
X198516Y156000D02*
X203508D01*
X199516Y157000D02*
X202508D01*
X200516Y158000D02*
X201508D01*
X198000Y155144D02*
Y155484D01*
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X437600Y309100D03*
X417600D03*
Y325700D03*
X437600D03*
G54D116*
X499200Y253700D03*
Y248700D03*
Y243700D03*
Y238700D03*
X477800D03*
Y243700D03*
Y248700D03*
Y253700D03*
X507500D03*
Y248700D03*
Y243700D03*
Y238700D03*
X477500D03*
Y243700D03*
Y248700D03*
Y253700D03*
X499200Y220500D03*
Y215500D03*
Y210500D03*
Y205500D03*
X477800D03*
Y210500D03*
Y215500D03*
Y220500D03*
X507500D03*
Y215500D03*
Y210500D03*
Y205500D03*
X477500D03*
Y210500D03*
Y215500D03*
Y220500D03*
X0Y0D02*
M02*

/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/P2.PHO
0,0 → 1,2284
*
*
G04 PADS 9.2 Build Number: 414666 generated Gerber (RS-274-X) file*
G04 PC Version=2.1*
*
%IN "S3AN01A.pcb"*%
*
%MOIN*%
*
%FSLAX35Y35*%
*
*
*
*
G04 PC Standard Apertures*
*
*
G04 Thermal Relief Aperture macro.*
%AMTER*
1,1,$1,0,0*
1,0,$1-$2,0,0*
21,0,$3,$4,0,0,45*
21,0,$3,$4,0,0,135*
%
*
*
G04 Annular Aperture macro.*
%AMANN*
1,1,$1,0,0*
1,0,$2,0,0*
%
*
*
G04 Odd Aperture macro.*
%AMODD*
1,1,$1,0,0*
1,0,$1-0.005,0,0*
%
*
*
G04 PC Custom Aperture Macros*
*
*
*
*
*
*
G04 PC Aperture Table*
*
%ADD024C,0.001*%
%ADD025C,0.01*%
%ADD040R,0.06X0.06*%
%ADD117R,0.096X0.051*%
%ADD118R,0.035X0.052*%
%ADD119R,0.052X0.035*%
%ADD120R,0.051X0.096*%
%ADD121R,0.036X0.036*%
%ADD122R,0.035X0.047*%
%ADD123R,0.047X0.035*%
%ADD124O,0.00866X0.08*%
%ADD125O,0.08X0.00866*%
%ADD126R,0.037X0.022*%
%ADD127O,0.01X0.048*%
%ADD128R,0.1X0.06*%
%ADD129R,0.068X0.056*%
%ADD130R,0.19X0.19*%
%ADD131R,0.066X0.076*%
%ADD132O,0.062X0.023*%
*
*
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
*
G04 PC Custom Flashes*
G04 Layer Name S3AN01A.pcb - flashes*
%LPD*%
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
G54D24*
G54D25*
G01X395288Y311482D02*
X392318Y308512D01*
X394086Y306744*
X397056Y309714*
X395288Y311482*
X393830Y307000D02*
X394342D01*
X392830Y308000D02*
X395342D01*
X392806Y309000D02*
X396342D01*
X393806Y310000D02*
X396770D01*
X394806Y311000D02*
X395770D01*
X393000Y307830D02*
Y309194D01*
X394000Y306830D02*
Y310194D01*
X395000Y307658D02*
Y311194D01*
X396000Y308658D02*
Y310770D01*
X397000Y309658D02*
Y309770D01*
X389914Y316856D02*
X386944Y313886D01*
X388712Y312118*
X391682Y315088*
X389914Y316856*
X387830Y313000D02*
X389594D01*
X387058Y314000D02*
X390594D01*
X388058Y315000D02*
X391594D01*
X389058Y316000D02*
X390770D01*
X387000Y313830D02*
Y313942D01*
X388000Y312830D02*
Y314942D01*
X389000Y312406D02*
Y315942D01*
X390000Y313406D02*
Y316770D01*
X391000Y314406D02*
Y315770D01*
X406488Y319582D02*
X403518Y316612D01*
X405286Y314844*
X408256Y317814*
X406488Y319582*
X405130Y315000D02*
X405442D01*
X404130Y316000D02*
X406442D01*
X403906Y317000D02*
X407442D01*
X404906Y318000D02*
X408070D01*
X405906Y319000D02*
X407070D01*
X404000Y316130D02*
Y317094D01*
X405000Y315130D02*
Y318094D01*
X406000Y315558D02*
Y319094D01*
X407000Y316558D02*
Y319070D01*
X408000Y317558D02*
Y318070D01*
X401114Y324956D02*
X398144Y321986D01*
X399912Y320218*
X402882Y323188*
X401114Y324956*
X399130Y321000D02*
X400694D01*
X398158Y322000D02*
X401694D01*
X399158Y323000D02*
X402694D01*
X400158Y324000D02*
X402070D01*
X399000Y321130D02*
Y322842D01*
X400000Y320306D02*
Y323842D01*
X401000Y321306D02*
Y324842D01*
X402000Y322306D02*
Y324070D01*
X199712Y218918D02*
X202682Y221888D01*
X200914Y223656*
X197944Y220686*
X199712Y218918*
X199630Y219000D02*
X199794D01*
X198630Y220000D02*
X200794D01*
X198258Y221000D02*
X201794D01*
X199258Y222000D02*
X202570D01*
X200258Y223000D02*
X201570D01*
X198000Y220630D02*
Y220742D01*
X199000Y219630D02*
Y221742D01*
X200000Y219206D02*
Y222742D01*
X201000Y220206D02*
Y223570D01*
X202000Y221206D02*
Y222570D01*
X205086Y213544D02*
X208056Y216514D01*
X206288Y218282*
X203318Y215312*
X205086Y213544*
X204630Y214000D02*
X205542D01*
X203630Y215000D02*
X206542D01*
X204006Y216000D02*
X207542D01*
X205006Y217000D02*
X207570D01*
X206006Y218000D02*
X206570D01*
X204000Y214630D02*
Y215994D01*
X205000Y213630D02*
Y216994D01*
X206000Y214458D02*
Y217994D01*
X207000Y215458D02*
Y217570D01*
X208000Y216458D02*
Y216570D01*
X242118Y221888D02*
X245088Y218918D01*
X246856Y220686*
X243886Y223656*
X242118Y221888*
X245006Y219000D02*
X245170D01*
X244006Y220000D02*
X246170D01*
X243006Y221000D02*
X246542D01*
X242230Y222000D02*
X245542D01*
X243230Y223000D02*
X244542D01*
X243000Y221006D02*
Y222770D01*
X244000Y220006D02*
Y223542D01*
X245000Y219006D02*
Y222542D01*
X246000Y219830D02*
Y221542D01*
X236744Y216514D02*
X239714Y213544D01*
X241482Y215312*
X238512Y218282*
X236744Y216514*
X239258Y214000D02*
X240170D01*
X238258Y215000D02*
X241170D01*
X237258Y216000D02*
X240794D01*
X237230Y217000D02*
X239794D01*
X238230Y218000D02*
X238794D01*
X237000Y216258D02*
Y216770D01*
X238000Y215258D02*
Y217770D01*
X239000Y214258D02*
Y217794D01*
X240000Y213830D02*
Y216794D01*
X241000Y214830D02*
Y215794D01*
X203982Y154112D02*
X201012Y157082D01*
X199244Y155314*
X202214Y152344*
X203982Y154112*
X201558Y153000D02*
X202870D01*
X200558Y154000D02*
X203870D01*
X199558Y155000D02*
X203094D01*
X199930Y156000D02*
X202094D01*
X200930Y157000D02*
X201094D01*
X200000Y154558D02*
Y156070D01*
X201000Y153558D02*
Y157070D01*
X202000Y152558D02*
Y156094D01*
X203000Y153130D02*
Y155094D01*
X209356Y159486D02*
X206386Y162456D01*
X204618Y160688*
X207588Y157718*
X209356Y159486*
X207306Y158000D02*
X207870D01*
X206306Y159000D02*
X208870D01*
X205306Y160000D02*
X208842D01*
X204930Y161000D02*
X207842D01*
X205930Y162000D02*
X206842D01*
X205000Y160306D02*
Y161070D01*
X206000Y159306D02*
Y162070D01*
X207000Y158306D02*
Y161842D01*
X208000Y158130D02*
Y160842D01*
X209000Y159130D02*
Y159842D01*
X245288Y157082D02*
X242318Y154112D01*
X244086Y152344*
X247056Y155314*
X245288Y157082*
X243430Y153000D02*
X244742D01*
X242430Y154000D02*
X245742D01*
X243206Y155000D02*
X246742D01*
X244206Y156000D02*
X246370D01*
X245206Y157000D02*
X245370D01*
X243000Y153430D02*
Y154794D01*
X244000Y152430D02*
Y155794D01*
X245000Y153258D02*
Y156794D01*
X246000Y154258D02*
Y156370D01*
X247000Y155258D02*
Y155370D01*
X239914Y162456D02*
X236944Y159486D01*
X238712Y157718*
X241682Y160688*
X239914Y162456*
X238430Y158000D02*
X238994D01*
X237430Y159000D02*
X239994D01*
X237458Y160000D02*
X240994D01*
X238458Y161000D02*
X241370D01*
X239458Y162000D02*
X240370D01*
X237000Y159430D02*
Y159542D01*
X238000Y158430D02*
Y160542D01*
X239000Y158006D02*
Y161542D01*
X240000Y159006D02*
Y162370D01*
X241000Y160006D02*
Y161370D01*
X360012Y218918D02*
X362982Y221888D01*
X361214Y223656*
X358244Y220686*
X360012Y218918*
X359930Y219000D02*
X360094D01*
X358930Y220000D02*
X361094D01*
X358558Y221000D02*
X362094D01*
X359558Y222000D02*
X362870D01*
X360558Y223000D02*
X361870D01*
X359000Y219930D02*
Y221442D01*
X360000Y218930D02*
Y222442D01*
X361000Y219906D02*
Y223442D01*
X362000Y220906D02*
Y222870D01*
X365386Y213544D02*
X368356Y216514D01*
X366588Y218282*
X363618Y215312*
X365386Y213544*
X364930Y214000D02*
X365842D01*
X363930Y215000D02*
X366842D01*
X364306Y216000D02*
X367842D01*
X365306Y217000D02*
X367870D01*
X366306Y218000D02*
X366870D01*
X364000Y214930D02*
Y215694D01*
X365000Y213930D02*
Y216694D01*
X366000Y214158D02*
Y217694D01*
X367000Y215158D02*
Y217870D01*
X368000Y216158D02*
Y216870D01*
X401018Y221888D02*
X403988Y218918D01*
X405756Y220686*
X402786Y223656*
X401018Y221888*
X403906Y219000D02*
X404070D01*
X402906Y220000D02*
X405070D01*
X401906Y221000D02*
X405442D01*
X401130Y222000D02*
X404442D01*
X402130Y223000D02*
X403442D01*
X402000Y220906D02*
Y222870D01*
X403000Y219906D02*
Y223442D01*
X404000Y218930D02*
Y222442D01*
X405000Y219930D02*
Y221442D01*
X395644Y216514D02*
X398614Y213544D01*
X400382Y215312*
X397412Y218282*
X395644Y216514*
X398158Y214000D02*
X399070D01*
X397158Y215000D02*
X400070D01*
X396158Y216000D02*
X399694D01*
X396130Y217000D02*
X398694D01*
X397130Y218000D02*
X397694D01*
X396000Y216158D02*
Y216870D01*
X397000Y215158D02*
Y217870D01*
X398000Y214158D02*
Y217694D01*
X399000Y213930D02*
Y216694D01*
X400000Y214930D02*
Y215694D01*
X362882Y154112D02*
X359912Y157082D01*
X358144Y155314*
X361114Y152344*
X362882Y154112*
X360458Y153000D02*
X361770D01*
X359458Y154000D02*
X362770D01*
X358458Y155000D02*
X361994D01*
X358830Y156000D02*
X360994D01*
X359830Y157000D02*
X359994D01*
X359000Y154458D02*
Y156170D01*
X360000Y153458D02*
Y156994D01*
X361000Y152458D02*
Y155994D01*
X362000Y153230D02*
Y154994D01*
X368256Y159486D02*
X365286Y162456D01*
X363518Y160688*
X366488Y157718*
X368256Y159486*
X366206Y158000D02*
X366770D01*
X365206Y159000D02*
X367770D01*
X364206Y160000D02*
X367742D01*
X363830Y161000D02*
X366742D01*
X364830Y162000D02*
X365742D01*
X364000Y160206D02*
Y161170D01*
X365000Y159206D02*
Y162170D01*
X366000Y158206D02*
Y161742D01*
X367000Y158230D02*
Y160742D01*
X368000Y159230D02*
Y159742D01*
X404088Y157082D02*
X401118Y154112D01*
X402886Y152344*
X405856Y155314*
X404088Y157082*
X402230Y153000D02*
X403542D01*
X401230Y154000D02*
X404542D01*
X402006Y155000D02*
X405542D01*
X403006Y156000D02*
X405170D01*
X404006Y157000D02*
X404170D01*
X402000Y153230D02*
Y154994D01*
X403000Y152458D02*
Y155994D01*
X404000Y153458D02*
Y156994D01*
X405000Y154458D02*
Y156170D01*
X398714Y162456D02*
X395744Y159486D01*
X397512Y157718*
X400482Y160688*
X398714Y162456*
X397230Y158000D02*
X397794D01*
X396230Y159000D02*
X398794D01*
X396258Y160000D02*
X399794D01*
X397258Y161000D02*
X400170D01*
X398258Y162000D02*
X399170D01*
X396000Y159230D02*
Y159742D01*
X397000Y158230D02*
Y160742D01*
X398000Y158206D02*
Y161742D01*
X399000Y159206D02*
Y162170D01*
X400000Y160206D02*
Y161170D01*
X472298Y124540D02*
X470460Y122702D01*
X471945Y121217*
X473783Y123055*
X472298Y124540*
X471162Y122000D02*
X472728D01*
X470758Y123000D02*
X473728D01*
X471758Y124000D02*
X472838D01*
X471000Y122162D02*
Y123242D01*
X472000Y121272D02*
Y124242D01*
X473000Y122272D02*
Y123838D01*
X468055Y128783D02*
X466217Y126945D01*
X467702Y125460*
X469540Y127298*
X468055Y128783*
X467162Y126000D02*
X468242D01*
X466272Y127000D02*
X469242D01*
X467272Y128000D02*
X468838D01*
X467000Y126162D02*
Y127728D01*
X468000Y125758D02*
Y128728D01*
X469000Y126758D02*
Y127838D01*
X462298Y124540D02*
X460460Y122702D01*
X461945Y121217*
X463783Y123055*
X462298Y124540*
X461162Y122000D02*
X462728D01*
X460758Y123000D02*
X463728D01*
X461758Y124000D02*
X462838D01*
X461000Y122162D02*
Y123242D01*
X462000Y121272D02*
Y124242D01*
X463000Y122272D02*
Y123838D01*
X458055Y128783D02*
X456217Y126945D01*
X457702Y125460*
X459540Y127298*
X458055Y128783*
X457162Y126000D02*
X458242D01*
X456272Y127000D02*
X459242D01*
X457272Y128000D02*
X458838D01*
X457000Y126162D02*
Y127728D01*
X458000Y125758D02*
Y128728D01*
X459000Y126758D02*
Y127838D01*
X452298Y124540D02*
X450460Y122702D01*
X451945Y121217*
X453783Y123055*
X452298Y124540*
X451162Y122000D02*
X452728D01*
X450758Y123000D02*
X453728D01*
X451758Y124000D02*
X452838D01*
X451000Y122162D02*
Y123242D01*
X452000Y121272D02*
Y124242D01*
X453000Y122272D02*
Y123838D01*
X448055Y128783D02*
X446217Y126945D01*
X447702Y125460*
X449540Y127298*
X448055Y128783*
X447162Y126000D02*
X448242D01*
X446272Y127000D02*
X449242D01*
X447272Y128000D02*
X448838D01*
X447000Y126162D02*
Y127728D01*
X448000Y125758D02*
Y128728D01*
X449000Y126758D02*
Y127838D01*
X442298Y124540D02*
X440460Y122702D01*
X441945Y121217*
X443783Y123055*
X442298Y124540*
X441162Y122000D02*
X442728D01*
X440758Y123000D02*
X443728D01*
X441758Y124000D02*
X442838D01*
X441000Y122162D02*
Y123242D01*
X442000Y121272D02*
Y124242D01*
X443000Y122272D02*
Y123838D01*
X438055Y128783D02*
X436217Y126945D01*
X437702Y125460*
X439540Y127298*
X438055Y128783*
X437162Y126000D02*
X438242D01*
X436272Y127000D02*
X439242D01*
X437272Y128000D02*
X438838D01*
X437000Y126162D02*
Y127728D01*
X438000Y125758D02*
Y128728D01*
X439000Y126758D02*
Y127838D01*
X432298Y124540D02*
X430460Y122702D01*
X431945Y121217*
X433783Y123055*
X432298Y124540*
X431162Y122000D02*
X432728D01*
X430758Y123000D02*
X433728D01*
X431758Y124000D02*
X432838D01*
X431000Y122162D02*
Y123242D01*
X432000Y121272D02*
Y124242D01*
X433000Y122272D02*
Y123838D01*
X428055Y128783D02*
X426217Y126945D01*
X427702Y125460*
X429540Y127298*
X428055Y128783*
X427162Y126000D02*
X428242D01*
X426272Y127000D02*
X429242D01*
X427272Y128000D02*
X428838D01*
X427000Y126162D02*
Y127728D01*
X428000Y125758D02*
Y128728D01*
X429000Y126758D02*
Y127838D01*
X422298Y124540D02*
X420460Y122702D01*
X421945Y121217*
X423783Y123055*
X422298Y124540*
X421162Y122000D02*
X422728D01*
X420758Y123000D02*
X423728D01*
X421758Y124000D02*
X422838D01*
X421000Y122162D02*
Y123242D01*
X422000Y121272D02*
Y124242D01*
X423000Y122272D02*
Y123838D01*
X418055Y128783D02*
X416217Y126945D01*
X417702Y125460*
X419540Y127298*
X418055Y128783*
X417162Y126000D02*
X418242D01*
X416272Y127000D02*
X419242D01*
X417272Y128000D02*
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Y127838D01*
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Y127728D01*
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X171000Y122162D02*
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X166272Y127000D02*
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X167272Y128000D02*
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X160758Y123000D02*
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X161000Y122162D02*
Y123242D01*
X162000Y121272D02*
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X156272Y127000D02*
X159242D01*
X157272Y128000D02*
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X157000Y126162D02*
Y127728D01*
X158000Y125758D02*
Y128728D01*
X159000Y126758D02*
Y127838D01*
X459800Y557300D02*
X482900D01*
Y538700*
X459800*
Y557300*
Y556699D02*
X482900D01*
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X459800Y554899D02*
X482900D01*
X459800Y553999D02*
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X459800Y553099D02*
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X459800Y552199D02*
X482900D01*
X459800Y551299D02*
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X459800Y550399D02*
X482900D01*
X459800Y549499D02*
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X459800Y547699D02*
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X459800Y546799D02*
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X459800Y545899D02*
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X459800Y544999D02*
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X459800Y543199D02*
X482900D01*
X459800Y542299D02*
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X459800Y541399D02*
X482900D01*
X459800Y540499D02*
X482900D01*
X459800Y539599D02*
X482900D01*
G54D40*
X450000Y210000D03*
X127000Y521000D03*
G54D117*
X414000Y568500D03*
Y581500D03*
X518000Y536500D03*
Y549500D03*
G54D118*
X279300Y285200D03*
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X266100Y354300D03*
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X395600Y371000D03*
X388000D03*
X265600Y317500D03*
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X264800Y364500D03*
X272400D03*
X505000Y169900D03*
X512600D03*
X402200Y343300D03*
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X265200Y328200D03*
X272800D03*
G54D119*
X470200Y268600D03*
Y261000D03*
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Y399900D03*
X347900Y406800D03*
Y399200D03*
X505000Y160800D03*
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X476000D03*
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X448200Y318200D03*
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X524000Y168700D03*
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G54D120*
X336500Y457500D03*
X323500D03*
G54D121*
X450700Y469500D03*
X458700D03*
X454700Y461500D03*
X460000Y494000D03*
X452000D03*
X456000Y502000D03*
X309000Y535000D03*
X301000D03*
X305000Y543000D03*
X283000Y535000D03*
X275000D03*
X279000Y543000D03*
X377000Y537000D03*
X369000D03*
X373000Y545000D03*
X349000Y536000D03*
X341000D03*
X345000Y544000D03*
X476000Y494000D03*
X468000D03*
X472000Y502000D03*
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X216000Y498500D03*
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Y486000D03*
X265000Y490000D03*
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X265000Y474000D03*
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X200000Y498500D03*
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G54D122*
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X436100Y260800D03*
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X222200Y291900D03*
X214600D03*
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X170000Y287300D03*
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X140800Y282500D03*
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X281200Y469000D03*
X288800D03*
X281200Y487000D03*
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X281200Y478000D03*
X288800D03*
X414300Y377200D03*
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X391800Y379700D03*
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X275200D03*
X282800D03*
X369200Y526000D03*
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X341200D03*
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X344800Y553000D03*
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X501500Y229600D03*
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G54D123*
X425000Y376800D03*
Y369200D03*
X421300Y270800D03*
Y278400D03*
X468800Y236900D03*
Y244500D03*
X495000Y153200D03*
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X485000D03*
Y153200D03*
X420000Y198200D03*
Y205800D03*
Y177800D03*
Y170200D03*
X344000Y177800D03*
Y170200D03*
Y200200D03*
Y207800D03*
X262000Y200200D03*
Y207800D03*
Y175800D03*
Y168200D03*
X184000Y175800D03*
Y168200D03*
Y200200D03*
Y207800D03*
X208000Y357200D03*
Y364800D03*
X198000Y357200D03*
Y364800D03*
X188000Y357200D03*
Y364800D03*
X178000Y357200D03*
Y364800D03*
X168000Y357200D03*
Y364800D03*
X158000Y357200D03*
Y364800D03*
X148000Y357200D03*
Y364800D03*
X138000Y357200D03*
Y364800D03*
X442700Y469100D03*
Y461500D03*
X476000Y473800D03*
Y466200D03*
X485000Y473800D03*
Y466200D03*
X209500Y482300D03*
Y474700D03*
X201000Y482300D03*
Y474700D03*
X527000Y396600D03*
Y389000D03*
X517000Y396600D03*
Y389000D03*
X507000Y396600D03*
Y389000D03*
X497000Y396600D03*
Y389000D03*
X487000Y396600D03*
Y389000D03*
X477000Y396600D03*
Y389000D03*
X467000Y396600D03*
Y389000D03*
X457000Y396600D03*
Y389000D03*
X136000Y478800D03*
Y471200D03*
X145000Y478800D03*
Y471200D03*
X136000Y493800D03*
Y486200D03*
X154000Y478800D03*
Y471200D03*
X163000Y478800D03*
Y471200D03*
X154000Y493800D03*
Y486200D03*
X172000Y478800D03*
Y471200D03*
X181000Y478800D03*
Y471200D03*
X172000Y493800D03*
Y486200D03*
X244000Y534300D03*
Y526700D03*
X235500Y534300D03*
Y526700D03*
X133000Y163800D03*
Y156200D03*
X382700Y397000D03*
Y389400D03*
X143000Y163800D03*
Y156200D03*
X293000Y566200D03*
Y573800D03*
X266000Y566200D03*
Y573800D03*
X360000Y566200D03*
Y573800D03*
X445000Y376800D03*
Y369200D03*
X435000Y376800D03*
Y369200D03*
X524500Y194200D03*
Y201800D03*
X228000Y498300D03*
Y490700D03*
X444000Y501800D03*
Y494200D03*
X352000Y430800D03*
Y423200D03*
X330000Y432300D03*
Y424700D03*
X321500Y432300D03*
Y424700D03*
X236500Y498300D03*
Y490700D03*
X361000Y430800D03*
Y423200D03*
X338500Y432300D03*
Y424700D03*
G54D124*
X299342Y380323D03*
X301311D03*
X303280D03*
X305249D03*
X307218D03*
X309187D03*
X311156D03*
X313125D03*
X315094D03*
X317063D03*
X319032D03*
X321001D03*
X322970D03*
X324939D03*
X326908D03*
X328877D03*
X330846D03*
X332815D03*
X334784D03*
X336753D03*
X338722D03*
X340691D03*
X342660D03*
X344629D03*
X346598D03*
X348567D03*
X350536D03*
X352505D03*
X354474D03*
X356443D03*
X358412D03*
X360381D03*
X362350D03*
X364319D03*
X366288D03*
X368257D03*
X368258Y295677D03*
X366289D03*
X364320D03*
X362351D03*
X360382D03*
X358413D03*
X356444D03*
X354475D03*
X352506D03*
X350537D03*
X348568D03*
X346599D03*
X344630D03*
X342661D03*
X340692D03*
X338723D03*
X336754D03*
X334785D03*
X332816D03*
X330847D03*
X328878D03*
X326909D03*
X324940D03*
X322971D03*
X321002D03*
X319033D03*
X317064D03*
X315095D03*
X313126D03*
X311157D03*
X309188D03*
X307219D03*
X305250D03*
X303281D03*
X301312D03*
X299343D03*
G54D125*
X376123Y372458D03*
Y370489D03*
Y368520D03*
Y366551D03*
Y364582D03*
Y362613D03*
Y360644D03*
Y358675D03*
Y356706D03*
Y354737D03*
Y352768D03*
Y350799D03*
Y348830D03*
Y346861D03*
Y344892D03*
Y342923D03*
Y340954D03*
Y338985D03*
Y337016D03*
Y335047D03*
Y333078D03*
Y331109D03*
Y329140D03*
Y327171D03*
Y325202D03*
Y323233D03*
Y321264D03*
Y319295D03*
Y317326D03*
Y315357D03*
Y313388D03*
Y311419D03*
Y309450D03*
Y307481D03*
Y305512D03*
Y303543D03*
X291477Y303542D03*
Y305511D03*
Y307480D03*
Y309449D03*
Y311418D03*
Y313387D03*
Y315356D03*
Y317325D03*
Y319294D03*
Y321263D03*
Y323232D03*
Y325201D03*
Y327170D03*
Y329139D03*
Y331108D03*
Y333077D03*
Y335046D03*
Y337015D03*
Y338984D03*
Y340953D03*
Y342922D03*
Y344891D03*
Y346860D03*
Y348829D03*
Y350798D03*
Y352767D03*
Y354736D03*
Y356705D03*
Y358674D03*
Y360643D03*
Y362612D03*
Y364581D03*
Y366550D03*
Y368519D03*
Y370488D03*
Y372457D03*
G54D126*
X484150Y175300D03*
Y171600D03*
Y167900D03*
X474450D03*
Y175300D03*
X513150Y154500D03*
Y158200D03*
Y161900D03*
X522850D03*
Y154500D03*
G54D127*
X353250Y206400D03*
X355750D03*
X358250D03*
X360750D03*
X363250D03*
X365750D03*
X368250D03*
X370750D03*
X373250D03*
X375750D03*
X378250D03*
X380750D03*
X383250D03*
X385750D03*
X388250D03*
X390750D03*
X393250D03*
X395750D03*
X398250D03*
X400750D03*
X403250D03*
X405750D03*
X408250D03*
X410750D03*
Y169600D03*
X408250D03*
X405750D03*
X403250D03*
X400750D03*
X398250D03*
X395750D03*
X393250D03*
X390750D03*
X388250D03*
X385750D03*
X383250D03*
X380750D03*
X378250D03*
X375750D03*
X373250D03*
X370750D03*
X368250D03*
X365750D03*
X363250D03*
X360750D03*
X358250D03*
X355750D03*
X353250D03*
X194250Y206400D03*
X196750D03*
X199250D03*
X201750D03*
X204250D03*
X206750D03*
X209250D03*
X211750D03*
X214250D03*
X216750D03*
X219250D03*
X221750D03*
X224250D03*
X226750D03*
X229250D03*
X231750D03*
X234250D03*
X236750D03*
X239250D03*
X241750D03*
X244250D03*
X246750D03*
X249250D03*
X251750D03*
Y169600D03*
X249250D03*
X246750D03*
X244250D03*
X241750D03*
X239250D03*
X236750D03*
X234250D03*
X231750D03*
X229250D03*
X226750D03*
X224250D03*
X221750D03*
X219250D03*
X216750D03*
X214250D03*
X211750D03*
X209250D03*
X206750D03*
X204250D03*
X201750D03*
X199250D03*
X196750D03*
X194250D03*
G54D128*
X427000Y537800D03*
Y557800D03*
Y547800D03*
G54D129*
X315200Y471500D03*
Y489700D03*
G54D130*
X345200Y480600D03*
G54D131*
X437600Y309100D03*
X417600D03*
Y325700D03*
X437600D03*
G54D132*
X499200Y253700D03*
Y248700D03*
Y243700D03*
Y238700D03*
X477800D03*
Y243700D03*
Y248700D03*
Y253700D03*
X507500D03*
Y248700D03*
Y243700D03*
Y238700D03*
X477500D03*
Y243700D03*
Y248700D03*
Y253700D03*
X499200Y220500D03*
Y215500D03*
Y210500D03*
Y205500D03*
X477800D03*
Y210500D03*
Y215500D03*
Y220500D03*
X507500D03*
Y215500D03*
Y210500D03*
Y205500D03*
X477500D03*
Y210500D03*
Y215500D03*
Y220500D03*
X0Y0D02*
M02*

/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/T1.PHO
0,0 → 1,8412
*
*
G04 PADS 9.2 Build Number: 414666 generated Gerber (RS-274-X) file*
G04 PC Version=2.1*
*
%IN "S3AN01A.pcb"*%
*
%MOIN*%
*
%FSLAX35Y35*%
*
*
*
*
G04 PC Standard Apertures*
*
*
G04 Thermal Relief Aperture macro.*
%AMTER*
1,1,$1,0,0*
1,0,$1-$2,0,0*
21,0,$3,$4,0,0,45*
21,0,$3,$4,0,0,135*
%
*
*
G04 Annular Aperture macro.*
%AMANN*
1,1,$1,0,0*
1,0,$2,0,0*
%
*
*
G04 Odd Aperture macro.*
%AMODD*
1,1,$1,0,0*
1,0,$1-0.005,0,0*
%
*
*
G04 PC Custom Aperture Macros*
*
*
*
*
*
*
G04 PC Aperture Table*
*
%ADD020C,0.012*%
%ADD024C,0.001*%
%ADD025C,0.01*%
%ADD026C,0.00787*%
%ADD029C,0.005*%
%ADD036C,0.008*%
*
*
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
*
G04 PC Custom Flashes*
G04 Layer Name S3AN01A.pcb - flashes*
%LPD*%
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
G54D20*
G01X115000Y210000D02*
X479000D01*
Y121000*
G54D24*
G54D25*
X226000Y436563D02*
X227136Y430000D01*
X228273Y436563D02*
X227136Y430000D01*
X228273Y436563D02*
X229409Y430000D01*
X230545Y436563D02*
X229409Y430000D01*
X232591Y436563D02*
X233727Y430000D01*
X234864Y436563D02*
X233727Y430000D01*
X234864Y436563D02*
X236000Y430000D01*
X237136Y436563D02*
X236000Y430000D01*
X239182Y436563D02*
X240318Y430000D01*
X241455Y436563D02*
X240318Y430000D01*
X241455Y436563D02*
X242591Y430000D01*
X243727Y436563D02*
X242591Y430000D01*
X246000Y430625D02*
X245773Y430313D01*
X245773D02*
X246000Y430000D01*
X246227Y430313*
X246227D02*
X246000Y430625D01*
X248273Y436563D02*
Y430000D01*
Y436563D02*
X250091Y430000D01*
X251909Y436563D02*
X250091Y430000D01*
X251909Y436563D02*
Y430000D01*
X253955Y436563D02*
Y430000D01*
X256682*
X260545Y436563D02*
X258727Y430000D01*
X260545Y436563D02*
X262364Y430000D01*
X259409Y432188D02*
X261682D01*
X264409Y436563D02*
Y430000D01*
Y436563D02*
X266455D01*
X266455D02*
X267136Y436250D01*
X267364Y435938*
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X189273*
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Y174750*
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X189455*
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X184000Y202250D02*
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Y202250D02*
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X193636Y189250*
X194455*
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Y187000*
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X220636*
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X222273Y187000*
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X222000Y190000*
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X219545*
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Y184000D01*
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Y191875D02*
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Y191875D02*
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X362091*
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Y530000*
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X363727Y527500*
Y526750*
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X362818Y526000*
X362091*
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X370455Y530000D02*
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Y527750*
X378818Y526500*
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Y530250D01*
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X445750Y278000*
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X478000*
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X479750Y274182*
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X478000*
Y273818D02*
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X474750Y276364D02*
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X474750Y280545D02*
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Y280545*
X485750Y272000D02*
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X496000Y274182*
X495750Y273818*
Y273091*
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X497750Y272000*
X499000*
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Y273818*
X500750Y274182*
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X497000Y279091D02*
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X496000Y278545*
X495750Y278182*
Y277455*
X496000Y277091*
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Y282909*
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X505750Y276182D02*
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X346727Y349000*
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X476000Y561000D02*
X486000Y571000D01*
X488000*
G74*
X0Y0D02*
M02*

/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V1.PHO
0,0 → 1,21155
*
*
G04 PADS 9.2 Build Number: 414666 generated Gerber (RS-274-X) file*
G04 PC Version=2.1*
*
%IN "S3AN01A.pcb"*%
*
%MOIN*%
*
%FSLAX35Y35*%
*
*
*
*
G04 PC Standard Apertures*
*
*
G04 Thermal Relief Aperture macro.*
%AMTER*
1,1,$1,0,0*
1,0,$1-$2,0,0*
21,0,$3,$4,0,0,45*
21,0,$3,$4,0,0,135*
%
*
*
G04 Annular Aperture macro.*
%AMANN*
1,1,$1,0,0*
1,0,$2,0,0*
%
*
*
G04 Odd Aperture macro.*
%AMODD*
1,1,$1,0,0*
1,0,$1-0.005,0,0*
%
*
*
G04 PC Custom Aperture Macros*
*
*
*
*
*
*
G04 PC Aperture Table*
*
%ADD011C,0.06*%
%ADD012R,0.07X0.07*%
%ADD013C,0.23622*%
%ADD014C,0.05*%
%ADD019C,0.03*%
%ADD020C,0.012*%
%ADD022C,0.055*%
%ADD024C,0.001*%
%ADD025C,0.01*%
%ADD031C,0.07*%
%ADD032R,0.08X0.08*%
%ADD040R,0.06X0.06*%
%ADD047C,0.025*%
%ADD055C,0.103*%
%ADD056C,0.177*%
%ADD057C,0.04331*%
%ADD058C,0.07874*%
%ADD059C,0.12*%
%ADD060C,0.118*%
*
*
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
*
G04 PC Custom Flashes*
G04 Layer Name S3AN01A.pcb - flashes*
%LPD*%
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
G54D11*
G01X255000Y120000D03*
X265000D03*
X275000D03*
X285000D03*
X295000D03*
X305000D03*
X315000D03*
X325000D03*
X335000D03*
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X355000D03*
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X375000D03*
X385000D03*
X395000D03*
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X215000Y140000D03*
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X195000Y140000D03*
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X185000Y140000D03*
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X175000Y140000D03*
Y130000D03*
X165000Y140000D03*
Y130000D03*
X155000Y140000D03*
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X245000Y120000D03*
X235000D03*
X225000D03*
X215000D03*
X205000D03*
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X185000D03*
X175000D03*
X165000D03*
X155000D03*
X351300Y271100D03*
X452600Y244700D03*
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X442600Y244700D03*
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X432600Y244700D03*
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X422600Y244700D03*
Y234700D03*
X412600Y244700D03*
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X402600Y244700D03*
Y234700D03*
X392600Y244700D03*
Y234700D03*
X382600Y244700D03*
Y234700D03*
X372600Y244700D03*
Y234700D03*
X362600Y244700D03*
Y234700D03*
X352600Y244700D03*
Y234700D03*
X342600Y244700D03*
Y234700D03*
X332600Y244700D03*
Y234700D03*
X322600Y244700D03*
Y234700D03*
X312600Y244700D03*
Y234700D03*
X302600Y244700D03*
Y234700D03*
X292600Y244700D03*
Y234700D03*
X282600Y244700D03*
Y234700D03*
X272600Y244700D03*
Y234700D03*
X262600Y244700D03*
Y234700D03*
X252600Y244700D03*
Y234700D03*
X242600Y244700D03*
Y234700D03*
X465000Y140000D03*
Y130000D03*
X455000Y140000D03*
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X445000Y140000D03*
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X435000Y140000D03*
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X425000Y140000D03*
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X415000Y140000D03*
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X405000Y140000D03*
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X395000Y140000D03*
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X385000Y140000D03*
Y130000D03*
X375000Y140000D03*
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X365000Y140000D03*
Y130000D03*
X355000Y140000D03*
Y130000D03*
X345000Y140000D03*
Y130000D03*
X335000Y140000D03*
Y130000D03*
X325000Y140000D03*
Y130000D03*
X315000Y140000D03*
Y130000D03*
X305000Y140000D03*
Y130000D03*
X295000Y140000D03*
Y130000D03*
X285000Y140000D03*
Y130000D03*
X275000Y140000D03*
Y130000D03*
X265000Y140000D03*
Y130000D03*
X255000Y140000D03*
Y130000D03*
X415000Y450000D03*
X425000D03*
X435000D03*
X445000D03*
X455000D03*
Y510000D03*
X445000D03*
X435000D03*
X425000D03*
X415000D03*
X405000D03*
X214000Y450000D03*
X224000D03*
X234000D03*
X244000D03*
X254000D03*
Y510000D03*
X244000D03*
X234000D03*
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X133479D01*
X112700Y345599D02*
X133301D01*
X112700Y335699D02*
X133232D01*
X112700Y375299D02*
X133230D01*
X112700Y367199D02*
X133031D01*
X112700Y343799D02*
X133030D01*
X112700Y353699D02*
X133013D01*
X112700Y374399D02*
X133000D01*
X112700Y373499D02*
X133000D01*
X112700Y372599D02*
X133000D01*
X112700Y371699D02*
X133000D01*
X112700Y370799D02*
X133000D01*
X112700Y369899D02*
X133000D01*
X112700Y368999D02*
X133000D01*
X112700Y368099D02*
X133000D01*
X112700Y352799D02*
X133000D01*
X112700Y351899D02*
X133000D01*
X112700Y350999D02*
X133000D01*
X112700Y350099D02*
X133000D01*
X112700Y349199D02*
X133000D01*
X112700Y348299D02*
X133000D01*
X112700Y347399D02*
X133000D01*
X112700Y346499D02*
X133000D01*
X112700Y342899D02*
X133000D01*
X112700Y341999D02*
X133000D01*
X112700Y341099D02*
X133000D01*
X112700Y340199D02*
X133000D01*
X112700Y339299D02*
X133000D01*
X112700Y338399D02*
X133000D01*
X112700Y337499D02*
X133000D01*
X112700Y336599D02*
X133000D01*
X112700Y395999D02*
X132501D01*
X112700Y405899D02*
X132428D01*
X112700Y396899D02*
X132073D01*
X112700Y404999D02*
X132050D01*
X112700Y404099D02*
X132000D01*
X112700Y403199D02*
X132000D01*
X112700Y402299D02*
X132000D01*
X112700Y401399D02*
X132000D01*
X112700Y400499D02*
X132000D01*
X112700Y399599D02*
X132000D01*
X112700Y398699D02*
X132000D01*
X112700Y397799D02*
X132000D01*
X112700Y245699D02*
X130766D01*
X112700Y246599D02*
X130168D01*
X112700Y252899D02*
X130000D01*
X112700Y251999D02*
X130000D01*
X112700Y251099D02*
X130000D01*
X112700Y250199D02*
X130000D01*
X112700Y249299D02*
X130000D01*
X112700Y248399D02*
X130000D01*
X112700Y247499D02*
X130000D01*
X128642Y253799D02*
X129896D01*
X128162Y168299D02*
X128588D01*
X112700Y253799D02*
X127358D01*
X112700Y529199D02*
X127314D01*
X112700Y550799D02*
X127304D01*
X112700Y278999D02*
X126599D01*
X112700Y269099D02*
X126430D01*
X112700Y269999D02*
X126303D01*
X112700Y278099D02*
X126300D01*
X112700Y277199D02*
X126300D01*
X112700Y276299D02*
X126300D01*
X112700Y275399D02*
X126300D01*
X112700Y274499D02*
X126300D01*
X112700Y273599D02*
X126300D01*
X112700Y272699D02*
X126300D01*
X112700Y271799D02*
X126300D01*
X112700Y270899D02*
X126300D01*
X112700Y293399D02*
X126177D01*
X112700Y305099D02*
X126064D01*
X112700Y294299D02*
X125509D01*
X112700Y304199D02*
X125467D01*
X112700Y254699D02*
X125323D01*
X112700Y295199D02*
X125302D01*
X112700Y303299D02*
X125300D01*
X112700Y302399D02*
X125300D01*
X112700Y301499D02*
X125300D01*
X112700Y300599D02*
X125300D01*
X112700Y299699D02*
X125300D01*
X112700Y298799D02*
X125300D01*
X112700Y297899D02*
X125300D01*
X112700Y296999D02*
X125300D01*
X112700Y296099D02*
X125300D01*
X112700Y268199D02*
X125202D01*
X112700Y261899D02*
X125094D01*
X112700Y260999D02*
X124988D01*
X112700Y530099D02*
X124916D01*
X112700Y549899D02*
X124911D01*
X112700Y255599D02*
X124493D01*
X112700Y267299D02*
X124425D01*
X112700Y262799D02*
X124364D01*
X112700Y260099D02*
X124304D01*
X112700Y256499D02*
X124024D01*
X112700Y266399D02*
X123987D01*
X112700Y263699D02*
X123954D01*
X112700Y259199D02*
X123923D01*
X112700Y257399D02*
X123793D01*
X112700Y265499D02*
X123779D01*
X112700Y264599D02*
X123769D01*
X112700Y258299D02*
X123760D01*
X112700Y530999D02*
X123453D01*
X112700Y548999D02*
X123450D01*
X112700Y531899D02*
X122368D01*
X112700Y548099D02*
X122365D01*
X112700Y532799D02*
X121513D01*
X112700Y547199D02*
X121511D01*
X112700Y533699D02*
X120825D01*
X112700Y546299D02*
X120824D01*
X112700Y534599D02*
X120268D01*
X112700Y545399D02*
X120267D01*
X112700Y535499D02*
X119821D01*
X112700Y544499D02*
X119820D01*
X112700Y536399D02*
X119469D01*
X112700Y543599D02*
X119468D01*
X112700Y537299D02*
X119203D01*
X112700Y542699D02*
X119202D01*
X112700Y538199D02*
X119017D01*
X112700Y541799D02*
X119016D01*
X112700Y539099D02*
X118906D01*
X112700Y540899D02*
X118906D01*
X112700Y539999D02*
X118870D01*
X112700Y178199D02*
X118444D01*
X112700Y168299D02*
X117901D01*
X112700Y177299D02*
X117666D01*
X112700Y169199D02*
X117523D01*
X112700Y176399D02*
X117500D01*
X112700Y175499D02*
X117500D01*
X112700Y174599D02*
X117500D01*
X112700Y173699D02*
X117500D01*
X112700Y172799D02*
X117500D01*
X112700Y171899D02*
X117500D01*
X112700Y170999D02*
X117500D01*
X112700Y170099D02*
X117500D01*
G54D31*
X531100Y407863D03*
X513500D03*
X535000Y539063D03*
X496000Y407863D03*
X478500D03*
X460800D03*
X443300D03*
X425700D03*
X408000D03*
X428363Y271700D03*
X190969Y534000D03*
X199984D03*
X209000D03*
X218016D03*
X227031D03*
X186461Y544000D03*
X195476D03*
X204492D03*
X213508D03*
X222524D03*
X190969Y554000D03*
X199984D03*
X209000D03*
X218016D03*
X227031D03*
X146000Y251000D03*
X166000D03*
X186000D03*
X196000D03*
X216000D03*
X300882Y555189D03*
X311118D03*
X292614D03*
X319386D03*
X292614Y545346D03*
X319386D03*
X367882Y555189D03*
X378118D03*
X359614D03*
X386386D03*
X359614Y545346D03*
X386386D03*
G54D32*
X226800Y299300D03*
X209800D03*
Y274100D03*
X226800D03*
X200800Y299300D03*
X183800D03*
Y274100D03*
X200800D03*
X174800Y299300D03*
X157800D03*
Y274100D03*
X174800D03*
X148800Y299300D03*
X131800D03*
Y274100D03*
X148800D03*
G54D40*
X405000Y450000D03*
X204000D03*
G54D47*
X471400Y278000D02*
Y306000D01*
G54D55*
X481900Y578300D03*
X426900D03*
G54D56*
X258213Y544000D03*
X159787D03*
G54D57*
X493269Y345000D03*
X489331Y340000D03*
Y335000D03*
X493269Y330000D03*
X489331Y325000D03*
Y320000D03*
X493269Y315000D03*
X246031Y322600D03*
X249969Y327600D03*
Y332600D03*
X246031Y337600D03*
X249969Y342600D03*
Y347600D03*
X246031Y352600D03*
G54D58*
X491300Y304488D03*
Y355512D03*
X248000Y363112D03*
Y312088D03*
G54D59*
X332575Y567000D03*
X279425D03*
X399575D03*
X346425D03*
G54D60*
X306000Y570150D03*
X373000D03*
G74*
X0Y0D02*
M02*

/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V2.PHO
0,0 → 1,8106
*
*
G04 PADS 9.2 Build Number: 414666 generated Gerber (RS-274-X) file*
G04 PC Version=2.1*
*
%IN "S3AN01A.pcb"*%
*
%MOIN*%
*
%FSLAX35Y35*%
*
*
*
*
G04 PC Standard Apertures*
*
*
G04 Thermal Relief Aperture macro.*
%AMTER*
1,1,$1,0,0*
1,0,$1-$2,0,0*
21,0,$3,$4,0,0,45*
21,0,$3,$4,0,0,135*
%
*
*
G04 Annular Aperture macro.*
%AMANN*
1,1,$1,0,0*
1,0,$2,0,0*
%
*
*
G04 Odd Aperture macro.*
%AMODD*
1,1,$1,0,0*
1,0,$1-0.005,0,0*
%
*
*
G04 PC Custom Aperture Macros*
*
*
*
*
*
*
G04 PC Aperture Table*
*
%ADD011C,0.06*%
%ADD012R,0.07X0.07*%
%ADD013C,0.23622*%
%ADD014C,0.05*%
%ADD016C,0.04*%
%ADD017C,0.02*%
%ADD019C,0.03*%
%ADD020C,0.012*%
%ADD022C,0.055*%
%ADD024C,0.001*%
%ADD025C,0.01*%
%ADD031C,0.07*%
%ADD032R,0.08X0.08*%
%ADD036C,0.008*%
%ADD040R,0.06X0.06*%
%ADD047C,0.025*%
%ADD055C,0.103*%
%ADD056C,0.177*%
%ADD057C,0.04331*%
%ADD058C,0.07874*%
%ADD059C,0.12*%
%ADD060C,0.118*%
%ADD061R,0.1X0.055*%
%ADD062R,0.039X0.056*%
%ADD063R,0.056X0.039*%
%ADD064R,0.055X0.1*%
%ADD065R,0.04X0.04*%
%ADD066R,0.039X0.051*%
%ADD067R,0.051X0.039*%
%ADD068O,0.012X0.08*%
%ADD069O,0.08X0.012*%
%ADD070R,0.045X0.024*%
%ADD071O,0.012X0.052*%
%ADD072R,0.105X0.065*%
%ADD073R,0.41X0.425*%
%ADD074R,0.072X0.06*%
%ADD075R,0.2X0.2*%
%ADD076R,0.07X0.08*%
%ADD077O,0.07X0.025*%
*
*
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
*
G04 PC Custom Flashes*
G04 Layer Name S3AN01A.pcb - flashes*
%LPD*%
*
*
G04 PC Circuitry*
G04 Layer Name S3AN01A.pcb - circuitry*
%LPD*%
*
G54D11*
G01X351300Y271100D03*
X415000Y450000D03*
X425000D03*
X435000D03*
X445000D03*
X455000D03*
Y510000D03*
X445000D03*
X435000D03*
X425000D03*
X415000D03*
X405000D03*
X214000Y450000D03*
X224000D03*
X234000D03*
X244000D03*
X254000D03*
Y510000D03*
X244000D03*
X234000D03*
X224000D03*
X214000D03*
X204000D03*
G54D12*
X531100Y417737D03*
X513500D03*
X535000Y548937D03*
X496000Y417737D03*
X478500D03*
X460800D03*
X443300D03*
X425700D03*
X408000D03*
X438237Y271700D03*
X494000Y581000D03*
X504000D03*
X494000Y571000D03*
X504000D03*
X494000Y561000D03*
X504000D03*
X537000Y161000D03*
Y171000D03*
Y181000D03*
Y191000D03*
Y201000D03*
Y211000D03*
Y221000D03*
Y231000D03*
Y241000D03*
Y251000D03*
X245000Y140000D03*
X235000D03*
X225000D03*
X215000D03*
X205000D03*
X195000D03*
X185000D03*
X175000D03*
X165000D03*
X155000D03*
X494000Y549000D03*
X504000D03*
X494000Y539000D03*
X504000D03*
X494000Y529000D03*
X504000D03*
X229700Y237400D03*
X219700D03*
X209700D03*
X199700D03*
X189700D03*
X179700D03*
X169700D03*
X159700D03*
X149700D03*
X139700D03*
X452600Y244700D03*
Y234700D03*
X442600Y244700D03*
Y234700D03*
X432600Y244700D03*
Y234700D03*
X422600Y244700D03*
Y234700D03*
X412600Y244700D03*
Y234700D03*
X402600Y244700D03*
Y234700D03*
X392600Y244700D03*
Y234700D03*
X382600Y244700D03*
Y234700D03*
X372600Y244700D03*
Y234700D03*
X362600Y244700D03*
Y234700D03*
X352600Y244700D03*
Y234700D03*
X342600Y244700D03*
Y234700D03*
X332600Y244700D03*
Y234700D03*
X322600Y244700D03*
Y234700D03*
X312600Y244700D03*
Y234700D03*
X302600Y244700D03*
Y234700D03*
X292600Y244700D03*
Y234700D03*
X282600Y244700D03*
Y234700D03*
X272600Y244700D03*
Y234700D03*
X262600Y244700D03*
Y234700D03*
X252600Y244700D03*
Y234700D03*
X242600Y244700D03*
Y234700D03*
X391100Y272100D03*
Y262100D03*
X381100Y272100D03*
Y262100D03*
X208000Y350000D03*
Y340000D03*
X198000Y350000D03*
Y340000D03*
X188000Y350000D03*
Y340000D03*
X178000Y350000D03*
Y340000D03*
X168000Y350000D03*
Y340000D03*
X158000Y350000D03*
Y340000D03*
X148000Y350000D03*
Y340000D03*
X138000Y350000D03*
Y340000D03*
X527000Y382800D03*
Y372800D03*
X517000Y382800D03*
Y372800D03*
X507000Y382800D03*
Y372800D03*
X497000Y382800D03*
Y372800D03*
X487000Y382800D03*
Y372800D03*
X477000Y382800D03*
Y372800D03*
X467000Y382800D03*
Y372800D03*
X457000Y382800D03*
Y372800D03*
X136000Y251000D03*
X123000Y173000D03*
X133000D03*
X143000D03*
X153000D03*
X414200Y396500D03*
Y386500D03*
X404200Y396500D03*
Y386500D03*
X394200Y396500D03*
Y386500D03*
X445600Y396000D03*
Y386000D03*
X435600Y396000D03*
Y386000D03*
X425600Y396000D03*
Y386000D03*
X275600Y276200D03*
Y266200D03*
X265600Y276200D03*
Y266200D03*
X255600Y276200D03*
Y266200D03*
X245600Y276200D03*
Y266200D03*
X505000Y145000D03*
Y135000D03*
X495000Y145000D03*
Y135000D03*
X485000Y145000D03*
Y135000D03*
X465000Y140000D03*
X455000D03*
X445000D03*
X435000D03*
X425000D03*
X415000D03*
X405000D03*
X395000D03*
X385000D03*
X375000D03*
X365000D03*
X355000D03*
X345000D03*
X335000D03*
X325000D03*
X315000D03*
X305000D03*
X295000D03*
X285000D03*
X275000D03*
X265000D03*
X255000D03*
X138000Y371000D03*
X148000D03*
X158000D03*
X168000D03*
X178000D03*
X188000D03*
X198000D03*
X208000D03*
Y401000D03*
X198000D03*
X188000D03*
X178000D03*
X168000D03*
X158000D03*
X148000D03*
X138000D03*
X488000Y265000D03*
X508000D03*
X498000D03*
X448000D03*
X528000D03*
X478000D03*
G54D13*
X130000Y570000D03*
X530000D03*
Y130000D03*
X130000D03*
G54D14*
Y540000D03*
X460000Y200000D03*
G54D16*
X130000Y130000D02*
X144500D01*
Y144300*
X153000Y152800*
Y173000*
X155000Y120000D02*
X145000Y130000D01*
X144500*
X155000Y120000D02*
X165000D01*
X175000*
X185000D02*
X175000D01*
X155000Y130000D02*
Y140000D01*
X165000Y130000D02*
Y140000D01*
X175000Y130000D02*
Y140000D01*
X185000Y130000D02*
Y140000D01*
X222121Y120000D02*
X224400D01*
X224700Y120300*
X255000Y130000D02*
Y140000D01*
X265000Y130000D02*
Y140000D01*
X195000Y120000D02*
X204200D01*
X204600Y120400*
X195000Y120000D02*
X185000D01*
X205000D02*
X214200D01*
X214600Y120400*
X215000Y120000D02*
X222121D01*
X225000D02*
X235000D01*
X245000*
X195000Y130000D02*
Y140000D01*
X205000Y130000D02*
Y140000D01*
X215000Y130000D02*
Y140000D01*
X225000Y130000D02*
Y140000D01*
X235000Y130000D02*
Y140000D01*
X245000Y130000D02*
Y140000D01*
X265000Y120000D02*
X273900D01*
X274450Y120550*
X265000Y120000D02*
X255000D01*
X245000*
X282121D02*
X275000D01*
Y130000D02*
Y140000D01*
X285000Y130000D02*
Y140000D01*
X295000Y130000D02*
Y140000D01*
X305000Y130000D02*
Y140000D01*
X315000Y130000D02*
Y140000D01*
X325000Y130000D02*
Y140000D01*
X335000Y130000D02*
Y140000D01*
X345000Y130000D02*
Y140000D01*
Y120000D02*
X335000D01*
X325000*
X315000*
X305000*
X295000*
X285000*
X282121*
X355000Y130000D02*
Y140000D01*
X365000Y130000D02*
Y140000D01*
X375000Y130000D02*
Y140000D01*
X385000Y130000D02*
Y140000D01*
X395000Y130000D02*
Y140000D01*
X405000Y130000D02*
Y140000D01*
X415000Y130000D02*
Y140000D01*
X425000Y130000D02*
Y140000D01*
Y120000D02*
X415000D01*
X405000*
X395000*
X385000*
X375000*
X365000*
X355000*
X345000*
X469900D02*
X520400D01*
X530400Y130000*
X530000*
X435000D02*
Y140000D01*
X445000Y130000D02*
Y140000D01*
X455000Y130000D02*
Y140000D01*
X465000Y130000D02*
Y140000D01*
X469900Y120000D02*
X465000D01*
X455400*
X455000D02*
X445000D01*
X435000*
X425000*
X530000Y130000D02*
X540200Y140200D01*
Y145900*
X537000Y149100*
Y161000*
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G74*
X0Y0D02*
M02*

/Modules/CPLD_FPGA/S3AN01B/PrjInfo.txt
0,0 → 1,28
//
// Toto je popisný soubor pro popis obsahu adresáře (příklad)
//
[InfoShortDescription.en]
Xilinx Spartan 3 XC3S50AN FPGA School Board
[InfoShortDescription.cs]
Školní deska Xilinx Spartan 3AN XC3S50AN
[InfoLongDescription.en]
The school board allows interested people to play with FPGA
from XILINX. The board contains LED display, some switches
and push buttons. It has VGA video port, PS/2 ports for
keyboard and mouse. Because the main chip is not 5V tolerant,
the board is equipped with 5V tolerant buffers (inputs).
The board is powered from 5V, internal power supply is included.
For timing there is one 100MHz crystal oscillator.
[InfoLongDescription.cs]
Školní deska umožňuje za rozumné peníze začít pracovat
s obvody FPGA firmy XILINX. Obsahuje LED display, sadu
tlačítek a přepínačů a porty pro připojení VGA monitoru
a PS/2 klávesnice nebo myši. Protože obvod není 5V tolerantní,
je před část vstupů předřazen 5V tolerantní budič (vstup).
Součástí desky jsou napájecí zdroje a oscilátor 100MHz.
[End]

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/HDL/S3AN01_ChipScope.ucf
0,0 → 1,112
# Board: www.mlab.cz S3AN01A
# Device: XC3S50AN-4TQG144C
# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes
# Main Clock (Embedded 100MHz board oscillator)
NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33;
NET "CLK100MHz" TNM_NET = CLK100MHz;
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;
# Enable suboptimal routing of CLK100MHz to DCM input
# (the CLK100MHz pin is across the whole chip realtive to DCM)
# PIN "DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
# Place BUFGMUX at the appropriate position
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;
# SPI Flash Vendor Mode Select (for external SPI boot Flash)
NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# DIP Switches (positive signals with pull-down)
NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# LED String (positive output signals)
NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33;
NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33;
NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33;
NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33;
NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33;
NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33;
NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33;
NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33;
# LED Display Output Signals (negative, multiplexed) - Segments
NET "LD_SEG_n[0]" LOC = P15 |IOSTANDARD = LVCMOS33; # Segment A A
NET "LD_SEG_n[1]" LOC = P30 |IOSTANDARD = LVCMOS33; # Segment B -----
NET "LD_SEG_n[2]" LOC = P21 |IOSTANDARD = LVCMOS33; # Segment C F | | B
NET "LD_SEG_n[3]" LOC = P19 |IOSTANDARD = LVCMOS33; # Segment D | G |
NET "LD_SEG_n[4]" LOC = P18 |IOSTANDARD = LVCMOS33; # Segment E -----
NET "LD_SEG_n[5]" LOC = P16 |IOSTANDARD = LVCMOS33; # Segment F E | | C
NET "LD_SEG_n[6]" LOC = P24 |IOSTANDARD = LVCMOS33; # Segment G | D |
NET "LD_SEG_n[7]" LOC = P20 |IOSTANDARD = LVCMOS33; # Segment DP ----- DP
# LED Display Output Signals (negative, multiplexed) - Common Anodas
NET "LD_CA_n[0]" LOC = P25 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[1]" LOC = P31 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[2]" LOC = P32 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[3]" LOC = P13 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.13 with U1.33
NET "LD_CA_n[4]" LOC = P27 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[5]" LOC = P29 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[6]" LOC = P28 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[7]" LOC = P12 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.12 with U1.35
# Bank 1 Port (input for tests, pull-up)
NET "P[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# Diferencial Signals on 4 pin header (J7)
NET "DIF1P" LOC = P110 |IOSTANDARD = LVDS_33;
NET "DIF1N" LOC = P111 |IOSTANDARD = LVDS_33;
NET "DIF2P" LOC = P112 |IOSTANDARD = LVDS_33;
NET "DIF2N" LOC = P113 |IOSTANDARD = LVDS_33;
# Timing Constraint for Crossing Time Domain
# Source is ChipScope_VIO_FreqSel output in CLK_FAST time domain
# Destination is SW_SYNC register in CLK100MHz time domain
INST "SW_SYNC_?" TNM = "TNM_SW_SYNC";
TIMESPEC "TS_SW_SYNC" = TO "TNM_SW_SYNC" TIG;
# Timing Constraint for Crossing Time Domain
# Source is SET_CLK_xxx register (FSM) in CLK100MHz time domain
# Destination is ChipScope_VIO_FreqSel inputs in CLK_FAST time domain
INST "SYNC_IN_?" TNM = "TNM_SET_CLK";
TIMESPEC "TS_SET_CLK" = TO "TNM_SET_CLK" TIG;
# Timing Constraint for Clock Switch
# Block BUFGMUX is used as Assynchronous switcher
PIN "BUFGMUX_CLK_FAST.S" TIG;

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/HDL/S3AN01_ChipScope.vhd
0,0 → 1,612
-- ========================================================================
--
-- S3AN01_ChipScope
--
-- Logic Analyser based on Xilinx ChipScope IP Core for S3AN01 Board
--
-- (c) miho 2013 / http://www.mlab.cz/PermaLink/XILINX_ChipScope
--
-- Demo application contains some Clock Logic (DCM block and
-- clock switch to be able to set different sample clocks).
-- The main function is ChipScope Logic Analyser with 16 data inputs
-- (with 24 bit trigger) and storage for 1024 Data Samples.
--
-- Sampling clock is selectable to 170/100/50/20/10/5/2/1MHz
--
-- To implement the design the ChipScope license is required.
--
-- To use (the logic analyser) no speceial license is needed,
-- WebPack ISE or Lab Tools is enough). Requires some compatible
-- JTAG cable. Compatible with MLAB Xilinx Virtual Cable as well
-- http://www.mlab.cz/PermaLink/XILINX_XVC
--
-- Device: Spartan3AN XC3S50AN-4TQG144C
--
-- Software: ISE WebPack 14.5
--
-- ========================================================================
-- Standard Library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Xilinx Library (necessary for DMC and other Xilinx blocks)
library UNISIM;
use UNISIM.VComponents.all;
-- Interface
entity S3AN01_ChipScope is
generic(
ILA_WIDE: boolean := TRUE; -- TRUE/FALSE -> 18bit x 1024 / 9bit x 2048 logic analyser
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
);
port(
-- Main Clock
CLK100MHz: in std_logic; -- 100MHz external xtal clock source
-- Mode Signals (usualy not used)
VS: out std_logic_vector(2 downto 0); -- SPI Flash Vendor Mode Select
-- Dipswitch Inputs
DIPSW: in std_logic_vector(7 downto 0);
-- LED Bar Outputs
LED: out std_logic_vector(7 downto 0);
-- LED Display (8 digits with 7 segments and decimal point)
LD_CA_n: out std_logic_vector(7 downto 0);
LD_SEG_n: out std_logic_vector(7 downto 0);
-- Bank 1 Pins Inputs
P: in std_logic_vector(24 downto 0);
-- Diferencial Signals on 4 pin header (J7)
DIF1P: inout std_logic;
DIF1N: inout std_logic;
DIF2P: inout std_logic;
DIF2N: inout std_logic
);
end S3AN01_ChipScope;
-- Implementation
architecture S3AN01_ChipScope_a of S3AN01_ChipScope is
-- Clock Signals
-- =============
-- DCM Signals
signal DCM_CLK0: std_logic; -- DCM output for feedback
signal DCM_CLKFX: std_logic; -- DCM output of the fastest clock
signal CLK_FAST: std_logic; -- Main clock for ILA
signal CLK_FAST_Q: std_logic; -- Auxiliary signal (for CLK_FAST sent to pin)
-- 100MHz Clock Switch
-- CLK100MHz Clock Domain
signal CLK100MHz_CE: std_logic; -- Gate Signal for slow dwn of the 100MHz clock
signal CLK100MHz_Gated: std_logic; -- Gated Clocks
signal CLK100MHz_CE_Cnt: unsigned(6 downto 0) := (others => '0'); -- Gate Signal Counter (min frequency is 1/100 of CLK100MHz
-- 1 Hot Clock Select Signals
-- CLK100MHz Clock Domain
signal SET_CLK_MAX: std_logic := '0'; -- Clock Select Signal - Maximim (150-170Mhz)
signal SET_CLK_100MHz: std_logic := '1'; -- Clock Select Signal - 100MHz
signal SET_CLK_50MHz: std_logic := '0'; -- Clock Select Signal - 50MHz
signal SET_CLK_20Mhz: std_logic := '0'; -- Clock Select Signal - 20MHz
signal SET_CLK_10Mhz: std_logic := '0'; -- Clock Select Signal - 10MHz
signal SET_CLK_5Mhz: std_logic := '0'; -- Clock Select Signal - 5MHz
signal SET_CLK_2Mhz: std_logic := '0'; -- Clock Select Signal - 2MHz
signal SET_CLK_1Mhz: std_logic := '0'; -- Clock Select Signal - 1MHz
-- Signals from and to ChipScope Virtual IO (set and display frequency)
-- CLK_FAST and CLK100MHz time domain
signal SYNC_IN: std_logic_vector(7 downto 0); -- Input to ChipScope VIO
signal SYNC_OUT: std_logic_vector(7 downto 0); -- Output from ChipScope VIO
signal SW_SYNC: std_logic_vector(7 downto 0) := (others => '0'); -- Asyn inputs synced
-- LED Ouput with time multiplex
-- =============================
signal WideBCD: std_logic_vector(2*5-1 downto 0); -- Constant width of ILA in BCD (2 char wide)
signal FrequencyBCD: std_logic_vector(3*5-1 downto 0); -- Selected frequency in BCD (3 char wide)
signal Code: std_logic_vector(4 downto 0); -- BCD to 7 Segment Decoder Output
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
-- Time Multiplex
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
signal LedEnable: std_logic; -- LED Display Brightness
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
-- Test Generator signals
-- ======================
signal Counter: std_logic_vector(7 downto 0); -- Counter
-- ChipScope Signals
-- =================
-- Input data
-- CLK_FAST Clock Domain
signal DataReg: std_logic_vector(P'range); -- Data and Trigger input
-- Trigger Output
signal TriggerOut: std_logic; -- Trigegr output from ChipScope ILA to pin
-- User Outputs from ChipScope Virtual IO
signal SYNC_OUT_USER: std_logic_vector(2 downto 0); -- Output from ChipScope VIO
-- ChipScope Control Signals
signal Control0: std_logic_vector(35 downto 0);
signal Control1: std_logic_vector(35 downto 0);
signal Control2: std_logic_vector(35 downto 0);
-- ChipScope Control Block
component ChipScope_ICON
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0)
);
end component;
-- ChipScope Virtual I/O Block
component ChipScope_VIO_FreqSel
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
SYNC_IN: in std_logic_vector(7 downto 0);
SYNC_OUT: out std_logic_vector(7 downto 0)
);
end component;
-- ChipScope Virtual I/O Block
component ChipScope_VIO_UserOut
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
SYNC_OUT: out std_logic_vector(2 downto 0)
);
end component;
-- ChipScope Integrated Logic Analyser
component ChipScope_ILA_18_1024
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(17 downto 0); -- 18 bits wide data
TRIG0: in std_logic_vector(23 downto 0);
TRIG_OUT: out std_logic
);
end component;
-- ChipScope Integrated Logic Analyser
component ChipScope_ILA_9_2048
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(8 downto 0); -- 9 bits wide data
TRIG0: in std_logic_vector(23 downto 0);
TRIG_OUT: out std_logic
);
end component;
begin
-- ===================================================
-- Clock Network and Clock Switching
-- ===================================================
--
-- The fastest clock signal is generated from 100MHz by DCM.
-- The design maximim is 170MHz for selected device.
--
-- For lower frequency the 100MHz clocks are gated in BUFGCE
-- acording to SET_CLK_xxx signals.
--
-- For Logic Analyser we use 170MHz from DCM or gated 100MHz
-- switchd by BUFGMUX block.
-- DCM_SP: Digital Clock Manager Circuit
-- Spartan-3A
-- Xilinx HDL Language Template, version 14.5
--
-- CLKFB without BUFG (we do not need phase relation to the original clock)
--
-- Design Limits (XC3S50AN-4):
--
-- 5/3 -> 166MHz - o.k. (best 5.9ns - 169.5MHz)
-- 17/10 -> 170MHz - o.k. (best 5.748ns - 174MHz) <------ Used Here
-- 12/7 -> 171MHz - Timing Error
-- 7/4 -> 175MHz - Timing Error
-- 18/10 -> 180MHz - Timing Error
--
DCM_SP_inst: DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 17, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 10.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15
DLL_FREQUENCY_MODE => "HIGH", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
)
port map (
CLK0 => DCM_CLK0, -- 0 degree DCM CLK ouptput
-- CLK180 => CLK180, -- 180 degree DCM CLK output
-- CLK270 => CLK270, -- 270 degree DCM CLK output
-- CLK2X => CLK2X, -- 2X DCM CLK output
-- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
-- CLK90 => CLK90, -- 90 degree DCM CLK output
-- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => DCM_CLKFX, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
-- LOCKED => LOCKED, -- DCM LOCK status output
-- PSDONE => PSDONE, -- Dynamic phase adjust done output
-- STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => DCM_CLK0, -- DCM clock feedback
CLKIN => CLK100MHz, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => PSCLK, -- Dynamic phase adjust clock input
-- PSEN => PSEN, -- Dynamic phase adjust enable input
-- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
-- Generate Clock Gate signal for 100MHz Clock
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if CLK100MHz_CE_Cnt=0 then
CLK100MHz_CE <= '1';
if SET_CLK_100MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(1-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_50MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(2-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_20MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(5-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_10MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(10-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_5MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(20-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_2MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(50-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_1MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(100-1, CLK100MHz_CE_Cnt'length);
end if;
else
CLK100MHz_CE <= '0';
CLK100MHz_CE_Cnt <= CLK100MHz_CE_Cnt-1;
end if;
end if;
end process;
-- Gate 100MHz Clocks (to produce 100/50/20/10/5/2/1 MHz)
-- Generates 5ns pulses with 10/20/50/100/200/500/1000ns period
BUFGCE_CLK100MHz: BUFGCE
port map (
I => CLK100MHz, -- Clock buffer input
CE => CLK100MHz_CE, -- Clock enable input
O => CLK100MHz_Gated -- Clock buffer ouptput
);
-- Switch (gated) 100MHz and the fastest Clock signal from DCM
BUFGMUX_CLK_FAST: BUFGMUX
port map (
I0 => CLK100MHz_Gated, -- Clock0 input -- 100/50/20/10/50/20/1MHz
I1 => DCM_CLKFX, -- Clock1 input -- 170MHz
S => SET_CLK_MAX, -- Clock select input
O => CLK_FAST -- Clock MUX output
);
-- Assynchrnous inputs and inputs from CLK_FAST clock domain must be synchronised
-- SYNC_OUT - CLK_FAST clock domain
-- DIPSW - External (off-chip) async inputs
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
SW_SYNC <= SYNC_OUT or DIPSW;
end if;
end process;
-- Ferquency Selector
-- FSM - 1 hot
process (CLK100MHz)
variable TMP: std_logic_vector(SYNC_OUT'range);
variable NEW_DATA: std_logic;
begin
if rising_edge(CLK100MHz) then
TMP := (others => '0');
NEW_DATA := '1';
if SW_SYNC(7)='1' then
TMP(7) := '1';
elsif SW_SYNC(6)='1' then
TMP(6) := '1';
elsif SW_SYNC(5)='1' then
TMP(5) := '1';
elsif SW_SYNC(4)='1' then
TMP(4) := '1';
elsif SW_SYNC(3)='1' then
TMP(3) := '1';
elsif SW_SYNC(2)='1' then
TMP(2) := '1';
elsif SW_SYNC(1)='1' then
TMP(1) := '1';
elsif SW_SYNC(0)='1' then
TMP(0) := '1';
else
NEW_DATA := '0';
end if;
if NEW_DATA='1' then
SET_CLK_MAX <= TMP(7);
SET_CLK_100MHz <= TMP(6);
SET_CLK_50MHz <= TMP(5);
SET_CLK_20MHz <= TMP(4);
SET_CLK_10MHz <= TMP(3);
SET_CLK_5MHz <= TMP(2);
SET_CLK_2MHz <= TMP(1);
SET_CLK_1MHz <= TMP(0);
end if;
end if;
end process;
-- Send selected frequency to ChipScope Virtual IO
-- Sync it to the CLK_FAST timing domain
SET_CLK_proc: process (CLK_FAST)
begin
if rising_edge(CLK_FAST) then
SYNC_IN(7) <= SET_CLK_MAX;
SYNC_IN(6) <= SET_CLK_100MHz;
SYNC_IN(5) <= SET_CLK_50MHz;
SYNC_IN(4) <= SET_CLK_20Mhz;
SYNC_IN(3) <= SET_CLK_10Mhz;
SYNC_IN(2) <= SET_CLK_5Mhz;
SYNC_IN(1) <= SET_CLK_2Mhz;
SYNC_IN(0) <= SET_CLK_1Mhz;
end if;
end process;
-- ===================================================
-- ChipScope Instance - Control / Virtual IO / ILA
-- ===================================================
-- ChipScope Instance - Control Block
MyChipScopeICON: ChipScope_ICON
port map (
CONTROL0 => Control0,
CONTROL1 => Control1,
CONTROL2 => Control2
);
-- ChipScope Instance - Virtual I/O Block
MyChipScopeVIO_FreqSel: ChipScope_VIO_FreqSel
port map (
CONTROL => Control0,
CLK => CLK_FAST,
SYNC_IN => SYNC_IN,
SYNC_OUT => SYNC_OUT
);
-- ChipScope Instance - Virtual I/O Block
MyChipScopeVIO_UserOut: ChipScope_VIO_UserOut
port map (
CONTROL => Control1,
CLK => CLK_FAST,
SYNC_OUT => SYNC_OUT_USER
);
-- ChipScope Instance - Integrated Logic Analyser
ILA_18_1024: if ILA_WIDE generate
begin
MyChipScopeILA: ChipScope_ILA_18_1024
port map (
CONTROL => Control2,
CLK => CLK_FAST,
DATA => DataReg(17 downto 0),
TRIG0 => DataReg(23 downto 0),
TRIG_OUT => TriggerOut
);
end generate;
ILA_9_2048: if not ILA_WIDE generate
begin
MyChipScopeILA: ChipScope_ILA_9_2048
port map (
CONTROL => Control2,
CLK => CLK_FAST,
DATA => DataReg(8 downto 0),
TRIG0 => DataReg(23 downto 0),
TRIG_OUT => TriggerOut
);
end generate;
-- Data inputs (ILA does not like to have data inputs connected to io pins)
process(CLK_FAST)
begin
if rising_edge(CLK_FAST) then
DataReg <= P(DataReg'range);
end if;
end process;
-- VIO User Outputs
VS <= SYNC_OUT_USER;
-- Trigger Output (Diferencial signal)
OBUFDS_TriggerOut: OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
I => TriggerOut, -- Buffer input
O => DIF1P, -- Diff_p output (connect directly to top-level port)
OB => DIF1N -- Diff_n output (connect directly to top-level port)
);
-- ===================================================
-- LED Display (multiplexed)
-- ===================================================
-- Frequency in BCD
FrequencyBCD <= "00001"&"00111"&"00000" when SET_CLK_MAX='1' else -- 170 MHz
"00001"&"00000"&"00000" when SET_CLK_100MHz='1' else -- 100 MHz
"11111"&"00101"&"00000" when SET_CLK_50MHz='1' else -- 50 MHz
"11111"&"00010"&"00000" when SET_CLK_20MHz='1' else -- 20 MHz
"11111"&"00001"&"00000" when SET_CLK_10MHz='1' else -- 10 MHz
"11111"&"11111"&"00101" when SET_CLK_5MHz='1' else -- 5 MHz
"11111"&"11111"&"00010" when SET_CLK_2MHz='1' else -- 2 MHz
"11111"&"11111"&"00001" when SET_CLK_1MHz='1' else -- 1 MHz
"11111"&"11111"&"11111";
-- ILA width in BCD
ILA_DCD_18_1024: if ILA_WIDE generate
begin
WideBCD <= "00001"&"01000";
end generate;
ILA_DCD_9_2048: if not ILA_WIDE generate
begin
WideBCD <= "11111"&"01001";
end generate;
-- Input data selector ( WIDE / ILA / FREQ )
Code <= FrequencyBCD( 4 downto 0) when Digits="00000001" else
FrequencyBCD( 9 downto 5) when Digits="00000010" else
FrequencyBCD(14 downto 10) when Digits="00000100" else
"10010" when Digits="00001000" else -- A
"10001" when Digits="00010000" else -- L
"10000" when Digits="00100000" else -- I
WideBCD( 4 downto 0) when Digits="01000000" else
WideBCD( 9 downto 5) when Digits="10000000" else
"11111";
-- Time Multiplex
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if MuxCounter < MUXCOUNT-1 then
MuxCounter <= MuxCounter + 1;
else
MuxCounter <= (others => '0');
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left (1 hot encoded)
end if;
-- Display brightness (1/2)
if MuxCounter > (MUXCOUNT-MUXCOUNT/2) then
LedEnable <= '1';
else
LedEnable <= '0';
end if;
end if;
end process;
-- BCD to 7 Segmet Decoder
-- -- A
-- | | F B
-- -- G
-- | | E C
-- -- D H
-- HGFEDCBA
Segments <= "00111111" when Code="00000" else -- Digit 0 -- Hex Didits
"00000110" when Code="00001" else -- Digit 1
"01011011" when Code="00010" else -- Digit 2
"01001111" when Code="00011" else -- Digit 3
"01100110" when Code="00100" else -- Digit 4
"01101101" when Code="00101" else -- Digit 5
"01111101" when Code="00110" else -- Digit 6
"00000111" when Code="00111" else -- Digit 7
"01111111" when Code="01000" else -- Digit 8
"01101111" when Code="01001" else -- Digit 9
"01110111" when Code="01010" else -- Digit A
"01111100" when Code="01011" else -- Digit b
"00111001" when Code="01100" else -- Digit C
"01011110" when Code="01101" else -- Digit d
"01111001" when Code="01110" else -- Digit E
"00110001" when Code="01111" else -- Digit F
"00000110" when Code="10000" else -- Digit I -- User Digits
"00111000" when Code="10001" else -- Digit L
"01110111" when Code="10010" else -- Digit A
"00000000"; -- none
-- Connect LED Display Output Ports (negative outputs)
LD_CA_n <= not Digits;
LD_SEG_n <= not Segments when LedEnable='1' else "11111111";
-- ===================================================
-- Test generator (counter)
-- ===================================================
-- Test counter
process(CLK100MHz)
begin
if rising_edge(CLK100MHz) then
Counter <= std_logic_vector(unsigned(Counter) + 1);
end if;
end process;
-- Test outputs
LED <= Counter;
-- CLK_FAST Output - DDR register
ODDR2_FastClk: ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset
)
port map (
C0 => CLK_FAST, -- 1-bit clock input
C1 => not CLK_FAST, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0', -- 1-bit set input
Q => CLK_FAST_Q -- 1-bit output data
);
-- CLK_FAST Output - differncial pin buffer
OBUFDS_FastClkOut: OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
I => CLK_FAST_Q, -- Buffer input
O => DIF2P, -- Diff_p output (connect directly to top-level port)
OB => DIF2N -- Diff_n output (connect directly to top-level port)
);
end S3AN01_ChipScope_a;

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.6/S3AN01_ChipScope_18x1024.bit
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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.6/S3AN01_ChipScope_9x2048.bit
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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.6/Version
0,0 → 1,4
TimeStamp: 2013_06_28__12_18
ComputerName: MIHO-W7
ISE Version: 14.6
ReleaseInfo: None

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/S3AN01_ChipScope_18x1024.bit
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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/S3AN01_ChipScope_9x2048.bit
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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/Version
0,0 → 1,4
TimeStamp: 2013_06_25__09_41
ComputerName: MIHOMSI
ISE Version: 13.3
ReleaseInfo: None

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/S3AN01_ChipScope_18x1024.bit
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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/S3AN01_ChipScope_9x2048.bit
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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/Version
0,0 → 1,4
TimeStamp: 2013_06_25__17_31
ComputerName: MIHO-W7
ISE Version: 14.5
ReleaseInfo: None

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser.ini
0,0 → 1,24
#ChipScope Pro Analyzer Configuration File
#Tue Jun 25 16:04:01 CEST 2013
OPEN_TARGET.host=localhost\:2542
xilinx_parallel.PORT=LPT1
previous_cable_name=xilinx_xvc
OPEN_TARGET.disableversioncheck=true
guiLocationY=14
guiLocationX=90
guiWidth=1448
guiHeight=907
previous_cable_cmd=open_target
lastParallelCable=xilinx_parallel3
projectDir=..\\ANALYSER
OPEN_TARGET.keylist=disableversioncheck host
xilinx_parallel.FREQUENCY=5000000
previous_cable_key=OPEN_TARGET
xilinx_parallel.keylist=FREQUENCY PORT
previous.defaultDirectory=..\\ANALYSER
openTarget.2=xilinx_parallel PORT\=LPT1 FREQUENCY\=2500000
openTarget.1=xilinx_platformusb PORT\=USB21 FREQUENCY\=6000000
debugOn=0
openTarget.0=xilinx_xvc host\=localhost\:2542 disableversioncheck\=true
project1=..\\ANALYSER\\Analyser_9_2048.cpj
project0=..\\ANALYSER\\Analyser_18_1024.cpj

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser_18_1024.cpj
0,0 → 1,1076
#ChipScope Pro Analyzer Project File, Version 3.0
#Tue Jun 25 09:46:51 CEST 2013
device.0.configFileDir=..\\BIN
device.0.configFilename=S3AN01_ChipScope_18x1024.bit
device.0.inserterCDCFileDir=
device.0.inserterCDCFilename=
deviceChain.deviceName0=XC3S50AN
deviceChain.iRLength0=6
deviceChain.name0=Trigger Setup
deviceIds=02610093
mdiAreaHeight=0.6990077177508269
mdiAreaHeightLast=0.6990077177508269
mdiCount=4
mdiDevice0=0
mdiDevice1=0
mdiDevice2=0
mdiDevice3=0
mdiType0=1
mdiType1=6
mdiType2=0
mdiType3=6
mdiUnit0=2
mdiUnit1=1
mdiUnit2=2
mdiUnit3=0
navigatorHeight=0.24807056229327454
navigatorHeightLast=0.2866593164277839
navigatorWidth=0.17472375690607736
navigatorWidthLast=0.14433701657458564
signalDisplayPath=0
unit.-1.-1.username=
unit.0.-1.username=
unit.0.0.0.HEIGHT0=0.3660856
unit.0.0.0.TriggerRow0=1
unit.0.0.0.TriggerRow1=1
unit.0.0.0.TriggerRow2=1
unit.0.0.0.WIDTH0=0.9940426
unit.0.0.0.X0=0.0
unit.0.0.0.Y0=0.0
unit.0.0.1.HEIGHT1=0.58161646
unit.0.0.1.WIDTH1=0.9940426
unit.0.0.1.X1=0.0
unit.0.0.1.Y1=0.3660856
unit.0.0.6.HEIGHT6=0.75594294
unit.0.0.6.WIDTH6=0.17021276
unit.0.0.6.X6=0.0025531915
unit.0.0.6.Y6=0.014263075
unit.0.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXX
unit.0.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXX
unit.0.0.MFBitsB0=000000000000000000000000
unit.0.0.MFBitsB1=000000000000000000000000
unit.0.0.MFCompareA0=0
unit.0.0.MFCompareA1=0
unit.0.0.MFCompareB0=999
unit.0.0.MFCompareB1=999
unit.0.0.MFCount=2
unit.0.0.MFDisplay0=0
unit.0.0.MFDisplay1=0
unit.0.0.MFEventType0=3
unit.0.0.MFEventType1=3
unit.0.0.RunMode=SINGLE RUN
unit.0.0.SQCondition=All Data
unit.0.0.SQContiguous0=0
unit.0.0.SequencerOn=0
unit.0.0.TCActive=0
unit.0.0.TCAdvanced0=0
unit.0.0.TCCondition0_0=M0
unit.0.0.TCCondition0_1=
unit.0.0.TCConditionType0=0
unit.0.0.TCCount=1
unit.0.0.TCEventCount0=1
unit.0.0.TCEventType0=3
unit.0.0.TCName0=TriggerCondition0
unit.0.0.TCOutputEnable0=0
unit.0.0.TCOutputHigh0=1
unit.0.0.TCOutputMode0=0
unit.0.0.coretype=VIO
unit.0.0.eventCount0=1
unit.0.0.eventCount1=1
unit.0.0.port.-1.buscount=0
unit.0.0.port.-1.channelcount=0
unit.0.0.port.-1.s.0.alias=
unit.0.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.0.name=DataPort[0]
unit.0.0.port.-1.s.0.orderindex=-1
unit.0.0.port.-1.s.0.visible=1
unit.0.0.port.-1.s.1.alias=
unit.0.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.1.name=DataPort[1]
unit.0.0.port.-1.s.1.orderindex=-1
unit.0.0.port.-1.s.1.visible=1
unit.0.0.port.-1.s.10.alias=
unit.0.0.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.10.name=DataPort[10]
unit.0.0.port.-1.s.10.orderindex=-1
unit.0.0.port.-1.s.10.visible=1
unit.0.0.port.-1.s.11.alias=
unit.0.0.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.11.name=DataPort[11]
unit.0.0.port.-1.s.11.orderindex=-1
unit.0.0.port.-1.s.11.visible=1
unit.0.0.port.-1.s.12.alias=
unit.0.0.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.12.name=DataPort[12]
unit.0.0.port.-1.s.12.orderindex=-1
unit.0.0.port.-1.s.12.visible=1
unit.0.0.port.-1.s.13.alias=
unit.0.0.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.13.name=DataPort[13]
unit.0.0.port.-1.s.13.orderindex=-1
unit.0.0.port.-1.s.13.visible=1
unit.0.0.port.-1.s.14.alias=
unit.0.0.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.14.name=DataPort[14]
unit.0.0.port.-1.s.14.orderindex=-1
unit.0.0.port.-1.s.14.visible=1
unit.0.0.port.-1.s.15.alias=
unit.0.0.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.15.name=DataPort[15]
unit.0.0.port.-1.s.15.orderindex=-1
unit.0.0.port.-1.s.15.visible=1
unit.0.0.port.-1.s.16.alias=
unit.0.0.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.16.name=DataPort[16]
unit.0.0.port.-1.s.16.orderindex=-1
unit.0.0.port.-1.s.16.visible=1
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unit.0.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.2.port.0.s.10.alias=
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unit.0.2.rep_trigger.clobber=1
unit.0.2.rep_trigger.dir=D\:\\MLAB\\Modules\\CPLD_FPGA\\XILINX_ChipScope\\MAKE\\BIN\\13.3
unit.0.2.rep_trigger.filename=waveform
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unit.0.2.rep_trigger.loggingEnabled=0
unit.0.2.rep_trigger.signals=All Signals/Buses
unit.0.2.samplesPerTrigger=1
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unit.0.2.triggerNSamplesTS=0
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unit.0.2.username=Logic Analyser
unit.0.2.waveform.count=18
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unit.0.2.waveform.posn.1.name=P[1]
unit.0.2.waveform.posn.1.type=signal
unit.0.2.waveform.posn.10.channel=10
unit.0.2.waveform.posn.10.name=P[10]
unit.0.2.waveform.posn.10.type=signal
unit.0.2.waveform.posn.11.channel=11
unit.0.2.waveform.posn.11.name=P[11]
unit.0.2.waveform.posn.11.type=signal
unit.0.2.waveform.posn.12.channel=12
unit.0.2.waveform.posn.12.name=P[12]
unit.0.2.waveform.posn.12.type=signal
unit.0.2.waveform.posn.13.channel=13
unit.0.2.waveform.posn.13.name=P[13]
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unit.0.2.waveform.posn.16.type=signal
unit.0.2.waveform.posn.17.channel=17
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unit.0.2.waveform.posn.2.channel=2
unit.0.2.waveform.posn.2.name=P[2]
unit.0.2.waveform.posn.2.type=signal
unit.0.2.waveform.posn.3.channel=3
unit.0.2.waveform.posn.3.name=P[3]
unit.0.2.waveform.posn.3.type=signal
unit.0.2.waveform.posn.4.channel=4
unit.0.2.waveform.posn.4.name=P[4]
unit.0.2.waveform.posn.4.type=signal
unit.0.2.waveform.posn.5.channel=5
unit.0.2.waveform.posn.5.name=P[5]
unit.0.2.waveform.posn.5.type=signal
unit.0.2.waveform.posn.6.channel=6
unit.0.2.waveform.posn.6.name=P[6]
unit.0.2.waveform.posn.6.type=signal
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unit.0.2.waveform.posn.7.type=signal
unit.0.2.waveform.posn.8.channel=8
unit.0.2.waveform.posn.8.name=P[8]
unit.0.2.waveform.posn.8.type=signal
unit.0.2.waveform.posn.9.channel=9
unit.0.2.waveform.posn.9.name=P[9]
unit.0.2.waveform.posn.9.type=signal

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser_9_2048.cpj
0,0 → 1,1076
#ChipScope Pro Analyzer Project File, Version 3.0
#Tue Jun 25 09:45:10 CEST 2013
device.0.configFileDir=..\\BIN
device.0.configFilename=S3AN01_ChipScope_9x2048.bit
device.0.inserterCDCFileDir=
device.0.inserterCDCFilename=
deviceChain.deviceName0=XC3S50AN
deviceChain.iRLength0=6
deviceChain.name0=Trigger Setup
deviceIds=02610093
mdiAreaHeight=0.6990077177508269
mdiAreaHeightLast=0.6990077177508269
mdiCount=4
mdiDevice0=0
mdiDevice1=0
mdiDevice2=0
mdiDevice3=0
mdiType0=1
mdiType1=6
mdiType2=0
mdiType3=6
mdiUnit0=2
mdiUnit1=1
mdiUnit2=2
mdiUnit3=0
navigatorHeight=0.24696802646085997
navigatorHeightLast=0.2866593164277839
navigatorWidth=0.17472375690607736
navigatorWidthLast=0.14433701657458564
signalDisplayPath=0
unit.-1.-1.username=
unit.0.-1.username=
unit.0.0.0.HEIGHT0=0.3660856
unit.0.0.0.TriggerRow0=1
unit.0.0.0.TriggerRow1=1
unit.0.0.0.TriggerRow2=1
unit.0.0.0.WIDTH0=0.9940426
unit.0.0.0.X0=0.0
unit.0.0.0.Y0=0.0
unit.0.0.1.HEIGHT1=0.58161646
unit.0.0.1.WIDTH1=0.9940426
unit.0.0.1.X1=0.0
unit.0.0.1.Y1=0.3660856
unit.0.0.6.HEIGHT6=0.75594294
unit.0.0.6.WIDTH6=0.17021276
unit.0.0.6.X6=0.0025531915
unit.0.0.6.Y6=0.014263075
unit.0.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXX
unit.0.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXX
unit.0.0.MFBitsB0=000000000000000000000000
unit.0.0.MFBitsB1=000000000000000000000000
unit.0.0.MFCompareA0=0
unit.0.0.MFCompareA1=0
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unit.0.0.MFCompareB1=999
unit.0.0.MFCount=2
unit.0.0.MFDisplay0=0
unit.0.0.MFDisplay1=0
unit.0.0.MFEventType0=3
unit.0.0.MFEventType1=3
unit.0.0.RunMode=SINGLE RUN
unit.0.0.SQCondition=All Data
unit.0.0.SQContiguous0=0
unit.0.0.SequencerOn=0
unit.0.0.TCActive=0
unit.0.0.TCAdvanced0=0
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unit.0.0.TCCondition0_1=
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unit.0.0.TCCount=1
unit.0.0.TCEventCount0=1
unit.0.0.TCEventType0=3
unit.0.0.TCName0=TriggerCondition0
unit.0.0.TCOutputEnable0=0
unit.0.0.TCOutputHigh0=1
unit.0.0.TCOutputMode0=0
unit.0.0.coretype=VIO
unit.0.0.eventCount0=1
unit.0.0.eventCount1=1
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unit.0.0.port.-1.s.10.alias=
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unit.0.0.port.0.b.0.alias=
unit.0.0.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
unit.0.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.b.0.name=TriggerPort0
unit.0.0.port.0.b.0.orderindex=-1
unit.0.0.port.0.b.0.radix=Hex
unit.0.0.port.0.b.0.signedOffset=0.0
unit.0.0.port.0.b.0.signedPrecision=0
unit.0.0.port.0.b.0.signedScaleFactor=1.0
unit.0.0.port.0.b.0.unsignedOffset=0.0
unit.0.0.port.0.b.0.unsignedPrecision=0
unit.0.0.port.0.b.0.unsignedScaleFactor=1.0
unit.0.0.port.0.b.0.visible=1
unit.0.0.port.0.buscount=0
unit.0.0.port.0.channelcount=8
unit.0.0.port.0.s.0.alias=1 MHz
unit.0.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.0.display=14
unit.0.0.port.0.s.0.name=SyncIn[0]
unit.0.0.port.0.s.0.orderindex=-1
unit.0.0.port.0.s.0.persistence=0
unit.0.0.port.0.s.0.value=0
unit.0.0.port.0.s.0.visible=1
unit.0.0.port.0.s.1.alias=2 MHz
unit.0.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.1.display=14
unit.0.0.port.0.s.1.name=SyncIn[1]
unit.0.0.port.0.s.1.orderindex=-1
unit.0.0.port.0.s.1.persistence=0
unit.0.0.port.0.s.1.value=0
unit.0.0.port.0.s.1.visible=1
unit.0.0.port.0.s.10.alias=
unit.0.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.10.name=TriggerPort0[10]
unit.0.0.port.0.s.10.orderindex=-1
unit.0.0.port.0.s.10.visible=1
unit.0.0.port.0.s.11.alias=
unit.0.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.11.name=TriggerPort0[11]
unit.0.0.port.0.s.11.orderindex=-1
unit.0.0.port.0.s.11.visible=1
unit.0.0.port.0.s.12.alias=
unit.0.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.12.name=TriggerPort0[12]
unit.0.0.port.0.s.12.orderindex=-1
unit.0.0.port.0.s.12.visible=1
unit.0.0.port.0.s.13.alias=
unit.0.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.13.name=TriggerPort0[13]
unit.0.0.port.0.s.13.orderindex=-1
unit.0.0.port.0.s.13.visible=1
unit.0.0.port.0.s.14.alias=
unit.0.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.14.name=TriggerPort0[14]
unit.0.0.port.0.s.14.orderindex=-1
unit.0.0.port.0.s.14.visible=1
unit.0.0.port.0.s.15.alias=
unit.0.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.15.name=TriggerPort0[15]
unit.0.0.port.0.s.15.orderindex=-1
unit.0.0.port.0.s.15.visible=1
unit.0.0.port.0.s.16.alias=
unit.0.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.16.name=TriggerPort0[16]
unit.0.0.port.0.s.16.orderindex=-1
unit.0.0.port.0.s.16.visible=1
unit.0.0.port.0.s.17.alias=
unit.0.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.17.name=TriggerPort0[17]
unit.0.0.port.0.s.17.orderindex=-1
unit.0.0.port.0.s.17.visible=1
unit.0.0.port.0.s.18.alias=
unit.0.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.18.name=TriggerPort0[18]
unit.0.0.port.0.s.18.orderindex=-1
unit.0.0.port.0.s.18.visible=1
unit.0.0.port.0.s.19.alias=
unit.0.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.19.name=TriggerPort0[19]
unit.0.0.port.0.s.19.orderindex=-1
unit.0.0.port.0.s.19.visible=1
unit.0.0.port.0.s.2.alias=5 MHz
unit.0.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.2.display=14
unit.0.0.port.0.s.2.name=SyncIn[2]
unit.0.0.port.0.s.2.orderindex=-1
unit.0.0.port.0.s.2.persistence=0
unit.0.0.port.0.s.2.value=0
unit.0.0.port.0.s.2.visible=1
unit.0.0.port.0.s.20.alias=
unit.0.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.20.name=TriggerPort0[20]
unit.0.0.port.0.s.20.orderindex=-1
unit.0.0.port.0.s.20.visible=1
unit.0.0.port.0.s.21.alias=
unit.0.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.21.name=TriggerPort0[21]
unit.0.0.port.0.s.21.orderindex=-1
unit.0.0.port.0.s.21.visible=1
unit.0.0.port.0.s.22.alias=
unit.0.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.22.name=TriggerPort0[22]
unit.0.0.port.0.s.22.orderindex=-1
unit.0.0.port.0.s.22.visible=1
unit.0.0.port.0.s.23.alias=
unit.0.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.23.name=TriggerPort0[23]
unit.0.0.port.0.s.23.orderindex=-1
unit.0.0.port.0.s.23.visible=1
unit.0.0.port.0.s.3.alias=10 MHz
unit.0.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.3.display=14
unit.0.0.port.0.s.3.name=SyncIn[3]
unit.0.0.port.0.s.3.orderindex=-1
unit.0.0.port.0.s.3.persistence=0
unit.0.0.port.0.s.3.value=0
unit.0.0.port.0.s.3.visible=1
unit.0.0.port.0.s.4.alias=20 MHz
unit.0.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.4.display=14
unit.0.0.port.0.s.4.name=SyncIn[4]
unit.0.0.port.0.s.4.orderindex=-1
unit.0.0.port.0.s.4.persistence=0
unit.0.0.port.0.s.4.value=0
unit.0.0.port.0.s.4.visible=1
unit.0.0.port.0.s.5.alias=50 MHz
unit.0.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.5.display=14
unit.0.0.port.0.s.5.name=SyncIn[5]
unit.0.0.port.0.s.5.orderindex=-1
unit.0.0.port.0.s.5.persistence=0
unit.0.0.port.0.s.5.value=0
unit.0.0.port.0.s.5.visible=1
unit.0.0.port.0.s.6.alias=100 MHz
unit.0.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.6.display=14
unit.0.0.port.0.s.6.name=SyncIn[6]
unit.0.0.port.0.s.6.orderindex=-1
unit.0.0.port.0.s.6.persistence=0
unit.0.0.port.0.s.6.value=0
unit.0.0.port.0.s.6.visible=1
unit.0.0.port.0.s.7.alias=170 MHz
unit.0.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.7.display=14
unit.0.0.port.0.s.7.name=SyncIn[7]
unit.0.0.port.0.s.7.orderindex=-1
unit.0.0.port.0.s.7.persistence=0
unit.0.0.port.0.s.7.value=0
unit.0.0.port.0.s.7.visible=1
unit.0.0.port.0.s.8.alias=
unit.0.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.8.name=TriggerPort0[8]
unit.0.0.port.0.s.8.orderindex=-1
unit.0.0.port.0.s.8.visible=1
unit.0.0.port.0.s.9.alias=
unit.0.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.9.name=TriggerPort0[9]
unit.0.0.port.0.s.9.orderindex=-1
unit.0.0.port.0.s.9.visible=1
unit.0.0.port.1.buscount=0
unit.0.0.port.1.channelcount=0
unit.0.0.port.2.buscount=0
unit.0.0.port.2.channelcount=8
unit.0.0.port.2.s.0.alias=Set 1 MHz
unit.0.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.0.display=5
unit.0.0.port.2.s.0.name=SyncOut[0]
unit.0.0.port.2.s.0.orderindex=-1
unit.0.0.port.2.s.0.persistence=0
unit.0.0.port.2.s.0.value=0100000000000000
unit.0.0.port.2.s.0.visible=1
unit.0.0.port.2.s.1.alias=Set 2 MHz
unit.0.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.1.display=5
unit.0.0.port.2.s.1.name=SyncOut[1]
unit.0.0.port.2.s.1.orderindex=-1
unit.0.0.port.2.s.1.persistence=0
unit.0.0.port.2.s.1.value=0100000000000000
unit.0.0.port.2.s.1.visible=1
unit.0.0.port.2.s.2.alias=Set 5 MHz
unit.0.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.2.display=5
unit.0.0.port.2.s.2.name=SyncOut[2]
unit.0.0.port.2.s.2.orderindex=-1
unit.0.0.port.2.s.2.persistence=0
unit.0.0.port.2.s.2.value=0100000000000000
unit.0.0.port.2.s.2.visible=1
unit.0.0.port.2.s.3.alias=Set 10 MHz
unit.0.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.3.display=5
unit.0.0.port.2.s.3.name=SyncOut[3]
unit.0.0.port.2.s.3.orderindex=-1
unit.0.0.port.2.s.3.persistence=0
unit.0.0.port.2.s.3.value=0100000000000000
unit.0.0.port.2.s.3.visible=1
unit.0.0.port.2.s.4.alias=Set 20 MHz
unit.0.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.4.display=5
unit.0.0.port.2.s.4.name=SyncOut[4]
unit.0.0.port.2.s.4.orderindex=-1
unit.0.0.port.2.s.4.persistence=0
unit.0.0.port.2.s.4.value=0100000000000000
unit.0.0.port.2.s.4.visible=1
unit.0.0.port.2.s.5.alias=Set 50 MHz
unit.0.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.5.display=5
unit.0.0.port.2.s.5.name=SyncOut[5]
unit.0.0.port.2.s.5.orderindex=-1
unit.0.0.port.2.s.5.persistence=0
unit.0.0.port.2.s.5.value=0100000000000000
unit.0.0.port.2.s.5.visible=1
unit.0.0.port.2.s.6.alias=Set 100 MHz
unit.0.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.6.display=5
unit.0.0.port.2.s.6.name=SyncOut[6]
unit.0.0.port.2.s.6.orderindex=-1
unit.0.0.port.2.s.6.persistence=0
unit.0.0.port.2.s.6.value=0100000000000000
unit.0.0.port.2.s.6.visible=1
unit.0.0.port.2.s.7.alias=Set 170 MHz
unit.0.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.7.display=5
unit.0.0.port.2.s.7.name=SyncOut[7]
unit.0.0.port.2.s.7.orderindex=-1
unit.0.0.port.2.s.7.persistence=0
unit.0.0.port.2.s.7.value=0100000000000000
unit.0.0.port.2.s.7.visible=1
unit.0.0.portcount=3
unit.0.0.rep_trigger.clobber=1
unit.0.0.rep_trigger.dir=C\:\\Users\\miho
unit.0.0.rep_trigger.filename=waveform
unit.0.0.rep_trigger.format=ASCII
unit.0.0.rep_trigger.loggingEnabled=0
unit.0.0.rep_trigger.signals=All Signals/Buses
unit.0.0.samplesPerTrigger=1
unit.0.0.triggerCapture=1
unit.0.0.triggerNSamplesTS=0
unit.0.0.triggerPosition=0
unit.0.0.triggerWindowCount=1
unit.0.0.triggerWindowDepth=1024
unit.0.0.triggerWindowTS=0
unit.0.0.username=Set Frequency
unit.0.0.vio.count=16
unit.0.0.vio.posn.0.channel=0
unit.0.0.vio.posn.0.name=1 MHz
unit.0.0.vio.posn.0.port=0
unit.0.0.vio.posn.0.type=signal
unit.0.0.vio.posn.1.channel=1
unit.0.0.vio.posn.1.name=2 MHz
unit.0.0.vio.posn.1.port=0
unit.0.0.vio.posn.1.type=signal
unit.0.0.vio.posn.10.channel=2
unit.0.0.vio.posn.10.name=Set 5 MHz
unit.0.0.vio.posn.10.port=2
unit.0.0.vio.posn.10.type=signal
unit.0.0.vio.posn.11.channel=3
unit.0.0.vio.posn.11.name=Set 10 MHz
unit.0.0.vio.posn.11.port=2
unit.0.0.vio.posn.11.type=signal
unit.0.0.vio.posn.12.channel=4
unit.0.0.vio.posn.12.name=Set 20 MHz
unit.0.0.vio.posn.12.port=2
unit.0.0.vio.posn.12.type=signal
unit.0.0.vio.posn.13.channel=5
unit.0.0.vio.posn.13.name=Set 50 MHz
unit.0.0.vio.posn.13.port=2
unit.0.0.vio.posn.13.type=signal
unit.0.0.vio.posn.14.channel=6
unit.0.0.vio.posn.14.name=Set 100 MHz
unit.0.0.vio.posn.14.port=2
unit.0.0.vio.posn.14.type=signal
unit.0.0.vio.posn.15.channel=7
unit.0.0.vio.posn.15.name=Set 170 MHz
unit.0.0.vio.posn.15.port=2
unit.0.0.vio.posn.15.type=signal
unit.0.0.vio.posn.2.channel=2
unit.0.0.vio.posn.2.name=5 MHz
unit.0.0.vio.posn.2.port=0
unit.0.0.vio.posn.2.type=signal
unit.0.0.vio.posn.3.channel=3
unit.0.0.vio.posn.3.name=10 MHz
unit.0.0.vio.posn.3.port=0
unit.0.0.vio.posn.3.type=signal
unit.0.0.vio.posn.4.channel=4
unit.0.0.vio.posn.4.name=20 MHz
unit.0.0.vio.posn.4.port=0
unit.0.0.vio.posn.4.type=signal
unit.0.0.vio.posn.5.channel=5
unit.0.0.vio.posn.5.name=50 MHz
unit.0.0.vio.posn.5.port=0
unit.0.0.vio.posn.5.type=signal
unit.0.0.vio.posn.6.channel=6
unit.0.0.vio.posn.6.name=100 MHz
unit.0.0.vio.posn.6.port=0
unit.0.0.vio.posn.6.type=signal
unit.0.0.vio.posn.7.channel=7
unit.0.0.vio.posn.7.name=170 MHz
unit.0.0.vio.posn.7.port=0
unit.0.0.vio.posn.7.type=signal
unit.0.0.vio.posn.8.channel=0
unit.0.0.vio.posn.8.name=Set 1 MHz
unit.0.0.vio.posn.8.port=2
unit.0.0.vio.posn.8.type=signal
unit.0.0.vio.posn.9.channel=1
unit.0.0.vio.posn.9.name=Set 2 MHz
unit.0.0.vio.posn.9.port=2
unit.0.0.vio.posn.9.type=signal
unit.0.0.vio.readperiod=0
unit.0.0.waveform.count=24
unit.0.0.waveform.posn.0.channel=0
unit.0.0.waveform.posn.0.name=DataPort[0]
unit.0.0.waveform.posn.0.type=signal
unit.0.0.waveform.posn.1.channel=1
unit.0.0.waveform.posn.1.name=DataPort[1]
unit.0.0.waveform.posn.1.type=signal
unit.0.0.waveform.posn.10.channel=10
unit.0.0.waveform.posn.10.name=DataPort[10]
unit.0.0.waveform.posn.10.type=signal
unit.0.0.waveform.posn.11.channel=11
unit.0.0.waveform.posn.11.name=DataPort[11]
unit.0.0.waveform.posn.11.type=signal
unit.0.0.waveform.posn.12.channel=12
unit.0.0.waveform.posn.12.name=DataPort[12]
unit.0.0.waveform.posn.12.type=signal
unit.0.0.waveform.posn.13.channel=13
unit.0.0.waveform.posn.13.name=DataPort[13]
unit.0.0.waveform.posn.13.type=signal
unit.0.0.waveform.posn.14.channel=14
unit.0.0.waveform.posn.14.name=DataPort[14]
unit.0.0.waveform.posn.14.type=signal
unit.0.0.waveform.posn.15.channel=15
unit.0.0.waveform.posn.15.name=DataPort[15]
unit.0.0.waveform.posn.15.type=signal
unit.0.0.waveform.posn.16.channel=16
unit.0.0.waveform.posn.16.name=DataPort[16]
unit.0.0.waveform.posn.16.type=signal
unit.0.0.waveform.posn.17.channel=17
unit.0.0.waveform.posn.17.name=DataPort[17]
unit.0.0.waveform.posn.17.type=signal
unit.0.0.waveform.posn.18.channel=18
unit.0.0.waveform.posn.18.name=DataPort[18]
unit.0.0.waveform.posn.18.type=signal
unit.0.0.waveform.posn.19.channel=19
unit.0.0.waveform.posn.19.name=DataPort[19]
unit.0.0.waveform.posn.19.type=signal
unit.0.0.waveform.posn.2.channel=2
unit.0.0.waveform.posn.2.name=DataPort[2]
unit.0.0.waveform.posn.2.type=signal
unit.0.0.waveform.posn.20.channel=20
unit.0.0.waveform.posn.20.name=DataPort[20]
unit.0.0.waveform.posn.20.type=signal
unit.0.0.waveform.posn.21.channel=21
unit.0.0.waveform.posn.21.name=DataPort[21]
unit.0.0.waveform.posn.21.type=signal
unit.0.0.waveform.posn.22.channel=22
unit.0.0.waveform.posn.22.name=DataPort[22]
unit.0.0.waveform.posn.22.type=signal
unit.0.0.waveform.posn.23.channel=23
unit.0.0.waveform.posn.23.name=DataPort[23]
unit.0.0.waveform.posn.23.type=signal
unit.0.0.waveform.posn.3.channel=3
unit.0.0.waveform.posn.3.name=DataPort[3]
unit.0.0.waveform.posn.3.type=signal
unit.0.0.waveform.posn.4.channel=4
unit.0.0.waveform.posn.4.name=DataPort[4]
unit.0.0.waveform.posn.4.type=signal
unit.0.0.waveform.posn.5.channel=5
unit.0.0.waveform.posn.5.name=DataPort[5]
unit.0.0.waveform.posn.5.type=signal
unit.0.0.waveform.posn.6.channel=6
unit.0.0.waveform.posn.6.name=DataPort[6]
unit.0.0.waveform.posn.6.type=signal
unit.0.0.waveform.posn.7.channel=7
unit.0.0.waveform.posn.7.name=DataPort[7]
unit.0.0.waveform.posn.7.type=signal
unit.0.0.waveform.posn.8.channel=8
unit.0.0.waveform.posn.8.name=DataPort[8]
unit.0.0.waveform.posn.8.type=signal
unit.0.0.waveform.posn.9.channel=9
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unit.0.2.port.0.s.22.visible=1
unit.0.2.port.0.s.23.alias=P[23]
unit.0.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.23.name=TriggerPort0[23]
unit.0.2.port.0.s.23.orderindex=-1
unit.0.2.port.0.s.23.visible=1
unit.0.2.port.0.s.3.alias=P[3]
unit.0.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.3.name=TriggerPort0[3]
unit.0.2.port.0.s.3.orderindex=-1
unit.0.2.port.0.s.3.visible=1
unit.0.2.port.0.s.4.alias=P[4]
unit.0.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.4.name=TriggerPort0[4]
unit.0.2.port.0.s.4.orderindex=-1
unit.0.2.port.0.s.4.visible=1
unit.0.2.port.0.s.5.alias=P[5]
unit.0.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.5.name=TriggerPort0[5]
unit.0.2.port.0.s.5.orderindex=-1
unit.0.2.port.0.s.5.visible=1
unit.0.2.port.0.s.6.alias=P[6]
unit.0.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.6.name=TriggerPort0[6]
unit.0.2.port.0.s.6.orderindex=-1
unit.0.2.port.0.s.6.visible=1
unit.0.2.port.0.s.7.alias=P[7]
unit.0.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.7.name=TriggerPort0[7]
unit.0.2.port.0.s.7.orderindex=-1
unit.0.2.port.0.s.7.visible=1
unit.0.2.port.0.s.8.alias=P[8]
unit.0.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.8.name=TriggerPort0[8]
unit.0.2.port.0.s.8.orderindex=-1
unit.0.2.port.0.s.8.visible=1
unit.0.2.port.0.s.9.alias=P[9]
unit.0.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.9.name=TriggerPort0[9]
unit.0.2.port.0.s.9.orderindex=-1
unit.0.2.port.0.s.9.visible=1
unit.0.2.portcount=1
unit.0.2.rep_trigger.clobber=1
unit.0.2.rep_trigger.dir=D\:\\MLAB\\Modules\\CPLD_FPGA\\XILINX_ChipScope\\MAKE\\BIN\\13.3
unit.0.2.rep_trigger.filename=waveform
unit.0.2.rep_trigger.format=ASCII
unit.0.2.rep_trigger.loggingEnabled=0
unit.0.2.rep_trigger.signals=All Signals/Buses
unit.0.2.samplesPerTrigger=1
unit.0.2.triggerCapture=1
unit.0.2.triggerNSamplesTS=0
unit.0.2.triggerPosition=0
unit.0.2.triggerWindowCount=1
unit.0.2.triggerWindowDepth=1024
unit.0.2.triggerWindowTS=0
unit.0.2.username=Analyser
unit.0.2.waveform.count=9
unit.0.2.waveform.posn.0.channel=0
unit.0.2.waveform.posn.0.name=P[0]
unit.0.2.waveform.posn.0.type=signal
unit.0.2.waveform.posn.1.channel=1
unit.0.2.waveform.posn.1.name=P[1]
unit.0.2.waveform.posn.1.type=signal
unit.0.2.waveform.posn.10.channel=10
unit.0.2.waveform.posn.10.name=P[10]
unit.0.2.waveform.posn.10.type=signal
unit.0.2.waveform.posn.11.channel=11
unit.0.2.waveform.posn.11.name=P[11]
unit.0.2.waveform.posn.11.type=signal
unit.0.2.waveform.posn.12.channel=12
unit.0.2.waveform.posn.12.name=P[12]
unit.0.2.waveform.posn.12.type=signal
unit.0.2.waveform.posn.13.channel=13
unit.0.2.waveform.posn.13.name=P[13]
unit.0.2.waveform.posn.13.type=signal
unit.0.2.waveform.posn.14.channel=14
unit.0.2.waveform.posn.14.name=P[14]
unit.0.2.waveform.posn.14.type=signal
unit.0.2.waveform.posn.15.channel=15
unit.0.2.waveform.posn.15.name=P[15]
unit.0.2.waveform.posn.15.type=signal
unit.0.2.waveform.posn.16.channel=16
unit.0.2.waveform.posn.16.name=P[16]
unit.0.2.waveform.posn.16.type=signal
unit.0.2.waveform.posn.17.channel=17
unit.0.2.waveform.posn.17.name=P[17]
unit.0.2.waveform.posn.17.type=signal
unit.0.2.waveform.posn.2.channel=2
unit.0.2.waveform.posn.2.name=P[2]
unit.0.2.waveform.posn.2.type=signal
unit.0.2.waveform.posn.3.channel=3
unit.0.2.waveform.posn.3.name=P[3]
unit.0.2.waveform.posn.3.type=signal
unit.0.2.waveform.posn.4.channel=4
unit.0.2.waveform.posn.4.name=P[4]
unit.0.2.waveform.posn.4.type=signal
unit.0.2.waveform.posn.5.channel=5
unit.0.2.waveform.posn.5.name=P[5]
unit.0.2.waveform.posn.5.type=signal
unit.0.2.waveform.posn.6.channel=6
unit.0.2.waveform.posn.6.name=P[6]
unit.0.2.waveform.posn.6.type=signal
unit.0.2.waveform.posn.7.channel=7
unit.0.2.waveform.posn.7.name=P[7]
unit.0.2.waveform.posn.7.type=signal
unit.0.2.waveform.posn.8.channel=8
unit.0.2.waveform.posn.8.name=P[8]
unit.0.2.waveform.posn.8.type=signal
unit.0.2.waveform.posn.9.channel=9
unit.0.2.waveform.posn.9.name=P[9]
unit.0.2.waveform.posn.9.type=signal

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/!____!.txt
0,0 → 1,20
CoreGenerator Project Files
---------------------------
Software: ISE 14.5 (WebPack)
Device: Spartan3AN XC3S50AN-4TQG144C
Input (source) Files
--------------------
S3AN01_ChipScopeILA.cgp - Core Generator Project File (used by GUI CoreGen)
ChipScope_ICON.xco - ChipScope Config Block Configuration File
ChipScope_ILA_18_1024.xco - ChipScope Integrated Logic Analyser Configuration File 18 bits 1024 smaples
ChipScope_ILA_9_2048.xco - ChipScope Integrated Logic Analyser Configuration File 9 bits 2048 smaples
ChipScope_VIO_FreqSel.xco - ChipScope Virtul IO Configuration File (used for Frequency Selection)
ChipScope_VIO_UserOut.xco - ChipScope Virtul IO Configuration File (used for User Output)
All other files may be deleted. Open .cgp file in CoreGenerator and let it regenerate
all cores.

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ICON.xco
0,0 → 1,56
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 12:54:35 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
CSET component_name=ChipScope_ICON
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=3
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:10Z
# END Extra information
GENERATE
# CRC: 1a9afcd1

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_18_1024.xco
0,0 → 1,141
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 12:43:44 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET check_bramcount=false
CSET component_name=ChipScope_ILA_18_1024
CSET constraint_type=external
CSET counter_width_1=4
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=18
CSET data_same_as_trigger=false
CSET disable_save_keep=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=true
CSET example_design=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic_with_edges
CSET match_type_11=basic_with_edges
CSET match_type_12=basic_with_edges
CSET match_type_13=basic_with_edges
CSET match_type_14=basic_with_edges
CSET match_type_15=basic_with_edges
CSET match_type_16=basic_with_edges
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic_with_edges
CSET match_type_5=basic_with_edges
CSET match_type_6=basic_with_edges
CSET match_type_7=basic_with_edges
CSET match_type_8=basic_with_edges
CSET match_type_9=basic_with_edges
CSET match_units_1=3
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=16
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=24
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=true
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:34Z
# END Extra information
GENERATE
# CRC: ab76e1ca

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_9_2048.xco
0,0 → 1,141
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 13:35:12 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET check_bramcount=false
CSET component_name=ChipScope_ILA_9_2048
CSET constraint_type=external
CSET counter_width_1=4
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=9
CSET data_same_as_trigger=false
CSET disable_save_keep=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=true
CSET example_design=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic_with_edges
CSET match_type_11=basic_with_edges
CSET match_type_12=basic_with_edges
CSET match_type_13=basic_with_edges
CSET match_type_14=basic_with_edges
CSET match_type_15=basic_with_edges
CSET match_type_16=basic_with_edges
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic_with_edges
CSET match_type_5=basic_with_edges
CSET match_type_6=basic_with_edges
CSET match_type_7=basic_with_edges
CSET match_type_8=basic_with_edges
CSET match_type_9=basic_with_edges
CSET match_units_1=3
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=16
CSET number_of_trigger_ports=1
CSET sample_data_depth=2048
CSET sample_on=Rising
CSET trigger_port_width_1=24
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=true
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:34Z
# END Extra information
GENERATE
# CRC: 100acb04

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_FreqSel.xco
0,0 → 1,59
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 12:56:15 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=8
CSET component_name=ChipScope_VIO_FreqSel
CSET constraint_type=external
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=false
CSET enable_synchronous_input_port=true
CSET enable_synchronous_output_port=true
CSET example_design=false
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:59Z
# END Extra information
GENERATE
# CRC: c6d481e1

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_UserOut.xco
0,0 → 1,59
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 12:55:33 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=8
CSET component_name=ChipScope_VIO_UserOut
CSET constraint_type=external
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=false
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=true
CSET example_design=false
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=3
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:59Z
# END Extra information
GENERATE
# CRC: 738ddf25

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/coregen.cgp
0,0 → 1,9
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET package = tqg144
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/DirInfo.txt
0,0 → 1,33
//
// Toto je popisný soubor pro popis obsahu adresáře
//
[InfoShortDescription.en]
Xilinx ChipScope Demo
[InfoShortDescription.cs]
Xilinx ChipScope Demo
[InfoLongDescription.en]
ChipScope IP Core from Xilinx company enable us to add pretty
powerful logic analyser into our own FPGA design. It is necessary
to have a valid license for generation of bitfile but not for
usage and debugging. The text here shows a realisation of
an universal logic analyser in Spartan device on MLAB
board S3AN01. It shows the use of Xilinx Virtual Cable technology
as well.
The maximum achieved sampling rate is 170 MS/s with 9 or 18 input channels.
[InfoLongDescription.cs]
IP jádro ChipScope firmy Xilinx umožňuje vložit do vlastního návrhu
FPGA obvodu docela výkonný logický analyzátor. K překladu takového
obvodu potřebujeme příslušnou licenci, ale pro použití (ladění)
už ne. Uvedený článek ukazuje realizaci univerzálního logického
analyzátoru v obvodu Spartan na desce S3AN01 ze stavebnice MLAB
a to současně s použitím technologie Xilinx Virtual Cable
s přenosem JTAG příkazů po síti.
Maximální dosažená rychlost vzorkování je 170 MS/s na 9 nebo 18 kanálech.
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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/FindXilinxTools.cmd
0,0 → 1,40
@echo off
rem Finds installation of Xilinx tools and makes necessary env settings
rem ----- Set 32/64 bit
if Defined PROCESSOR_ARCHITEW6432 (
Set ProcArch=%PROCESSOR_ARCHITEW6432%
) else (
Set ProcArch=%PROCESSOR_ARCHITECTURE%
)
if "%ProcArch%" == "AMD64" Set ProcArch=x64
rem echo %ProcArch%
if "%ProcArch%" == "x64" (
set fileXilinxSet=settings64.bat
) else (
set fileXilinxSet=settings32.bat
)
rem ----- Find Xilinx directory
echo Find Xilinx Tools
for %%i in (C:\SW32\Xilinx C:\Xilinx) do (
rem Take the last directory
for /F %%j in ('dir %%i\*.* /AD /B /O-N') do (
for %%k in (%%i\%%j\ISE_DS) do (
rem echo %%j\%fileXilinxSet%
if exist %%k\%fileXilinxSet% (
echo Found at %%k\%fileXilinxSet%
call %%k\%fileXilinxSet%
set XILINX_VERSION=%%j
if not "%1"=="" (
rem Call script
call %1
) else (
rem Just set env
goto Label1
)
)
)
)
)
:Label1

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_CoreGen.cmd
0,0 → 1,81
@echo off
rem Batch to (re)generate IP cores (ChipScope components)
rem Run once, takes several minutes to finish.
rem
rem Do not modify source files directory structure
rem
rem Tested with Xilinx ISE WebPack 13.3 and 14.5
rem This step does not require ChipScope License
rem
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
rem ----- Run Coregen in paralel (we all have multicore cpu don't we?)
rem Unfortunately CoreGen can't be run in parallel.
rem There is some conflict (You cenrtainly know what all that cores are good for...)
rem start "CoreGen ICON" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r
rem start "CoreGen ILA 18x1024" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r
rem start "CoreGen ILA 9x2048" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r
rem start "CoreGen VIO FreqSel" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r
rem start "CoreGen VIO UserOut" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r
rem ----- Run CoreGen one after one for all components
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_ICON
echo ===============================
pause
exit 1
)
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_ILA_18_1024
echo ======================================
pause
exit 1
)
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_ILA_9_2048
echo =====================================
pause
exit 1
)
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_VIO_FreqSel
echo ======================================
pause
exit 1
)
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_VIO_UserOut
echo ======================================
pause
exit 1
)
rem ----- Finished
rm coregen.log
echo.
echo CoreGen Finished with no Errors

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_S3AN01_ChipScope.cmd
0,0 → 1,179
@echo off
rem Batch generates bitfile for Logic Analyser Demo
rem
rem Parameters:
rem
rem 18x1024|9x2048 ... select analyser size (width and depth)
rem
rem Do not modify srouce files directory structure
rem
rem Tested with Xilinx ISE WebPack 14.5 with ChipScope License
rem
rem ----- first parameter
set product=%1%
if "%product%"=="18x1024" (
echo 18x1024
) else if "%product%" == "9x2048" (
echo 9x2048
) else (
echo Missing parameter %product%
echo usage: %0% 18x1024^|9x2048
pause
exit 1
)
echo.
echo Product: %product%
echo.
rem ----- Set core (top VHDL entity) name
set core=S3AN01_ChipScope
rem ----- Set FPGA part
set fpgaPart=xc3s50an-tqg144-4
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
rem ----- Set WORK dir
if exist WORK_%core%_%product% rmdir /S /Q WORK_%core%_%product%
mkdir WORK_%core%_%product%
cd WORK_%core%_%product%
rem ----- Set TEMP dir (relative to WORK dir)
mkdir TMP
set TMP=TMP
rem ----- INPUT UCF and VHDL files (linux format c:/.../... )
set srcPath=../..
set ucfFile=VHDL/S3AN01_ChipScope.ucf
echo vhdl work "%srcPath%/COREGEN/ChipScope_ICON.vhd" > srcFiles.prj
echo vhdl work "%srcPath%/COREGEN/ChipScope_VIO_FreqSel.vhd" >>srcFiles.prj
echo vhdl work "%srcPath%/COREGEN/ChipScope_ILA_9_2048.vhd" >>srcFiles.prj
echo vhdl work "%srcPath%/VHDL/S3AN01_ChipScope.vhd" >>srcFiles.prj
rem ----- SET XST setting
echo set -xsthdpdir "xst" > setXst.xst
echo run >>setXst.xst
echo -ifn "srcFiles.prj" >>setXst.xst
echo -ofn %core% >>setXst.xst
echo -ofmt NGC >>setXst.xst
echo -top %core% >>setXst.xst
echo -iob True >>setXst.xst
echo -p %fpgaPart% >>setXst.xst
if "%product%"=="18x1024" (
echo -generics { ILA_WIDE=TRUE } >>setXst.xst
) else (
echo -generics { ILA_WIDE=FALSE } >>setXst.xst
)
rem ----- SET BITGEN setting
echo -w > setBitGen.ut
echo -g ConfigRate:25 >>setBitGen.ut
echo -g UnusedPin:PullUp >>setBitGen.ut
echo -g DriveDone:Yes >>setBitGen.ut
call xst -ifn "setXst.xst" -ofn "%core%.log"
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in xst
echo ============
pause
exit 1
)
call ngdbuild -intstyle ise -dd _ngo -sd ../../COREGEN -nt timestamp -uc "%srcPath%/%ucfFile%" -p %fpgaPart% %core%.ngc %core%.ngd
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in ngdbuild
echo =================
pause
exit 1
)
call map -intstyle ise -p %fpgaPart% -cm area -ir off -pr off -c 100 -o %core%.ncd %core%.ngd %core%.pcf
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in map
echo ============
pause
exit 1
)
call par -w -intstyle ise -ol high -t 1 %core%.ncd %core%.ncd %core%.pcf
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in par
echo ============
pause
exit 1
)
call trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml %core%.twx %core%.ncd -o %core%.twr %core%.pcf
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in trace
echo ==============
pause
exit 1
)
call bitgen -f "setBitGen.ut" %core%.ncd
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in bidgen
echo ===============
pause
exit 1
)
rem ----- Verify Timing
findstr /B /C:"All constraints were met." %core%.par
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in Timing
echo ===============
pause
exit 1
)
if exist ..\BIN\%XILINX_VERSION% (
rem ----- Copy result to BIN\{ISE_VER} directory
copy /Y %core%.bit ..\BIN\%XILINX_VERSION%\%core%_%product%.bit
rem copy /Y %core%.par ..\BIN\%XILINX_VERSION%\%core%_%product%.par
rem ----- Remove WORK dir
rem (bitgen starts wbtc.exe as a secondary process)
cd ..
rem Wait for xwebtalk has finished its work (sending stat data to Xilinx)
echo | set /p=Waiting for WebTalk...
:StartLoop
tasklist | findstr /i /c:"wbtc.exe" > nul
if %errorlevel% NEQ 0 (
goto ExitLoop
)
sleep 1
echo | set /p=*
goto StartLoop
)
:ExitLoop
rem Tohle nefunguje, protože výstup wmic je UTF-16 a to finstr neumí
rem wmic process | findstr /c:"%core%_%product%"
rem wmic process > ..\"%core%_%product%".wmic
rmdir /S /Q WORK_%core%_%product%
exit 0
)
exit 1

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_all.cmd
0,0 → 1,53
@echo off
rem Batch to generate bitstream
rem
rem S3AN01_ChipScope_18x1024.bit
rem S3AN01_ChipScope_9x2048.bit
rem
rem Do not modify srouce files directory structure
rem
rem Tested with Xilinx ISE WebPack 14.5 with ChipScope License
rem
rem ----- Check if ChipScope IP Cores are ready
if not exist ..\COREGEN\ChipScope_ICON.vhd goto coregen
if not exist ..\COREGEN\ChipScope_ILA_18_1024.vhd goto coregen
if not exist ..\COREGEN\ChipScope_ILA_9_2048.vhd goto coregen
if not exist ..\COREGEN\ChipScope_VIO_FreqSel.vhd goto coregen
if not exist ..\COREGEN\ChipScope_VIO_UserOut.vhd goto coregen
goto next
:coregen
rem ----- Regenerate ChipScope IP Cores
echo.
echo Missing ChipScope IP Core output files
echo Regenerating will take a long time (5 minutes on i5-3770)
echo.
pause
call make_CoreGen.cmd
:next
rem ----- Clear target directory
rmdir /S /Q BIN 2> nul
mkdir BIN
rem ----- Get Current date and time
for /F "Tokens=2-4 Delims=. " %%A in ("%DATE%") do (
set CurDate=%%C_%%B_%%A
)
for /F "Tokens=1-2 Delims=:,. " %%D in ("%TIME: =0%") do (
set CurTime=%%D_%%E
)
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
mkdir BIN\%XILINX_VERSION%
rem ----- Create Version metafile
echo TimeStamp: %CurDate%__%CurTime%> BIN\%XILINX_VERSION%\Version
echo ComputerName: %COMPUTERNAME%>> BIN\%XILINX_VERSION%\Version
echo ISE Version: %XILINX_VERSION%>> BIN\%XILINX_VERSION%\Version
echo ReleaseInfo: None>> BIN\%XILINX_VERSION%\Version
rem ----- Compile variants (paralel run)
start "compile S3AN01_ChipScope_18x1024" make_S3AN01_ChipScope.cmd 18x1024
start "compile S3AN01_ChipScope_9x2048" make_S3AN01_ChipScope.cmd 9x2048

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_18_1024.cmd
0,0 → 1,24
@echo off
rem
rem Script for starting Analyser.exe with predefined settings.
rem The script starts mlab_xvcd.exe deamon for users who use
rem Xilinx Virtual Cable and FTDI JTAG cable. Those users
rem should select in ChipScope Analyser setting
rem JTAG Chain / Open Plug-in.
rem
rem ----- Run Xilinx Virtual Cable Daemon (as separate process)
rem Run it if you use XVC cable connected to the local computer
rem To start the daemon if already runnig does no harm
if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe (
start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe
)
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
rem ----- Run ChipScope Analyser
analyzer.exe -project ..\ANALYSER\Analyser_18_1024.cpj -init ..\ANALYSER\Analyser.ini

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_9_2048.cmd
0,0 → 1,24
@echo off
rem
rem Script for starting Analyser.exe with predefined settings.
rem The script starts mlab_xvcd.exe deamon for users who use
rem Xilinx Virtual Cable and FTDI JTAG cable. Those users
rem should select in ChipScope Analyser setting
rem JTAG Chain / Open Plug-in.
rem
rem ----- Run Xilinx Virtual Cable Daemon (as separate process)
rem Run it if you use XVC cable connected to the local computer
rem To start the daemon if already runnig does no harm
if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe (
start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe
)
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
rem ----- Run ChipScope Analyser
analyzer.exe -project ..\ANALYSER\Analyser_9_2048.cpj -init ..\ANALYSER\Analyser.ini

/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/img/XVC_FT220X01A_QRcode.png
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/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/FT_Prog.png
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/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/FT_Prog_Description.png
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/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/IMPACT_Plugin.png
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/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/IMPACT_Prog.png
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