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/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN |
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/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls |
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svn:mime-type = application/octet-stream |
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/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC |
---|
0,0 → 1,785 |
*PADS-PCB* |
*PART* |
C1 C-ELYT,22uF/6.3V@ELYTB |
C10 C,100nF@C0805 |
C11 C,100nF@C0805 |
C12 C,100nF@C0805 |
C13 C,100nF@C0805 |
C14 C,100nF@C0805 |
C15 C,100nF@C0805 |
C16 C,100nF@C0805 |
C17 C,100nF@C0805 |
C18 C,100nF@C0805 |
C19 C,100nF@C0805 |
C2 C-ELYT,22uF/6.3V@ELYTB |
C20 C,4n7@C0805 |
C21 C,4n7@C0805 |
C22 C,4n7@C0805 |
C23 C,100nF@C0805 |
C24 C,100nF@C0805 |
C25 C,100nF@C0805 |
C26 C,100nF@C0805 |
C27 C,100nF@C0805 |
C28 C,100nF@C0805 |
C29 C,100nF@C0805 |
C3 C-ELYT,22uF/6.3V@ELYTB |
C30 C,100nF@C0805 |
C31 C,100nF@C0805 |
C32 C,100nF@C0805 |
C33 C,100nF@C0805 |
C34 C,10nF@C0805 |
C4 C,100nF@C0805 |
C5 C,100nF@C0805 |
C6 C,100nF@C0805 |
C7 C,100nF@C0805 |
C8 C,100nF@C0805 |
C9 C,100nF@C0805 |
D0 LED,LED3mm_RED@LED3 |
D1 LED,LED3mm_RED@LED3 |
D10 LED,LED3mm_RED@LED3 |
D2 LED,LED3mm_RED@LED3 |
D3 LED,LED3mm_RED@LED3 |
D4 LED,LED3mm_RED@LED3 |
D5 LED,LED3mm_RED@LED3 |
D6 LED,LED3mm_RED@LED3 |
D7 LED,LED3mm_RED@LED3 |
D8 LED,LED3mm_RED@LED3 |
D9 D,1N5820@DO201 |
J1 JUMP2X3,JUMP2X3@JUMP2X3 |
J10 JUMP22,JUMP22@JUMP22 |
J100 JUMP10,JUMP10@JUMP10 |
J11 JUMP2X10,JUMP2X10@JUMP2X10 |
J12 JUMP10,JUMP10@JUMP10 |
J13 JUMP2,JUMP2@JUMP2 |
J14 JUMP2,JUMP2@JUMP2 |
J15 JUMP2,JUMP2@JUMP2 |
J16 JUMP2,JUMP2@JUMP2 |
J17 JUMP2,JUMP2@JUMP2 |
J18 JUMP2,JUMP2@JUMP2 |
J19 JUMP2,JUMP2@JUMP2 |
J2 JUMP2X3,JUMP2X3@JUMP2X3 |
J20 JUMP2,JUMP2@JUMP2 |
J21 JUMP10,JUMP10@JUMP10 |
J22 JUMP1,#JUMP1@JUMP1 |
J23 JUMP2X22,JUMP2X22@JUMP2X22 |
J24 JUMP2X2,JUMP2X2@JUMP2X2 |
J25 JUMP2X8,JUMP2X8@JUMP2X8 |
J26 JUMP2X8,JUMP2X8@JUMP2X8 |
J27 DB15F_3L,DB15F_3L_90@DB15F_3L_90 |
J28 SATA_DATA,#SATA_DATA@SATA_DATA |
J29 SATA_DATA,#SATA_DATA@SATA_DATA |
J3 JUMP9_X3_X5_X8,JUMP9_X3_X5_X8@JUMP9_X3_X5_X8 |
J30 JUMP4,JUMP4@JUMP4 |
J31 MINIDIN6,MINIDIN6_PS2@MINIDIN6 |
J32 MINIDIN6,MINIDIN6_PS2@MINIDIN6 |
J33 JUMP1,JUMP1@JUMP1 |
J34 JUMP1,JUMP1@JUMP1 |
J35 JUMP1,JUMP1@JUMP1 |
J36 JUMP1,JUMP1@JUMP1 |
J37 JUMP1,JUMP1@JUMP1 |
J38 JUMP1,JUMP1@JUMP1 |
J4 JUMP2X3,JUMP2X3@JUMP2X3 |
J5 JUMP2X3,JUMP2X3@JUMP2X3 |
J6 JUMP2,JUMP2@JUMP2 |
J7 JUMP2X4,JUMP2X4@JUMP2X4 |
J8 JUMP2X3,JUMP2X3@JUMP2X3 |
J9 JUMP2X22,JUMP2X22@JUMP2X22 |
LD0 4LED7_12PIN_14_2,FT-M514RD@4LED7_12PIN_14_2 |
LD1 4LED7_12PIN_14_2,FT-M514RD@4LED7_12PIN_14_2 |
M1 PAD,HOLE_M3@HOLE_M3 |
M10 FIDU_PASTE,FIDU_PASTE@FIDU_PASTE |
M2 PAD,HOLE_M3@HOLE_M3 |
M3 PAD,HOLE_M3@HOLE_M3 |
M4 PAD,HOLE_M3@HOLE_M3 |
M5 FIDU,FIDU@FIDU |
M6 FIDU,FIDU@FIDU |
M7 FIDU,FIDU@FIDU |
M8 FIDU,FIDU@FIDU |
M9 FIDU_PASTE,FIDU_PASTE@FIDU_PASTE |
Q0 T-BEC,BC856@SOT23 |
Q1 T-BEC,BC856@SOT23 |
Q10 T-FET-GSD,BS170SMD@SOT23 |
Q11 T-FET-GSD,BS170SMD@SOT23 |
Q12 T-FET-GSD,BS170SMD@SOT23 |
Q13 T-FET-GSD,BS170SMD@SOT23 |
Q2 T-BEC,BC856@SOT23 |
Q3 T-BEC,BC856@SOT23 |
Q4 T-BEC,BC856@SOT23 |
Q5 T-BEC,BC856@SOT23 |
Q6 T-BEC,BC856@SOT23 |
Q7 T-BEC,BC856@SOT23 |
Q8 T-FET-GSD,BS170SMD@SOT23 |
Q9 T-FET-GSD,BS170SMD@SOT23 |
R1 R,100@R0805 |
R10 R,100@R0805 |
R100 R,100k@R0603 |
R101 R,100k@R0603 |
R102 R,100k@R0603 |
R103 R,100k@R0603 |
R104 R,100k@R0603 |
R105 R,100k@R0603 |
R106 R,100k@R0603 |
R107 R,100k@R0603 |
R108 R,100k@R0603 |
R109 R,100k@R0603 |
R11 R,820@R0805 |
R110 R,100k@R0603 |
R111 R,100k@R0603 |
R112 R,100k@R0603 |
R113 R,100k@R0603 |
R114 R,100k@R0603 |
R115 R,100k@R0603 |
R116 R,100k@R0603 |
R117 R,100k@R0603 |
R118 R,100k@R0603 |
R119 R,100k@R0603 |
R12 R,390@R0805 |
R120 R,100k@R0603 |
R121 R,100k@R0603 |
R122 R,100k@R0603 |
R123 R,100k@R0603 |
R124 R,100k@R0603 |
R125 R,100k@R0603 |
R126 R,100k@R0603 |
R127 R,100k@R0603 |
R128 R,100k@R0603 |
R129 R,100k@R0603 |
R13 R,4k7@R0805 |
R130 R,100k@R0603 |
R131 R,100k@R0603 |
R14 R,390@R0805 |
R15 R,4k7@R0805 |
R16 R,3k3@R0805 |
R17 R,3k3@R0805 |
R18 R,3k3@R0805 |
R19 R,3k3@R0805 |
R2 R,100@R0805 |
R20 R,4k7@R0805 |
R21 R,4k7@R0805 |
R22 R,4k7@R0805 |
R23 R,4k7@R0805 |
R24 R,4k7@R0805 |
R25 R,4k7@R0805 |
R26 R,4k7@R0805 |
R27 R,4k7@R0805 |
R28 R,0R@R0805 |
R29 R,390@R0805 |
R3 R,100@R0805 |
R30 R,390@R0805 |
R31 R,390@R0805 |
R32 R,390@R0805 |
R33 R,390@R0805 |
R34 R,390@R0805 |
R35 R,390@R0805 |
R36 R,390@R0805 |
R37 R,390@R0805 |
R38 R,390@R0805 |
R39 R,390@R0805 |
R4 R,100@R0805 |
R40 R,390@R0805 |
R41 R,820@R0805 |
R42 R,820@R0805 |
R43 R,820@R0805 |
R44 R,820@R0805 |
R45 R,820@R0805 |
R46 R,820@R0805 |
R47 R,820@R0805 |
R48 R,820@R0805 |
R49 R,390@R0805 |
R5 R,100@R0805 |
R50 R,390@R0805 |
R51 R,390@R0805 |
R52 R,390@R0805 |
R53 R,390@R0805 |
R54 R,390@R0805 |
R55 R,390@R0805 |
R56 R,390@R0805 |
R57 R,510@R0805 |
R58 R,270@R0805 |
R59 R,120@R0805 |
R6 R,100@R0805 |
R60 R,510@R0805 |
R61 R,270@R0805 |
R62 R,120@R0805 |
R63 R,510@R0805 |
R64 R,270@R0805 |
R65 R,120@R0805 |
R66 R,100@R0805 |
R67 R,100@R0805 |
R68 R,4k7@R0805 |
R69 R,#4k7@R0805 |
R7 R,100@R0805 |
R70 R,4k7@R0805 |
R71 R,#4k7@R0805 |
R72 R,4k7@R0805 |
R73 R,4k7@R0805 |
R74 R,4k7@R0805 |
R75 R,4k7@R0805 |
R76 R,4k7@R0805 |
R77 R,4k7@R0805 |
R78 R,4k7@R0805 |
R79 R,4k7@R0805 |
R8 R,100@R0805 |
R80 R,1k2@R0805 |
R81 R,100@R0805 |
R82 R,100@R0805 |
R83 R,100@R0805 |
R84 R,100@R0805 |
R85 R,100@R0805 |
R86 R,100@R0805 |
R87 R,100@R0805 |
R88 R,100@R0805 |
R89 R,4k7@R0805 |
R9 R,100@R0805 |
SW0 PB4PIN,PUSH050x050@PUSH050x050 |
SW1 PB4PIN,PUSH050x050@PUSH050x050 |
SW2 PB4PIN,PUSH050x050@PUSH050x050 |
SW3 PB4PIN,PUSH050x050@PUSH050x050 |
SW4 DIPSW8,DIPSW8@DIPSW8 |
TPS1 TP,TPS@TPS |
TPS2 TP,TPS@TPS |
TPS3 TP,TPS@TPS |
TPS4 TP,TPS@TPS |
TPS5 TP,TPS@TPS |
TPS6 TP,TPS@TPS |
U1 TQFP144,XC3S50AN-4TQG144C@TQFP144 |
U10 SOT23-5,MCP6546T-E/OT@SOT23-5 |
U11 SSOIII_48_300,SN74LVC16244ADL@SSOIII_48_300 |
U12 SSOIII_48_300,SN74LVC16244ADL@SSOIII_48_300 |
U2 TO263,AP1086K33G-13@TO263 |
U3 TO252,TS1117BCP12R0@TO252 |
U4 XOSC,CFPS-73-100M@SG8002 |
U5 SO8_150,AT45DB011D-SSH-B@SO8_150 |
U6 SO8_210,AT45DB011D-SH-B@SO8_210 |
U7 SO8_150,AT25DF0xxA-SSH@SO8_150 |
U8 SO8_210,SST24LF040A-33-4C-S2AE@SO8_210 |
U9 SOT23-5,MCP6001T-I/OT@SOT23-5 |
*NET* |
*SIGNAL* IP12 |
U11.43 J9.25 J9.26 R112.2 |
*SIGNAL* DIF1N |
U1.111 J7.3 |
*SIGNAL* N24251 |
SW2.1 R31.2 |
*SIGNAL* IP13 |
J9.27 J9.28 U11.44 R113.2 |
*SIGNAL* DIF2P |
U1.112 J7.5 |
*SIGNAL* N24231 |
SW0.1 R29.2 |
*SIGNAL* IP14 |
J9.29 J9.30 U11.46 R114.2 |
*SIGNAL* DIF1P |
U1.110 J7.1 |
*SIGNAL* N24253 |
SW3.1 R32.2 |
*SIGNAL* IP15 |
U11.47 J9.31 J9.32 R115.2 |
*SIGNAL* DIF2N |
U1.113 J7.7 |
*SIGNAL* N24249 |
SW1.1 R30.2 |
*SIGNAL* IP16 |
U12.26 J9.33 J9.34 R116.2 |
*SIGNAL* N07427 |
SW4.5 R36.2 |
*SIGNAL* IP17 |
J9.35 J9.36 U12.27 R117.2 |
*SIGNAL* N07433 |
SW4.4 R37.2 |
*SIGNAL* IP18 |
J9.37 J9.38 U12.29 R118.2 |
*SIGNAL* N07415 |
SW4.7 R34.2 |
*SIGNAL* IP19 |
U12.30 J9.39 J9.40 R119.2 |
*SIGNAL* N07409 |
SW4.8 R33.2 |
*SIGNAL* IP20 |
J9.41 J9.42 U12.32 R120.2 |
*SIGNAL* N07451 |
R40.2 SW4.1 |
*SIGNAL* IP21 |
U12.33 J9.43 J9.44 R121.2 |
*SIGNAL* N07445 |
SW4.2 R39.2 |
*SIGNAL* IX22 |
J11.1 J11.2 U12.35 R122.2 |
*SIGNAL* N07421 |
R35.2 SW4.6 |
*SIGNAL* IX23 |
U12.36 J11.3 J11.4 R123.2 |
*SIGNAL* N07439 |
R38.2 SW4.3 |
*SIGNAL* IX24 |
U12.37 J11.5 J11.6 R124.2 |
*SIGNAL* IX25 |
J11.7 J11.8 U12.38 R125.2 |
*SIGNAL* IX26 |
U12.40 J11.9 J11.10 R126.2 |
*SIGNAL* IX27 |
J11.11 J11.12 U12.41 R127.2 |
*SIGNAL* IX28 |
J11.13 J11.14 U12.43 R128.2 |
*SIGNAL* IX29 |
U12.44 J11.15 J11.16 R129.2 |
*SIGNAL* IX30 |
J11.17 J11.18 U12.46 R130.2 |
*SIGNAL* N51046 |
R14.1 D10.A |
*SIGNAL* VGA_HS |
U1.11 R66.2 |
*SIGNAL* IX31 |
J11.19 J11.20 U12.47 R131.2 |
*SIGNAL* VGA_G0 |
U1.5 R60.2 |
*SIGNAL* PB1 |
U1.120 R30.1 |
*SIGNAL* X31 |
U12.2 J21.10 |
*SIGNAL* VGA_G1 |
U1.6 R61.2 |
*SIGNAL* PB2 |
U1.117 R31.1 |
*SIGNAL* X30 |
J21.9 U12.3 |
*SIGNAL* VGA_B0 |
U1.7 R63.2 |
*SIGNAL* PB0 |
U1.121 R29.1 |
*SIGNAL* X29 |
J21.8 U12.5 |
*SIGNAL* VGA_R0 |
U1.3 R57.2 |
*SIGNAL* PB3 |
U1.116 R32.1 |
*SIGNAL* X28 |
J21.7 U12.6 |
*SIGNAL* VGA_R1 |
U1.4 R58.2 |
*SIGNAL* X27 |
J21.6 U12.8 |
*SIGNAL* VGA_B1 |
U1.8 R64.2 |
*SIGNAL* X26 |
J21.5 U12.9 |
*SIGNAL* VGA_VS |
U1.10 R67.2 |
*SIGNAL* X25 |
J21.4 U12.11 |
*SIGNAL* VGA_RED |
J27.1 R57.1 R58.1 R59.2 |
*SIGNAL* X24 |
J21.3 U12.12 |
*SIGNAL* VGA_GREEN |
J27.2 R60.1 R62.2 R61.1 |
*SIGNAL* X23 |
J21.2 U12.13 |
*SIGNAL* VGA_BLUE |
J27.3 R63.1 R64.1 R65.2 |
*SIGNAL* X22 |
J21.1 U12.14 |
*SIGNAL* P0 |
U1.75 U11.23 J23.1 J23.2 |
*SIGNAL* P2 |
U1.77 J23.5 J23.6 U11.20 |
*SIGNAL* P1 |
J23.3 J23.4 U11.22 U1.76 |
*SIGNAL* P3 |
U11.19 J23.7 J23.8 U1.78 |
*SIGNAL* P4 |
U1.82 J23.9 J23.10 U11.17 |
*SIGNAL* P5 |
U1.83 J23.11 J23.12 U11.16 |
*SIGNAL* P6 |
U11.14 U1.84 J23.13 J23.14 |
*SIGNAL* P7 |
U11.13 U1.85 J23.15 J23.16 |
*SIGNAL* P8 |
U1.87 U11.12 J23.17 J23.18 |
*SIGNAL* P9 |
U1.88 J23.19 J23.20 U11.11 |
*SIGNAL* P10 |
U1.90 U11.9 J23.21 J23.22 |
*SIGNAL* N10957 |
J27.13 R66.1 |
*SIGNAL* P11 |
U11.8 J23.23 J23.24 U1.91 |
*SIGNAL* N10968 |
J27.14 R67.1 |
*SIGNAL* P12 |
U1.92 U11.6 J23.25 J23.26 |
*SIGNAL* P13 |
J23.27 J23.28 U11.5 U1.93 |
*SIGNAL* P14 |
U11.3 J23.29 J23.30 U1.96 |
*SIGNAL* P15 |
U1.98 U11.2 J23.31 J23.32 |
*SIGNAL* N05189 |
R56.1 D7.A |
*SIGNAL* P16 |
J23.33 J23.34 U12.23 U1.99 |
*SIGNAL* N06136 |
R55.1 D6.A |
*SIGNAL* P17 |
U1.101 J23.35 J23.36 U12.22 |
*SIGNAL* N06223 |
R54.1 D5.A |
*SIGNAL* P18 |
U1.102 U12.20 J23.37 J23.38 |
*SIGNAL* N02505 |
J3.9 R4.1 |
*SIGNAL* N06313 |
R53.1 D4.A |
*SIGNAL* P19 |
J23.39 J23.40 U1.103 U12.19 |
*SIGNAL* N02508 |
J3.7 R3.1 |
*SIGNAL* N06394 |
R52.1 D3.A |
*SIGNAL* P20 |
U12.17 J23.41 J23.42 U1.104 |
*SIGNAL* N02511 |
J3.6 R2.1 |
*SIGNAL* N06476 |
R51.1 D2.A |
*SIGNAL* P21 |
U12.16 U1.105 J23.43 J23.44 |
*SIGNAL* N02521 |
J3.4 R1.1 |
*SIGNAL* DONE |
J36.1 R12.2 U1.73 |
*SIGNAL* N06557 |
R50.1 D1.A |
*SIGNAL* P22 |
U1.79 J24.1 J24.2 |
*SIGNAL* TMS |
U1.1 R4.2 |
*SIGNAL* N06657 |
R49.1 D0.A |
*SIGNAL* P23 |
U1.80 U1.97 J24.3 J24.4 |
*SIGNAL* TCK |
U1.109 R1.2 |
*SIGNAL* LED7 |
U1.46 J26.15 J26.16 R56.2 |
*SIGNAL* TDO |
U1.107 R2.2 |
*SIGNAL* LED5 |
U1.48 R54.2 J26.11 J26.12 |
*SIGNAL* TDI |
U1.2 R3.2 |
*SIGNAL* LED6 |
U1.47 J26.13 J26.14 R55.2 |
*SIGNAL* PROG |
J6.1 U1.144 |
*SIGNAL* LED4 |
U1.49 J26.9 J26.10 R53.2 |
*SIGNAL* LED3 |
U1.50 J26.7 J26.8 R52.2 |
*SIGNAL* LED2 |
U1.51 J26.5 J26.6 R51.2 |
*SIGNAL* LED0 |
U1.64 J26.1 J26.2 R49.2 |
*SIGNAL* LED1 |
U1.63 R50.2 J26.3 J26.4 |
*SIGNAL* N03324 |
R13.2 U1.74 |
*SIGNAL* N30971 |
Q1.C LD0.8 |
*SIGNAL* N58963 |
R73.1 J31.1 Q10.D |
*SIGNAL* N31019 |
Q2.C LD0.9 |
*SIGNAL* N58687 |
J31.5 R75.1 Q11.D |
*SIGNAL* N30951 |
Q0.C LD0.6 |
*SIGNAL* N59441 |
Q12.D R77.1 J32.1 |
*SIGNAL* N31013 |
R43.1 Q2.B |
*SIGNAL* N59451 |
R79.1 Q13.D J32.5 |
*SIGNAL* PS2_DATA1 |
U1.130 Q10.S R72.1 |
*SIGNAL* N30989 |
R42.1 Q1.B |
*SIGNAL* PS2_CLK1 |
U1.127 R74.1 Q11.S |
*SIGNAL* N31009 |
Q3.C LD0.12 |
*SIGNAL* PS2_CLK2 |
U1.42 R78.1 Q13.S |
*SIGNAL* PS2_DATA2 |
U1.58 R76.1 Q12.S |
*SIGNAL* N30985 |
R41.1 Q0.B |
*SIGNAL* I2C_SCL |
U1.115 R68.1 Q8.S |
*SIGNAL* N61543 |
Q8.D R69.1 J30.2 |
*SIGNAL* I2C_SDA |
U1.114 R70.1 Q9.S |
*SIGNAL* N61555 |
J30.3 Q9.D R71.1 |
*SIGNAL* N128209 |
J6.2 R11.2 |
*SIGNAL* ANA_IND |
U1.69 R19.2 U10.1 |
*SIGNAL* N03524 |
R12.1 D8.A |
*SIGNAL* N118416 |
R18.1 U10.3 C22.2 |
*SIGNAL* ANA_IN |
R18.2 J8.5 |
*SIGNAL* ANA_REF |
U10.4 C21.2 R17.1 J8.3 |
*SIGNAL* ANA_OUTD |
U1.67 J37.1 R80.2 |
*SIGNAL* SPI_WP# |
U6.5 U5.5 U8.3 U7.3 R15.1 U1.70 |
*SIGNAL* ANA_OUT |
J8.1 C34.1 U9.1 U9.4 |
*SIGNAL* N09709 |
J5.2 R8.1 |
*SIGNAL* ANA_REFD |
U1.68 R17.2 |
*SIGNAL* N09715 |
J5.4 R9.1 |
*SIGNAL* N09721 |
J5.6 R10.1 |
*SIGNAL* N0 |
U11.24 J13.1 R20.2 |
*SIGNAL* N1 |
J14.1 U11.25 R21.2 |
*SIGNAL* N2 |
J15.1 U11.48 R22.2 |
*SIGNAL* N3 |
U11.1 J16.1 R23.2 |
*SIGNAL* N4 |
U12.24 J17.1 R24.2 |
*SIGNAL* N5 |
U12.25 J18.1 R25.2 |
*SIGNAL* N6 |
J19.1 U12.48 R26.2 |
*SIGNAL* N7 |
U12.1 J20.1 R27.2 |
*SIGNAL* N119011 |
R16.1 U9.3 C20.2 |
*SIGNAL* LD_CA0# |
U1.25 R41.2 |
*SIGNAL* LD_CA4# |
U1.27 R45.2 |
*SIGNAL* LD_CA5# |
U1.29 R46.2 |
*SIGNAL* LD_CA6# |
U1.28 R47.2 |
*SIGNAL* LD_CA1# |
U1.31 R42.2 |
*SIGNAL* LD_CA2# |
U1.32 R43.2 |
*SIGNAL* LD_CA3# |
U1.13 R44.2 |
*SIGNAL* LD_CA7# |
U1.12 R48.2 |
*SIGNAL* LD_SEG0# |
R81.2 U1.15 |
*SIGNAL* DIPSW3 |
U1.139 J25.7 J25.8 R36.1 |
*SIGNAL* LD_SEG5# |
R86.2 U1.16 |
*SIGNAL* DIPSW2 |
U1.140 R35.1 J25.5 J25.6 |
*SIGNAL* LD_SEG4# |
U1.18 R85.2 |
*SIGNAL* DIPSW5 |
U1.135 R38.1 J25.11 J25.12 |
*SIGNAL* LD_SEG7# |
U1.20 R88.2 |
*SIGNAL* DIPSW4 |
U1.138 R37.1 J25.9 J25.10 |
*SIGNAL* LD_SEG3# |
U1.19 R84.2 |
*SIGNAL* DIPSW7 |
U1.132 R40.1 J25.15 J25.16 |
*SIGNAL* VDD_5V |
U2.2 C1.A D9.C J1.3 J1.4 J32.4 J30.1 R69.2 |
R79.2 R75.2 R71.2 J31.4 R73.2 R77.2 |
*SIGNAL* LD_SEG6# |
R87.2 U1.24 |
*SIGNAL* DIPSW1 |
U1.142 R34.1 J25.3 J25.4 |
*SIGNAL* VDD_1V2 |
U1.122 U1.22 U1.52 U1.94 C8.2 C5.2 C7.2 C6.2 |
C3.A U3.3 |
*SIGNAL* LD_SEG2# |
U1.21 R83.2 |
*SIGNAL* DIPSW6 |
U1.134 R39.1 J25.13 J25.14 |
*SIGNAL* VDD_3V3 |
U7.7 U8.7 U8.8 C10.2 U5.3 U6.3 C15.1 U7.8 |
U6.6 R14.2 U3.2 J2.3 J2.4 C9.2 J100.10 C2.A |
J3.1 U5.6 J33.1 C12.2 C11.2 C13.2 U1.40 C14.2 |
U1.36 U1.108 U1.66 U2.3 U1.133 U4.1 U4.4 C4.2 |
U2.4 R15.2 U1.61 R89.2 U9.5 C18.2 C19.2 U1.14 |
U1.23 U1.136 C17.2 U1.119 C16.2 C23.1 U10.5 R19.1 |
C24.2 U12.7 C31.2 C30.2 R23.1 U11.18 C27.2 C25.2 |
U11.42 C28.2 C29.2 C26.2 R25.1 R27.1 R21.1 R26.1 |
U11.31 R24.1 R22.1 U12.18 U12.42 U12.31 U11.7 R20.1 |
R28.2 Q4.E Q2.E Q3.E Q1.E Q7.E Q6.E Q5.E |
SW4.16 SW4.15 SW4.9 R72.2 Q11.G R74.2 R76.2 Q12.G |
SW4.14 SW4.13 SW4.12 SW4.11 SW4.10 R70.2 Q9.G Q10.G |
Q0.E Q13.G R78.2 SW1.2 SW0.2 SW2.2 SW3.2 Q8.G |
R68.2 |
*SIGNAL* LD_SEG1# |
R82.2 U1.30 |
*SIGNAL* DIPSW0 |
U1.143 R33.1 J25.1 J25.2 |
*SIGNAL* GND |
U1.9 U1.17 U1.26 U1.34 M1.1 U1.56 U1.65 U1.81 |
U1.89 U1.100 U1.106 J5.3 J5.5 U1.118 J5.1 M3.1 |
U1.137 C15.2 U1.128 J2.5 J2.6 J2.1 J2.2 R13.1 |
U3.1 C1.C J100.1 J4.1 J4.3 J4.5 D9.A U6.7 |
C13.1 C14.1 U5.7 J3.2 D8.C C6.1 C7.1 C8.1 |
C5.1 U4.2 U2.1 U7.4 U8.4 M4.1 M2.1 J38.1 |
J1.1 J1.2 J1.5 J1.6 C2.C D10.C C4.1 C3.C |
R11.1 C9.1 C12.1 C11.1 C10.1 C16.1 J8.2 J8.4 |
J8.6 C17.1 C22.1 U10.2 J7.2 J7.4 J7.6 J7.8 |
C20.1 C18.1 C19.1 C23.2 U9.2 C21.1 U12.10 J12.8 |
C25.1 J13.2 U12.4 J12.5 J10.21 J10.4 J10.3 J12.1 |
J12.4 J12.10 J10.5 J18.2 C32.1 R116.1 R117.1 R118.1 |
R119.1 R120.1 R121.1 R122.1 R123.1 R110.1 R115.1 R108.1 |
R113.1 R112.1 R109.1 R114.1 R111.1 R105.1 R100.1 R103.1 |
R102.1 R106.1 R104.1 R101.1 R107.1 R126.1 R131.1 R124.1 |
R129.1 R128.1 R125.1 R130.1 R127.1 U12.45 C33.1 C28.1 |
J12.9 J17.2 J10.9 J10.8 J10.16 J19.2 J14.2 U11.39 |
J15.2 U11.28 C24.1 C31.1 U11.34 U12.15 U11.4 J10.18 |
J10.2 J10.1 J12.3 J10.12 J10.22 C27.1 J20.2 J10.13 |
U12.28 U11.21 U11.45 J12.2 J10.20 C26.1 J10.6 U11.10 |
U12.39 J10.14 J10.11 J12.6 J10.10 J10.15 J10.7 J12.7 |
U12.34 J10.19 U11.15 U12.21 J10.17 J16.2 C30.1 C29.1 |
D4.C D3.C D1.C D5.C J30.4 J28.4 J28.8 J28.7 |
J28.1 J28.9 J31.3 J29.9 J29.1 J29.4 J29.7 J29.8 |
J27.10 J27.8 J27.6 J27.7 J27.5 D7.C R59.1 R65.1 |
R62.1 D6.C D0.C D2.C J27.16 J27.17 J32.3 |
*SIGNAL* N01338 |
R7.1 J4.6 |
*SIGNAL* N01352 |
J4.4 R6.1 |
*SIGNAL* N01358 |
J4.2 R5.1 |
*SIGNAL* M2 |
R7.2 U1.39 |
*SIGNAL* M1 |
R6.2 U1.37 |
*SIGNAL* M0 |
R5.2 U1.38 |
*SIGNAL* CLK100MHZ |
U1.60 U4.3 |
*SIGNAL* VS2 |
R10.2 U1.43 |
*SIGNAL* VS1 |
R9.2 U1.44 |
*SIGNAL* VS0 |
R8.2 U1.45 |
*SIGNAL* N197552 |
R48.1 Q7.B |
*SIGNAL* N197801 |
R44.1 Q3.B |
*SIGNAL* LD_SEG5#R |
R86.1 LD1.10 LD0.10 |
*SIGNAL* LD_SEG2#R |
R83.1 LD0.4 LD1.4 |
*SIGNAL* LD_SEG7#R |
R88.1 LD1.3 LD0.3 |
*SIGNAL* LD_SEG6#R |
R87.1 LD1.5 LD0.5 |
*SIGNAL* LD_SEG1#R |
R82.1 LD0.7 LD1.7 |
*SIGNAL* LD_SEG0#R |
R81.1 LD0.11 LD1.11 |
*SIGNAL* LD_SEG4#R |
R85.1 LD0.1 LD1.1 |
*SIGNAL* LD_SEG3#R |
R84.1 LD0.2 LD1.2 |
*SIGNAL* SPI_CS# |
R89.1 U5.4 U6.4 U7.1 U8.1 U1.41 |
*SIGNAL* SPI_CLK |
U7.6 U8.6 U1.72 J35.1 U6.2 U5.2 |
*SIGNAL* SPI_DI |
U6.1 U5.1 U7.5 U8.5 U1.62 |
*SIGNAL* SPI_DO |
U1.71 U7.2 U8.2 U6.8 U5.8 J34.1 |
*SIGNAL* VDD_BANK1 |
J22.1 U1.86 C33.2 R28.1 U1.95 C32.2 |
*SIGNAL* SD1BN |
U1.57 J28.5 |
*SIGNAL* SD1AP |
U1.54 J28.2 |
*SIGNAL* SD1BP |
U1.59 J28.6 |
*SIGNAL* SD1AN |
U1.55 J28.3 |
*SIGNAL* SD2AN |
U1.126 J29.3 |
*SIGNAL* SD2BP |
U1.131 J29.6 |
*SIGNAL* SD2BN |
U1.129 J29.5 |
*SIGNAL* N200530 |
C34.2 R80.1 R16.2 |
*SIGNAL* SD2AP |
U1.124 J29.2 |
*SIGNAL* N22079 |
Q7.C LD1.12 |
*SIGNAL* N22088 |
Q6.C LD1.9 |
*SIGNAL* N22096 |
Q5.C LD1.8 |
*SIGNAL* N22104 |
Q4.C LD1.6 |
*SIGNAL* N22119 |
R45.1 Q4.B |
*SIGNAL* N22122 |
R46.1 Q5.B |
*SIGNAL* N64005 |
U1.125 TPS2.1 |
*SIGNAL* N22125 |
R47.1 Q6.B |
*SIGNAL* N201217 |
U1.35 TPS4.1 |
*SIGNAL* N201219 |
U1.33 TPS3.1 |
*SIGNAL* N64014 |
U1.141 TPS5.1 |
*SIGNAL* IP0 |
J9.1 J9.2 U11.26 R100.2 |
*SIGNAL* N64017 |
U1.123 TPS6.1 |
*SIGNAL* IP1 |
U11.27 J9.3 J9.4 R101.2 |
*SIGNAL* IP2 |
U11.29 J9.5 J9.6 R102.2 |
*SIGNAL* IP3 |
U11.30 J9.7 J9.8 R103.2 |
*SIGNAL* IP4 |
U11.32 J9.9 J9.10 R104.2 |
*SIGNAL* N63818 |
U1.53 TPS1.1 |
*SIGNAL* IP5 |
U11.33 J9.11 J9.12 R105.2 |
*SIGNAL* IP6 |
U11.35 J9.13 J9.14 R106.2 |
*SIGNAL* IP7 |
U11.36 J9.15 J9.16 R107.2 |
*SIGNAL* IP8 |
U11.37 J9.17 J9.18 R108.2 |
*SIGNAL* IP9 |
U11.38 J9.19 J9.20 R109.2 |
*SIGNAL* IP10 |
J9.21 J9.22 U11.40 R110.2 |
*SIGNAL* IP11 |
U11.41 J9.23 J9.24 R111.2 |
*END* |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_SCH.PDF |
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/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/src/PulseGen.vhd |
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---------------------------------------------------------------------------------- |
-- Company: www.mlab.cz |
-- Based on code written by MIHO. |
-- |
-- Design Name: S3AN01A |
-- Project Name: PulseGen |
-- Target Devices: XC3S50AN-4 |
-- Tool versions: ISE 13.3 |
-- Description: Sample of Pulse Generator at S3AN01A MLAB board. |
-- |
-- Dependencies: External PS/2 Keyboard has to be connected. |
-- |
-- Version: $Id$ |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.numeric_std.ALL; |
use WORK.PS2_pkg.ALL; |
library UNISIM; |
use UNISIM.vcomponents.all; |
entity PulseGen is |
generic ( |
-- Top Value for 100MHz Clock Counter |
MAXCOUNT: integer := 30_000_000; |
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
); |
port ( |
-- Main Clock |
CLK100MHz: in std_logic; |
-- Mode Signals (usualy not used) |
M: in std_logic_vector(2 downto 0); |
VS: in std_logic_vector(2 downto 0); |
-- Dipswitch Inputs |
DIPSW: in std_logic_vector(7 downto 0); |
-- Push Buttons |
PB: in std_logic_vector(3 downto 0); |
-- LED Bar Outputs |
LED: out std_logic_vector(7 downto 0); |
-- LED Display (8 digit with 7 segments and ddecimal point) |
LD_A_n: out std_logic; |
LD_B_n: out std_logic; |
LD_C_n: out std_logic; |
LD_D_n: out std_logic; |
LD_E_n: out std_logic; |
LD_F_n: out std_logic; |
LD_G_n: out std_logic; |
LD_DP_n: out std_logic; |
LD_0_n: out std_logic; |
LD_1_n: out std_logic; |
LD_2_n: out std_logic; |
LD_3_n: out std_logic; |
LD_4_n: out std_logic; |
LD_5_n: out std_logic; |
LD_6_n: out std_logic; |
LD_7_n: out std_logic; |
-- VGA Video Out Port |
VGA_R: out std_logic_vector(1 downto 0); |
VGA_G: out std_logic_vector(1 downto 0); |
VGA_B: out std_logic_vector(1 downto 0); |
VGA_VS: out std_logic; |
VGA_HS: out std_logic; |
-- Bank 1 Pins - Inputs for this Test |
B: inout std_logic_vector(24 downto 0); |
-- PS/2 Bidirectional Port (open collector, J31 and J32) |
-- PS2_CLK1: inout std_logic; |
-- PS2_DATA1: inout std_logic; |
PS2_CLK2: inout std_logic; |
PS2_DATA2: inout std_logic; |
-- Diferencial Signals on 4 pin header (J7) |
DIF1P: inout std_logic; |
DIF1N: inout std_logic; |
DIF2P: inout std_logic; |
DIF2N: inout std_logic; |
-- I2C Signals (on connector J30) |
I2C_SCL: inout std_logic; |
I2C_SDA: inout std_logic; |
-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
SD1AP: inout std_logic; |
SD1AN: inout std_logic; |
SD1BP: inout std_logic; |
SD1BN: inout std_logic; |
SD2AP: inout std_logic; |
SD2AN: inout std_logic; |
SD2BP: inout std_logic; |
SD2BN: inout std_logic; |
-- Analog In Out |
ANA_OUTD: out std_logic; |
ANA_REFD: out std_logic; |
ANA_IND: in std_logic; |
-- SPI Memory Interface |
SPI_CS_n: inout std_logic; |
SPI_DO: inout std_logic; |
SPI_DI: inout std_logic; |
SPI_CLK: inout std_logic; |
SPI_WP_n: inout std_logic |
); |
end entity PulseGen; |
architecture PulseGen_a of PulseGen is |
function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is |
variable i : integer:=0; |
variable mybcd : std_logic_vector(11 downto 0) := (others => '0'); |
variable bint : std_logic_vector(7 downto 0) := bin; |
begin |
for i in 0 to 7 loop -- repeating 8 times. |
mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits. |
mybcd(0) := bint(7); |
bint(7 downto 1) := bint(6 downto 0); |
bint(0) :='0'; |
if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
end if; |
if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
end if; |
if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
end if; |
end loop; |
return mybcd; |
end to_bcd; |
-- O1: ____|^^^^^^^|______ |
-- O2: _________|^^|______ |
-- t1 t2 |
-- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz |
signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2 |
signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2 |
signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer |
signal O1: std_logic := '0'; -- Output 1 |
signal O2: std_logic := '0'; -- Output 2 |
signal CTburst: unsigned(15 downto 0) := X"0000"; -- Pulse counter |
-- LED Demo Signals |
-- ---------------- |
signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary) |
signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) |
signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) |
-- LED Display |
-- ----------- |
signal Number: std_logic_vector(32 downto 0); -- LED Display Input |
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
signal Enable: std_logic; |
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
-- PS/2 Port |
-- --------- |
-- Interface Signals |
signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code |
signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock) |
signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code |
-- Result |
signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory) |
-- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese |
-- VGA Demo Signals |
-- ---------------- |
signal CLK: std_logic; -- Main Clock - global distribution network |
signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG |
signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network |
signal VGA_Blank: boolean; -- Blank |
signal VGA_Hsync: boolean; -- Horisontal Synchronisation |
signal VGA_Vsync: boolean; -- Vertical Synchronisation |
signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter |
signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter |
signal PinState: std_logic; -- For IB1 Port Test |
signal Red: std_logic_vector(1 downto 0); |
signal Green: std_logic_vector(1 downto 0); |
signal Blue: std_logic_vector(1 downto 0); |
-- ADDA |
signal ADDA_DataIn: std_logic_vector(7 downto 0); |
begin |
-- Basic LED Blinking Test |
-- ======================= |
-- LED Bar Counter |
process (CLK100MHz) |
begin |
if rising_edge(CLK100MHz) then |
if Counter < MAXCOUNT-1 then |
Counter <= Counter + 1; |
else |
Counter <= (others => '0'); |
Bar <= Bar + 1; |
end if; |
end if; |
end process; |
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter |
FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity |
-- LED Display (multiplexed) |
-- ========================= |
-- Connect LED Display Output Ports (negative outputs) |
LD_A_n <= not (Segments(0) and Enable); |
LD_B_n <= not (Segments(1) and Enable); |
LD_C_n <= not (Segments(2) and Enable); |
LD_D_n <= not (Segments(3) and Enable); |
LD_E_n <= not (Segments(4) and Enable); |
LD_F_n <= not (Segments(5) and Enable); |
LD_G_n <= not (Segments(6) and Enable); |
LD_DP_n <= not (Segments(7) and Enable); |
LD_0_n <= not Digits(0); |
LD_1_n <= not Digits(1); |
LD_2_n <= not Digits(2); |
LD_3_n <= not Digits(3); |
LD_4_n <= not Digits(4); |
LD_5_n <= not Digits(5); |
LD_6_n <= not Digits(6); |
LD_7_n <= not Digits(7); |
-- Time Multiplex |
process (CLK100MHz) |
begin |
if rising_edge(CLK100MHz) then |
if MuxCounter < MUXCOUNT-1 then |
MuxCounter <= MuxCounter + 1; |
else |
MuxCounter <= (others => '0'); |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
Enable <= '0'; |
end if; |
if MuxCounter > (MUXCOUNT-4) then |
Enable <= '1'; |
end if; |
end if; |
end process; |
-- BCD to 7 Segmet Decoder |
-- -- A |
-- | | F B |
-- -- G |
-- | | E C |
-- -- D H |
-- ABCDEFGH |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
"01100000" when Code="0001" else -- Digit 1 |
"11011010" when Code="0010" else -- Digit 2 |
"11110010" when Code="0011" else -- Digit 3 |
"01100110" when Code="0100" else -- Digit 4 |
"10110110" when Code="0101" else -- Digit 5 |
"10111110" when Code="0110" else -- Digit 6 |
"11100000" when Code="0111" else -- Digit 7 |
"11111110" when Code="1000" else -- Digit 8 |
"11110110" when Code="1001" else -- Digit 9 |
"11101110" when Code="1010" else -- Digit A |
"00111110" when Code="1011" else -- Digit b |
"10011100" when Code="1100" else -- Digit C |
"01111010" when Code="1101" else -- Digit d |
"10011110" when Code="1110" else -- Digit E |
"10001110" when Code="1111" else -- Digit F |
"00000000"; |
Code <= Number( 3 downto 0) when Digits="00000001" else |
Number( 7 downto 4) when Digits="00000010" else |
Number(11 downto 8) when Digits="00000100" else |
Number(15 downto 12) when Digits="00001000" else |
Number(19 downto 16) when Digits="00010000" else |
Number(23 downto 20) when Digits="00100000" else |
Number(27 downto 24) when Digits="01000000" else |
Number(31 downto 28) when Digits="10000000" else |
"0000"; |
-- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0 |
-- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1 |
-- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2 |
-- "11111111"; |
-- Number(31 downto 28) <= Key(3 downto 0); |
-- Number( 7 downto 0) <= std_logic_vector(BAR); |
-- Number(31 downto 24) <= DIPSW; |
-- PS/2 Port |
-- ========= |
-- Instantiate PS/2 Keyboard Interface Handler |
PS2_Keyboard: PS2 generic map( |
CLKFREQ => 100_000_000 |
) |
port map( |
-- Main Clock |
Clk => CLK100MHz, |
-- PS/2 Port |
PS2_Clk => PS2_CLK2, |
PS2_Data => PS2_DATA2, |
-- Result - valid when PS2_Valid |
PS2_Code => PS2_Code, |
PS2_Attribs => PS2_Attribs, |
PS2_Valid => PS2_Valid, |
-- Immediate State of Shifts |
PS2_Shifts => PS2_Shifts |
); -- PS2 |
process (CLK100MHz) |
begin |
if rising_edge(CLK100MHz) then |
if PS2_Valid and PS2_Attribs(7)='0' then |
-- Valid Scan Code with no Break Attribute |
PS2_Result( 7 downto 0) <= PS2_Code; |
PS2_Result(15 downto 8) <= PS2_Attribs; |
end if; |
if PS2_Valid and PS2_Attribs(7)='0' then |
if PS2_Code = X"74" and T1<2000 then T1<=T1+1; end if; |
if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if; |
if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if; |
if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if; |
CT0<=X"0000"; |
O1<='0'; |
O2<='0'; |
CTburst<=X"0000"; |
end if; |
if PB(0)='1' then |
T1<=X"0000"; |
T2<=X"0000"; |
end if; |
if DIPSW(0)='1' then |
if CT0>X"F000" then |
CT0<=X"0000"; |
else |
CT0<=CT0+1; |
end if; |
else |
if CT0>X"0200" then |
CT0<=X"0000"; |
else |
CT0<=CT0+1; |
end if; |
end if; |
if CTburst>2000 then |
CTburst<=X"0000"; |
end if; |
if (CTburst<1000) or (DIPSW(1)='0') then |
if CT0=X"0000" then |
O1<='1'; |
end if; |
if CT0=T1+X"0000" then |
O2<='1'; |
end if; |
end if; |
if CT0=T2+T1+X"0000" then |
O1<='0'; |
O2<='0'; |
CTburst<=CTburst+1; |
end if; |
end if; |
end process; |
-- Display Result on LED |
Number(3 downto 0) <= (others=>'0'); |
Number(15 downto 4) <= to_bcd(std_logic_vector(T2)); |
Number(19 downto 16) <= (others=>'0'); |
Number(31 downto 20) <= to_bcd(std_logic_vector(T1)); |
-- Test Diferencial In/Outs |
-- ======================== |
-- Output Signal on SATA Connector |
SD1AP <= Bar(0); |
SD1AN <= Bar(1); |
SD1BP <= Bar(2); |
SD1BN <= Bar(3); |
-- Input Here via SATA Cable |
SD2AP <= 'Z'; |
SD2AN <= 'Z'; |
SD2BP <= 'Z'; |
SD2BN <= 'Z'; |
-- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them |
-- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!! |
DIF1P <= O1; |
B(0) <= O1; |
DIF1N <= not O1; |
B(1) <= not O1; |
DIF2P <= O2; |
B(2) <= O2; |
DIF2N <= not O2; |
B(3) <= not O2; |
VGA_R(0) <= O1; |
VGA_R(1) <= O2; |
-- Unused Signals |
-- ============== |
-- I2C Signals (on connector J30) |
I2C_SCL <= 'Z'; |
I2C_SDA <= 'Z'; |
-- SPI Memory Interface |
SPI_CS_n <= 'Z'; |
SPI_DO <= 'Z'; |
SPI_DI <= 'Z'; |
SPI_CLK <= 'Z'; |
SPI_WP_n <= 'Z'; |
ANA_OUTD <= 'Z'; |
ANA_REFD <= 'Z'; |
VGA_R <= "ZZ"; |
VGA_G <= "ZZ"; |
VGA_B <= "ZZ"; |
VGA_VS <= 'Z'; |
VGA_HS <= 'Z'; |
end architecture PulseGen_a; |
Property changes: |
Added: svn:keywords |
+Id |
\ No newline at end of property |
/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/src/LIB/PS2.vhd |
---|
0,0 → 1,520 |
---------------------------------------------------------------------------------- |
-- Company: www.mlab.cz |
-- Engineer: miho |
-- |
-- Create Date: 19:31:10 02/20/2011 |
-- Design Name: S3AN01A Test Design |
-- Module Name: PS2 |
-- Project Name: S3AN01A Test Design |
-- Target Devices: XILINX FPGA (Spartan3A/3AN) |
-- Tool versions: ISE 12.4 / 13.1 / 13.3 |
-- Description: Test design for PCB verification |
-- |
-- Dependencies: None |
-- |
-- Revision: 0.01 File Created |
-- |
---------------------------------------------------------------------------------- |
-- |
-- PS/2 Keyboard Driver |
-- ==================== |
-- |
-- PS2_Code |
-- -------- |
-- |
-- Standard PS/2 Scan Code |
-- |
-- |
-- PS2_Attribs |
-- ----------- |
-- |
-- Bit 0 - Shift |
-- Bit 1 - Ctrl |
-- Bit 2 - Alt |
-- Bit 3 - Ext0 (arrows, ...) |
-- Bit 4 - Ext1 |
-- Bit 5 - Shift Num (arrows with NumLock) |
-- Bit 6 |
-- Bit 7 - Break (key release) |
-- |
-- |
-- PS2_Shifts |
-- ---------- |
-- |
-- Bit 0 - Shift Left |
-- Bit 1 - Shift Right |
-- Bit 2 - Ctrl Left |
-- Bit 3 - Ctrl Right |
-- Bit 4 - Alt Left |
-- Bit 5 - Alt Right |
-- Bit 6 - Num Lock |
-- Bit 7 - Caps Lock |
-- Bit 8 - Scroll Lock |
-- Bit 9 - Shift Num (virtual state) - Not to be used |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
entity PS2 is |
generic ( |
-- Top Value for 100MHz Clock Counter |
CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000) |
); |
port ( |
-- Main Clock |
Clk: in std_logic; |
-- PS/2 Port |
PS2_Clk: inout std_logic; |
PS2_Data: inout std_logic; |
-- Result - valid when PS2_Valid |
PS2_Valid: out boolean; -- Valid Data (synchronous with Clk) |
PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code |
PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
-- Immediate State of Shifts |
PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc. |
); |
end entity PS2; |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
package PS2_pkg is |
component PS2 |
generic ( |
-- Top Value for 100MHz Clock Counter |
CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000) |
); |
port ( |
-- Main Clock |
Clk: in std_logic; |
-- PS/2 Port |
PS2_Clk: inout std_logic; |
PS2_Data: inout std_logic; |
-- Result - valid when PS2_Valid |
PS2_Valid: out boolean; -- Valid Data (synchronous with Main Clock) |
PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code |
PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
-- Immediate State of Shifts |
PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc. |
); |
end component PS2; |
end package; |
architecture PS2_a of PS2 is |
function to_std_logic(State: boolean) return std_logic is |
begin |
if State then |
return '1'; |
else |
return '0'; |
end if; |
end function to_std_logic; |
-- Sampled PS/2 Clock and Data |
signal PS2_Clk_d: std_logic := '0'; -- For sync with systerm clock |
signal PS2_Clk_dd: std_logic := '0'; -- For falling edge detection |
signal PS2_Data_d: std_logic := '0'; -- For sync with systerm clock |
-- Level 0 - Read Byte from PS/2 Interface |
type ReadByte_t is ( -- Read Byte FSM State Type |
Idle, -- Inactive State |
D0, D1, D2, D3, D4, D5, D6, D7, -- Receiving Bits |
Parity, -- Receiving Parity |
Final -- Receiving Stop Bit and Sending ReadByte_rdy |
); |
signal ReadByteState: ReadByte_t := Idle; -- Read Byte FSM State |
signal ReadByte: std_logic_vector(7 downto 0) := (others => '0'); -- Read Byte (Raw Scan Code Byte) |
signal ReadByte_rdy: boolean := false; -- Read Byte Ready (synchronous with Clk) |
-- Level 1 - Process Raw Scan Codes E0,F1 and F0 - valid only when Level1_rdy |
signal FlagE0: boolean := false; -- E0 - Ext0 Key |
signal FlagE1: boolean := false; -- E1 - Ext1 Key |
signal FlagF0: boolean := false; -- F0 - Break (release) Key |
signal Level1_rdy: boolean := false; -- Send Data and Flags to the next level |
-- Level 2 - Process Raw Scan Codes and Shift-Like Atributes E0, E1 and F0 - valid only when Level2_rdy |
signal FlagBreak: boolean := false; -- F0 - Break (depress) Key |
signal FlagAltR: boolean := false; -- E0 11 - State of Right Alt Key |
signal FlagAltL: boolean := false; -- 11 - State of Left Alt Key |
signal FlagShiftNum: boolean := false; -- E0 12 - State of Ext Left Shift (pseudo key) |
signal FlagShiftL: boolean := false; -- 12 |
signal FlagShiftR: boolean := false; -- 59 |
signal FlagCtrlR: boolean := false; -- E0 14 |
signal FlagCtrlL: boolean := false; -- 14 |
signal FlagExt0: boolean := false; -- E0 Keys (extended keys) |
signal FlagExt1: boolean := false; -- E1 Keys (extended keys - Prt_Scr and Pause_Brk) |
signal FlagNumLock: boolean := false; -- 77 Num Lock State |
signal FlagScrollLock: boolean := false; -- 7E Scroll Lock State |
signal FlagCapsLock: boolean := false; -- 58 Caps Lock State |
signal Level2_rdy: boolean := false; -- Send Data and Flags to the next level |
signal Level2a_rdy: boolean := false; -- Send Read Ack for Write Byte |
-- Write Byte |
type WriteByteState_t is ( -- Write Byte FSM State Type |
Idle, -- Idle State |
WriteStart, -- Start (pull PS2_Clk down) |
WaitStart, -- Wait |
SendBits, -- Send Data Bits |
WriteParity, -- Send Parity |
WriteStop, -- Send Stop Bit |
AckBit, -- Wait for Ack Bit from Keyboard |
Final, -- Wait for Idle on PS2_Clk and PS2_Data |
WaitAckByte -- Wait for Ack Byte from Keyboard |
); |
signal WriteByteState: WriteByteState_t := Idle; -- Write Byte FSM State |
signal WriteCode: std_logic_vector(7 downto 0) := (others =>'0'); -- What to Write |
signal WriteByte: boolean := false; -- Init Write Byte Sequence |
signal SendingData: boolean := false; -- Block Receiver when Sending Data |
signal WriteByte_ack: boolean := false; -- Ack Writen Byte |
signal WriteReg: std_logic_vector(7 downto 0) := (others =>'0'); -- Transmit Shift Register |
signal ParityBit: std_logic := '0'; -- Parity Bit |
signal StartTime: unsigned(31 downto 0) := (others =>'0'); -- Timer for Start of Write (PS2_Clk low) |
signal WriteBits: unsigned(3 downto 0) := (others =>'0'); -- Bit Counter |
-- Update LED Indicators |
type UpdState_t is ( -- Update Led Indicators FSM State Type |
Idle, -- Inactive State |
SendReset, -- For Debug - Reset Keyboard |
SendLed1, -- Send FD |
SendLed2, -- Send New LED State |
SendFinal -- |
); |
signal UpdState: UpdState_t := Idle; -- Update Led Indicators FSM State |
signal UpdateLed: boolean := false; -- Send new LED State to the Keyboard |
signal UpdateLed_ack: boolean := false; -- Ack (1 clock pulse) |
begin |
-- Sync External Signals with Clock |
process (Clk) |
begin |
if rising_edge(Clk) then |
-- Sync |
PS2_Clk_d <= PS2_Clk; |
PS2_Data_d <= PS2_Data; |
-- For Falling Edge Detection |
PS2_Clk_dd <= PS2_Clk_d; |
end if; |
end process; |
-- Level 0 - Read Byte from PS/2 Interface |
process (Clk) |
begin |
if rising_edge(Clk) then |
ReadByte_rdy <= false; |
if PS2_Clk_dd='1' and PS2_Clk_d='0' and not SendingData then |
-- Falling Edge of PS2_Clk |
case ReadByteState is |
when Idle => |
-- Test Start Bit |
if PS2_Data='0' then |
ReadByteState <= D0; |
end if; |
when D0 => |
-- Bit 0 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
ReadByteState <= D1; |
when D1 => |
-- Bit 1 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
ReadByteState <= D2; |
when D2 => |
-- Bit 2 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
ReadByteState <= D3; |
when D3 => |
-- Bit 3 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
ReadByteState <= D4; |
when D4 => |
-- Bit 4 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
ReadByteState <= D5; |
when D5 => |
-- Bit 5 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
ReadByteState <= D6; |
when D6 => |
-- Bit 6 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
ReadByteState <= D7; |
when D7 => |
-- Bit 7 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
ReadByteState <= Parity; |
when Parity => |
-- Check Parity Here... |
ReadByteState <= Final; |
when Final => |
-- End of Byte |
ReadByteState <= Idle; |
ReadByte_rdy <= true; -- Scan Code Ready (8 bit word) |
end case; |
end if; |
end if; |
end process; |
-- Level 1 - Process Raw Scan Codes and ESC Atributes E0, E1 and F0 |
process (Clk) |
begin |
if rising_edge(Clk) then |
if Level1_rdy then |
-- Clean State when Sent Data from Level1 processing |
Level1_rdy <= false; |
FlagE0 <= false; |
FlagE1 <= false; |
FlagF0 <= false; |
else |
if ReadByte_rdy then |
-- Process Scan Code Byte from Level 0 |
if ReadByte=X"E0" then |
-- Ext Code |
FlagE0 <= true; |
elsif ReadByte=X"E1" then |
-- Special Ext Code |
FlagE1 <= true; |
elsif ReadByte=X"F0" then |
-- Break Flag |
FlagF0 <= true; |
else |
-- Scan Code |
Level1_rdy <= true; |
end if; |
end if; |
end if; |
end if; |
end process; |
-- Level 2 - Process Shift (left and right shift, alt and ctrl) and Num Lock (numeric virtual shift) |
process (Clk) |
begin |
if rising_edge(Clk) then |
-- Clear Comands to Higher Level |
UpdateLed <= false; |
Level2a_rdy <= false; |
Level2_rdy <= false; |
-- Process Read Byte |
if Level1_rdy then |
if ReadByte=X"11" then |
-- Alt Key |
if FlagE0 then |
FlagAltR <= not FlagF0; |
else |
FlagAltL <= not FlagF0; |
end if; |
elsif ReadByte=X"12" then |
-- Left Shift |
if FlagE0 then |
FlagShiftNum <= not FlagF0; |
else |
FlagShiftL <= not FlagF0; |
end if; |
elsif ReadByte=X"59" then |
-- Right Shift |
FlagShiftR <= not FlagF0; |
elsif ReadByte=X"14" then |
-- Ctrl |
if FlagE0 then |
FlagCtrlR <= not FlagF0; |
else |
FlagCtrlL <= not FlagF0; |
end if; |
elsif ReadByte=X"77" and not FlagCtrlL and not FlagCtrlR and not FlagAltL and not FlagAltR then |
-- Num Lock On/Off |
if not FlagF0 then |
FlagNumLock <= not FlagNumLock; |
UpdateLed <= true; -- Set UpdateLed Request |
end if; |
elsif ReadByte=X"58" then |
-- Caps Lock |
if not FlagF0 then |
FlagCapsLock <= not FlagCapsLock; |
UpdateLed <= true; -- Set UpdateLed Request |
end if; |
elsif ReadByte=X"7E" then |
if not FlagF0 then |
FlagScrollLock <= not FlagScrollLock; |
UpdateLed <= true; -- Set UpdateLed Request |
end if; |
else |
-- Send Data to the next Level |
FlagExt0 <= FlagE0; |
FlagExt1 <= FlagE1; |
FlagBreak <= FlagF0; |
if WriteByteState=WaitAckByte then |
-- Send Data (Ack Byte) to WriteByte |
Level2a_rdy <= true; |
else |
-- Send Scan Code to the next Level |
Level2_rdy <= true; |
end if; |
end if; |
end if; |
end if; |
end process; |
-- Send Data |
PS2_Valid <= Level2_rdy; |
-- Scan COde |
PS2_Code(7 downto 0) <= ReadByte; |
-- Attribs |
PS2_Attribs(0) <= '1' when FlagShiftL or FlagShiftR else '0'; -- Bit 0 - Shift |
PS2_Attribs(1) <= '1' when FlagCtrlL or FlagCtrlR else '0'; -- Bit 1 - Ctrl |
PS2_Attribs(2) <= '1' when FlagAltL or FlagAltR else '0'; -- Bit 2 - Alt |
PS2_Attribs(3) <= '1' when FlagExt0 else '0'; -- Bit 3 - Ext Code E0 |
PS2_Attribs(4) <= '1' when FlagExt1 else '0'; -- Bit 4 - Ext Code E1 |
PS2_Attribs(5) <= '1' when FlagShiftNum else '0'; -- Bit 5 - Shift Num (Arrows,...) - only if NumLock Led is Off |
PS2_Attribs(6) <= '0'; |
PS2_Attribs(7) <= '1' when FlagBreak else '0'; -- Bit 7 - Break (release) Key |
-- Immediate State of Shift Like Keys |
PS2_Shifts(0) <= '1' when FlagShiftL else '0'; -- Bit 0 - Shift Left |
PS2_Shifts(1) <= '1' when FlagShiftR else '0'; -- Bit 1 - Shift Right |
PS2_Shifts(2) <= '1' when FlagCtrlL else '0'; -- Bit 2 - Ctrl Left |
PS2_Shifts(3) <= '1' when FlagCtrlR else '0'; -- Bit 3 - Ctrl Right |
PS2_Shifts(4) <= '1' when FlagAltL else '0'; -- Bit 4 - Alt Left |
PS2_Shifts(5) <= '1' when FlagAltR else '0'; -- Bit 5 - Alt Right |
PS2_Shifts(6) <= '1' when FlagNumLock else '0'; -- Bit 7 - Num Lock |
PS2_Shifts(7) <= '1' when FlagCapsLock else '0'; -- Bit 8 - Caps Lock |
PS2_Shifts(8) <= '1' when FlagScrollLock else '0'; -- Bit 9 - Scroll Lock |
PS2_Shifts(9) <= '1' when FlagShiftNum else '0'; -- Bit 6 - Shift Num (virtual state) - Not to be used |
-- Write Byte to PS/2 Interface |
-- Init By: WriteByte |
-- Finish Indication: WriteByte_ack |
process (Clk) |
begin |
if rising_edge(Clk) then |
WriteByte_ack <= false; |
case WriteByteState is |
when Idle => |
PS2_Clk <= 'Z'; |
PS2_Data <= 'Z'; |
if WriteByte then |
WriteByteState <= WriteStart; |
WriteReg <= WriteCode; |
end if; |
when WriteStart => |
if PS2_Data_d='1' and PS2_Clk_d='1' then |
-- PS2 Interface in Idle State |
PS2_Clk <= '0'; -- Start of Write (PS2_Clk=L) |
StartTime <= to_unsigned(CLKFREQ/16000, StartTime'length); -- cca 60us Start |
WriteBits <= to_unsigned(7, WriteBits'length); -- 8 bits |
WriteByteState <= WaitStart; |
SendingData <= true; |
end if; |
when WaitStart => |
if StartTime>0 then |
StartTime <= StartTime - 1; |
else |
PS2_Data <= '0'; -- Start Bit |
PS2_Clk <= 'Z'; -- Release Clk |
ParityBit <= '1'; -- Init Parity Generator (code 1111_1111 has parity 1) |
WriteByteState <= SendBits; |
end if; |
when SendBits => |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
PS2_Data <= WriteReg(0); |
ParityBit <= ParityBit xor WriteReg(0); |
WriteReg <= '1' & WriteReg(7 downto 1); |
if WriteBits>0 then |
WriteBits <= WriteBits - 1; |
else |
WriteByteState <= WriteParity; |
end if; |
end if; |
when WriteParity => |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
PS2_Data <= ParityBit; |
WriteByteState <= WriteStop; |
end if; |
when WriteStop => |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
PS2_Data <= '1'; |
WriteByteState <= AckBit; |
end if; |
when AckBit => |
PS2_Data <= 'Z'; |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
WriteByteState <= Final; |
end if; |
when Final => |
if PS2_Clk_d='1' then |
WriteByteState <= WaitAckByte; |
SendingData <= false; |
end if; |
when WaitAckByte => |
if Level2a_rdy then |
WriteByteState <= Idle; |
WriteByte_ack <= true; |
end if; |
end case; |
end if; |
end process; |
-- Level 3 - Update LED Indicators |
-- Init By: UpdateLed or Level2_rdy(with scan code and attrib) |
-- Finish Indication: UpdateLed_ack (not used) |
process (Clk) |
begin |
if rising_edge(Clk) then |
UpdateLed_ack <= false; -- 1 Clock Pulse |
WriteByte <= false; |
case UpdState is |
when Idle => |
-- Register the request |
if Level2_rdy and ReadByte=X"07" and not FlagBreak then |
WriteCode <= X"FF"; |
WriteByte <= true; |
elsif UpdateLed then |
UpdateLed_ack <= true; |
UpdState <= SendLed1; |
end if; |
when SendReset => |
if WriteByteState=Idle then |
-- Send Keyborad Reset |
WriteCode <= X"FF"; |
WriteByte <= true; |
UpdState <= SendFinal; |
end if; |
when SendLed1 => |
if WriteByteState=Idle then |
-- Send LED Command |
WriteCode <= X"ED"; |
WriteByte <= true; |
UpdState <= SendLed2; |
end if; |
when SendLed2 => |
if WriteByte_ack then |
-- Send LED State |
WriteCode <= "00000" & to_std_logic(FlagCapsLock) |
& to_std_logic(FlagNumLock) |
& to_std_logic(FlagScrollLock); |
WriteByte <= true; |
UpdState <= SendFinal; |
end if; |
when SendFinal => |
if WriteByte_ack then ---WriteByteState=Idle then |
-- Last Data has been Send |
UpdState <= Idle; |
end if; |
end case; |
end if; |
end process; |
end architecture PS2_a; |
/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/src/S3AN01B.ucf |
---|
0,0 → 1,152 |
# Board: www.mlab.cz S3AN01A |
# Device: XC3S50AN-4C |
# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes |
# Main Clock (Embedded 100MHz board oscillator) |
NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33; |
#NET "CLK100MHz" LOC = P125 | IOSTANDARD = LVCMOS33; |
NET "CLK100MHz" TNM_NET = CLK100MHz; |
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%; |
# For DCM connection across the whole chip |
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE; |
NET "PS2_CLK2" CLOCK_DEDICATED_ROUTE = FALSE; |
# Mode signals |
NET "M[0]" LOC = P38 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "M[1]" LOC = P37 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M1 and M2 for boot from external SPI Flash Memory |
NET "M[2]" LOC = P39 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M2 for boot from internal Flash memory |
# SPI Flash Vendor Mode Select (for external SPI boot Flash) |
NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
# DIP Switches (positive signals with pull-down) |
NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
# Push Buttons (positive signals with pull-down) |
NET "PB[0]" LOC = P121 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "PB[1]" LOC = P120 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "PB[2]" LOC = P117 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "PB[3]" LOC = P116 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
# LED String (positive output signals) |
NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33; |
NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33; |
NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33; |
NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33; |
NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33; |
NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33; |
NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33; |
NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33; |
# LED Display Output Signals (negative, multiplexed) |
NET "LD_A_n" LOC = P15 |IOSTANDARD = LVCMOS33; |
NET "LD_B_n" LOC = P30 |IOSTANDARD = LVCMOS33; |
NET "LD_C_n" LOC = P21 |IOSTANDARD = LVCMOS33; |
NET "LD_D_n" LOC = P19 |IOSTANDARD = LVCMOS33; |
NET "LD_E_n" LOC = P18 |IOSTANDARD = LVCMOS33; |
NET "LD_F_n" LOC = P16 |IOSTANDARD = LVCMOS33; |
NET "LD_G_n" LOC = P24 |IOSTANDARD = LVCMOS33; |
NET "LD_DP_n" LOC = P20 |IOSTANDARD = LVCMOS33; |
NET "LD_0_n" LOC = P25 |IOSTANDARD = LVCMOS33; |
NET "LD_1_n" LOC = P31 |IOSTANDARD = LVCMOS33; |
NET "LD_2_n" LOC = P32 |IOSTANDARD = LVCMOS33; |
NET "LD_3_n" LOC = P13 |IOSTANDARD = LVCMOS33; # !!! Connect U1.13 with U1.33 |
NET "LD_4_n" LOC = P27 |IOSTANDARD = LVCMOS33; |
NET "LD_5_n" LOC = P29 |IOSTANDARD = LVCMOS33; |
NET "LD_6_n" LOC = P28 |IOSTANDARD = LVCMOS33; |
NET "LD_7_n" LOC = P12 |IOSTANDARD = LVCMOS33; # !!! Connect U1.12 with U1.35 |
# VGA Analog Display Connection (outputs) |
NET "VGA_R[0]" LOC = P3 |IOSTANDARD = LVCMOS33; |
NET "VGA_R[1]" LOC = P4 |IOSTANDARD = LVCMOS33; |
NET "VGA_G[0]" LOC = P5 |IOSTANDARD = LVCMOS33; |
NET "VGA_G[1]" LOC = P6 |IOSTANDARD = LVCMOS33; |
NET "VGA_B[0]" LOC = P7 |IOSTANDARD = LVCMOS33; |
NET "VGA_B[1]" LOC = P8 |IOSTANDARD = LVCMOS33; |
NET "VGA_VS" LOC = P10 |IOSTANDARD = LVCMOS33; |
NET "VGA_HS" LOC = P11 |IOSTANDARD = LVCMOS33; |
# Bank 1 Port (input for tests, pull-up) |
NET "B[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "B[24]" LOC = P97 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Connected with B[23] on PCB |
# PS/2 Bidirectional Port (open collector, J31 and J32) |
#NET "PS2_CLK1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # S3AN01A PCB Design has bug so these pins |
#NET "PS2_DATA1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # will be assinged after PCB redesign |
NET "PS2_CLK2" LOC = P42 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "PS2_DATA2" LOC = P58 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
# Diferencial Signals on 4 pin header (J7) |
NET "DIF1P" LOC = P110 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIF1N" LOC = P111 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIF2P" LOC = P112 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "DIF2N" LOC = P113 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
# I2C Signals (on connector J30) |
NET "I2C_SCL" LOC = P115 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "I2C_SDA" LOC = P114 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
# Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
NET "SD1AP" LOC = P54 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SD1AN" LOC = P55 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SD1BP" LOC = P59 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SD1BN" LOC = P57 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SD2AP" LOC = P124 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SD2AN" LOC = P126 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SD2BP" LOC = P131 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SD2BN" LOC = P129 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
# SPI Memory Interface |
NET "SPI_CS_n" LOC = P41 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
NET "SPI_DO" LOC = P71 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SPI_DI" LOC = P62 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SPI_CLK" LOC = P72 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
NET "SPI_WP_n" LOC = P70 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
# Analog In Out |
NET "ANA_OUTD" LOC = P67 |IOSTANDARD = LVCMOS33; |
NET "ANA_REFD" LOC = P68 |IOSTANDARD = LVCMOS33; |
NET "ANA_IND" LOC = P69 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
/* |
# Used Signals (test points) |
NET "TPS1" LOC = P53 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
NET "TPS2" LOC = P125 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
NET "TPS3" LOC = P127 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
NET "TPS4" LOC = P130 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
NET "TPS5" LOC = P141 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
NET "TPS6" LOC = P123 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
NET "XXX1" LOC = P33 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only |
NET "XXX2" LOC = P35 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only |
*/ |
/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/PulseGen.xise |
---|
0,0 → 1,350 |
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
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<!-- project source files, project and process properties. This file, --> |
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<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
</header> |
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/> |
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<file xil_pn:name="src/PulseGen.vhd" xil_pn:type="FILE_VHDL"> |
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<!-- ============== TEXT ============== --> |
<div class="Text"> |
<p class="Title"> |
Vývojová deska s obvodem FPGA XILINX Spartan 3AN |
</p> |
<p class="Autor"> |
Milan Horkel |
</p> |
<p class="Subtitle"> |
Před časem mne kluci na kroužku ukecali, abych udělal jednoduchou |
vývojovou desku s nějakým programovatelným obvodem. Nakonec jsem |
zvolil obvod FPGA od firmy XILINX z řady Spartan3AN, protože |
poskytuje rozumné možnosti za rozumnou cenu. Deska je osazena obvodem |
XC3S50AN v pouzdru TQFP 144. |
</p> |
<p class="Subtitle"> |
Tento dokument popisuje hardware desky, její testování a použití |
naleznete v dalších dokumentech. |
</p> |
<p class="Subtitle"> |
<img width="453" height="517" |
src="S3AN01B_HW_Reference.cs_soubory/image001.jpg" |
alt="Deska S3AN01B, pohled shora"> |
</p> |
<p> |
<a href="../S3AN01B_HW_Reference.cs.pdf"><img class="NoBorder" |
src="../../../../../Web/PIC/FileIco_PDF.ico" |
alt="Acrobat"> PDF verze</a> |
</p> |
<h1> Technické parametry </h1> |
<table> |
<tr> |
<th> Parametr </th> |
<th> Hodnota </th> |
<th> Poznámka </th> |
</tr> |
<tr> |
<td> Použitý obvod </td> |
<td> XC3S50AN, TQFP144 </td> |
<td> XILINX FPGA Spartan 3AN </td> |
</tr> |
<tr> |
<td> Napájení desky </td> |
<td> +5V </td> |
<td> Cca. 250mA (závisí na funkci) </td> |
</tr> |
<tr> |
<td> Vnitřní napájení </td> |
<td> +3.3V (napájení logiky) </td> |
<td> Vlastní stabilizátor </td> |
</tr> |
<tr> |
<td> </td> |
<td> +1.2V (napájení jádra FPGA) </td> |
<td> Vlastní stabilizátor </td> |
</tr> |
<tr> |
<td> Periferie na desce </td> |
<td> LED displej 8 míst </td> |
<td> Zapojený multiplexně </td> |
</tr> |
<tr> |
<td> </td> |
<td> LED indikátory 8 bitů </td> |
<td> Zapojené na samostatné výstupy </td> |
</tr> |
<tr> |
<td> </td> |
<td> DIP spínače 8 bitů </td> |
<td> Zapojené na samostatné vstupy </td> |
</tr> |
<tr> |
<td> </td> |
<td> Tlačítka 4 bity </td> |
<td> Zapojené na samostatné vstupy </td> |
</tr> |
<tr> |
<td> </td> |
<td> VGA výstup </td> |
<td> 2 bity na barvu </td> |
</tr> |
<tr> |
<td> </td> |
<td> PS/2 rozhraní 2 kusy </td> |
<td> 5V tolerantní </td> |
</tr> |
<tr> |
<td> </td> |
<td> I2C rozhraní </td> |
<td> 5V tolerantní </td> |
</tr> |
<tr> |
<td> </td> |
<td> Obvod 5V tolerantních vstupů </td> |
<td> Celkem 32 vstupů </td> |
</tr> |
<tr> |
<td> </td> |
<td> Jednoduchý A/D a D/A </td> |
<td> Pomocí PWM </td> |
</tr> |
<tr> |
<td> Konfigurace </td> |
<td> Interní paměť obvodu FPGA </td> |
<td> Platí pro obvody řady AN </td> |
</tr> |
<tr> |
<td> </td> |
<td> Volitelně paměť SPI FLASH </td> |
<td> Pro obvody řady A i AN </td> |
</tr> |
<tr> |
<td> Rozměry </td> |
<td> Cca 112x122x20mm </td> |
<td> Výška nad základnou </td> |
</tr> |
</table> |
<p> |
<i class="Big">Důrazně</i> <i>připomínám hned na začátku, že obvod FPGA |
není 5V tolerantní! Znamená to, že se na jeho vstupy smí připojit pouze |
signály do velikosti +3.3V (absolutní maximum je +4.6V).</i> |
</p> |
<p> |
<i>Stejně důrazně musím upozornit na to, že na vstupech obvodu nejsou |
ochranné diody mezi vstupem a kladným napájecím napětím! To je zásadní |
rozdíl od většiny jednočipových mikroprocesorů. Nelze se tedy spoléhat |
na to, že když budeme vstupy budit přes velký sériový odpor, že se nic |
nestane. Stane! Při zvýšeném napětí na vstupech může být životnost |
vstupních tranzistorů v řádu minut nebo hodin.</i> |
</p> |
<h1> Popis konstrukce </h1> |
<h2> Úvodem </h2> |
<p> |
Školní deska pro práci s obvody FPGA XILINX řady Spartan 3AN vznikla na |
popud kluků v kroužku radiotechniky. Protože s obvody FPGA firmy XILINX |
pracuji, ujal jsem se tohoto úkolu. Nejdřív jsem uvažoval, že bychom |
začali s deskou s některým obvodem CPLD, ale po prozkoumání |
ceníku, jsem se přiklonil k obvodu FPGA řady Spartan3AN. |
</p> |
<p> |
Obvody FPGA mají mnohem propracovanější vnitřní architekturu a obsahují |
mnohem víc logiky než obvody CPLD. Obvod samotný stojí pouhých 210Kč |
včetně DPH (podzim 2010). |
</p> |
<p> |
Je to vlastně nejpokročilejší obvod FPGA v pouzdru TQFP, tedy |
v pouzdru, které si dokážeme sami připájet a v nouzi si |
dokonce dokážeme sami vyrobit i plošný spoj. Viz dokumentace od první |
verze této desky na adrese |
<a href="http://www.mlab.cz/PermaLink/S3AN01A">http://www.mlab.cz/PermaLink/S3AN01A</a> |
</p> |
<p> |
Snad by měl existovat i obvod z řady Spartan6 v pouzdru TQFP, |
ale nikde jsem ho neviděl na skladě. Až ho uvidím, tak z něj možná |
taky něco udělám, pokud čas dovolí. |
</p> |
<h2> Zapojení modulu </h2> |
<p> |
Zapojení desky odpovídá účelu desky. Jako vývojová a školní deska je |
vybavena obvody pro snadnou práci s obvodem FPGA. Na desce |
nalezneme LED displej, skupinu LED diod, několik tlačítek a DIP |
přepínačů. Vstupy a výstupy jsou vyvedeny na propojovací hřebínky. |
</p> |
<h3> Napájení </h3> |
<p> |
Celá deska se napájí napětím +5V přivedeným na konektor J1. Opět |
důrazně připomínám, že použitý obvod FPGA vydrží na vývodech napětí |
3.3V, ale ne 5V! |
</p> |
<p> |
<img width="697" height="308" |
src="S3AN01B_HW_Reference.cs_soubory/image002.png" |
alt="Schéma napájecí části"> |
</p> |
<p> |
Z napětí +5V se lineárním stabilizátorem U2 vytváří napětí +3.3V |
pro napájení vstupů a výstupů obvodu FPGA. Přítomnost napětí +3.3V |
indikuje dioda D10 umístěná v rohu desky. Napětí +3.3V je vyvedeno |
na konektor J2 k dalšímu použití. <i>Pozor, nezapojit sem napájení |
+5V, došlo by ke zničení obvodu FPGA!</i> Abych na tento konektor |
omylem nepřipojil +5V, dávám si ta prostřední vývody zkratovací |
propojku. Dioda D9 slouží jako ochrana před přepólováním napájení. |
</p> |
<p> |
Z napětí +3.3V se lineárním stabilizátorem vytváří napětí |
+1.2V pro napájení jádra obvodu FPGA. |
</p> |
<h3> Konfigurace obvodu FPGA </h3> |
<p> |
Po zapnutí napájení je obvod FPGA potřeba naplnit obsahem, tedy |
definovat, jak bude uvnitř zapojen. Toto vnitřní zapojení se nahrává do |
vnitřní konfigurační paměti RAM a lze to udělat několika způsoby: |
</p> |
<ul> |
<li> Prostřednictvím JTAG rozhraní přímo z návrhového systému </li> |
<li> Z interní paměti obvodu FPGA </li> |
<li> Z vnější SPI paměti FLASH (obvod U5/U6/U7 nebo U8) – volitelná možnost </li> |
<li> Z nadřazeného procesoru (paralelně nebo sériově) – zde se tento způsob neužívá </li> |
</ul> |
<p> |
Při úspěšném nahrání konfigurace obvodu FPGA se rozsvítí LED D8 |
s nápisem DONE. Při vypnutí napájení se samozřejmě obsah vnitřní |
konfigurační paměti RAM ztratí. |
</p> |
<p> |
Pro JTAG programování slouží konektor J3, který je zapojen obvyklým |
způsobem (jako například na programátoru XILINX Parallel Cable III). |
Jeho prostřednictví lze nahrát obsah do konfigurační paměti RAM obvodu |
FPGA, naprogramovat vnitřní paměť FLASH obvodu FPGA (jen obvod AN), |
nebo provádět další činnosti, které tento port umožňuje (pokud |
k tomu máte příslušné nástroje). JTAG rozhraní lze použít vždy. |
</p> |
<p> |
<img width="240" height="176" |
src="S3AN01B_HW_Reference.cs_soubory/image003.png" |
alt="JTAG programovací konektor"> |
</p> |
<p> |
Další způsoby načítání konfigurace se volí prostřednictvím signálů M0 |
M1 a M2 dle tabulky na schématu. Pro defaultní způsob konfigurace |
z interní FLASH paměti FPGA musí být zkratován signál M0 na zem |
prostřednictvím propojky mezi vývody J4.1 a J4.2. V takovém |
případě, pokud je nahraný platný obsah interní FLASH paměti obvodu FPGA |
dojde k automatické konfiguraci součástky při každém zapnutí |
napájení (konfigurace trvá řádově milisekundy). |
</p> |
<p> |
<img width="250" height="260" |
src="S3AN01B_HW_Reference.cs_soubory/image004.png" |
alt="Konfigurace (mode)"> |
<img width="258" height="230" |
src="S3AN01B_HW_Reference.cs_soubory/image005.png" |
alt="Konfigurace (SPI režim)"> |
</p> |
<p> |
Při načítání konfigurace z vnější SPI paměti FLASH je třeba podle |
použitého typu paměti nastavit propojky na konektoru J5 aby se použil |
správný příkaz pro čtení dat. Externí paměť SPI osazujeme samozřejmě |
jen jednu podle zapojení osazované paměti a velikosti jejího pouzdra. |
Tuto možnost využijeme zejména pokud osadíme obvod Spartan3A (nemá |
interní FLASH paměť) místo obvodu Spartan3AN (má interní FLASH paměť). |
</p> |
<p> |
V případě potřeby lze konfigurovat obvod FPGA i z nadřazeného |
systému, ale jen v režimu sériového přenosu (režim slave serial). |
K tomu slouží konektory J33 až J38. |
</p> |
<h3> Oscilátor </h3> |
<p> |
Jako zdroj hodinového signálu je na desce osazen obvod U4, oscilátor |
s kmitočtem 100MHz. Pokud potřebuje aplikace jiný kmitočet, lze |
osadit oscilátor s odlišným kmitočtem, nebo využít vnitřních |
programovatelných obvodů (blok DCM) pro generování potřebného kmitočtu. |
Vnitřními obvody lze generovat kmitočty odvozené od externích hodin |
v dosti širokém rozmezí. |
</p> |
<h3> Řada LED indikátorů </h3> |
<p> |
Asi první školní aplikací je blikání LED indikátory. Proto tu je |
osazeno 8 LED diod s příslušnými rezistory. Výstupy jsou dále |
vyvedeny na konektor J26. |
</p> |
<p> |
<img width="640" height="306" |
src="S3AN01B_HW_Reference.cs_soubory/image006.png" |
alt="Schéma LED indikátorů"> |
</p> |
<h3> Display LED </h3> |
<p> |
Pro sofistikovanější výpisy je zde umístěn osmimístný LED displej, |
který je zapojený v multiplexním režimu, abychom nespotřebovali |
zbytečně mnoho vývodů. |
</p> |
<p> |
<img width="714" height="368" |
src="S3AN01B_HW_Reference.cs_soubory/image007.png" |
alt="Schéma LED displeje"> |
</p> |
<h3> Vstupní tlačítka a přepínače </h3> |
<p> |
Pro jednoduché vstupy jsou na desce umístěna 4 tlačítka a jeden |
osminásobný DIP přepínač. Vstupy jsou dále opatřeny hřebínky pro další |
využití vývodů. Protože se jedná o školní desku, jsou zde osazeny |
ochranné sériové rezistory. Použití tlačítek a přepínačů předpokládá, |
že jsou vstupy nakonfigurovány s pull-down odpory. |
</p> |
<p> |
<img width="359" height="216" |
src="S3AN01B_HW_Reference.cs_soubory/image008.png" |
alt="Schéma tlačítek"> |
<img width="366" height="406" |
src="S3AN01B_HW_Reference.cs_soubory/image009.png" |
alt="Schéma DIP přepínačů"> |
</p> |
<h3> Rozhraní PS/2 a I²C </h3> |
<p> |
Deska je osazena dvěma porty PS/2 a jedním portem I²C. |
</p> |
<p> |
Rozhraní PS/2 se používá pro připojení klávesnice a/nebo myši. Obě tyto |
periferie se liší pouze protokolem. Rozhraní I²C je určeno pro |
připojení periferií pro toto rozhraní. |
</p> |
<p> |
Obě rozhraní jsou po hardwarové stránce triviální, neboť se jedná vždy |
o dva vodiče (hodiny a data) buzené výstupy s otevřeným |
kolektorem. Komunikace je obousměrná. Protože signalizační napětí |
těchto rozhraní může být větší, než je +3.3V, je zde osazen omezovací |
obvod s tranzistorem FET, který zajistí, že napětí na vstupu FPGA |
nikdy nepřekročí napájecí napětí. |
</p> |
<p> |
<img width="334" height="296" |
src="S3AN01B_HW_Reference.cs_soubory/image010.png" |
alt="Schéma ochrannýcj obvodů pro PS/2 port"> |
<img width="318" height="296" |
src="S3AN01B_HW_Reference.cs_soubory/image011.png" |
alt="Schéma ochranných obvodů pro I2C port"> |
</p> |
<h3> VGA port </h3> |
<p> |
Pro připojení VGA monitoru k desce je zde realizováno triviální |
VGA rozhraní. Využívá se jen 4 úrovní (2 bity) pro každou základní |
barvu (tedy celkem 64 barev). Převod na analogové úrovně je realizován |
pomocí rezistorové sítě. Deska je osazena standardním VGA konektorem |
DB15. |
</p> |
<p> |
<img width="348" height="516" |
src="S3AN01B_HW_Reference.cs_soubory/image012.png" |
alt="Schéma VGA portu"> |
</p> |
<h3> Diferenciální signály </h3> |
<p> |
Protože obvod FPGA řady Spartan3A/3AN podporuje diferenciální signály, |
je několik těchto signálů vyvedeno na konektor. Hledal jsem vhodný |
konektor a na konec jsem použil konektor SATA, protože jej lze snadno |
získat ze šrotu. Standardně se tyto konektory neosazují. Signály |
z těchto konektorů jsou připojeny na vývody obvodu FPGA, které |
mohou sloužit i jako hodinové vstupy. |
</p> |
<p> |
<img width="332" height="196" |
src="S3AN01B_HW_Reference.cs_soubory/image013.png" |
alt="Konektory pro diferenciální signály"> |
<img width="158" height="110" |
src="S3AN01B_HW_Reference.cs_soubory/image014.png" |
alt="Hřebínek pro diferenciální signály"> |
</p> |
<p> |
Další diferenciální signály jsou vyvedeny na hřebínek J7 k volnému |
použití. |
</p> |
<p> |
Protože jsou pro diferenciální signály využity banky 0 a 2, mohou být |
použity jako vstupní i výstupní. Banky 1 a 3 mají naproti tomu silnější |
výstupní budiče ale nepodporují diferenciální výstupy. Něco za něco. |
</p> |
<h3> 5V tolerantní vstupy </h3> |
<p> |
Protože obvod FPGA samotný (stejně jako všechny novější a rychlejší |
obvody) nesnese na svých vstupech 5V signály, použili jsme na desce |
vstupní budiče SN74LVC16244, které poskytují 2x16 vstupů. Jsou to |
obvody U11 a U12 a prvních 22 signálů je připojeno rovnou na vstupy |
FPGA (zbývajících 10 signálů je vyvedeno na hřebínky). Kdo nepotřebuje |
5V tolerantní vstupy, nemusí tyto obvody vůbec osazovat. |
</p> |
<p> |
Vstupní budiče je možné po čtveřicích (nibble) aktivovat propojkami J13 |
až J20. Zkratovací propojka povoluje příslušnou čtveřici budičů |
(otevírá třístavový výstup obvodu SN74LVC16244). |
</p> |
<p> |
<i>Použité budiče nemají na vstupu ochranné diody do |
plusu! Nesmějí se tedy budit signály většími než 5V a to ani přes velký |
sériová rezistor.</i> |
</p> |
<p> |
Aby byla definována logická úroveň na vstupu budičů, jsou na všech |
vstupech rezistory 100KΩ do země. |
</p> |
<p> |
<img width="642" height="690" |
src="S3AN01B_HW_Reference.cs_soubory/image015.png" |
alt="Schéma převodníku 5V signálů - první část"> |
</p> |
<p> |
<img width="642" height="672" |
src="S3AN01B_HW_Reference.cs_soubory/image016.png" |
alt="Schéma převodníku 5V signálů - druhá část"> |
</p> |
<h3> Analogové obvody </h3> |
<p> |
Pro pokusy s analogovými obvody je na desce osazen zesilovač |
s dolní propustí a komparátor. Lze tak realizovat jednoduchý D/A i |
A/D převodník. Viz aplikační poznámky XILINX XAPP154 a XAPP155. Nicméně |
neočekávejte zázraky, poctivý převodník tím nenhradíte. |
</p> |
<p> |
<img width="669" height="279" |
src="S3AN01B_HW_Reference.cs_soubory/image017.png" |
alt="Schéma A/D a D/A analogových obvodů"> |
</p> |
<h2> Mechanická konstrukce </h2> |
<p> |
Vývojová deska má standardní rozměry a upevňovací šrouby v rozích |
jako ostatní desky stavebnice MLAB. |
</p> |
<h1> Osazení a oživení </h1> |
<h2> Osazení </h2> |
<p> |
Pro osazování je vhodné použít mikropáječku a postupovat obezřetně |
z hlediska elektrostatického náboje. Dále je potřeba jemná pinzeta |
a další obvyklé nářadí. |
</p> |
<p> |
Při osazování je vhodné nejprve osadit obvody napájecích zdrojů U2 a U3 |
a SMD součástky okolo nich. Poté je vhodné připojit +5V na vstup a |
zkontrolovat výstupní napětí +3.3V a +1.2V dokud nemáme osazeny další |
obvody. |
</p> |
<p> |
Poté osadíme obvod FPGA U1 a obvody budičů U11 a U12. Tyto obvody |
osazujeme s velkou pečlivostí, protože mají hodně vývodů |
s malou roztečí. Používáme minimální množství pájky a vhodné |
pastovité tavidlo. Obvod vždy nejprve připájíme za 2 protilehlé nožičky |
a teprve poté, co se ujistíme, že jsou obvody umístěny na všech |
stranách správně postupně zapájíme všechny vývody. Po osazení |
zkontrolujeme pod lupou kvalitu pájení a zda nejsou zkraty mezi vývody. |
</p> |
<p> |
Pak osadíme zbývající SMD součástky podle schématu a osazovacího plánu. |
Pak následují klasické součástky. Začínáme LED displejem, všemi |
hřebínky a nakonec konektory pro PS/2 a VGA port. |
</p> |
<p> |
Na závěr desku opticky zkontrolujeme (orientace součástek, zkraty, |
zapomenuté spoje a podobně) a přišroubujeme rohové šrouby se sloupky. |
Poslední operací je umytí zbytků tavidla, vysušení a finální optická |
kontrola. |
</p> |
<h3> Osazovací plán, horní strana </h3> |
<p> |
<img width="676" height="737" |
src="S3AN01B_HW_Reference.cs_soubory/image018.jpg" |
alt="Osazení - strana součástek"> |
</p> |
<h3> Osazovací plán, spodní strana </h3> |
<p> |
<img width="677" height="737" |
src="S3AN01B_HW_Reference.cs_soubory/image019.jpg" |
alt="Osazení - strana spojů"> |
</p> |
<h3> Seznam součástek </h3> |
<table class="Soupiska"> |
<tr> |
<th> Počet </th> |
<th> Reference </th> |
<th> Hodnota </th> |
<th> Pouzdro </th> |
<th> Poznámka </th> |
</tr> |
<tr> |
<th colspan="5"> Rezistory </th> |
</tr> |
<tr> |
<td> 1 </td> |
<td> R28 </td> |
<td> 0R </td> |
<td> </td> |
<td> </td> |
</tr> |
<tr> |
<td> 20 </td> |
<td> R1-R10, R66, R67, R81-R88 </td> |
<td> 100 </td> |
<td> R0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 3 </td> |
<td> R59, R62, R65 </td> |
<td> 120 </td> |
<td> R0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 3 </td> |
<td> R58, R61, R64 </td> |
<td> 270 </td> |
<td> R0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 22 </td> |
<td> R12, R14, R29, R30-R40, R49-R56 </td> |
<td> 390 </td> |
<td> R0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 3 </td> |
<td> R57, R60, R63 </td> |
<td> 510 </td> |
<td> R0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 9 </td> |
<td> R11, R41-R48 </td> |
<td> 820 </td> |
<td> R0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> R80 </td> |
<td> 1k2 </td> |
<td> R0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 4 </td> |
<td> R16, R17, R18, R19 </td> |
<td> 3k3 </td> |
<td> R0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 21 </td> |
<td> R13, R15, R20-R27, R68, R70, R72-R79, R89 </td> |
<td> 4k7 </td> |
<td> R0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 2 </td> |
<td> R69, R71 </td> |
<td> #4k7 </td> |
<td> R0805 </td> |
<td> Neosazuje se </td> |
</tr> |
<tr> |
<td> 32 </td> |
<td> R100-R131 </td> |
<td> 100k </td> |
<td> R0603 </td> |
<td> </td> |
</tr> |
<tr> |
<th colspan="5"> Kondenzátory keramické </th> |
</tr> |
<tr> |
<td> 3 </td> |
<td> C20-C22 </td> |
<td> 4n7 </td> |
<td> C0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> C34 </td> |
<td> 10nF </td> |
<td> C0805 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 27 </td> |
<td> C4-C19, C23-C33 </td> |
<td> 100nF </td> |
<td> C0805 </td> |
<td> </td> |
</tr> |
<tr> |
<th colspan="5"> Kondenzátory tantalové </th> |
</tr> |
<tr> |
<td> 3 </td> |
<td> C1, C2, C3 </td> |
<td> 22uF/6.3V </td> |
<td> ELYTB </td> |
<td> </td> |
</tr> |
<tr> |
<th colspan="5"> Diody </th> |
</tr> |
<tr> |
<td> 1 </td> |
<td> D9 </td> |
<td> 1N5820 </td> |
<td> DO201 </td> |
<td> </td> |
</tr> |
<tr> |
<th colspan="5"> Diody LED a displeje LED </th> |
</tr> |
<tr> |
<td> 10 </td> |
<td> D0-D8, D10 </td> |
<td> LED3mm_RED </td> |
<td> LED3 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 2 </td> |
<td> LD0, LD1 </td> |
<td> FT-M514RD </td> |
<td> 4LED7_12PIN_14_2 </td> |
<td> </td> |
</tr> |
<tr> |
<th colspan="5"> Tranzistory </th> |
</tr> |
<tr> |
<td> 8 </td> |
<td> Q0-Q7 </td> |
<td> BC856 </td> |
<td> SOT23 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 6 </td> |
<td> Q8-Q13 </td> |
<td> BS170SMD </td> |
<td> SOT23 </td> |
<td> </td> |
</tr> |
<tr> |
<th colspan="5"> Integrované obvody </th> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U1 </td> |
<td> XC3S50AN-4TQG144C </td> |
<td> TQFP144 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U2 </td> |
<td> AP1086K33G-13 </td> |
<td> TO263 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U3 </td> |
<td> TS1117BCP12R0 </td> |
<td> TO252 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U4 </td> |
<td> CFPS-73-100M </td> |
<td> SG8002 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U5 </td> |
<td> AT45DB011D-SSH-B </td> |
<td> SO8_150 </td> |
<td> Volitelné </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U6 </td> |
<td> AT45DB011D-SH-B </td> |
<td> SO8_210 </td> |
<td> Volitelné </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U7 </td> |
<td> AT25DF0xxA-SSH </td> |
<td> SO8_150 </td> |
<td> Volitelné </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U8 </td> |
<td> SST24LF040A-33-4C-S2AE </td> |
<td> SO8_210 </td> |
<td> Volitelné </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U9 </td> |
<td> MCP6001T-I/OT </td> |
<td> SOT23-5 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> U10 </td> |
<td> MCP6546T-E/OT </td> |
<td> SOT23-5 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 2 </td> |
<td> U11, U12 </td> |
<td> SN74LVC16244ADL </td> |
<td> SSOIII_48_300 </td> |
<td> </td> |
</tr> |
<tr> |
<th colspan="5"> Mechanické součástky </th> |
</tr> |
<tr> |
<td> 4 </td> |
<td> SW0-SW3 </td> |
<td> PUSH050x050 </td> |
<td> PUSH050x050 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> SW4 </td> |
<td> DIPSW8 </td> |
<td> DIPSW8 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 12 </td> |
<td> Propojka </td> |
<td> </td> |
<td> </td> |
<td> </td> |
</tr> |
<tr> |
<th colspan="5"> Konektory </th> |
</tr> |
<tr> |
<td> 1 </td> |
<td> J27 </td> |
<td> DB15F_3L_90 </td> |
<td> DB15F_3L_90 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 2 </td> |
<td> J31, J32 </td> |
<td> MINIDIN6_PS2 </td> |
<td> MINIDIN6 </td> |
<td> </td> |
</tr> |
<tr> |
<td> 2 </td> |
<td> J28, J29 </td> |
<td> #SATA_DATA </td> |
<td> SATA_DATA </td> |
<td> Neosazuje se </td> |
</tr> |
<tr> |
<th colspan="5"> Jednořadé hřebínky </th> |
</tr> |
<tr> |
<td> 1 </td> |
<td> J33+J34+J35+J36+J37+J38 </td> |
<td> JUMP9 </td> |
<td> JUMP9 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> J22 </td> |
<td> #JUMP1 </td> |
<td> JUMP1 </td> |
<td> Neosazuje se </td> |
</tr> |
<tr> |
<td> 9 </td> |
<td> J6, J13, J14, J15, J16, J17, J18, J19, J20 </td> |
<td> JUMP2 </td> |
<td> JUMP2 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> J30 </td> |
<td> JUMP4 </td> |
<td> JUMP4 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 3 </td> |
<td> J12, J21, J100 </td> |
<td> JUMP10 </td> |
<td> JUMP10 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> J10 </td> |
<td> JUMP22 </td> |
<td> JUMP22 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> J3 </td> |
<td> JUMP9_X3_X5_X8</td> |
<td> JUMP9_X3_X5_X8</td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<th colspan="5"> Douřadé hřebínky </th> |
</tr> |
<tr> |
<td> 1 </td> |
<td> J24 </td> |
<td> JUMP2X2 </td> |
<td> JUMP2X2 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 5 </td> |
<td> J1, J2, J4, J5, J8 </td> |
<td> JUMP2X3 </td> |
<td> JUMP2X3 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> J7 </td> |
<td> JUMP2X4 </td> |
<td> JUMP2X4 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 2 </td> |
<td> J25, J26 </td> |
<td> JUMP2X8 </td> |
<td> JUMP2X8 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 1 </td> |
<td> J11 </td> |
<td> JUMP2X10 </td> |
<td> JUMP2X10 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<td> 2 </td> |
<td> J9, J23 </td> |
<td> JUMP2X22 </td> |
<td> JUMP2X22 </td> |
<td> Nalámat </td> |
</tr> |
<tr> |
<th colspan="5"> Konstrukční součástky </th> |
</tr> |
<tr> |
<td> 1 </td> |
<td> Plošný spoj </td> |
<td> PCB S3AN01B </td> |
<td> </td> |
<td> </td> |
</tr> |
<tr> |
<td> 4 </td> |
<td> Šroub M3x12mm křížový, válcová hlava, pozinkovaný </td> |
<td> </td> |
<td> </td> |
<td> </td> |
</tr> |
<tr> |
<td> 4 </td> |
<td> Matice M3, pozinkovaná </td> |
<td> /td> |
<td> </td> |
<td> </td> |
</tr> |
<tr> |
<td> 4 </td> |
<td> Podložka M3, pozinkovaná </td> |
<td> </td> |
<td> </td> |
<td> </td> |
</tr> |
</table> |
<h2> Oživení </h2> |
<h3> První zapnutí </h3> |
<p> |
Prvním krokem je připojení k laboratornímu zdroji a kontrola |
funkčnosti napájecích zdrojů. Postupně zvyšujeme napájecí napětí až |
k hranici +5V a měříme spotřebu (orientačně) a napětí na vnitřních |
stabilizátorech U2 a U3. Vnitřní napájecí napětí jsou +3.3V a +1.2V |
(mohou se lišit řekněme o desítky milivoltů). Spotřeba desky bez |
nahrané konfigurace je cca 50-60mA. |
</p> |
<p> |
Nyní je třeba ověřit, zda pracují ochranné obvody na PS/2 portech. |
Měříme napětí na Q10.D, které má být cca +5V a Q10.S, které má být o |
něco menší, než +3.3V. Toto měření opakujeme pro všechny 4 tranzistory, |
tedy pro Q10 až Q13. |
</p> |
<p> |
Podobně zkontrolujeme i ochranné obvody I²C portu. Jen je třeba |
z vnějšku připojit +4V na hřebínek J30.2 a J30.3 a měřit na |
tranzistorech Q8 a Q9. Opět se nesmí směrem k FPGA dostávat napětí |
větší, než je napájení +3.3V. |
</p> |
<h3> Testovací obsah </h3> |
<p> |
Protože samotný obvod FPGA bez nahrané konfigurace je „mrtvým broukem“ |
je pro další oživování a testování potřeba použít nějaký vhodný obsah, |
aby bylo možno otestovat celou funkčnost desky. Testování desky je |
popsáno v dokumentu S3AN01B_HW_Test. |
</p> |
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0,0 → 1,8320 |
+%âãÏÓ |
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