/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/!____!.txt |
---|
0,0 → 1,20 |
CoreGenerator Project Files |
--------------------------- |
Software: ISE 14.5 (WebPack) |
Device: Spartan3AN XC3S50AN-4TQG144C |
Input (source) Files |
-------------------- |
S3AN01_ChipScopeILA.cgp - Core Generator Project File (used by GUI CoreGen) |
ChipScope_ICON.xco - ChipScope Config Block Configuration File |
ChipScope_ILA_18_1024.xco - ChipScope Integrated Logic Analyser Configuration File 18 bits 1024 smaples |
ChipScope_ILA_9_2048.xco - ChipScope Integrated Logic Analyser Configuration File 9 bits 2048 smaples |
ChipScope_VIO_FreqSel.xco - ChipScope Virtul IO Configuration File (used for Frequency Selection) |
ChipScope_VIO_UserOut.xco - ChipScope Virtul IO Configuration File (used for User Output) |
All other files may be deleted. Open .cgp file in CoreGenerator and let it regenerate |
all cores. |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ICON.xco |
---|
0,0 → 1,56 |
############################################################## |
# |
# Xilinx Core Generator version 14.5 |
# Date: Thu Jun 20 12:54:35 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = true |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = VHDL |
SET device = xc3s50an |
SET devicefamily = spartan3a |
SET flowvendor = Other |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = tqg144 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -4 |
SET verilogsim = false |
SET vhdlsim = true |
# END Project Options |
# BEGIN Select |
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a |
# END Select |
# BEGIN Parameters |
CSET component_name=ChipScope_ICON |
CSET constraint_type=external |
CSET enable_jtag_bufg=true |
CSET example_design=false |
CSET number_control_ports=3 |
CSET use_ext_bscan=false |
CSET use_softbscan=false |
CSET use_unused_bscan=false |
CSET user_scan_chain=USER1 |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2013-03-26T22:44:10Z |
# END Extra information |
GENERATE |
# CRC: 1a9afcd1 |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_18_1024.xco |
---|
0,0 → 1,141 |
############################################################## |
# |
# Xilinx Core Generator version 14.5 |
# Date: Thu Jun 20 12:43:44 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = true |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = VHDL |
SET device = xc3s50an |
SET devicefamily = spartan3a |
SET flowvendor = Other |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = tqg144 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -4 |
SET verilogsim = false |
SET vhdlsim = true |
# END Project Options |
# BEGIN Select |
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a |
# END Select |
# BEGIN Parameters |
CSET check_bramcount=false |
CSET component_name=ChipScope_ILA_18_1024 |
CSET constraint_type=external |
CSET counter_width_1=4 |
CSET counter_width_10=Disabled |
CSET counter_width_11=Disabled |
CSET counter_width_12=Disabled |
CSET counter_width_13=Disabled |
CSET counter_width_14=Disabled |
CSET counter_width_15=Disabled |
CSET counter_width_16=Disabled |
CSET counter_width_2=Disabled |
CSET counter_width_3=Disabled |
CSET counter_width_4=Disabled |
CSET counter_width_5=Disabled |
CSET counter_width_6=Disabled |
CSET counter_width_7=Disabled |
CSET counter_width_8=Disabled |
CSET counter_width_9=Disabled |
CSET data_port_width=18 |
CSET data_same_as_trigger=false |
CSET disable_save_keep=false |
CSET enable_storage_qualification=true |
CSET enable_trigger_output_port=true |
CSET example_design=false |
CSET exclude_from_data_storage_1=true |
CSET exclude_from_data_storage_10=true |
CSET exclude_from_data_storage_11=true |
CSET exclude_from_data_storage_12=true |
CSET exclude_from_data_storage_13=true |
CSET exclude_from_data_storage_14=true |
CSET exclude_from_data_storage_15=true |
CSET exclude_from_data_storage_16=true |
CSET exclude_from_data_storage_2=true |
CSET exclude_from_data_storage_3=true |
CSET exclude_from_data_storage_4=true |
CSET exclude_from_data_storage_5=true |
CSET exclude_from_data_storage_6=true |
CSET exclude_from_data_storage_7=true |
CSET exclude_from_data_storage_8=true |
CSET exclude_from_data_storage_9=true |
CSET match_type_1=basic_with_edges |
CSET match_type_10=basic_with_edges |
CSET match_type_11=basic_with_edges |
CSET match_type_12=basic_with_edges |
CSET match_type_13=basic_with_edges |
CSET match_type_14=basic_with_edges |
CSET match_type_15=basic_with_edges |
CSET match_type_16=basic_with_edges |
CSET match_type_2=basic_with_edges |
CSET match_type_3=basic_with_edges |
CSET match_type_4=basic_with_edges |
CSET match_type_5=basic_with_edges |
CSET match_type_6=basic_with_edges |
CSET match_type_7=basic_with_edges |
CSET match_type_8=basic_with_edges |
CSET match_type_9=basic_with_edges |
CSET match_units_1=3 |
CSET match_units_10=1 |
CSET match_units_11=1 |
CSET match_units_12=1 |
CSET match_units_13=1 |
CSET match_units_14=1 |
CSET match_units_15=1 |
CSET match_units_16=1 |
CSET match_units_2=1 |
CSET match_units_3=1 |
CSET match_units_4=1 |
CSET match_units_5=1 |
CSET match_units_6=1 |
CSET match_units_7=1 |
CSET match_units_8=1 |
CSET match_units_9=1 |
CSET max_sequence_levels=16 |
CSET number_of_trigger_ports=1 |
CSET sample_data_depth=1024 |
CSET sample_on=Rising |
CSET trigger_port_width_1=24 |
CSET trigger_port_width_10=8 |
CSET trigger_port_width_11=8 |
CSET trigger_port_width_12=8 |
CSET trigger_port_width_13=8 |
CSET trigger_port_width_14=8 |
CSET trigger_port_width_15=8 |
CSET trigger_port_width_16=8 |
CSET trigger_port_width_2=8 |
CSET trigger_port_width_3=8 |
CSET trigger_port_width_4=8 |
CSET trigger_port_width_5=8 |
CSET trigger_port_width_6=8 |
CSET trigger_port_width_7=8 |
CSET trigger_port_width_8=8 |
CSET trigger_port_width_9=8 |
CSET use_rpms=true |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2013-03-26T22:44:34Z |
# END Extra information |
GENERATE |
# CRC: ab76e1ca |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_9_2048.xco |
---|
0,0 → 1,141 |
############################################################## |
# |
# Xilinx Core Generator version 14.5 |
# Date: Thu Jun 20 13:35:12 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = true |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = VHDL |
SET device = xc3s50an |
SET devicefamily = spartan3a |
SET flowvendor = Other |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = tqg144 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -4 |
SET verilogsim = false |
SET vhdlsim = true |
# END Project Options |
# BEGIN Select |
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a |
# END Select |
# BEGIN Parameters |
CSET check_bramcount=false |
CSET component_name=ChipScope_ILA_9_2048 |
CSET constraint_type=external |
CSET counter_width_1=4 |
CSET counter_width_10=Disabled |
CSET counter_width_11=Disabled |
CSET counter_width_12=Disabled |
CSET counter_width_13=Disabled |
CSET counter_width_14=Disabled |
CSET counter_width_15=Disabled |
CSET counter_width_16=Disabled |
CSET counter_width_2=Disabled |
CSET counter_width_3=Disabled |
CSET counter_width_4=Disabled |
CSET counter_width_5=Disabled |
CSET counter_width_6=Disabled |
CSET counter_width_7=Disabled |
CSET counter_width_8=Disabled |
CSET counter_width_9=Disabled |
CSET data_port_width=9 |
CSET data_same_as_trigger=false |
CSET disable_save_keep=false |
CSET enable_storage_qualification=true |
CSET enable_trigger_output_port=true |
CSET example_design=false |
CSET exclude_from_data_storage_1=true |
CSET exclude_from_data_storage_10=true |
CSET exclude_from_data_storage_11=true |
CSET exclude_from_data_storage_12=true |
CSET exclude_from_data_storage_13=true |
CSET exclude_from_data_storage_14=true |
CSET exclude_from_data_storage_15=true |
CSET exclude_from_data_storage_16=true |
CSET exclude_from_data_storage_2=true |
CSET exclude_from_data_storage_3=true |
CSET exclude_from_data_storage_4=true |
CSET exclude_from_data_storage_5=true |
CSET exclude_from_data_storage_6=true |
CSET exclude_from_data_storage_7=true |
CSET exclude_from_data_storage_8=true |
CSET exclude_from_data_storage_9=true |
CSET match_type_1=basic_with_edges |
CSET match_type_10=basic_with_edges |
CSET match_type_11=basic_with_edges |
CSET match_type_12=basic_with_edges |
CSET match_type_13=basic_with_edges |
CSET match_type_14=basic_with_edges |
CSET match_type_15=basic_with_edges |
CSET match_type_16=basic_with_edges |
CSET match_type_2=basic_with_edges |
CSET match_type_3=basic_with_edges |
CSET match_type_4=basic_with_edges |
CSET match_type_5=basic_with_edges |
CSET match_type_6=basic_with_edges |
CSET match_type_7=basic_with_edges |
CSET match_type_8=basic_with_edges |
CSET match_type_9=basic_with_edges |
CSET match_units_1=3 |
CSET match_units_10=1 |
CSET match_units_11=1 |
CSET match_units_12=1 |
CSET match_units_13=1 |
CSET match_units_14=1 |
CSET match_units_15=1 |
CSET match_units_16=1 |
CSET match_units_2=1 |
CSET match_units_3=1 |
CSET match_units_4=1 |
CSET match_units_5=1 |
CSET match_units_6=1 |
CSET match_units_7=1 |
CSET match_units_8=1 |
CSET match_units_9=1 |
CSET max_sequence_levels=16 |
CSET number_of_trigger_ports=1 |
CSET sample_data_depth=2048 |
CSET sample_on=Rising |
CSET trigger_port_width_1=24 |
CSET trigger_port_width_10=8 |
CSET trigger_port_width_11=8 |
CSET trigger_port_width_12=8 |
CSET trigger_port_width_13=8 |
CSET trigger_port_width_14=8 |
CSET trigger_port_width_15=8 |
CSET trigger_port_width_16=8 |
CSET trigger_port_width_2=8 |
CSET trigger_port_width_3=8 |
CSET trigger_port_width_4=8 |
CSET trigger_port_width_5=8 |
CSET trigger_port_width_6=8 |
CSET trigger_port_width_7=8 |
CSET trigger_port_width_8=8 |
CSET trigger_port_width_9=8 |
CSET use_rpms=true |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2013-03-26T22:44:34Z |
# END Extra information |
GENERATE |
# CRC: 100acb04 |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_FreqSel.xco |
---|
0,0 → 1,59 |
############################################################## |
# |
# Xilinx Core Generator version 14.5 |
# Date: Thu Jun 20 12:56:15 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = true |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = VHDL |
SET device = xc3s50an |
SET devicefamily = spartan3a |
SET flowvendor = Other |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = tqg144 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -4 |
SET verilogsim = false |
SET vhdlsim = true |
# END Project Options |
# BEGIN Select |
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a |
# END Select |
# BEGIN Parameters |
CSET asynchronous_input_port_width=8 |
CSET asynchronous_output_port_width=8 |
CSET component_name=ChipScope_VIO_FreqSel |
CSET constraint_type=external |
CSET enable_asynchronous_input_port=false |
CSET enable_asynchronous_output_port=false |
CSET enable_synchronous_input_port=true |
CSET enable_synchronous_output_port=true |
CSET example_design=false |
CSET invert_clock_input=false |
CSET synchronous_input_port_width=8 |
CSET synchronous_output_port_width=8 |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2013-03-26T22:44:59Z |
# END Extra information |
GENERATE |
# CRC: c6d481e1 |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_UserOut.xco |
---|
0,0 → 1,59 |
############################################################## |
# |
# Xilinx Core Generator version 14.5 |
# Date: Thu Jun 20 12:55:33 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = true |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = VHDL |
SET device = xc3s50an |
SET devicefamily = spartan3a |
SET flowvendor = Other |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = tqg144 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -4 |
SET verilogsim = false |
SET vhdlsim = true |
# END Project Options |
# BEGIN Select |
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a |
# END Select |
# BEGIN Parameters |
CSET asynchronous_input_port_width=8 |
CSET asynchronous_output_port_width=8 |
CSET component_name=ChipScope_VIO_UserOut |
CSET constraint_type=external |
CSET enable_asynchronous_input_port=false |
CSET enable_asynchronous_output_port=false |
CSET enable_synchronous_input_port=false |
CSET enable_synchronous_output_port=true |
CSET example_design=false |
CSET invert_clock_input=false |
CSET synchronous_input_port_width=8 |
CSET synchronous_output_port_width=3 |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2013-03-26T22:44:59Z |
# END Extra information |
GENERATE |
# CRC: 738ddf25 |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/coregen.cgp |
---|
0,0 → 1,9 |
SET busformat = BusFormatAngleBracketNotRipped |
SET designentry = VHDL |
SET device = xc3s50an |
SET devicefamily = spartan3a |
SET flowvendor = Other |
SET package = tqg144 |
SET speedgrade = -4 |
SET verilogsim = false |
SET vhdlsim = true |