0,0 → 1,56 |
############################################################## |
# |
# Xilinx Core Generator version 14.5 |
# Date: Thu Jun 20 12:54:35 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = true |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = VHDL |
SET device = xc3s50an |
SET devicefamily = spartan3a |
SET flowvendor = Other |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = tqg144 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -4 |
SET verilogsim = false |
SET vhdlsim = true |
# END Project Options |
# BEGIN Select |
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a |
# END Select |
# BEGIN Parameters |
CSET component_name=ChipScope_ICON |
CSET constraint_type=external |
CSET enable_jtag_bufg=true |
CSET example_design=false |
CSET number_control_ports=3 |
CSET use_ext_bscan=false |
CSET use_softbscan=false |
CSET use_unused_bscan=false |
CSET user_scan_chain=USER1 |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2013-03-26T22:44:10Z |
# END Extra information |
GENERATE |
# CRC: 1a9afcd1 |