0,0 → 1,59 |
############################################################## |
# |
# Xilinx Core Generator version 14.5 |
# Date: Thu Jun 20 12:55:33 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = true |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = VHDL |
SET device = xc3s50an |
SET devicefamily = spartan3a |
SET flowvendor = Other |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = tqg144 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -4 |
SET verilogsim = false |
SET vhdlsim = true |
# END Project Options |
# BEGIN Select |
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a |
# END Select |
# BEGIN Parameters |
CSET asynchronous_input_port_width=8 |
CSET asynchronous_output_port_width=8 |
CSET component_name=ChipScope_VIO_UserOut |
CSET constraint_type=external |
CSET enable_asynchronous_input_port=false |
CSET enable_asynchronous_output_port=false |
CSET enable_synchronous_input_port=false |
CSET enable_synchronous_output_port=true |
CSET example_design=false |
CSET invert_clock_input=false |
CSET synchronous_input_port_width=8 |
CSET synchronous_output_port_width=3 |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2013-03-26T22:44:59Z |
# END Extra information |
GENERATE |
# CRC: 738ddf25 |