| /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/coregen.cgp |
|---|
| 0,0 → 1,9 |
| SET busformat = BusFormatAngleBracketNotRipped |
| SET designentry = VHDL |
| SET device = xc3s50an |
| SET devicefamily = spartan3a |
| SET flowvendor = Other |
| SET package = tqg144 |
| SET speedgrade = -4 |
| SET verilogsim = false |
| SET vhdlsim = true |