/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/FindXilinxTools.cmd |
---|
0,0 → 1,40 |
@echo off |
rem Finds installation of Xilinx tools and makes necessary env settings |
rem ----- Set 32/64 bit |
if Defined PROCESSOR_ARCHITEW6432 ( |
Set ProcArch=%PROCESSOR_ARCHITEW6432% |
) else ( |
Set ProcArch=%PROCESSOR_ARCHITECTURE% |
) |
if "%ProcArch%" == "AMD64" Set ProcArch=x64 |
rem echo %ProcArch% |
if "%ProcArch%" == "x64" ( |
set fileXilinxSet=settings64.bat |
) else ( |
set fileXilinxSet=settings32.bat |
) |
rem ----- Find Xilinx directory |
echo Find Xilinx Tools |
for %%i in (C:\SW32\Xilinx C:\Xilinx) do ( |
rem Take the last directory |
for /F %%j in ('dir %%i\*.* /AD /B /O-N') do ( |
for %%k in (%%i\%%j\ISE_DS) do ( |
rem echo %%j\%fileXilinxSet% |
if exist %%k\%fileXilinxSet% ( |
echo Found at %%k\%fileXilinxSet% |
call %%k\%fileXilinxSet% |
set XILINX_VERSION=%%j |
if not "%1"=="" ( |
rem Call script |
call %1 |
) else ( |
rem Just set env |
goto Label1 |
) |
) |
) |
) |
) |
:Label1 |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_CoreGen.cmd |
---|
0,0 → 1,81 |
@echo off |
rem Batch to (re)generate IP cores (ChipScope components) |
rem Run once, takes several minutes to finish. |
rem |
rem Do not modify source files directory structure |
rem |
rem Tested with Xilinx ISE WebPack 13.3 and 14.5 |
rem This step does not require ChipScope License |
rem |
rem ----- Find and Set Xilinx Tools |
call FindXilinxTools.cmd |
rem ----- Run Coregen in paralel (we all have multicore cpu don't we?) |
rem Unfortunately CoreGen can't be run in parallel. |
rem There is some conflict (You cenrtainly know what all that cores are good for...) |
rem start "CoreGen ICON" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r |
rem start "CoreGen ILA 18x1024" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r |
rem start "CoreGen ILA 9x2048" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r |
rem start "CoreGen VIO FreqSel" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r |
rem start "CoreGen VIO UserOut" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r |
rem ----- Run CoreGen one after one for all components |
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in coregen ChipScope_ICON |
echo =============================== |
pause |
exit 1 |
) |
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in coregen ChipScope_ILA_18_1024 |
echo ====================================== |
pause |
exit 1 |
) |
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in coregen ChipScope_ILA_9_2048 |
echo ===================================== |
pause |
exit 1 |
) |
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in coregen ChipScope_VIO_FreqSel |
echo ====================================== |
pause |
exit 1 |
) |
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in coregen ChipScope_VIO_UserOut |
echo ====================================== |
pause |
exit 1 |
) |
rem ----- Finished |
rm coregen.log |
echo. |
echo CoreGen Finished with no Errors |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_S3AN01_ChipScope.cmd |
---|
0,0 → 1,179 |
@echo off |
rem Batch generates bitfile for Logic Analyser Demo |
rem |
rem Parameters: |
rem |
rem 18x1024|9x2048 ... select analyser size (width and depth) |
rem |
rem Do not modify srouce files directory structure |
rem |
rem Tested with Xilinx ISE WebPack 14.5 with ChipScope License |
rem |
rem ----- first parameter |
set product=%1% |
if "%product%"=="18x1024" ( |
echo 18x1024 |
) else if "%product%" == "9x2048" ( |
echo 9x2048 |
) else ( |
echo Missing parameter %product% |
echo usage: %0% 18x1024^|9x2048 |
pause |
exit 1 |
) |
echo. |
echo Product: %product% |
echo. |
rem ----- Set core (top VHDL entity) name |
set core=S3AN01_ChipScope |
rem ----- Set FPGA part |
set fpgaPart=xc3s50an-tqg144-4 |
rem ----- Find and Set Xilinx Tools |
call FindXilinxTools.cmd |
rem ----- Set WORK dir |
if exist WORK_%core%_%product% rmdir /S /Q WORK_%core%_%product% |
mkdir WORK_%core%_%product% |
cd WORK_%core%_%product% |
rem ----- Set TEMP dir (relative to WORK dir) |
mkdir TMP |
set TMP=TMP |
rem ----- INPUT UCF and VHDL files (linux format c:/.../... ) |
set srcPath=../.. |
set ucfFile=VHDL/S3AN01_ChipScope.ucf |
echo vhdl work "%srcPath%/COREGEN/ChipScope_ICON.vhd" > srcFiles.prj |
echo vhdl work "%srcPath%/COREGEN/ChipScope_VIO_FreqSel.vhd" >>srcFiles.prj |
echo vhdl work "%srcPath%/COREGEN/ChipScope_ILA_9_2048.vhd" >>srcFiles.prj |
echo vhdl work "%srcPath%/VHDL/S3AN01_ChipScope.vhd" >>srcFiles.prj |
rem ----- SET XST setting |
echo set -xsthdpdir "xst" > setXst.xst |
echo run >>setXst.xst |
echo -ifn "srcFiles.prj" >>setXst.xst |
echo -ofn %core% >>setXst.xst |
echo -ofmt NGC >>setXst.xst |
echo -top %core% >>setXst.xst |
echo -iob True >>setXst.xst |
echo -p %fpgaPart% >>setXst.xst |
if "%product%"=="18x1024" ( |
echo -generics { ILA_WIDE=TRUE } >>setXst.xst |
) else ( |
echo -generics { ILA_WIDE=FALSE } >>setXst.xst |
) |
rem ----- SET BITGEN setting |
echo -w > setBitGen.ut |
echo -g ConfigRate:25 >>setBitGen.ut |
echo -g UnusedPin:PullUp >>setBitGen.ut |
echo -g DriveDone:Yes >>setBitGen.ut |
call xst -ifn "setXst.xst" -ofn "%core%.log" |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in xst |
echo ============ |
pause |
exit 1 |
) |
call ngdbuild -intstyle ise -dd _ngo -sd ../../COREGEN -nt timestamp -uc "%srcPath%/%ucfFile%" -p %fpgaPart% %core%.ngc %core%.ngd |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in ngdbuild |
echo ================= |
pause |
exit 1 |
) |
call map -intstyle ise -p %fpgaPart% -cm area -ir off -pr off -c 100 -o %core%.ncd %core%.ngd %core%.pcf |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in map |
echo ============ |
pause |
exit 1 |
) |
call par -w -intstyle ise -ol high -t 1 %core%.ncd %core%.ncd %core%.pcf |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in par |
echo ============ |
pause |
exit 1 |
) |
call trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml %core%.twx %core%.ncd -o %core%.twr %core%.pcf |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in trace |
echo ============== |
pause |
exit 1 |
) |
call bitgen -f "setBitGen.ut" %core%.ncd |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in bidgen |
echo =============== |
pause |
exit 1 |
) |
rem ----- Verify Timing |
findstr /B /C:"All constraints were met." %core%.par |
if %errorlevel% NEQ 0 ( |
echo. |
echo. |
echo ERROR in Timing |
echo =============== |
pause |
exit 1 |
) |
if exist ..\BIN\%XILINX_VERSION% ( |
rem ----- Copy result to BIN\{ISE_VER} directory |
copy /Y %core%.bit ..\BIN\%XILINX_VERSION%\%core%_%product%.bit |
rem copy /Y %core%.par ..\BIN\%XILINX_VERSION%\%core%_%product%.par |
rem ----- Remove WORK dir |
rem (bitgen starts wbtc.exe as a secondary process) |
cd .. |
rem Wait for xwebtalk has finished its work (sending stat data to Xilinx) |
echo | set /p=Waiting for WebTalk... |
:StartLoop |
tasklist | findstr /i /c:"wbtc.exe" > nul |
if %errorlevel% NEQ 0 ( |
goto ExitLoop |
) |
sleep 1 |
echo | set /p=* |
goto StartLoop |
) |
:ExitLoop |
rem Tohle nefunguje, protoe výstup wmic je UTF-16 a to finstr neumí |
rem wmic process | findstr /c:"%core%_%product%" |
rem wmic process > ..\"%core%_%product%".wmic |
rmdir /S /Q WORK_%core%_%product% |
exit 0 |
) |
exit 1 |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_all.cmd |
---|
0,0 → 1,53 |
@echo off |
rem Batch to generate bitstream |
rem |
rem S3AN01_ChipScope_18x1024.bit |
rem S3AN01_ChipScope_9x2048.bit |
rem |
rem Do not modify srouce files directory structure |
rem |
rem Tested with Xilinx ISE WebPack 14.5 with ChipScope License |
rem |
rem ----- Check if ChipScope IP Cores are ready |
if not exist ..\COREGEN\ChipScope_ICON.vhd goto coregen |
if not exist ..\COREGEN\ChipScope_ILA_18_1024.vhd goto coregen |
if not exist ..\COREGEN\ChipScope_ILA_9_2048.vhd goto coregen |
if not exist ..\COREGEN\ChipScope_VIO_FreqSel.vhd goto coregen |
if not exist ..\COREGEN\ChipScope_VIO_UserOut.vhd goto coregen |
goto next |
:coregen |
rem ----- Regenerate ChipScope IP Cores |
echo. |
echo Missing ChipScope IP Core output files |
echo Regenerating will take a long time (5 minutes on i5-3770) |
echo. |
pause |
call make_CoreGen.cmd |
:next |
rem ----- Clear target directory |
rmdir /S /Q BIN 2> nul |
mkdir BIN |
rem ----- Get Current date and time |
for /F "Tokens=2-4 Delims=. " %%A in ("%DATE%") do ( |
set CurDate=%%C_%%B_%%A |
) |
for /F "Tokens=1-2 Delims=:,. " %%D in ("%TIME: =0%") do ( |
set CurTime=%%D_%%E |
) |
rem ----- Find and Set Xilinx Tools |
call FindXilinxTools.cmd |
mkdir BIN\%XILINX_VERSION% |
rem ----- Create Version metafile |
echo TimeStamp: %CurDate%__%CurTime%> BIN\%XILINX_VERSION%\Version |
echo ComputerName: %COMPUTERNAME%>> BIN\%XILINX_VERSION%\Version |
echo ISE Version: %XILINX_VERSION%>> BIN\%XILINX_VERSION%\Version |
echo ReleaseInfo: None>> BIN\%XILINX_VERSION%\Version |
rem ----- Compile variants (paralel run) |
start "compile S3AN01_ChipScope_18x1024" make_S3AN01_ChipScope.cmd 18x1024 |
start "compile S3AN01_ChipScope_9x2048" make_S3AN01_ChipScope.cmd 9x2048 |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_18_1024.cmd |
---|
0,0 → 1,24 |
@echo off |
rem |
rem Script for starting Analyser.exe with predefined settings. |
rem The script starts mlab_xvcd.exe deamon for users who use |
rem Xilinx Virtual Cable and FTDI JTAG cable. Those users |
rem should select in ChipScope Analyser setting |
rem JTAG Chain / Open Plug-in. |
rem |
rem ----- Run Xilinx Virtual Cable Daemon (as separate process) |
rem Run it if you use XVC cable connected to the local computer |
rem To start the daemon if already runnig does no harm |
if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe ( |
start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe |
) |
rem ----- Find and Set Xilinx Tools |
call FindXilinxTools.cmd |
rem ----- Run ChipScope Analyser |
analyzer.exe -project ..\ANALYSER\Analyser_18_1024.cpj -init ..\ANALYSER\Analyser.ini |
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_9_2048.cmd |
---|
0,0 → 1,24 |
@echo off |
rem |
rem Script for starting Analyser.exe with predefined settings. |
rem The script starts mlab_xvcd.exe deamon for users who use |
rem Xilinx Virtual Cable and FTDI JTAG cable. Those users |
rem should select in ChipScope Analyser setting |
rem JTAG Chain / Open Plug-in. |
rem |
rem ----- Run Xilinx Virtual Cable Daemon (as separate process) |
rem Run it if you use XVC cable connected to the local computer |
rem To start the daemon if already runnig does no harm |
if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe ( |
start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe |
) |
rem ----- Find and Set Xilinx Tools |
call FindXilinxTools.cmd |
rem ----- Run ChipScope Analyser |
analyzer.exe -project ..\ANALYSER\Analyser_9_2048.cpj -init ..\ANALYSER\Analyser.ini |