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/Modules/Clock/CLKDIV01A/PrjInfo.txt
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[InfoShortDescription.en]
PECL Clock divider
Diff input Clock divider
 
[InfoShortDescription.cs]
Dělička hodin s PECL vstupem
Dělička hodin s differenčním vstupem
 
[InfoLongDescription.en]
Multiple division ration can be selected by FSEL pin. Possible division ration are: (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) every output is synchronous each other. The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the internal clock is already in the LOW state.
Multiple division ration can be selected by jumpers. Possible division ration are: (÷1, ÷2, ÷4, ÷8) or (÷2, ÷4, ÷8, ÷16) every output is synchronous each other. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state.
 
[InfoLongDescription.cs]
Může být nastaveno více dělících poměrů. Možnosti jsou (÷1, ÷2, ÷4) nebo (÷2, ÷4, ÷8). EN vstup je synchronní s interními hodinami, proto dojde k vypnutí při návratu na nulu.
Může být nastaveno více dělících poměrů. Možnosti jsou (÷1, ÷2, ÷4, ÷8) nebo (÷2, ÷4, ÷8, ÷16). EN vstup je synchronní s interními hodinami, proto dojde k vypnutí při návratu na nulu.
 
[End]