Problem with comparison.
| /Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc |
|---|
| 0,0 → 1,59 |
| *PADS-PCB* |
| *PART* |
| C1 C-ELYT,10uF@ELYTB |
| C2 C,100nF@C0805 |
| C3 C,100nF@C0805 |
| C4 C,100nF@C0805 |
| D1 D,M4@MELF |
| J1 SATA,JUMP7@SATA |
| J12 JUMP2X3,JUMP2X3@JUMP2X3 |
| J13 JUMP2X2,JUMP2X2@JUMP2X2 |
| J2 SATA,JUMP7@SATA |
| J3 SATA,JUMP7@SATA |
| J4 SATA,JUMP7@SATA |
| M1 PAD,HOLE_M3@HOLE_M3 |
| M2 PAD,HOLE_M3@HOLE_M3 |
| M3 PAD,HOLE_M3@HOLE_M3 |
| M4 PAD,HOLE_M3@HOLE_M3 |
| M5 FIDU_PASTE,FIDU_PASTE@FIDU_PASTE |
| M6 FIDU,FIDU@FIDU |
| R1 R,127@R0805 |
| R2 R,127@R0805 |
| R3 R,83@R0805 |
| R4 R,83@R0805 |
| U1 SO16_150,SY100S834L@SO16_150 |
| *NET* |
| *SIGNAL* GND |
| J2.1 J2.4 J2.7 M2.1 D1.A M3.1 M4.1 J12.1 |
| J12.2 J12.5 J12.6 C2.1 C1.C M1.1 C3.1 J1.1 |
| J1.4 J1.7 R3.1 R4.1 C4.1 J3.1 J3.4 J3.7 |
| J4.1 J4.4 J4.7 U1.9 |
| *SIGNAL* N27272 |
| J1.2 R3.2 R1.1 U1.15 |
| *SIGNAL* N27304 |
| J1.5 R4.2 R2.1 U1.10 |
| *SIGNAL* N28535 |
| C4.2 J13.1 J13.2 U1.11 |
| *SIGNAL* N28645 |
| J13.3 J13.4 U1.14 |
| *SIGNAL* N29135 |
| J3.3 U1.2 |
| *SIGNAL* N29489 |
| J3.2 U1.1 |
| *SIGNAL* N29759 |
| J4.5 U1.4 |
| *SIGNAL* N29767 |
| J4.6 U1.5 |
| *SIGNAL* N29775 |
| J4.2 U1.7 |
| *SIGNAL* N29783 |
| J4.3 U1.8 |
| *SIGNAL* N30203 |
| J2.2 U1.13 |
| *SIGNAL* N30210 |
| J2.3 U1.12 |
| *SIGNAL* VCC |
| D1.C J12.3 J12.4 C2.2 C1.A C3.2 R2.2 R1.2 |
| U1.3 U1.6 U1.16 |
| *END* |