Problem with comparison.
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc |
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0,0 → 1,66 |
*PADS-PCB* |
*PART* |
C1 C-ELYT,10uF@ELYTB |
C2 C,100nF@C0805 |
C3 C,100nF@C0805 |
D1 D,M4@MELF |
J1 SATA,JUMP7@SATA |
J10 JUMP2X1,JUMP2X1@JUMP2X1 |
J11 JUMP2X1,JUMP2X1@JUMP2X1 |
J2 SATA,JUMP7@SATA |
J3 SATA,JUMP7@SATA |
J4 SATA,JUMP7@SATA |
J5 JUMP2X3,JUMP2X3@JUMP2X3 |
J6 JUMP2X1,JUMP2X1@JUMP2X1 |
J7 JUMP2X1,JUMP2X1@JUMP2X1 |
J8 JUMP2X2,JUMP2X2@JUMP2X2 |
J9 JUMP2X2,JUMP2X2@JUMP2X2 |
M1 PAD,HOLE_M3@HOLE_M3 |
M2 PAD,HOLE_M3@HOLE_M3 |
M3 PAD,HOLE_M3@HOLE_M3 |
M4 PAD,HOLE_M3@HOLE_M3 |
M5 FIDU_PASTE,FIDU_PASTE@FIDU_PASTE |
M6 FIDU,FIDU@FIDU |
R1 R,0R_@R0805 |
R2 R,50@R0805 |
TP1 TP,TP@TP |
U1 QFN16-3x3,NB6L239@QFN16-3x3 |
*NET* |
*SIGNAL* GND |
J1.1 J1.4 J1.7 M2.1 D1.A M3.1 M4.1 J5.1 |
J5.2 J5.5 J5.6 C2.1 C1.C M1.1 C3.1 J3.1 |
J3.4 J3.7 J4.1 J4.4 J4.7 J2.1 J2.4 J2.7 |
R2.1 U1.8 U1.17 |
*SIGNAL* N30203 |
J1.2 U1.2 |
*SIGNAL* N30210 |
J1.3 U1.3 |
*SIGNAL* N31970 |
U1.6 J9.1 J9.2 |
*SIGNAL* N31974 |
U1.7 J9.3 J9.4 |
*SIGNAL* N31978 |
U1.14 J8.3 J8.4 |
*SIGNAL* N31982 |
U1.15 J8.1 J8.2 |
*SIGNAL* N32586 |
R2.2 R1.1 U1.1 |
*SIGNAL* N33184 |
J4.2 J2.6 U1.12 |
*SIGNAL* N33196 |
J4.3 J2.5 U1.11 |
*SIGNAL* N33232 |
J3.2 J2.3 U1.9 |
*SIGNAL* N33244 |
J3.3 J2.2 U1.10 |
*SIGNAL* N33366 |
U1.4 TP1.1 |
*SIGNAL* N33426 |
U1.5 J10.1 J10.2 |
*SIGNAL* N33433 |
U1.16 J11.1 J11.2 |
*SIGNAL* VCC |
D1.C J5.3 J5.4 C2.2 C1.A C3.2 R1.2 U1.13 |
J6.1 J6.2 J7.1 J7.2 |
*END* |