/Modules/Clock/CLKGEN01A/SW/DG8SAQ synthesiser_Emulator/rm18f4550.lkr
0,0 → 1,37
// FileName: rm18f4550.lkr
// Sample linker command file for 18F4550 with Bootloader
//
//Change History:
// Rev Date Description
// 1.0 10/30/2004 Initial release
 
LIBPATH .
 
FILES c018i.o
FILES clib.lib
FILES p18f4550.lib
 
CODEPAGE NAME=boot START=0x0 END=0x7FF PROTECTED
CODEPAGE NAME=vectors START=0x800 END=0x0x829 PROTECTED
CODEPAGE NAME=page START=0x82A END=0x7FFF
CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED
CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED
CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED
CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED
 
ACCESSBANK NAME=accessram START=0x0 END=0x5F
DATABANK NAME=gpr0 START=0x60 END=0xFF
DATABANK NAME=gpr1 START=0x100 END=0x1FF
DATABANK NAME=gpr2 START=0x200 END=0x2FF
DATABANK NAME=gpr3 START=0x300 END=0x3FF
DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED
DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED
DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED
DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED
ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED
 
SECTION NAME=CONFIG ROM=config
 
STACK SIZE=0x100 RAM=gpr3
 
SECTION NAME=USB_VARS RAM=usb4