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/Modules/PowerSW/NFET4X01B/PCB/NFET4X01B.pcb |
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/Modules/PowerSW/NFET4X01B/SCH/NFET4X01B.opj |
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0,0 → 1,107 |
(ExpressProject "" |
(ProjectVersion "19981106") |
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(BuildFileAddedOrDeleted "x") |
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(DRC_Check_Ports "FALSE") |
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(DRC_SDT_Compatibility "FALSE") |
(DRC_Report_Off-grid_Objects "FALSE") |
(DRC_Check_Unconnected_Nets "TRUE") |
(DRC_Check_for_Misleading_TAP "FALSE") |
(DRC_Report_Netnames "FALSE") |
(DRC_Check_Single_Node_Nets "TRUE") |
(DRC_Check_No_Driving_Source "TRUE") |
(DRC_Check_Duplicate_NetNames "TRUE") |
(DRC_Check_Floating_Pins "TRUE") |
(DRC_Check_Physical_Power_Pins_Visibility "TRUE") |
(DRC_Check_PCB_Footprint_Property "TRUE") |
(DRC_Check_Normal_Convert_View_Sync "TRUE") |
(DRC_Check_Incorrect_PinGroup_Assignment "TRUE") |
(DRC_Check_High_Speed_Props_Syntax "TRUE") |
(DRC_Check_Missing_Pin_Numbers "TRUE") |
(DRC_Check_Device_With_No_Pins "TRUE") |
(DRC_Check_Power_Ground_Short "TRUE") |
(DRC_Identical_References "TRUE") |
(DRC_Type_Mismatch "TRUE") |
(DRC_Visible_Power_pins "FALSE") |
(DRC_Report_Unused_Part_Packages "TRUE") |
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(Folder "Referenced Projects") |
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/Modules/PowerSW/NFET4X01B/SCH/NFET4X01B.pdf |
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/Modules/PowerSW/NFET4X01B/SCH/NFET4X01B.DSN |
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/Modules/PowerSW/NFET4X01B/SCH/NFET4X01B.asc |
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0,0 → 1,115 |
*PADS-PCB* |
*PART* |
C1 C,100nF@C0805 |
C2 C,100nF@C0805 |
C3 C,100nF@C0805 |
C4 C,100nF@C0805 |
C5 C-ELYT,47uF@ELYTC |
C6 C-ELYT,47uF@ELYTC |
C7 C-ELYT,47uF@ELYTC |
C8 C-ELYT,47uF@ELYTC |
D1 D,BAT43SMD@SOD87 |
D2 D,1N5818@SMB |
D3 D,BAT43SMD@SOD87 |
D4 D,1N5818@SMB |
D5 D,BAT43SMD@SOD87 |
D6 D,1N5818@SMB |
D7 D,BAT43SMD@SOD87 |
D8 D,1N5818@SMB |
J1 JUMP2X4,JUMP2X4@JUMP2X4 |
J10 SCW2,ARK210/2@WAGO256 |
J11 SCW2,ARK210/2@WAGO256 |
J12 SCW2,ARK210/2@WAGO256 |
J13 SCW2,ARK210/2@WAGO256 |
J14 JUMP2X1,JUMP2X1@JUMP2X1 |
J15 JUMP2X1,JUMP2X1@JUMP2X1 |
J16 JUMP2X1,JUMP2X1@JUMP2X1 |
J17 JUMP2X1,JUMP2X1@JUMP2X1 |
J4 SCW2,ARK210/2@WAGO256 |
J5 JUMP2X4,JUMP2X4@JUMP2X4 |
J6 JUMP3,JUMP3@JUMP3 |
J7 JUMP3,JUMP3@JUMP3 |
J8 JUMP3,JUMP3@JUMP3 |
J9 JUMP3,JUMP3@JUMP3 |
M1 PAD,HOLE_M3@HOLE_M3 |
M2 PAD,HOLE_M3@HOLE_M3 |
M3 PAD,HOLE_M3@HOLE_M3 |
M4 PAD,HOLE_M3@HOLE_M3 |
M5 FIDU,FIDU@FIDU |
M6 FIDU_PASTE,FIDU_PASTE@FIDU_PASTE |
Q1 T-FET-GSD,AP60N03S@TO252 |
Q2 T-FET-GSD,AP60N03S@TO252 |
Q3 T-FET-GSD,AP60N03S@TO252 |
Q4 T-FET-GSD,AP60N03S@TO252 |
R1 R,100@R1206 |
R10 R,0,1@R1206 |
R11 R,0,1@R1206 |
R12 R,0,1@R1206 |
R2 R,100k@R0805 |
R3 R,100@R1206 |
R4 R,100k@R0805 |
R5 R,100@R1206 |
R6 R,100k@R0805 |
R7 R,100@R1206 |
R8 R,100k@R0805 |
R9 R,0,1@R1206 |
*NET* |
*SIGNAL* GND |
R2.1 R4.1 R6.1 R8.1 J4.2 J5.1 J5.2 J5.7 |
J5.8 M1.1 M2.1 M3.1 M4.1 D1.A D3.A D5.A |
D7.A R9.1 R10.1 R11.1 R12.1 C5.C C6.C C7.C |
C8.C |
*SIGNAL* IN1 |
J1.1 J1.2 R1.1 |
*SIGNAL* IN2 |
J1.3 J1.4 R3.1 |
*SIGNAL* IN3 |
J1.5 J1.6 R5.1 |
*SIGNAL* IN4 |
J1.7 J1.8 R7.1 |
*SIGNAL* N00029 |
C1.1 J6.1 R1.2 |
*SIGNAL* N00057 |
Q1.G C1.2 J6.2 R2.2 |
*SIGNAL* N00121 |
J6.3 D1.C |
*SIGNAL* N00520 |
C2.2 R4.2 Q2.G J7.2 |
*SIGNAL* N00522 |
C2.1 J7.1 R3.2 |
*SIGNAL* N00546 |
J7.3 D3.C |
*SIGNAL* N00754 |
J8.2 C3.2 Q3.G R6.2 |
*SIGNAL* N00756 |
J8.1 C3.1 R5.2 |
*SIGNAL* N00802 |
J8.3 D5.C |
*SIGNAL* N00896 |
J9.1 C4.1 R7.2 |
*SIGNAL* N00898 |
J9.2 R8.2 C4.2 Q4.G |
*SIGNAL* N00910 |
J9.3 D7.C |
*SIGNAL* N62246 |
Q1.S R9.2 J14.1 J14.2 |
*SIGNAL* N62250 |
Q2.S R10.2 J15.1 J15.2 |
*SIGNAL* N62254 |
Q3.S R11.2 J16.1 J16.2 |
*SIGNAL* N62258 |
Q4.S R12.2 J17.1 J17.2 |
*SIGNAL* OUT1 |
Q1.D D2.A J10.2 |
*SIGNAL* OUT2 |
D4.A Q2.D J11.2 |
*SIGNAL* OUT3 |
D6.A Q3.D J12.2 |
*SIGNAL* OUT4 |
Q4.D D8.A J13.2 |
*SIGNAL* VDD |
D2.C D4.C D6.C D8.C J4.1 J5.3 J5.4 J5.5 |
J5.6 J10.1 J11.1 J12.1 J13.1 C5.A C6.A C7.A |
C8.A |
*END* |
/Modules/PowerSW/NFET4X01B/PrjInfo.txt |
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0,0 → 1,17 |
// |
// This is a project description file. |
// |
[InfoShortDescription.en] |
4NFET Power Driver |
[InfoShortDescription.cs] |
4NFET výkonový budič |
[InfoLongDescription.en] |
There are 4 NFETs switching to GND. Parameters depending on type of soldered FETs. Inductive load is allowed. |
[InfoLongDescription.cs] |
Modul slouží jako čtyřnásobný výkonový budič se spínáním do GND. Parametry závisí na typu osazených FET tranzistorů, předpokládá se pouzdro D-PAK. Spínaná zátěž může mít indukční charakter. |
[End] |