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+[InfoShortDescription.en]
+Universal protected 8 channels input
+[InfoShortDescription.cs]
+Univerzalní 8mi vstup
+[InfoLongDescription.en]
+Construction of universal high voltage protected / galvanic isolated input. Can be used both for analog and digital signals.
+[InfoLongDescription.cs]
+Vstupní modul s ochranou proti vysokému napětí. Může být použit v režimu se společnou zemí či s galvanickým oddělením. Je použitelný jak pro digitální, tak i pro analogové signály.
+[InfoBuyUST]
+http://www.ust.cz/shop/product_info.php?cPath=22_27&products_id=77
+[End]

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+--------
+*SYM 19
+TO220AB 1 N
+trm=2
+0 -1905000 -228600 -2438400
+0 1905000 -342900 1409700
+pin=1
+Y 15
+lbl=2
+Attr=2
+Description
+108
+diodove pouzdro TO220AB
+Geometry.Height
+104
+mm
+--------
+*SYM 20
+SMA 1 N
+trm=2
+0 -3825000 0 -3825000
+0 3825000 0 3825000
+pin=1
+Y 16
+lbl=2
+Attr=2
+Description
+108
+SMD dioda v pouzdre SMA
+Geometry.Height
+104
+.5mm
+--------
+*SYM 22
+SMC 1 N
+trm=2
+0 -5640000 0 -5640000
+0 5640000 0 5640000
+pin=1
+Y 18
+lbl=2
+Attr=2
+Description
+108
+SMD dioda v pouzdre SMC
+Geometry.Height
+104
+.8mm
+--------
+*SYM 28
+LED3 0 N
+trm=2
+C -1881000 0 -2025015 -600075
+A 1881000 0 1575054 -449961
+pin=2
+Y 20
+N 6
+lbl=2
+Attr=2
+Description
+108
+LED 3 mm, roztec 2.54 mm - 100 mils
+Geometry.Height
+104
+mm
+--------
+*SYM 23
+LED0603 0 N
+trm=2
+-1143000 0 -1333500 -571500
+1143000 0 838200 -571500
+pin=1
+Y 4
+lbl=2
+Attr=2
+Description
+108
+LED SMD velikost 0603
+Geometry.Height
+104
+mm
+--------
+*SYM 24
+LED0805-1206 0 N
+trm=2
+-1714500 0 -1826700 -600000
+1714500 0 1421700 -585000
+pin=1
+Y 7
+lbl=2
+Attr=2
+Description
+108
+univerzalni plosky pro LED pro pouzdro 0805 i 1206
+Geometry.Height
+104
+.50000mm
+--------
+*SYM 25
+LED0805 0 N
+trm=2
+-1447800 0 -1333500 -571500
+1447800 0 1481570 -571500
+pin=1
+Y 19
+lbl=2
+Attr=2
+Description
+108
+LED SMD velikost 0805
+Geometry.Height
+104
+mm
+--------
+*SYM 26
+LED1206 0 N
+trm=2
+-2171700 0 -2283900 -600000
+2171700 0 1878900 -585000
+pin=1
+Y 5
+lbl=2
+Attr=2
+Description
+108
+rezistor SMD velikost 1206
+Geometry.Height
+104
+mm
+--------
+*SYM 27
+LED1.8 0 N
+trm=2
+-1881000 0 -2025000 -600000
+1881000 0 1575000 -450000
+pin=2
+Y 6
+N 20
+lbl=2
+Attr=2
+Description
+108
+LED 1.8 mm roztec 2.54 mm - 100 mils
+Geometry.Height
+104
+mm
+--------
+*SYM 29
+LED10 0 N
+trm=2
+-1881000 0 -2025000 -600000
+1881000 0 1575000 -450000
+pin=2
+Y 6
+N 20
+lbl=2
+Attr=2
+Description
+108
+LED 10 mm roztec 2.54 mm - 100 mils
+Geometry.Height
+104
+mm
+--------
+*SYM 30
+LED5 0 N
+trm=2
+-1881000 0 -2025000 -600000
+1881000 0 1575000 -450000
+pin=2
+Y 6
+N 20
+lbl=2
+Attr=2
+Description
+108
+LED 5 mm roztec 2.54 mm - 100 mils
+Geometry.Height
+104
+mm
+--------
+*SYM 45
+MFSOP6 0 N
+trm=4
+-1905000 -4876800 -1905000 -4876800
+1905000 -4876800 1905000 -4876800
+1905000 4876800 1905000 4876800
+-1905000 4876800 -1905000 4876800
+pin=1
+Y 39
+lbl=2
+Attr=0
+--------
+*SYM 46
+R0805 0 N
+trm=2
+-1447800 0 -1333500 -571500
+1447800 0 1481570 -571500
+pin=1
+Y 19
+lbl=2
+Attr=2
+Description
+108
+rezistor SMD velikost 0805
+Geometry.Height
+104
+mm
+--------
+*SYM 47
+R0603 0 N
+trm=2
+-1143000 0 -1333500 -571500
+1143000 0 838200 -571500
+pin=1
+Y 4
+lbl=2
+Attr=2
+Description
+108
+rezistor SMD velikost 0603
+Geometry.Height
+104
+mm
+--------
+*SYM 48
+R1206 0 N
+trm=2
+-2171700 0 -2283900 -600000
+2171700 0 1878900 -585000
+pin=1
+Y 5
+lbl=2
+Attr=2
+Description
+108
+rezistor SMD velikost 1206
+Geometry.Height
+104
+mm
+--------
+*SYM 49
+RS025 0 N
+trm=2
+-1905000 0 -2055000 -600000
+1905000 0 1605000 -450000
+pin=1
+Y 6
+lbl=2
+Attr=2
+Description
+108
+bezny rezistor  nastojato roztec 2,54 mm, 100 mils
+Geometry.Height
+104
+mm
+--------
+*SYM 50
+RL090 1 N
+trm=2
+-6667500 0 -6817500 -600000
+6667500 0 6367500 -450000
+pin=1
+Y 6
+lbl=2
+Attr=2
+Description
+108
+bezny rezistor roztec 8.89mm, 350mils
+Geometry.Height
+104
+mm
+--------
+*SYM 51
+RL140 1 N
+trm=2
+-10477500 0 -10627500 -600000
+10477500 0 10177500 -450000
+pin=1
+Y 6
+lbl=2
+Attr=2
+Description
+108
+rezistor 2W nalezato roztec 13.97mm, 550mils
+Geometry.Height
+104
+.6mm
+--------
+*SYM 52
+RS040 1 N
+trm=2
+-2857500 0 -3007500 -600000
+2857500 0 2557500 -450000
+pin=1
+Y 6
+lbl=2
+Attr=2
+Description
+108
+rezistor 2W nastojato, roztec 3.81 mm ,150 mils
+Geometry.Height
+104
+mm
+--------
+*SYM 53
+R1812 0 N
+trm=2
+-3543300 0 -3429000 -571500
+3543300 0 3577070 -571500
+pin=1
+Y 40
+lbl=2
+Attr=2
+Description
+108
+rezistor SMD velikost 1812
+Geometry.Height
+104
+mm
+--------
+*SYM 54
+RL060 1 N
+trm=2
+-4500000 0 -4650000 -600000
+4500000 0 4200000 -450000
+pin=1
+Y 6
+lbl=2
+Attr=2
+Description
+108
+bezny rezistor roztec 6mm
+Geometry.Height
+104
+mm
+--------
+*SYM 31
+ARK210/2 1 N
+trm=4
+-3750000 3750000 -3978600 3254700
+3750000 3750000 3750000 3750000
+-3750000 -3750000 -3750000 -3750000
+3750000 -3750000 3750000 -3750000
+pin=2
+Y 25
+N 24
+lbl=2
+Attr=2
+Description
+108
+svorkovnice se dvema piny, roztec 5.08 mm - 200 mils
+Geometry.Height
+104
+mm
+--------
+*PKG = 6
+*PKG 0
+C 0 CAP
+PinName=0
+SignalPin=0
+Gate=1
+GatePin=2
+1 6
+1 6
+sym=9
+Attr=1
+Description
+108
+ruzne druhy kondenzatoru
+--------
+*PKG 1
+D 0 DIO
+PinName=2
+C
+A
+SignalPin=0
+Gate=1
+GatePin=2
+C 0 9
+A 0 9
+sym=12
+Attr=1
+Description
+108
+ruzne druhy diod
+--------
+*PKG 2
+LED 0 DIO
+PinName=2
+C
+A
+SignalPin=0
+Gate=1
+GatePin=2
+C 0 9
+A 0 9
+sym=8
+Attr=1
+Description
+108
+ruzne druhy LED
+--------
+*PKG 6
+MFSOP6 0 UND
+PinName=0
+SignalPin=0
+Gate=0
+sym=1
+Attr=1
+Description
+108
+,5mm   99mils
+--------
+*PKG 7
+R 0 RES
+PinName=0
+SignalPin=0
+Gate=1
+GatePin=2
+0 6
+0 6
+sym=9
+Attr=1
+Description
+108
+rezistory ruznych typu
+--------
+*PKG 3
+SCW2 0 CON
+PinName=0
+SignalPin=0
+Gate=0
+sym=1
+Attr=0
+--------
+*COM = 10
+*COM 6
+C7 14458477 2622694 486000000 YN
+NNNNN
+lbl=2
+Attr=1
+Value
+108
+C0805
+--------
+*COM 12
+D13 19017282 58366 0 YN
+NNNNN
+lbl=2
+Attr=1
+Value
+108
+TRANSIL
+--------
+*COM 13
+D14 24922782 4439866 0 NN
+NNNNN
+lbl=2
+Attr=1
+Value
+108
+LED3MM
+--------
+*COM 36
+Q7 33975861 -2078574 162000000 YN
+NNNNN
+lbl=2
+Attr=1
+Value
+108
+TLP127_SMD
+--------
+*COM 54
+R46 14458477 -2933350 486000000 YN
+NNNNN
+lbl=2
+Attr=1
+Value
+108
+R0805
+--------
+*COM 55
+R47 24732282 -3942134 0 YN
+NNNNN
+lbl=2
+Attr=1
+Value
+108
+R0805
+--------
+*COM 56
+R48 25000714 1198067 0 YN
+NNNNN
+lbl=2
+Attr=1
+Value
+108
+R0805
+--------
+*COM 83
+J16 7364730 377952 486000000 NN
+NNNNN
+lbl=0
+Attr=1
+Value
+108
+ARK210/2
+--------
+*COM 89
+R45 0 0 0 YN
+NNNNN
+lbl=2
+Attr=1
+Value
+108
+R1206
+--------
+*COM 104
+R50 -1554861 4098417 324000000 YN
+NNNNN
+lbl=2
+Attr=1
+Value
+108
+R1206
+--------
+*PRO = 15
+*PRO 362
+5 2 2 2 0 -1 0 89 1
+2502789 -2668143
+2622042 -2548890
+2622042 -1402842
+1447800 -228600
+1447800 0
+YNN
+90 0 NNN
+90 0 NNN
+--------
+*PRO 247
+2 2 2 2 0 -1 0 83 2
+5653276 -3372048
+11114730 -3372048
+NNN
+90 0 NNN
+90 0 YNN
+--------
+*PRO 91
+2 2 2 0 2 83 4 -1 0
+3614730 -3372048
+5653276 -3372048
+NNN
+90 0 NNN
+90 0 NNN
+--------
+*PRO 368
+4 2 2 0 0 54 2 83 2
+14458477 -4381150
+14458477 -4019200
+13867927 -4019200
+11114730 -3372048
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 374
+4 2 2 0 0 12 1 54 1
+19017282 -3841634
+18642282 -3841634
+16286198 -1485550
+14458477 -1485550
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 370
+3 2 2 0 0 55 2 12 1
+23284482 -3942134
+19017282 -3942134
+19017282 -3841634
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 378
+3 2 2 0 0 36 1 55 1
+29099061 -3983574
+26180082 -3983574
+26180082 -3942134
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 358
+2 2 2 0 0 83 3 83 1
+3614730 4127952
+11114730 4127952
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 366
+3 2 2 0 0 6 1 83 1
+14458477 4070494
+11114730 4070494
+11114730 4127952
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 364
+2 2 2 0 0 54 1 6 2
+14458477 -1485550
+14458477 1174894
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 376
+3 2 2 0 0 12 2 13 1
+19017282 3958366
+19017282 4439866
+23041782 4439866
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 372
+3 2 2 0 0 12 2 6 1
+19017282 3958366
+14458477 3958366
+14458477 4070494
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 384
+3 2 2 0 0 56 2 13 1
+23552914 1198067
+23552914 4439866
+23041782 4439866
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*PRO 534
+4 2 2 0 0 36 2 56 1
+29099061 -173574
+28832361 -173574
+27460720 1198067
+26448514 1198067
+NNN
+90 0 NNN
+90 0 YNN
+--------
+*PRO 380
+4 2 2 0 0 56 1 13 2
+26448514 1198067
+26540621 1198067
+26540621 4439866
+26803782 4439866
+NNN
+90 0 YNN
+90 0 YNN
+--------
+*NET = 5
+*NET 2
+4
+2
+2
+1
+--------
+*NET 4
+1
+2
+2
+1
+--------
+*NET 3
+1
+1
+--------
+*NET 5
+2
+3
+1
+1
+2
+1
+2
+--------
+*NET 6
+2
+2
+1
+--------
+*PIN = 24
+*PIN 13
+3614730 -3372048 0 4 0 0 NNNNNYNNNNN
+-1 -1 2 -1
+Attr=0
+--------
+*PIN 25
+14458477 -4381150 0 2 0 0 NNNNNYNNNNN
+-1 -1 2 -1
+Attr=0
+--------
+*PIN 11
+11114730 -3372048 0 2 0 0 NNNNNYNNNNN
+-1 -1 2 -1
+Attr=0
+--------
+*PIN 28
+19017282 -3841634 0 1 0 0 NNNNNYNNNNN
+-1 -1 4 -1
+Attr=0
+--------
+*PIN 23
+23284482 -3942134 0 2 0 0 NNNNNYNNNNN
+-1 -1 4 -1
+Attr=0
+--------
+*PIN 22
+26180082 -3942134 0 1 0 0 NNNNNYNNNNN
+-1 -1 3 -1
+Attr=0
+--------
+*PIN 18
+29099061 -3983574 0 1 0 0 NNNNNYNNNNN
+-1 -1 3 -1
+Attr=0
+--------
+*PIN 21
+38852661 -3983574 0 4 0 0 NNNNNYNNNNN
+-1 -1 -1 -1
+Attr=0
+--------
+*PIN 281
+-1447800 0 0 2 0 0 NNNNNYNNNYN
+-1 -1 -1 -1
+Attr=0
+--------
+*PIN 280
+1447800 0 0 1 0 0 NNNNNYNNNYN
+-1 -1 2 -1
+Attr=0
+--------
+*PIN 311
+4098417 0 2 0 0 NNNNNYNNNYN
+-1 -1 5 -1
+Attr=0
+--------
+*PIN 310
+-3726561 4098417 0 1 0 0 NNNNNYNNNYN
+-1 -1 -1 -1
+Attr=0
+--------
+*PIN 12
+3614730 4127952 0 3 0 0 NNNNNYNNNNN
+-1 -1 5 -1
+Attr=0
+--------
+*PIN 27
+14458477 1174894 0 2 0 0 NNNNNYNNNNN
+-1 -1 4 -1
+Attr=0
+--------
+*PIN 26
+14458477 4070494 0 1 0 0 NNNNNYNNNNN
+-1 -1 5 -1
+Attr=0
+--------
+*PIN 24
+14458477 -1485550 0 1 0 0 NNNNNYNNNNN
+-1 -1 4 -1
+Attr=0
+--------
+*PIN 10
+11114730 4127952 0 1 0 0 NNNNNYNNNNN
+-1 -1 5 -1
+Attr=0
+--------
+*PIN 29
+19017282 3958366 0 2 0 0 NNNNNYNNNNN
+-1 -1 5 -1
+Attr=0
+--------
+*PIN 16
+23041782 4439866 0 1 0 0 NNNNNYNNNNN
+-1 -1 5 -1
+Attr=0
+--------
+*PIN 15
+23552914 1198067 0 2 0 0 NNNNNYNNNNN
+-1 -1 5 -1
+Attr=0
+--------
+*PIN 19
+29099061 -173574 0 2 0 0 NNNNNYNNNNN
+-1 -1 6 -1
+Attr=0
+--------
+*PIN 17
+26803782 4439866 0 2 0 0 NNNNNYNNNNN
+-1 -1 6 -1
+Attr=0
+--------
+*PIN 14
+26448514 1198067 0 1 0 0 NNNNNYNNNNN
+-1 -1 6 -1
+Attr=0
+--------
+*PIN 20
+38852661 -173574 0 3 0 0 NNNNNYNNNNN
+-1 -1 -1 -1
+Attr=0
+--------
+*EOF
+!PADS-POWERPCB-V9.0-MILS! DESIGN DATABASE ASCII FILE 1.0
+*PCB*        GENERAL PARAMETERS OF THE PCB DESIGN
+UNITS        0              2=Inches 1=Metric 0=Mils
+USERGRID     0.01   0.01    Space between USER grid points
+MAXIMUMLAYER 2              Maximum routing layer
+WORKLEVEL    2              Level items will be created on
+DISPLAYLEVEL 1              toggle for displaying working level last
+LAYERPAIR    1      2       Layer pair used to route connection
+VIAMODE      T              Type of via to use when routing between layers
+LINEWIDTH    12             Width items will be created with
+TEXTSIZE     100    10      Height and LineWidth text will be created with
+JOBTIME      197            Amount of time spent on this PCB design
+DOTGRID      1000   1000    Space between graphic dots
+SCALE        36.968          Scale of window expansion
+ORIGIN       27915  22540   User defined origin location
+WINDOWCENTER 28604.36 23061.69  Point defining the center of the window
+BACKUPTIME   20             Number of minutes between database backups
+REAL WIDTH   10             Widths greater then this are displayed real size
+ALLSIGONOFF  1              All signal nets displayed on/off
+REFNAMESIZE  100    10      Height and LineWidth used by part ref. names
+HIGHLIGHT    0              Highlight nets flag
+JOBNAME      INPUTUNI01.pcb
+CONCOL 1
+FBGCOL 1 0
+HATCHGRID    10             Copper pour hatching grid
+TEARDROP     2713690        Teardrop tracks
+THERLINEWID  15             Copper pour thermal line width
+PSVIAGRID    0.01   0.01    Push & Shove Via Grid
+PADFILLWID   10             CAM finger pad fill width
+THERSMDWID   10             Copper pour thermal line width for SMD
+MINHATAREA   0              Minimum hatch area
+HATCHMODE    0              Hatch generation mode
+HATCHDISP    0              Hatch display flag
+DRILLHOLE    6              Drill hole checking spacing
+MITRERADII   0.5 1.0 1.5 2.0 2.5 3.0 3.5
+MITRETYPE    1              Mitring type
+HATCHRAD     0.500000       Hatch outline smoothing radius
+MITREANG     180 180 180 180 180 180 90
+HATCHANG     0              Hatch angle
+THERFLAGS    0              Copper pour thermal line flags
+DRLOVERSIZE  3              Drill oversize for plated holes
+PLANERAD     0.000000       Plane outline smoothing radius
+PLANEFLAGS   OUTLINE THERMALS Y Y Y N N Y Y Y N N Y Y N Y Y N N N   Plane and Test Points flags
+COMPHEIGHT   0              Board Top Component Height Restriction
+KPTHATCHGRID 100            Copper pour hatching grid
+BOTCMPHEIGHT 0              Board Bottom Component Height Restriction
+FANOUTGRID   25     25      Fanout grid
+FANOUTLENGTH 250            Maximum fanout length
+ROUTERFLAGS  83879441       Autorouter specific flags
+VERIFYFLAGS  1861           Verify Design flags
+FABCHKFLAGS  3967           Fabrication checks flags
+ATMAXSIZE    3              Acid Traps Maximum Size
+ATMAXANGLE   161999820      Acid Traps Maximum Angle
+SLMINCOPPER  3              Slivers Minimum Copper
+SLMINMASK    3              Slivers Minimum Mask
+STMINCLEAR   5              Starved Thermal Minimum Clearance
+STMINSPOKES  4              Starved Thermal Minimum Spokes
+TPMINWIDTH   3              Minimum Trace Width
+TPMINSIZE    3              Mimimum Pad Size
+SSMINGAP     3              Silk Screen Over Pads Minimum Gap
+SBMINGAP     3              Solder Bridges Minimum Gap
+SBLAYER      1              Solder Bridges Layer
+ARPTOM       3              Pad To Mask Annular Ring
+ARPTOMLAYER  1              Pad To Mask Annular Ring Layer
+ARDTOM       3              Drill To Mask Annular Ring
+ARDTOMLAYER  1              Drill To Mask Annular Ring Layer
+ARDTOP       3              Drill To Pad Annular Ring
+ARDTOPLAYER  0              Drill To Pad Annular Ring Layer
+VIAPSPACING  100            Via patterns via spacing
+VIAPSHAPE    6              Via patterns via to shape spacing
+VIAPTOTRACE  -0             Via patterns via to edge spacing
+VIAPFILL     1              Via patterns fill type
+VIAPSHSIG    NONE
+VIAPSHVIA    NONE
+VIAPFLAG     4              Via patterns flags
+PLNSEPGAP    6              Plane separation gap
+IDFSHAPELAY  0              IDF shapes layer
+TEARDROPDATA     90     90
+*VIA*  ITEMS
+*REMARK* NAME  DRILL STACKLINES [DRILL START] [DRILL END]
+*REMARK* LEVEL SIZE SHAPE [INNER DIAMETER] [CORNER RADIUS]
+JMPVIA_AAAAA     37 3
+-2 55 R
+-1 70 R
+55 R
+STANDARDVIA      37 3
+-2 55 R
+-1 55 R
+55 R
+*MISC*      MISCELLANEOUS PARAMETERS
+*REMARK*    PARENT_KEYWORD PARENT_VALUE
+*REMARK*  [ {
+*REMARK*       CHILD_KEYWORD CHILD_VALUE
+*REMARK*     [ CHILD_KEYWORD CHILD_VALUE
+*REMARK*     [ {
+*REMARK*          GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...]
+*REMARK*       } ]]
+*REMARK*    } ]
+LAYER DATA
+{
+LAYER 1
+{
+LAYER_NAME Top
+LAYER_TYPE COMPONENT
+PLANE NONE
+ROUTING_DIRECTION HORIZONTAL
+ASSOCIATED_SILK_SCREEN Silkscreen Top
+ASSOCIATED_PASTE_MASK Paste Mask Top
+ASSOCIATED_SOLDER_MASK Solder Mask Top
+ASSOCIATED_ASSEMBLY Assembly Drawing Top
+COMPONENT Y
+ROUTABLE Y
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
+ROUTE 3
+VIA 3
+PAD 3
+COPPER 3
+DLINE 3
+TEXT 3
+ERROR 5
+TOPCOMPONENT 1
+BOTTOMCOMPONENT 0
+REFDES 1
+PARTTYPE 0
+ATTRIBUTE 0
+KEEPOUT 0
+}
+LAYER_THICKNESS 381000
+COPPER_THICKNESS 51435
+DIELECTRIC 4.300000
+COST 0
+}
+LAYER 2
+{
+LAYER_NAME Bottom
+LAYER_TYPE COMPONENT
+PLANE NONE
+ROUTING_DIRECTION VERTICAL
+ASSOCIATED_SILK_SCREEN Silkscreen Bottom
+ASSOCIATED_PASTE_MASK Paste Mask Bottom
+ASSOCIATED_SOLDER_MASK Solder Mask Bottom
+ASSOCIATED_ASSEMBLY Assembly Drawing Bottom
+COMPONENT Y
+ROUTABLE Y
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
+ROUTE 11
+VIA 11
+PAD 11
+COPPER 11
+DLINE 11
+TEXT 11
+ERROR 13
+TOPCOMPONENT 0
+BOTTOMCOMPONENT 14
+REFDES 14
+PARTTYPE 0
+ATTRIBUTE 0
+KEEPOUT 0
+}
+LAYER_THICKNESS 0
+COPPER_THICKNESS 51435
+DIELECTRIC 3.300000
+COST 0
+}
+LAYER 3
+{
+LAYER_NAME Layer_3
+LAYER_TYPE UNASSIGNED
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
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+{
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+{
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+{
+LAYER_NAME Layer_8
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+LAYER 12
+{
+LAYER_NAME Layer_12
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+}
+LAYER 13
+{
+LAYER_NAME Layer_13
+LAYER_TYPE UNASSIGNED
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+SELECTABLE Y
+ENABLED Y
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+LAYER 14
+{
+LAYER_NAME Layer_14
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+}
+LAYER 15
+{
+LAYER_NAME Layer_15
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+}
+LAYER 16
+{
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+LAYER_NAME Layer_17
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+}
+LAYER 18
+{
+LAYER_NAME Layer_18
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+ENABLED Y
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+}
+LAYER 19
+{
+LAYER_NAME Layer_19
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+ENABLED Y
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+}
+LAYER 20
+{
+LAYER_NAME Layer_20
+LAYER_TYPE UNASSIGNED
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+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
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+}
+LAYER 21
+{
+LAYER_NAME Solder Mask Top
+LAYER_TYPE SOLDER_MASK
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
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+}
+LAYER 22
+{
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+LAYER_TYPE PASTE_MASK
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
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+}
+LAYER 23
+{
+LAYER_NAME Paste Mask Top
+LAYER_TYPE PASTE_MASK
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
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+}
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+COST 0
+}
+LAYER 24
+{
+LAYER_NAME Drill Drawing
+LAYER_TYPE DRILL
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
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+}
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+}
+LAYER 25
+{
+LAYER_NAME Layer_25
+LAYER_TYPE UNASSIGNED
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
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+}
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+COPPER_THICKNESS 0
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+COST 0
+}
+LAYER 26
+{
+LAYER_NAME Silkscreen Top
+LAYER_TYPE SILK_SCREEN
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
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+ATTRIBUTE 0
+KEEPOUT 0
+}
+LAYER_THICKNESS 0
+COPPER_THICKNESS 0
+DIELECTRIC 3.300000
+COST 0
+}
+LAYER 27
+{
+LAYER_NAME Assembly Drawing Top
+LAYER_TYPE ASSEMBLY
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
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+KEEPOUT 0
+}
+LAYER_THICKNESS 0
+COPPER_THICKNESS 0
+DIELECTRIC 3.300000
+COST 0
+}
+LAYER 28
+{
+LAYER_NAME Solder Mask Bottom
+LAYER_TYPE SOLDER_MASK
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
+ROUTE 0
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+PAD 0
+COPPER 0
+DLINE 0
+TEXT 0
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+PARTTYPE 0
+ATTRIBUTE 0
+KEEPOUT 0
+}
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+COPPER_THICKNESS 0
+DIELECTRIC 3.300000
+COST 0
+}
+LAYER 29
+{
+LAYER_NAME Silkscreen Bottom
+LAYER_TYPE SILK_SCREEN
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
+ROUTE 0
+VIA 0
+PAD 0
+COPPER 0
+DLINE 0
+TEXT 0
+ERROR 0
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+BOTTOMCOMPONENT 0
+REFDES 0
+PARTTYPE 0
+ATTRIBUTE 0
+KEEPOUT 0
+}
+LAYER_THICKNESS 0
+COPPER_THICKNESS 0
+DIELECTRIC 3.300000
+COST 0
+}
+LAYER 30
+{
+LAYER_NAME Assembly Drawing Bottom
+LAYER_TYPE ASSEMBLY
+PLANE NONE
+ROUTING_DIRECTION NO_PREFERENCE
+VISIBLE Y
+SELECTABLE Y
+ENABLED Y
+COLORS :
+{
+ROUTE 0
+VIA 0
+PAD 0
+COPPER 0
+DLINE 0
+TEXT 0
+ERROR 0
+TOPCOMPONENT 0
+BOTTOMCOMPONENT 0
+REFDES 0
+PARTTYPE 0
+ATTRIBUTE 0
+KEEPOUT 0
+}
+LAYER_THICKNESS 0
+COPPER_THICKNESS 0
+DIELECTRIC 3.300000
+COST 0
+}
+}
+SELECTABILITY DATA
+{
+PARTS Y
+PINS Y
+TRACES Y
+VIAS Y
+TACKS Y
+UNROUTED Y
+EDGES Y
+NODES Y
+SHAPES Y
+DIMENSIONS Y
+TEXT Y
+AREA_PARTS Y
+AREA_PINS Y
+AREA_TRACES Y
+AREA_VIAS Y
+AREA_TACKS Y
+AREA_UNROUTED Y
+AREA_EDGES Y
+AREA_NODES Y
+AREA_SHAPES Y
+AREA_DIMENSIONS Y
+AREA_TEXT Y
+}
+VISIBILITY DATA
+{
+PADS Y
+TRACKS Y
+VIAS Y
+COPPER Y
+LINES Y
+TEXT Y
+ERRORS Y
+CLUSTER Y
+TOP_COMPONENT Y
+BOTTOM_COMPONENT Y
+SELECTION_COLOR 15
+HIGHLIGHT_COLOR 14
+FIXED_COLOR 3
+}
+*MISC*      MISCELLANEOUS PARAMETERS
+*REMARK*    PARENT_KEYWORD PARENT_VALUE
+*REMARK*  [ {
+*REMARK*       CHILD_KEYWORD CHILD_VALUE
+*REMARK*     [ CHILD_KEYWORD CHILD_VALUE
+*REMARK*     [ {
+*REMARK*          GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...]
+*REMARK*       } ]]
+*REMARK*    } ]
+RULES_SECTION PARENT
+{
+DESIGN RULES
+{
+RULE_SET (1)
+{
+FOR :
+{
+DEFAULT :
+}
+AGAINST :
+{
+DEFAULT :
+}
+LAYER 0
+CLEARANCE_RULE :
+{
+TRACK_TO_TRACK 342900
+VIA_TO_TRACK 342900
+VIA_TO_VIA 342900
+PAD_TO_TRACK 342900
+PAD_TO_VIA 342900
+PAD_TO_PAD 342900
+SMD_TO_TRACK 342900
+SMD_TO_VIA 342900
+SMD_TO_PAD 342900
+SMD_TO_SMD 342900
+COPPER_TO_TRACK 342900
+COPPER_TO_VIA 342900
+COPPER_TO_PAD 342900
+COPPER_TO_SMD 342900
+TEXT_TO_TRACK 342900
+TEXT_TO_VIA 342900
+TEXT_TO_PAD 342900
+TEXT_TO_SMD 342900
+OUTLINE_TO_TRACK 342900
+OUTLINE_TO_VIA 342900
+OUTLINE_TO_PAD 342900
+OUTLINE_TO_SMD 342900
+OUTLINE_TO_COPPER 342900
+DRILL_TO_TRACK 342900
+DRILL_TO_VIA 342900
+DRILL_TO_PAD 342900
+DRILL_TO_SMD 342900
+DRILL_TO_COPPER 342900
+SAME_NET_SMD_TO_VIA 228600
+SAME_NET_SMD_TO_CRN 228600
+SAME_NET_VIA_TO_VIA 228600
+SAME_NET_PAD_TO_CRN 228600
+MIN_TRACK_WIDTH 457200
+REC_TRACK_WIDTH 762000
+MAX_TRACK_WIDTH 952500
+DRILL_TO_DRILL 228600
+BODY_TO_BODY 228600
+SAME_NET_TRACK_TO_CRN 0
+}
+}
+RULE_SET (2)
+{
+FOR :
+{
+DEFAULT :
+}
+AGAINST :
+{
+DEFAULT :
+}
+LAYER 0
+HIGH_SPEED_RULE :
+{
+MIN_LENGTH 0
+MAX_LENGTH 1904999936
+STUB_LENGTH 0
+PARALLEL_LENGTH 38100000
+PARALLEL_GAP 7620000
+TANDEM_LENGTH 38100000
+TANDEM_GAP 7620000
+MIN_DELAY 0.000000
+MAX_DELAY 10.000000
+MIN_CAPACITANCE 0.000000
+MAX_CAPACITANCE 10.000000
+MIN_IMPEDANCE 50.000000
+MAX_IMPEDANCE 150.000000
+SHIELD_NET *
+SHIELD_GAP 7620000
+MATCH_LENGTH_TOLERANCE 7620000
+}
+}
+RULE_SET (3)
+{
+FOR :
+{
+DEFAULT :
+}
+AGAINST :
+{
+DEFAULT :
+}
+LAYER 0
+ROUTE_RULE :
+{
+LENGTH_MINIMIZATION_TYPE 1
+VIA_SHARE Y
+TRACE_SHARE Y
+AUTO_ROUTE Y
+RIPUP Y
+SHOVE Y
+ROUTE_PRIORITY 3
+VALID_LAYER 2
+VALID_VIA_TYPE STANDARDVIA
+}
+}
+}
+}
+*MISC*      MISCELLANEOUS PARAMETERS
+ATTRIBUTES DICTIONARY
+{
+ATTRIBUTE Rules.Fanout.Alignment
+{
+TYPE LIST N
+{
+Aligned
+Alternate
+}
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Alignment.Multi-Row
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Direction
+{
+TYPE LIST N
+{
+Inside
+Outside
+Both Sides
+}
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.ViaSpacing
+{
+TYPE LIST N
+{
+Use Grid
+Trace
+Trace
+}
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Sharing.Pin
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Sharing.SMD
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Sharing.Via
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Sharing.Trace
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Nets.Plane
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Nets.Signal
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Nets.UnusedPins
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Length.Unlimited
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.Length.Maximum
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 2000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.AlignmentBGA
+{
+TYPE LIST N
+{
+Quadrant
+Diagonal
+X-pattern
+}
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.DirectionBGA
+{
+TYPE LIST N
+{
+Clockwise
+Counterclockwise
+}
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Fanout.DirectionBGAstaggered
+{
+TYPE LIST N
+{
+Horizontal
+Vertical
+}
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.PadEntry.Side
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.PadEntry.Corner
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.PadEntry.AnyAngle
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.PadEntry.Soft
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.ViaAtSMD
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.ViaAtSMD.FitInside
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.ViaAtSMD.Center
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.ViaAtSMD.Ends
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Trace.Trace
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Via.Trace
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Via.Via
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Pad.Trace
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Pad.Via
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Pad.Pad
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.SMD.Trace
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.SMD.Via
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.SMD.Pad
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.SMD.SMD
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Copper.Trace
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Copper.Via
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Copper.Pad
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Copper.SMD
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Text.Trace
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Text.Via
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Text.Pad
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Text.SMD
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Board.Trace
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Board.Via
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Board.Pad
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Board.SMD
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Drill.Trace
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Drill.Via
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Drill.Pad
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Clearance.Drill.SMD
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.SameNet.SMD.Via
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.SameNet.SMD.Crn
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.SameNet.Via.Via
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.SameNet.Pad.Crn
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.SameNet.Trace.Crn
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 1000.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Width.Minimum
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 250.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Width.Recommended
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 250.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Rules.Width.Maximum
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 250.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Value
+{
+TYPE FREETEXT N
+INHERITANCE PART PARTTYPE
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE Tolerance
+{
+TYPE FREETEXT N
+INHERITANCE PART PARTTYPE
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE Part Number
+{
+TYPE FREETEXT N
+INHERITANCE PART PARTTYPE
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM N
+HIDDEN N
+}
+ATTRIBUTE Description
+{
+TYPE FREETEXT N
+INHERITANCE PART PARTTYPE DECAL
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM N
+HIDDEN N
+}
+ATTRIBUTE Cost
+{
+TYPE FREETEXT N
+INHERITANCE PART PARTTYPE
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM N
+HIDDEN N
+}
+ATTRIBUTE Manufacturer #1
+{
+TYPE FREETEXT N
+INHERITANCE PART PARTTYPE
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM N
+HIDDEN N
+}
+ATTRIBUTE Manufacturer #2
+{
+TYPE FREETEXT N
+INHERITANCE PART PARTTYPE
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM N
+HIDDEN N
+}
+ATTRIBUTE PowerGround
+{
+TYPE BOOLEAN
+INHERITANCE NET NETCLASS PCB
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE Voltage
+{
+TYPE QUANTITY
+QUANTITY Voltage
+ABBR V
+UNIT Volt
+MIN -100kV
+MAX 100kV
+INHERITANCE NET NETCLASS
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE Geometry.Height
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 25000.00mil
+INHERITANCE PCB
+INHERITANCE PART PARTTYPE DECAL
+ECO_REGISTRATION N
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE DFT.Nail Count Per Net
+{
+TYPE INTEGER
+MIN 0
+MAX 1000
+INHERITANCE NET NETCLASS PCB
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE DFT.Nail Diameter
+{
+TYPE FREETEXT N
+INHERITANCE PIN
+INHERITANCE VIA
+ECO_REGISTRATION N
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE DFT.Nail Number
+{
+TYPE FREETEXT N
+INHERITANCE PIN
+INHERITANCE VIA
+ECO_REGISTRATION N
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE HyperLynx.Model
+{
+TYPE FREETEXT N
+INHERITANCE PART PARTTYPE
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE HyperLynx.Model File
+{
+TYPE FREETEXT N
+INHERITANCE PART PARTTYPE
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE HyperLynx.Sim Direction
+{
+TYPE LIST N
+{
+SIM_BOTH
+SIM_IN
+SIM_OUT
+}
+INHERITANCE PIN
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE HyperLynx.Frequency
+{
+TYPE QUANTITY
+QUANTITY Frequency
+ABBR Hz
+UNIT Hertz
+MIN 0Hz
+MAX 1000GHz
+INHERITANCE NET NETCLASS
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE HyperLynx.Duty Cycle
+{
+TYPE QUANTITY
+QUANTITY
+ABBR %
+UNIT percent
+MIN 0%
+MAX 100%
+INHERITANCE NET NETCLASS
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE HyperLynx.Signal Type
+{
+TYPE LIST N
+{
+Address
+Analog High Speed
+Analog Low Speed
+Clock
+Data
+Do Not Analyze
+Power Supply
+Strobe
+}
+INHERITANCE NET NETCLASS
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE HyperLynx.Default IC.Model
+{
+TYPE FREETEXT N
+INHERITANCE NET NETCLASS
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE HyperLynx.Default IC.Model File
+{
+TYPE FREETEXT N
+INHERITANCE NET NETCLASS
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE HyperLynx.Default IC.Model Pin
+{
+TYPE FREETEXT N
+INHERITANCE NET NETCLASS
+ECO_REGISTRATION Y
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE Strategy.Fanout.Pass
+{
+TYPE LIST N
+{
+No
+Yes
+Done
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Fanout.Protect
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Fanout.Pause
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Fanout.Intensity
+{
+TYPE LIST N
+{
+Low
+Medium
+High
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Fanout.Priority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PART
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Fanout.PlanePriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Fanout.DiffPairPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Fanout.MLGPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PINPAIR GROUP
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Patterns.Pass
+{
+TYPE LIST N
+{
+No
+Yes
+Done
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Patterns.Protect
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Patterns.Pause
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Patterns.Intensity
+{
+TYPE LIST N
+{
+Low
+Medium
+High
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Patterns.Priority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PART
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Patterns.PlanePriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Patterns.DiffPairPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Patterns.MLGPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PINPAIR GROUP
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Route.Pass
+{
+TYPE LIST N
+{
+No
+Yes
+Done
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Route.Protect
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Route.Pause
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Route.Intensity
+{
+TYPE LIST N
+{
+Low
+Medium
+High
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Route.Priority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PART
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Route.PlanePriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Route.DiffPairPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Route.MLGPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PINPAIR GROUP
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Optimize.Pass
+{
+TYPE LIST N
+{
+No
+Yes
+Done
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Optimize.Protect
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Optimize.Pause
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Optimize.Intensity
+{
+TYPE LIST N
+{
+Low
+Medium
+High
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Optimize.Priority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PART
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Optimize.PlanePriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Optimize.DiffPairPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Optimize.MLGPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PINPAIR GROUP
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Miters.Pass
+{
+TYPE LIST N
+{
+No
+Yes
+Done
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Miters.Protect
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Miters.Pause
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Miters.Intensity
+{
+TYPE LIST N
+{
+Low
+Medium
+High
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Miters.Priority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PART
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Miters.PlanePriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Miters.DiffPairPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Miters.MLGPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PINPAIR GROUP
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.TestPoint.Pass
+{
+TYPE LIST N
+{
+No
+Yes
+Done
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.TestPoint.Protect
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.TestPoint.Pause
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.TestPoint.Intensity
+{
+TYPE LIST N
+{
+Low
+Medium
+High
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.TestPoint.Priority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PART
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.TestPoint.PlanePriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.TestPoint.DiffPairPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.TestPoint.MLGPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PINPAIR GROUP
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Center.Pass
+{
+TYPE LIST N
+{
+No
+Yes
+Done
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Center.Protect
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Center.Pause
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Center.Intensity
+{
+TYPE LIST N
+{
+Low
+Medium
+High
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Center.PlanePriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Center.Priority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PART
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Center.DiffPairPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Center.MLGPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PINPAIR GROUP
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Tune.Pass
+{
+TYPE LIST N
+{
+No
+Yes
+Done
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Tune.Protect
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Tune.Pause
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Tune.Intensity
+{
+TYPE LIST N
+{
+Low
+Medium
+High
+}
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Tune.PlanePriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Tune.Priority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PART
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Tune.DiffPairPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET
+INHERITANCE PINPAIR
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Strategy.Tune.MLGPriority
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE NET NETCLASS PCB
+INHERITANCE PINPAIR GROUP
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.FormatId
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.ChipLength
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.ChipWidth
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.ChipHeight
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.WBRules.MinLength
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.WBRules.MaxLength
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.WBRules.WToWDistance
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.WBRules.WBtoPad
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.WBRules.MaxAngle
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.SBPCount
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.SBP1
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.CBPCount
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.CBP1
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.WBCount
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.WB1
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.SBPGuideCount
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.SBPGuide1
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DIE.CBPAssignment1
+{
+TYPE FREETEXT N
+INHERITANCE DECAL
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE AutoDimensioning.Marker_Shape
+{
+TYPE FREETEXT N
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE AutoDimensioning.Text_NumberPrecision
+{
+TYPE FREETEXT N
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE AutoDimensioning.Text_AngularPrecision
+{
+TYPE FREETEXT N
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE AutoDimensioning.Text_Suffix
+{
+TYPE FREETEXT N
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE AutoDimensioning.Text_Layer
+{
+TYPE INTEGER
+MIN 0
+MAX 250
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE AutoDimensioning.Line_Layer
+{
+TYPE INTEGER
+MIN 0
+MAX 250
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE AutoDimensioning.Preview_Type
+{
+TYPE INTEGER
+MIN 1
+MAX 5
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Placement.Grid.Use
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Placement.Grid.X
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 2000.00mil
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Placement.Grid.Y
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 2000.00mil
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Accordion.Amplitude.Min
+{
+TYPE INTEGER
+MIN 3
+MAX 300
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Accordion.Amplitude.Max
+{
+TYPE INTEGER
+MIN 4
+MAX 300
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Accordion.Gap.Min
+{
+TYPE INTEGER
+MIN 1
+MAX 10
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Accordion.HierarchyLevel
+{
+TYPE INTEGER
+MIN 1
+MAX 8
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Accordion.Miters.Arcs
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Accordion.Miters.Ratio
+{
+TYPE FLOAT
+MIN 0.5
+MAX 250
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Routing.MaxChannelWidth
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN 0.00mil
+MAX 10000.00mil
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Routing.SoftLengthRrules
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Routing.MeanderBeforeTune
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Routing.ExtraLengthPercent
+{
+TYPE INTEGER
+MIN 0
+MAX 100
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Routing.MitersArcs
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE MatchLength.Name
+{
+TYPE FREETEXT N
+INHERITANCE NET NETCLASS
+INHERITANCE PINPAIR GROUP
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Planning.Scheduled
+{
+TYPE BOOLEAN
+INHERITANCE NET
+ECO_REGISTRATION Y
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Library.Timestamp
+{
+TYPE FREETEXT N
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Design.Timestamp
+{
+TYPE FREETEXT N
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DiffPair.RestrictPairTuneInGap
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DiffPair.RestrictSmallAccordionsInPairs
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DiffPair.TunePairsToZeroTolerance
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DiffPair.MinControlledLength
+{
+TYPE FLOAT
+MIN 20
+MAX 100
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE DiffPair.MaxIrregularLength
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE CAM.Solder mask.Adjust
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN -250.00mil
+MAX 250.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+INHERITANCE VIA
+ECO_REGISTRATION N
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE CAM.Paste mask.Adjust
+{
+TYPE QUANTITY
+QUANTITY Size/Dimension
+ABBR
+UNIT
+MIN -250.00mil
+MAX 250.00mil
+INHERITANCE PCB
+INHERITANCE PART DECAL
+INHERITANCE VIA
+ECO_REGISTRATION N
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE CAM.Apply Oversize To All Pads
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY N
+SYSTEM Y
+HIDDEN N
+}
+ATTRIBUTE CHK.Use Visible Workspace Box for Latium Checking
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY N
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Single Sided Board
+{
+TYPE BOOLEAN
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY N
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Guard.BandColor
+{
+TYPE INTEGER
+MIN 0
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Blaze.TestPoint.Color
+{
+TYPE INTEGER
+MIN 0
+MAX 100
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+ATTRIBUTE Blaze.Thermal.Color
+{
+TYPE INTEGER
+MIN 0
+MAX 100
+INHERITANCE PCB
+ECO_REGISTRATION N
+READONLY Y
+SYSTEM Y
+HIDDEN Y
+}
+}
+ATTRIBUTE VALUES
+{
+PCB DEFAULT
+{
+Accordion.HierarchyLevel 8
+Accordion.Amplitude.Max 30
+Accordion.Amplitude.Min 3
+Accordion.Gap.Min 1
+Accordion.Miters.Arcs No
+Accordion.Miters.Ratio 1.5
+AutoDimensioning.Line_Layer 24
+AutoDimensioning.Marker_Shape YYNNNY
+AutoDimensioning.Preview_Type 1
+AutoDimensioning.Text_AngularPrecision 0 0 0
+AutoDimensioning.Text_Layer 24
+AutoDimensioning.Text_NumberPrecision 0 1 2
+AutoDimensioning.Text_Suffix mil##mm##"
+Blaze.TestPoint.Color 8
+Blaze.Thermal.Color 8
+"CAM.Apply Oversize To All Pads" Yes
+DiffPair.MaxIrregularLength 500.00mil
+DiffPair.MinControlledLength 80
+DiffPair.RestrictPairTuneInGap No
+DiffPair.RestrictSmallAccordionsInPairs No
+DiffPair.TunePairsToZeroTolerance Yes
+Guard.BandColor 7
+Placement.Grid.Use No
+Placement.Grid.X 100.00mil
+Placement.Grid.Y 100.00mil
+Routing.ExtraLengthPercent 100
+Routing.MaxChannelWidth 100.00mil
+Routing.MeanderBeforeTune Yes
+Routing.MitersArcs No
+Routing.SoftLengthRrules Yes
+Rules.ViaAtSMD No
+Rules.Fanout.Alignment Alternate
+Rules.Fanout.AlignmentBGA Quadrant
+Rules.Fanout.Direction Both Sides
+Rules.Fanout.DirectionBGA 45
+Rules.Fanout.DirectionBGAstaggered Horizontal
+Rules.Fanout.ViaSpacing Use Grid
+Rules.Fanout.Alignment.Multi-Row Yes
+Rules.Fanout.Length.Maximum 250.00mil
+Rules.Fanout.Length.Unlimited Yes
+Rules.Fanout.Nets.Plane Yes
+Rules.Fanout.Nets.Signal No
+Rules.Fanout.Nets.UnusedPins No
+Rules.Fanout.Sharing.Pin Yes
+Rules.Fanout.Sharing.SMD Yes
+Rules.Fanout.Sharing.Trace No
+Rules.Fanout.Sharing.Via Yes
+Rules.PadEntry.AnyAngle Yes
+Rules.PadEntry.Corner Yes
+Rules.PadEntry.Side Yes
+Rules.PadEntry.Soft Yes
+Rules.ViaAtSMD.Center Yes
+Rules.ViaAtSMD.Ends Yes
+Rules.ViaAtSMD.FitInside Yes
+Strategy.Center.Intensity Low
+Strategy.Center.Pass No
+Strategy.Center.Pause No
+Strategy.Center.PlanePriority 0
+Strategy.Center.Priority 1
+Strategy.Center.Protect No
+Strategy.Fanout.Intensity Medium
+Strategy.Fanout.Pass No
+Strategy.Fanout.Pause No
+Strategy.Fanout.PlanePriority 0
+Strategy.Fanout.Priority 1
+Strategy.Fanout.Protect No
+Strategy.Miters.Intensity Low
+Strategy.Miters.Pass No
+Strategy.Miters.Pause No
+Strategy.Miters.PlanePriority 0
+Strategy.Miters.Priority 1
+Strategy.Miters.Protect No
+Strategy.Optimize.Intensity Low
+Strategy.Optimize.Pass Done
+Strategy.Optimize.Pause No
+Strategy.Optimize.PlanePriority 0
+Strategy.Optimize.Priority 1
+Strategy.Optimize.Protect No
+Strategy.Patterns.Intensity Medium
+Strategy.Patterns.Pass No
+Strategy.Patterns.Pause No
+Strategy.Patterns.PlanePriority 0
+Strategy.Patterns.Priority 1
+Strategy.Patterns.Protect No
+Strategy.Route.Intensity Medium
+Strategy.Route.Pass Done
+Strategy.Route.Pause No
+Strategy.Route.PlanePriority 0
+Strategy.Route.Priority 1
+Strategy.Route.Protect No
+Strategy.TestPoint.Intensity Low
+Strategy.TestPoint.Pass No
+Strategy.TestPoint.Pause No
+Strategy.TestPoint.PlanePriority 0
+Strategy.TestPoint.Priority 1
+Strategy.TestPoint.Protect No
+Strategy.Tune.Intensity Medium
+Strategy.Tune.Pass No
+Strategy.Tune.Pause No
+Strategy.Tune.PlanePriority 0
+Strategy.Tune.Priority 1
+Strategy.Tune.Protect No
+}
+}
+*REMARK*    PARENT_KEYWORD PARENT_VALUE
+*REMARK*  [ {
+*REMARK*       CHILD_KEYWORD CHILD_VALUE
+*REMARK*     [ CHILD_KEYWORD CHILD_VALUE
+*REMARK*     [ {
+*REMARK*          GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...]
+*REMARK*       } ]]
+*REMARK*    } ]
+REUSE_RULES_SECTION PARENT
+{
+NET_CLASS DATA
+GROUP DATA
+DESIGN RULES
+{
+}
+}
+*END*

 /Modules/Universal/INPUTUNI01A/CAM_PROFI/BOARD.PHO
 ,0 → 1,376
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 /Modules/Universal/INPUTUNI01A/CAM_PROFI/T1.PHO
 ,0 → 1,2249
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 /Modules/Universal/INPUTUNI01A/CAM_PROFI/DRILL.DRL
 ,0 → 1,101
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 /Modules/Universal/INPUTUNI01A/CAM_PROFI/M2.PHO
 ,0 → 1,515
+*
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 /Modules/Universal/INPUTUNI01A/CAM_PROFI/V2.PHO
 ,0 → 1,1293
+*
+*
+G04 PADS9.0.2 Build Number: 372616 generated Gerber (RS-274-X) file*
+G04 PC Version=2.1*
+*
+%IN "INPUTUNI01.pcb"*%
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+*
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+G04 PC Aperture Table*
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+G04 Layer Name INPUTUNI01.pcb - circuitry*
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