/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/gtime.ipf
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/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/gtime.xise
9,10 → 9,10
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL">
47,7 → 47,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
73,7 → 73,7
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/S3AN01B.ucf
125,8 → 125,8
NET "SD1AN" LOC = P55 |IOSTANDARD = LVPECL_33;
NET "SD1BP" LOC = P59 |IOSTANDARD = LVCMOS33 ;
NET "SD1BN" LOC = P57 |IOSTANDARD = LVCMOS33 ;
NET "SD2AP" LOC = P124 |IOSTANDARD = LVCMOS33 ;
NET "SD2AN" LOC = P126 |IOSTANDARD = LVCMOS33 ;
NET "SD2AP" LOC = P124 |IOSTANDARD = LVDS_33 ;
NET "SD2AN" LOC = P126 |IOSTANDARD = LVDS_33 ;
NET "SD2BP" LOC = P131 |IOSTANDARD = LVCMOS33 ;
NET "SD2BN" LOC = P129 |IOSTANDARD = LVCMOS33 ;
 
/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/gtime.vhd
117,29 → 117,38
 
architecture gtime_a of gtime is
 
function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable mybcd : std_logic_vector(11 downto 0) := (others => '0');
variable bint : std_logic_vector(7 downto 0) := bin;
variable mybcd : std_logic_vector(19 downto 0) := (others => '0');
variable bint : std_logic_vector(15 downto 0) := bin;
begin
for i in 0 to 7 loop -- repeating 8 times.
mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits.
mybcd(0) := bint(7);
bint(7 downto 1) := bint(6 downto 0);
for i in 0 to 15 loop -- repeating 16 times.
mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits.
mybcd(0) := bint(15);
bint(15 downto 1) := bint(14 downto 0);
bint(0) :='0';
 
 
if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
end if;
 
if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
end if;
 
if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
end if;
 
if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
end if;
 
if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
end if;
 
end loop;
return mybcd;
149,16 → 158,17
-- LED Demo Signals
-- ----------------
 
signal Counter: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary)
signal CounterMaxcount: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary)
signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary)
signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
signal CounterMaxcount: unsigned(14 downto 0) := "000000000000000"; -- Main Counter 10 kHz, max. 327.67 MHz (binary)
signal Bar: unsigned(7 downto 0) := X"00"; -- Register for Bar output (binary)
 
signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz)
 
-- LED Display
-- -----------
 
signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input
signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
signal HalfFreq: std_logic_vector(31 downto 0);
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
signal Enable: std_logic;
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
173,10 → 183,7
begin
 
-- Basic LED Blinking Test
-- =======================
 
-- LED Bar Counter
-- Counter
process (LO_CLOCK)
begin
191,8 → 198,8
end if;
end if;
if (State = 1) then
Number(15 downto 0) <= std_logic_vector(Counter(15 downto 0));
Number(31 downto 16) <= std_logic_vector(CounterMaxcount(15 downto 0));
Freq(15 downto 0) <= std_logic_vector("00"&Counter);
Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount);
end if;
if (State = 2) then
CounterMaxcount <= (others => '0');
203,13 → 210,15
end process;
 
 
-- Sampling 1PPS signal
process (LO_CLOCK)
begin
if rising_edge(LO_CLOCK) then
Decko <= DIPSW(0);
Decko <= B(22);
end if;
end process;
 
-- Automata for controling the Counter
process (LO_CLOCK)
begin
if rising_edge(LO_CLOCK) then
223,12 → 232,21
end if;
end process;
 
-- Coding to BCD for LED Display
-- HalfFreq(14 downto 0) <= Freq(15 downto 1);
-- HalfFreq(15) <= '0';
-- HalfFreq(30 downto 16) <= Freq(31 downto 17);
-- HalfFreq(31) <= '0';
-- Number(15 downto 0) <= to_bcd(HalfFreq(15 downto 0))(15 downto 0);
-- Number(35 downto 16) <= to_bcd(HalfFreq(31 downto 16))(19 downto 0);
Number(15 downto 0) <= Freq(15 downto 0);
Number(31 downto 16) <= Freq(31 downto 16);
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
LED(6 downto 4) <= (others => '0');
LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
 
-- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
 
-- LED Display (multiplexed)
-- =========================
 
316,7 → 334,7
DIFbuffer1 : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer,
-- "0"-"16"
IOSTANDARD => "DEFAULT")
port map (
325,6 → 343,14
O => LO_CLOCK -- Buffer output
);
 
OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => SD2AP, -- Diff_p output (connect directly to top-level port)
OB => SD2AN, -- Diff_n output (connect directly to top-level port)
I => LO_CLOCK -- Buffer input
);
-- Output Signal on SATA Connector
-- SD1AP <= 'Z';
333,8 → 359,8
SD1BN <= 'Z';
 
-- Input Here via SATA Cable
SD2AP <= 'Z';
SD2AN <= 'Z';
-- SD2AP <= 'Z';
-- SD2AN <= 'Z';
SD2BP <= 'Z';
SD2BN <= 'Z';