/Designs/MRAKOMER4/SW/irmrak4.c
90,7 → 90,7
setup_comparator(NC_NC_NC_NC);
setup_vref(FALSE);
// setup_oscillator(OSC_4MHZ|OSC_INTRC,+2); // Pokud je nutna kalibrace RCosc
setup_oscillator(OSC_8MHZ|OSC_INTRC);
setup_oscillator(OSC_4MHZ|OSC_INTRC);
 
delay_ms(1000);
restart_wdt();
190,7 → 190,7
j=0; while(output[j]!=0) { delay(SEND_DELAY); putc(output[j++]); }
sprintf(output,"%Ld ", to);
j=0; while(output[j]!=0) { delay(SEND_DELAY); putc(output[j++]); }
sprintf(output,"%u ", heat);
sprintf(output,"%u", heat);
j=0; while(output[j]!=0) { delay(SEND_DELAY); putc(output[j++]); }
sprintf(output,"%u\n\r\0", open);
j=0; while(output[j]!=0) { delay(SEND_DELAY); putc(output[j++]); }
/Designs/MRAKOMER4/SW/irmrak4.h
14,7 → 14,7
#FUSES NOFCMEN //Fail-safe clock monitor disabled
#FUSES NOIESO //Internal External Switch Over mode disabled
 
#use delay(clock=8000000)
#use delay(clock=4000000)
#use rs232(baud=2400,parity=N,xmit=PIN_B5,rcv=PIN_B2,bits=8)//,FORCE_SW)
//#use i2c(MASTER,SLOW,sda=PIN_B1,scl=PIN_B0,SMBUS)
 
/Designs/MRAKOMER4/SW/smb.c
48,6 → 48,8
mSCL_LOW(); // Clear SCL line
// enable_interrupts(GLOBAL);
delay_us( TBUF ); // Wait a few microseconds
toggle_dome();
}
//*********************************************************************************************
// STOP CONDITION ON SMBus
71,6 → 73,8
delay_us( TBUF ); // Stop condition setup time(Tsu:sto=4.0us min)
mSDA_HIGH(); // Set SDA line
// enable_interrupts(GLOBAL);
 
toggle_dome();
}
 
 
83,14 → 87,11
mSCL_HIGH(); // Set SCL line
delay_us( HIGHLEV ); // High Level of Clock Pulse
mSCL_LOW(); // Clear SCL line
 
toggle_dome();
 
delay_us( LOWLEV ); // Low Level of Clock Pulse
// mSDA_HIGH(); // Master release SDA line ,
// enable_interrupts(GLOBAL);
 
toggle_dome();
toggle_dome();
return;
}
 
105,13 → 106,10
if(input(SDA)) Ack_bit=1; // \ Read acknowledgment bit, save it in Ack_bit
else Ack_bit=0; // /
mSCL_LOW(); // Clear SCL line
 
toggle_dome();
 
delay_us( LOWLEV ); // Low Level of Clock Pulse
// enable_interrupts(GLOBAL);
 
toggle_dome();
toggle_dome();
return Ack_bit;
}
 
214,7 → 212,6
j=0x00;
i--;
}
toggle_dome();
}
 
shift=BitPosition-8; /*Get shift value for crc value*/
237,7 → 234,6
crc[i]+=temp;
}
shift--;
toggle_dome();
}
 
//Exclusive OR between pec and crc
245,7 → 241,7
{
pec[i] ^=crc[i];
}
} while(BitPosition>8);
} while(BitPosition>8);/*End of do-while*/
 
return pec[0];
}