/Designs/HAM Constructions/SDRX01A/DOC/SRC/mereniSDRX.txt
0,0 → 1,33
SDR01B:
Potlaceni zrcadla 50db zhruba naladeno na miste (vcetne fazove korekce na zvukovce).
 
Prahova hodnota:
150MHz generator
 
bez LNA mezni signal -120dbm.
 
pro 3db nad sumem -117dbm, s LNA01A -136dbm.
 
Problem, vyzarovani do anteny, norma -70dbm! Reseni izolator (izolacni zesilovac).
 
LNA:
 
VSWR bridge mereni vstupniho SWR LNA. (skoro vsechen signal se odrazi 3db rozdil oproti otevrenemu konci) 50 ohm vedeni.
 
Tracerem zmerena krivka propopustnosti, u mereneho kusu vubec neni tak spicata, jako v Upici, nebo v puvodni dokumentaci..
tj. vstupni propust je naladena jinam, zesileni je jenom 19 dB a to v pasmu od 150MHz do 200MHz, mezi 100-150 pokles ve smeru nizsich frekvenci o 10 db!
 
FR4 udajne zvysi sumove cislo. (o cca 0,5db)
 
modelovaci software:
serenade SV antsoft designer
 
"ARL design studio"
 
Anteny:
 
Eagg beater
Turnstyle,
Skrizene dipoly
 
 
/Designs/Measuring_instruments/ABL01A/SW/models/list.txt
0,0 → 1,3
http://www.cuspaceflight.co.uk/wiki/
 
 
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/XVC_FT220X02A.gvp
0,0 → 1,8
(gerbv-file-version! "2.0A")
(define-layer! 4 (cons 'filename "V1.PHO")(cons 'visible #t)(cons 'color #(0 50115 50115)))
(define-layer! 3 (cons 'filename "T2.PHO")(cons 'visible #t)(cons 'color #(30069 62194 26471)))
(define-layer! 2 (cons 'filename "M1.PHO")(cons 'visible #t)(cons 'color #(49601 0 57568)))
(define-layer! 1 (cons 'filename "DRILL.DRL")(cons 'visible #f)(cons 'color #(65535 32639 29555))(cons 'attribs (list (list 'autodetect 'Boolean 1) (list 'zero_supression 'Enum 0) (list 'units 'Enum 0) (list 'digits 'Integer 4))))
(define-layer! 0 (cons 'filename "BOARD.PHO")(cons 'visible #t)(cons 'color #(29555 29555 57054)))
(define-layer! -1 (cons 'filename "/home/kaklik/svnMLAB/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI")(cons 'visible #f)(cons 'color #(0 0 0)))
(set-render-type! 3)
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/TODO.txt
0,0 → 1,2
Nektere soucasky maji moc malou mezeru v odmaskovanych ploskach. a asi bude dochazet k jejich slevani pri letovani
 
/Modules/CommSerial/I2CHUB02A/SCH_PCB/untitled.brd
1,6 → 1,6
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="6.1">
<eagle version="6.3">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
427,7 → 427,7
<class number="0" name="default" width="0" drill="0">
</class>
</classes>
<designrules>
<designrules name="default">
<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
&lt;p&gt;
Die Standard-Design-Rules sind so gewählt, dass sie für
/Modules/CommSerial/I2CHUB02A/SCH_PCB/untitled.sch
1,12 → 1,12
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="6.1">
<eagle version="6.3">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
<setting verticaltext="up"/>
</settings>
<grid distance="0.05" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
<layers>
<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
/Modules/CommSerial/I2CHUB02A/TODO.txt
0,0 → 1,12
Pridat do popisu skrtaci tabulku s moznymi adresami. V HEX formatu. tj 0x70, 0x71 atd.
 
Nejde zvetsit chladici plosku pod stabilizatorem?
 
Zmensit tabulku moznych vystupnich napeti. (Smazat napis select nad tabulkou a u konektoru a jej nahradit OUT)
To by melo uvolnit misto na tabulku s moznou konfiguraci 4 adres.
 
Zkontrolovat velikost a orientaci pouzdra.
 
Trochu se obavam, jestli hrebinky nejsou moc blizko sroubu.
 
Podle datasheetu jsou zenerovy diody na datovych dratech zbytecne, protoze budic ma sam o sobe dost velkou ESD odolnost.