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/Modules/Clock/CLKGEN01B/DOC/CLKGEN01B.cs.pdf
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/Modules/Clock/CLKGEN01B/DOC/SRC/CLKGEN01B_Top_Big.jpg
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/Modules/Clock/CLKGEN01B/DOC/SRC/CLKGEN.cs.tex
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\begin{figure} [htbp]
\begin{center}
\includegraphics [width=80mm] {CLKGEN01B_Top_Big.jpg}
\includegraphics [width=80mm] {./img/CLKGEN01B_Top_Big.jpg}
\end{center}
\end{figure}
71,6 → 71,37
Modul je možné osadit i ručně, avšak je třeba dbát zvýšené opatrnosti kvůli elektrostatickým nábojům, neboť čipy Si570 je snadné poškodit.
\begin{figure} [htbp]
\begin{center}
\includegraphics [width=75mm] {./img/O1.png}
\includegraphics [width=75mm] {./img/O2.png}
\end{center}
\end{figure}
Osazení rezistorů R4 a R5 je volitelné pro případ, že je zbytený I$^2$C napěťový translátor U2.
\begin{tabular}{|c|c|c|c|}
\hline
Počet & Označení & Typ & Pouzdro \\
\hline
2 & C1,C2 & 10uF & Elyt-B \\
2 & C5,C6 & 100nF & 0805 \\
2 & D1,D2 & 1N4007 & SMA \\
2 & J1,J3 & JUMP2X3 & Pinheader \\
1 & J2 & SATA-connector & \\
2 & J4,J5 & JUMP2X1 & \\
1 & J6 & JUMP2X2 & \\
4 & R1,R2,R6,R7 & 4k7 & 0805 \\
1 & R3 & 200k & 0805 \\
2 & R4,R5 & 0R & 0805\\
2 & R10,R11 & 195R & 0805 \\
1 & U1 & LM1117MPX & SOT-23 \\
1 & U2 & Si570 & 5x7 mm \\
1 & U3 & GTL2002 & SO8 \\
\hline
\end{tabular}
\subsubsection{Nastavení}
Při připojení modulu k napájení generuje frekvenci nastavenou při výrobě v Silicon Labs. Je ale možné zpřesnit generovanou frekvenci. K tomu je nutné zprovoznit komunikaci přes I2C sběrnici.

/Modules/Clock/CLKGEN01B/DOC/SRC/img/CLKGEN01A_Bottom_Big.jpg
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/Modules/Clock/CLKGEN01B/DOC/SRC/img/DG8SAQ_emulator_Big.jpg
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/Modules/Clock/CLKGEN01B/DOC/SRC/img/O1.png
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/Modules/Clock/CLKGEN01B/DOC/SRC/img/O2.png
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