| 0,0 → 1,60 |
|---|
| --------------------------------------------- |
| -- glue incoming data (from MSB position) |
| -- |
| -- in: D1, D2, D3, D4... |
| -- out: D1D2, D3D4... |
| -- |
| -- |
| -- NOTE: hardwired for 8 + 8, beware if changing dimensions. swap_endianness only works on 8-bits |
| |
| library ieee; |
| use ieee.std_logic_1164.all; |
| |
| library utilities; |
| |
| entity glue_data is |
| port ( |
| |
| i_clk : in std_logic; |
| i_reset_n : in std_logic; |
| |
| i_data : in std_logic_vector( 7 downto 0 ); |
| i_valid : in std_logic; |
| o_enable : out std_logic; |
| |
| o_data : out std_logic_vector( 15 downto 0 ); |
| o_valid : out std_logic; |
| i_enable : in std_logic |
| |
| ); |
| |
| end glue_data; |
| |
| architecture behavioral of glue_data is |
| |
| component swap_endianness |
| port ( |
| i_data : in std_logic_vector; |
| o_data : out std_logic_vector |
| ); |
| end component; |
| |
| signal s_rst_n : std_logic; |
| signal s_packed_data : std_logic_vector( 15 downto 0 ); |
| |
| begin |
| |
| -- pack data: |
| pack_data_inst : entity utilities.pack_data |
| generic map ( G_OUTPUT_WIDTH => 16 ) |
| port map ( |
| i_clk => i_clk, i_reset_n => i_reset_n, |
| i_data => i_data, i_valid => i_valid, o_enable => o_enable, |
| o_data => s_packed_data, o_valid => o_valid, i_enable => i_enable ); |
| |
| -- and swap the bytes to have the first to come on MSB: |
| swap_endianness_inst : swap_endianness |
| port map( i_data => s_packed_data, o_data => o_data ); |
| |
| end architecture; |
| |