/Designs/HAM Constructions/SDRX02B/HDL/project_src/saw_generator_wrapper.vhd
0,0 → 1,47
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-- increase output every fourth clock cycle
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library sychro1;
 
entity saw_generator_wrapper is
generic (
G_INCREASE_EVERY_NTH : positive := 4
);
port (
i_clk : in std_logic;
i_rst : in std_logic;
o_valid : out std_logic;
o_data : out std_logic_vector
);
end saw_generator_wrapper;
 
architecture behavioral of saw_generator_wrapper is
signal s_modulo_counter_carry : std_logic;
begin
 
-- first counter that counts modulo G_INCREASE_EVERY_NTH to generate a valid signal for the second counter
-- and the output:
modulo_up_counter : entity sychro1.up_counter
generic map ( G_MIN_NUMBER => 0, G_MAX_NUMBER => G_INCREASE_EVERY_NTH - 1 )
port map ( i_clk => i_clk, i_rst => i_rst, i_valid => '1', o_data => open, o_carry => s_modulo_counter_carry );
-- the second counter:
main_up_counter : entity sychro1.up_counter_stdlv
generic map ( G_BITS => o_data'length, G_MIN_NUMBER => ( o_data'range => '0' ), G_MAX_NUMBER => ( o_data'range => '1' ) )
port map( i_clk => i_clk, i_rst => i_rst, i_valid => s_modulo_counter_carry, o_data => o_data, o_carry => open );
-- signal connection:
o_valid <= s_modulo_counter_carry;
end architecture;