/Designs/Laboratory_instruments/AtomicCounter/VHDL/AtomicCounter.ipf
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/Designs/Laboratory_instruments/AtomicCounter/VHDL/atomiccounter.bit
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/Designs/Laboratory_instruments/AtomicCounter/VHDL/atomiccounter.xsvf
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/Designs/Laboratory_instruments/AtomicCounter/VHDL/src/AtomicCounter.vhd
118,38 → 118,54
 
architecture AtomicCounter_a of AtomicCounter is
 
function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is
function to_bcd ( bin : std_logic_vector(31 downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable mybcd : std_logic_vector(19 downto 0) := (others => '0');
variable bint : std_logic_vector(15 downto 0) := bin;
variable mybcd : std_logic_vector(35 downto 0) := (others => '0');
variable bint : std_logic_vector(31 downto 0) := bin;
begin
for i in 0 to 15 loop -- repeating 16 times.
mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits.
mybcd(0) := bint(15);
bint(15 downto 1) := bint(14 downto 0);
for i in 0 to 31 loop -- repeating 16 times.
mybcd(35 downto 1) := mybcd(34 downto 0); --shifting the bits.
mybcd(0) := bint(31);
bint(31 downto 1) := bint(30 downto 0);
bint(0) :='0';
 
 
if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
if(i < 31 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
end if;
 
if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
if(i < 31 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
end if;
 
if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
if(i < 31 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
end if;
 
if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
if(i < 31 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
end if;
 
if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
if(i < 31 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
end if;
 
if(i < 31 and mybcd(23 downto 20) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(23 downto 20) := std_logic_vector(unsigned(mybcd(23 downto 20)) + 3);
end if;
 
if(i < 31 and mybcd(27 downto 24) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(27 downto 24) := std_logic_vector(unsigned(mybcd(27 downto 24)) + 3);
end if;
 
if(i < 31 and mybcd(31 downto 28) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(31 downto 28) := std_logic_vector(unsigned(mybcd(31 downto 28)) + 3);
end if;
 
if(i < 31 and mybcd(35 downto 32) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(35 downto 32) := std_logic_vector(unsigned(mybcd(35 downto 32)) + 3);
end if;
 
end loop;
return mybcd;
159,14 → 175,12
-- Counters
-- ----------------
 
signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
signal CounterMaxcount: unsigned(15 downto 0) := "0000000000000000"; -- Main Counter 10 kHz, max. 655.35 MHz (binary)
signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
 
 
-- LED Display
-- -----------
 
signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- Variable for bin/BCD conversion
signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
200,19 → 214,16
if rising_edge(LO_CLOCK) then
if (State = 3) or (State = 0) then
if Counter < MAXCOUNT-1 then
if DIPSW(7) = '0' then -- Half/Full frequency
Counter <= Counter + 1;
else
Counter <= (others => '0');
CounterMaxcount <= CounterMaxcount + 1;
Counter <= Counter + 2;
end if;
end if;
if (State = 1) then
Freq(15 downto 0) <= std_logic_vector("00"&Counter);
Freq(31 downto 16) <= std_logic_vector(CounterMaxcount);
Freq(31 downto 0) <= std_logic_vector(Counter);
end if;
if (State = 2) then
CounterMaxcount <= (others => '0');
Counter <= (others => '0');
end if;
end if;
247,17 → 258,11
process (Decko)
begin
if falling_edge(Decko) then
if DIPSW(7) = '0' then
NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0); -- Half frequency
NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0);
else
NumberPom(15 downto 0) <= to_bcd(Freq(14 downto 1)&"0")(15 downto 0); -- Full frequency
NumberPom(35 downto 16) <= to_bcd(Freq(30 downto 15))(19 downto 0);
end if;
Number(35 downto 0) <= to_bcd(Freq(31 downto 0));
end if;
end process;
 
Number(35 downto 0) <= NumberPom(35 downto 0);
-- Number(35 downto 0) <= NumberPom(35 downto 0);
LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
LED(6 downto 4) <= (others => '0');
/Designs/Laboratory_instruments/AtomicCounter/VHDL/src/S3AN01B.ucf
9,7 → 9,7
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;
 
NET "LO_CLOCK" TNM_NET = LO_CLOCK;
TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.0 ns HIGH 50%;
TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.2 ns HIGH 50%;
 
# For DCM connection across the whole chip
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;