| 9,10 → 9,10 |
|---|
| <!-- along with the project source files, is sufficient to open and --> |
| <!-- implement in ISE Project Navigator. --> |
| <!-- --> |
| <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> |
| <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> |
| </header> |
| |
| <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/> |
| <version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/> |
| |
| <files> |
| <file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL"> |
| 47,7 → 47,7 |
|---|
| <property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/> |
| <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/> |
| <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
| <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
| <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> |
| <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
| <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
| <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |