/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/gtime.ipf
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/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/gtime.xise
17,18 → 17,11
<files>
<file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="src/LIB/PS2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="src/S3AN01B.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ILA.cdc" xil_pn:type="FILE_CDC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
 
<properties>
/Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/gtime.vhd
17,7 → 17,6
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use WORK.PS2_pkg.ALL;
 
library UNISIM;
use UNISIM.vcomponents.all;
147,18 → 146,6
end to_bcd;
 
 
-- O1: ____|^^^^^^^|______
-- O2: _________|^^|______
-- t1 t2
-- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz
 
signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2
signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2
signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer
signal O1: std_logic := '0'; -- Output 1
signal O2: std_logic := '0'; -- Output 2
signal CTburst: unsigned(15 downto 0) := X"0000"; -- Pulse counter
-- LED Demo Signals
-- ----------------
 
177,44 → 164,12
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
 
-- PS/2 Port
-- ---------
 
-- Interface Signals
signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code
signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code
signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock)
signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code
 
-- Result
signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory)
 
-- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese
-- VGA Demo Signals
-- ----------------
signal LO_CLOCK: std_logic;
 
signal CLK: std_logic; -- Main Clock - global distribution network
signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG
signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network
signal VGA_Blank: boolean; -- Blank
signal VGA_Hsync: boolean; -- Horisontal Synchronisation
signal VGA_Vsync: boolean; -- Vertical Synchronisation
 
signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter
signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter
 
signal PinState: std_logic; -- For IB1 Port Test
signal Red: std_logic_vector(1 downto 0);
signal Green: std_logic_vector(1 downto 0);
signal Blue: std_logic_vector(1 downto 0);
 
-- ADDA
signal ADDA_DataIn: std_logic_vector(7 downto 0);
signal Decko: std_logic;
signal Disp: std_logic := '0';
signal LO_CLOCK: std_logic;
 
begin
 
-- Basic LED Blinking Test
221,11 → 176,8
-- =======================
 
-- LED Bar Counter
--!!!KAKL process (CLK100MHz)
process (LO_CLOCK)
begin
-- if rising_edge(CLK100MHz) then
if DIPSW(0)='1' then
if rising_edge(LO_CLOCK) then
if Counter < MAXCOUNT-1 then
Counter <= Counter + 1;
234,12 → 186,37
Bar <= Bar + 1;
end if;
end if;
end if;
end process;
 
process (LO_CLOCK)
begin
if rising_edge(LO_CLOCK) then
Decko <= DIPSW(0);
end if;
end process;
 
process (LO_CLOCK)
begin
if rising_edge(LO_CLOCK) then
if Decko = '1' then
if Disp = '0' then
Number(3 downto 0) <= std_logic_vector(Bar(3 downto 0));
Number(7 downto 4) <= std_logic_vector(Bar(7 downto 4));
Number(15 downto 8) <= (others=>'0');
Number(19 downto 16) <= (others=>'0');
Number(31 downto 20) <= (others=>'0'); --to_bcd(std_logic_vector(T1));
Disp <= '1';
end if;
else
Disp <= '0';
end if;
end if;
end process;
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
 
FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
-- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
 
-- LED Display (multiplexed)
-- =========================
280,7 → 257,7
end if;
end process;
 
-- BCD to 7 Segmet Decoder
-- HEX to 7 Segmet Decoder
-- -- A
-- | | F B
-- -- G
315,111 → 292,15
Number(31 downto 28) when Digits="10000000" else
"0000";
 
-- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0
-- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1
-- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2
-- "11111111";
-- Number(31 downto 28) <= Key(3 downto 0);
 
-- Number( 7 downto 0) <= std_logic_vector(BAR);
-- Number(31 downto 24) <= DIPSW;
 
-- PS/2 Port
-- =========
 
-- Instantiate PS/2 Keyboard Interface Handler
PS2_Keyboard: PS2 generic map(
CLKFREQ => 100_000_000
)
port map(
-- Main Clock
Clk => CLK100MHz,
 
-- PS/2 Port
PS2_Clk => PS2_CLK2,
PS2_Data => PS2_DATA2,
 
-- Result - valid when PS2_Valid
PS2_Code => PS2_Code,
PS2_Attribs => PS2_Attribs,
PS2_Valid => PS2_Valid,
 
-- Immediate State of Shifts
PS2_Shifts => PS2_Shifts
); -- PS2
 
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if PS2_Valid and PS2_Attribs(7)='0' then
-- Valid Scan Code with no Break Attribute
PS2_Result( 7 downto 0) <= PS2_Code;
PS2_Result(15 downto 8) <= PS2_Attribs;
end if;
if PS2_Valid and PS2_Attribs(7)='0' then
if PS2_Code = X"74" and T1<2000 then T1<=T1+1; end if;
if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if;
if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if;
if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if;
CT0<=X"0000";
O1<='0';
O2<='0';
CTburst<=X"0000";
end if;
 
if PB(0)='1' then
T1<=X"0000";
T2<=X"0000";
end if;
-- Display on 7seg.
-- Number(3 downto 0) <= (others=>'0');
-- Number(15 downto 4) <= (others=>'1'); --to_bcd(std_logic_vector(T2));
-- Number(19 downto 16) <= (others=>'0');
-- Number(31 downto 20) <= (others=>'1'); --to_bcd(std_logic_vector(T1));
if DIPSW(0)='1' then
if CT0>X"F000" then
CT0<=X"0000";
else
CT0<=CT0+1;
end if;
else
if CT0>X"0200" then
CT0<=X"0000";
else
CT0<=CT0+1;
end if;
end if;
if CTburst>2000 then
CTburst<=X"0000";
end if;
 
if (CTburst<1000) or (DIPSW(1)='0') then
if CT0=X"0000" then
O1<='1';
end if;
if CT0=T1+X"0000" then
O2<='1';
end if;
end if;
if CT0=T2+T1+X"0000" then
O1<='0';
O2<='0';
CTburst<=CTburst+1;
end if;
end if;
end process;
 
-- Display Result on LED
Number(3 downto 0) <= (others=>'0');
Number(15 downto 4) <= to_bcd(std_logic_vector(T2));
Number(19 downto 16) <= (others=>'0');
Number(31 downto 20) <= to_bcd(std_logic_vector(T1));
 
-- Test Diferencial In/Outs
-- Diferencial In/Outs
-- ========================
DIFbuffer1 : IBUFGDS
generic map (
435,8 → 316,8
 
-- Output Signal on SATA Connector
-- SD1AP <= Bar(0);
-- SD1AN <= Bar(1);
-- SD1AP <= 'Z';
-- SD1AN <= 'Z';
SD1BP <= 'Z';
SD1BN <= 'Z';
 
446,19 → 327,6
SD2BP <= 'Z';
SD2BN <= 'Z';
 
-- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them
-- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!!
DIF1P <= O1;
B(0) <= O1;
DIF1N <= not O1;
B(1) <= not O1;
DIF2P <= O2;
B(2) <= O2;
DIF2N <= not O2;
B(3) <= not O2;
VGA_R(0) <= O1;
VGA_R(1) <= O2;
 
-- Unused Signals
-- ==============