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| // |
| // Toto je popisný soubor pro popis obsahu adresáře |
| // |
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| [InfoShortDescription.en] |
| Modules with CPLD or FPGA |
| |
| [InfoShortDescription.cs] |
| Moduly s obvody CPLD nebo FPGA |
| |
| [InfoLongDescription.en] |
| Modules for work with CPLD (Complex Programmable |
| Logic Devices) or FPGA (Field Programmable Logic). |
| CPLDs are bigger brothers of well known GAL devices. |
| FPGA chips contain logic and routing resources |
| spread across the whole chip. |
| |
| [InfoLongDescription.cs] |
| Moduly pro práci s obvody programovatelné logiky |
| CPLD (Complex Logical Devices) nebo FPGA (Field |
| Programmable Logic). Obvody CPLD jsou |
| většími bratry obvodů GAL, Obvody FPGA mají |
| rozprostřenou logiku a propojení na celém čipu. |
| |
| [SortPreferences] |
| |
| [End] |
| /Modules/CPLD_FPGA/ISPLSI1016A/SCH/ISPLSI1016A.ASC |
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| 0,0 → 1,105 |
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| *PADS-PCB* |
| *PART* |
| C1 C-ELYT,10uF/6.3V@CE025X6 |
| C2 C,100nF@C0603 |
| D1 D,1N4007@DO41 |
| J10 JUMP2X11,JUMP2X11@JUMP2X11 |
| J11 JUMP2X11,JUMP2X11@JUMP2X11 |
| J7 JUMP2X11,JUMP2X11@JUMP2X11 |
| J8 JUMP2X11,JUMP2X11@JUMP2X11 |
| J9 JUMP2X3,JUMP2X3@JUMP2X3 |
| M1 PAD,HOLE_M3@HOLE_M3 |
| M2 PAD,HOLE_M3@HOLE_M3 |
| M3 PAD,HOLE_M3@HOLE_M3 |
| M4 PAD,HOLE_M3@HOLE_M3 |
| U3 PLCC44,ISPLSI1016@PLCC44 |
| |
| *NET* |
| *SIGNAL* VCC |
| C2.2 C1.A J10.12 J10.11 U3.34 J7.11 J7.12 U3.12 |
| D1.C J9.3 J9.4 |
| *SIGNAL* GND |
| U3.1 J8.11 J11.12 U3.23 J11.11 C1.C J9.1 J9.2 |
| J9.5 J9.6 C2.1 D1.A M2.1 M1.1 M3.1 M4.1 |
| J8.12 |
| *SIGNAL* N18760 |
| J7.2 U3.7 J7.1 |
| *SIGNAL* N18910 |
| J7.4 U3.8 J7.3 |
| *SIGNAL* N19060 |
| J7.6 U3.9 J7.5 |
| *SIGNAL* N19210 |
| J7.7 J7.8 U3.10 |
| *SIGNAL* N19360 |
| J7.10 U3.11 J7.9 |
| *SIGNAL* N19660 |
| J7.14 U3.13 J7.13 |
| *SIGNAL* N19810 |
| J7.15 J7.16 U3.14 |
| *SIGNAL* N19960 |
| J7.17 J7.18 U3.15 |
| *SIGNAL* N20110 |
| J7.20 U3.16 J7.19 |
| *SIGNAL* N20260 |
| J7.21 J7.22 U3.17 |
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| J8.2 J8.1 U3.6 |
| *SIGNAL* N20560 |
| U3.5 J8.3 J8.4 |
| *SIGNAL* N20710 |
| J8.5 U3.4 J8.6 |
| *SIGNAL* N20860 |
| U3.3 J8.7 J8.8 |
| *SIGNAL* N21010 |
| J8.10 J8.9 U3.2 |
| *SIGNAL* N21310 |
| J8.13 U3.44 J8.14 |
| *SIGNAL* N21460 |
| J8.15 J8.16 U3.43 |
| *SIGNAL* N21610 |
| J8.17 U3.42 J8.18 |
| *SIGNAL* N21760 |
| U3.41 J8.19 J8.20 |
| *SIGNAL* N21910 |
| J8.21 U3.40 J8.22 |
| *SIGNAL* N22060 |
| U3.39 J10.1 J10.2 |
| *SIGNAL* N22210 |
| J10.3 U3.38 J10.4 |
| *SIGNAL* N22360 |
| U3.37 J10.5 J10.6 |
| *SIGNAL* N22510 |
| J10.8 J10.7 U3.36 |
| *SIGNAL* N22660 |
| U3.35 J10.9 J10.10 |
| *SIGNAL* N22960 |
| U3.33 J10.13 J10.14 |
| *SIGNAL* N23110 |
| J10.16 J10.15 U3.32 |
| *SIGNAL* N23260 |
| J10.17 J10.18 U3.31 |
| *SIGNAL* N23410 |
| J10.19 U3.30 J10.20 |
| *SIGNAL* N23560 |
| U3.29 J10.21 J10.22 |
| *SIGNAL* N23710 |
| U3.18 J11.2 J11.1 |
| *SIGNAL* N23860 |
| J11.4 U3.19 J11.3 |
| *SIGNAL* N24010 |
| U3.20 J11.6 J11.5 |
| *SIGNAL* N24160 |
| J11.8 U3.21 J11.7 |
| *SIGNAL* N24310 |
| J11.10 J11.9 U3.22 |
| *SIGNAL* N24610 |
| U3.24 J11.14 J11.13 |
| *SIGNAL* N24760 |
| J11.15 J11.16 U3.25 |
| *SIGNAL* N24910 |
| J11.18 J11.17 U3.26 |
| *SIGNAL* N25060 |
| J11.20 U3.27 J11.19 |
| *SIGNAL* N25210 |
| J11.22 J11.21 U3.28 |
| *END* |
| /Modules/CPLD_FPGA/ISPLSI1016A/SCH/LATTICE.OLB |
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