/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/M1.PHO
47,24 → 47,23
*
G04 PC Aperture Table*
*
%ADD011C,0.06*%
%ADD012R,0.07X0.07*%
%ADD016C,0.04*%
%ADD024C,0.001*%
%ADD032R,0.08X0.08*%
%ADD033C,0.24622*%
%ADD041C,0.08*%
%ADD044R,0.05X0.05*%
%ADD066R,0.066X0.049*%
%ADD067R,0.049X0.066*%
%ADD068R,0.06X0.085*%
%ADD069C,0.075*%
%ADD052R,0.046X0.046*%
%ADD070C,0.15*%
%ADD071R,0.049X0.061*%
%ADD072R,0.061X0.049*%
%ADD073O,0.022X0.07*%
%ADD074R,0.0415X0.07299*%
%ADD075C,0.0415*%
%ADD100R,0.062X0.045*%
%ADD101R,0.045X0.062*%
%ADD102R,0.056X0.081*%
%ADD103C,0.071*%
%ADD104R,0.076X0.076*%
%ADD105C,0.076*%
%ADD106C,0.24213*%
%ADD107C,0.2*%
%ADD108R,0.045X0.057*%
%ADD109R,0.057X0.045*%
%ADD110O,0.018X0.066*%
%ADD111C,0.036*%
%ADD112R,0.0374X0.0689*%
%ADD113C,0.0374*%
*
*
*
83,47 → 82,18
G04 Layer Name XVC_FT220X01A.pcb - circuitry*
%LPD*%
*
G54D11*
G01X120000Y145000D03*
X246000D03*
G54D12*
X120000Y175000D03*
X246000D03*
G54D16*
X197000Y179000D03*
X212500Y141500D03*
X216500Y142000D03*
G54D24*
G54D32*
X218000Y211000D03*
X230000Y155000D03*
Y165000D03*
Y175000D03*
X191000Y169000D03*
Y179000D03*
X181000Y169000D03*
Y179000D03*
X171000Y169000D03*
Y179000D03*
G54D33*
X120000Y120000D03*
X240000D03*
Y200000D03*
X120000D03*
G54D41*
X208000Y211000D03*
X188000D03*
X168000D03*
X158000D03*
X138000D03*
G54D44*
X216000Y110000D03*
G54D52*
G01X216000Y110000D03*
X224000D03*
X220000Y118000D03*
X222000Y135000D03*
X214000D03*
X218000Y127000D03*
G54D66*
G54D70*
X142000Y136000D03*
Y184000D03*
G54D100*
X161500Y140200D03*
Y147800D03*
X153000Y140200D03*
134,23 → 104,47
Y139800D03*
X222000Y157200D03*
Y164800D03*
G54D67*
G54D101*
X172200Y187000D03*
X179800D03*
X192800Y159000D03*
X185200D03*
G54D68*
G54D102*
X215900Y202500D03*
X202100D03*
G54D69*
G54D103*
X161000Y165000D03*
Y155000D03*
X153000D03*
Y165000D03*
G54D70*
X142000Y136000D03*
Y184000D03*
G54D71*
G54D104*
X218000Y211000D03*
X230000Y155000D03*
Y165000D03*
Y175000D03*
X191000Y169000D03*
Y179000D03*
X181000Y169000D03*
Y179000D03*
X171000Y169000D03*
Y179000D03*
G54D105*
X208000Y211000D03*
X188000D03*
X168000D03*
X158000D03*
X138000D03*
G54D106*
X120000Y120000D03*
X240000D03*
Y200000D03*
X120000D03*
G54D107*
Y145000D03*
X246000D03*
X120000Y175000D03*
X246000D03*
G54D108*
X170200Y141000D03*
X177800D03*
X170200Y151000D03*
165,7 → 159,7
X154200D03*
X170200Y159000D03*
X177800D03*
G54D72*
G54D109*
X232000Y136200D03*
Y143800D03*
X222000Y149800D03*
178,7 → 172,7
Y115200D03*
X186000Y143200D03*
Y150800D03*
G54D73*
G54D110*
X215750Y172500D03*
X213250D03*
X210750D03*
195,7 → 189,11
X210750D03*
X213250D03*
X215750D03*
G54D74*
G54D111*
X197000Y179000D03*
X212500Y141500D03*
X216500Y142000D03*
G54D112*
X210087Y114000D03*
X195913D03*
X181087D03*
202,7 → 200,7
X166913D03*
X152087D03*
X137913D03*
G54D75*
G54D113*
X203000D03*
X174000D03*
X145000D03*
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/TODO.txt
1,2 → 1,15
Nektere soucasky maji moc malou mezeru v odmaskovanych ploskach. a asi bude dochazet k jejich slevani pri letovani
KAKLIK:
 
Nektere soucasky maji moc malou mezeru v odmaskovanych ploskach.
Asi bude dochazet k jejich slevani pri letovani.
 
MIHO:
 
Problematické souèatky jsem posunul.
Opravil jsem i CAM výstup (chybìlo odmaskování FIDU znaèek).
 
 
Pro pøíštì
----------
 
Na malé desce staèí po jedné FIDU znaèce.