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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser.ini
0,0 → 1,24
#ChipScope Pro Analyzer Configuration File
#Tue Jun 25 16:04:01 CEST 2013
OPEN_TARGET.host=localhost\:2542
xilinx_parallel.PORT=LPT1
previous_cable_name=xilinx_xvc
OPEN_TARGET.disableversioncheck=true
guiLocationY=14
guiLocationX=90
guiWidth=1448
guiHeight=907
previous_cable_cmd=open_target
lastParallelCable=xilinx_parallel3
projectDir=..\\ANALYSER
OPEN_TARGET.keylist=disableversioncheck host
xilinx_parallel.FREQUENCY=5000000
previous_cable_key=OPEN_TARGET
xilinx_parallel.keylist=FREQUENCY PORT
previous.defaultDirectory=..\\ANALYSER
openTarget.2=xilinx_parallel PORT\=LPT1 FREQUENCY\=2500000
openTarget.1=xilinx_platformusb PORT\=USB21 FREQUENCY\=6000000
debugOn=0
openTarget.0=xilinx_xvc host\=localhost\:2542 disableversioncheck\=true
project1=..\\ANALYSER\\Analyser_9_2048.cpj
project0=..\\ANALYSER\\Analyser_18_1024.cpj

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser_18_1024.cpj
0,0 → 1,1076
#ChipScope Pro Analyzer Project File, Version 3.0
#Tue Jun 25 09:46:51 CEST 2013
device.0.configFileDir=..\\BIN
device.0.configFilename=S3AN01_ChipScope_18x1024.bit
device.0.inserterCDCFileDir=
device.0.inserterCDCFilename=
deviceChain.deviceName0=XC3S50AN
deviceChain.iRLength0=6
deviceChain.name0=Trigger Setup
deviceIds=02610093
mdiAreaHeight=0.6990077177508269
mdiAreaHeightLast=0.6990077177508269
mdiCount=4
mdiDevice0=0
mdiDevice1=0
mdiDevice2=0
mdiDevice3=0
mdiType0=1
mdiType1=6
mdiType2=0
mdiType3=6
mdiUnit0=2
mdiUnit1=1
mdiUnit2=2
mdiUnit3=0
navigatorHeight=0.24807056229327454
navigatorHeightLast=0.2866593164277839
navigatorWidth=0.17472375690607736
navigatorWidthLast=0.14433701657458564
signalDisplayPath=0
unit.-1.-1.username=
unit.0.-1.username=
unit.0.0.0.HEIGHT0=0.3660856
unit.0.0.0.TriggerRow0=1
unit.0.0.0.TriggerRow1=1
unit.0.0.0.TriggerRow2=1
unit.0.0.0.WIDTH0=0.9940426
unit.0.0.0.X0=0.0
unit.0.0.0.Y0=0.0
unit.0.0.1.HEIGHT1=0.58161646
unit.0.0.1.WIDTH1=0.9940426
unit.0.0.1.X1=0.0
unit.0.0.1.Y1=0.3660856
unit.0.0.6.HEIGHT6=0.75594294
unit.0.0.6.WIDTH6=0.17021276
unit.0.0.6.X6=0.0025531915
unit.0.0.6.Y6=0.014263075
unit.0.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXX
unit.0.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXX
unit.0.0.MFBitsB0=000000000000000000000000
unit.0.0.MFBitsB1=000000000000000000000000
unit.0.0.MFCompareA0=0
unit.0.0.MFCompareA1=0
unit.0.0.MFCompareB0=999
unit.0.0.MFCompareB1=999
unit.0.0.MFCount=2
unit.0.0.MFDisplay0=0
unit.0.0.MFDisplay1=0
unit.0.0.MFEventType0=3
unit.0.0.MFEventType1=3
unit.0.0.RunMode=SINGLE RUN
unit.0.0.SQCondition=All Data
unit.0.0.SQContiguous0=0
unit.0.0.SequencerOn=0
unit.0.0.TCActive=0
unit.0.0.TCAdvanced0=0
unit.0.0.TCCondition0_0=M0
unit.0.0.TCCondition0_1=
unit.0.0.TCConditionType0=0
unit.0.0.TCCount=1
unit.0.0.TCEventCount0=1
unit.0.0.TCEventType0=3
unit.0.0.TCName0=TriggerCondition0
unit.0.0.TCOutputEnable0=0
unit.0.0.TCOutputHigh0=1
unit.0.0.TCOutputMode0=0
unit.0.0.coretype=VIO
unit.0.0.eventCount0=1
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unit.0.2.rep_trigger.clobber=1
unit.0.2.rep_trigger.dir=D\:\\MLAB\\Modules\\CPLD_FPGA\\XILINX_ChipScope\\MAKE\\BIN\\13.3
unit.0.2.rep_trigger.filename=waveform
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unit.0.2.rep_trigger.loggingEnabled=0
unit.0.2.rep_trigger.signals=All Signals/Buses
unit.0.2.samplesPerTrigger=1
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unit.0.2.waveform.posn.10.type=signal
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unit.0.2.waveform.posn.12.channel=12
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unit.0.2.waveform.posn.12.type=signal
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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser_9_2048.cpj
0,0 → 1,1076
#ChipScope Pro Analyzer Project File, Version 3.0
#Tue Jun 25 09:45:10 CEST 2013
device.0.configFileDir=..\\BIN
device.0.configFilename=S3AN01_ChipScope_9x2048.bit
device.0.inserterCDCFileDir=
device.0.inserterCDCFilename=
deviceChain.deviceName0=XC3S50AN
deviceChain.iRLength0=6
deviceChain.name0=Trigger Setup
deviceIds=02610093
mdiAreaHeight=0.6990077177508269
mdiAreaHeightLast=0.6990077177508269
mdiCount=4
mdiDevice0=0
mdiDevice1=0
mdiDevice2=0
mdiDevice3=0
mdiType0=1
mdiType1=6
mdiType2=0
mdiType3=6
mdiUnit0=2
mdiUnit1=1
mdiUnit2=2
mdiUnit3=0
navigatorHeight=0.24696802646085997
navigatorHeightLast=0.2866593164277839
navigatorWidth=0.17472375690607736
navigatorWidthLast=0.14433701657458564
signalDisplayPath=0
unit.-1.-1.username=
unit.0.-1.username=
unit.0.0.0.HEIGHT0=0.3660856
unit.0.0.0.TriggerRow0=1
unit.0.0.0.TriggerRow1=1
unit.0.0.0.TriggerRow2=1
unit.0.0.0.WIDTH0=0.9940426
unit.0.0.0.X0=0.0
unit.0.0.0.Y0=0.0
unit.0.0.1.HEIGHT1=0.58161646
unit.0.0.1.WIDTH1=0.9940426
unit.0.0.1.X1=0.0
unit.0.0.1.Y1=0.3660856
unit.0.0.6.HEIGHT6=0.75594294
unit.0.0.6.WIDTH6=0.17021276
unit.0.0.6.X6=0.0025531915
unit.0.0.6.Y6=0.014263075
unit.0.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXX
unit.0.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXX
unit.0.0.MFBitsB0=000000000000000000000000
unit.0.0.MFBitsB1=000000000000000000000000
unit.0.0.MFCompareA0=0
unit.0.0.MFCompareA1=0
unit.0.0.MFCompareB0=999
unit.0.0.MFCompareB1=999
unit.0.0.MFCount=2
unit.0.0.MFDisplay0=0
unit.0.0.MFDisplay1=0
unit.0.0.MFEventType0=3
unit.0.0.MFEventType1=3
unit.0.0.RunMode=SINGLE RUN
unit.0.0.SQCondition=All Data
unit.0.0.SQContiguous0=0
unit.0.0.SequencerOn=0
unit.0.0.TCActive=0
unit.0.0.TCAdvanced0=0
unit.0.0.TCCondition0_0=M0
unit.0.0.TCCondition0_1=
unit.0.0.TCConditionType0=0
unit.0.0.TCCount=1
unit.0.0.TCEventCount0=1
unit.0.0.TCEventType0=3
unit.0.0.TCName0=TriggerCondition0
unit.0.0.TCOutputEnable0=0
unit.0.0.TCOutputHigh0=1
unit.0.0.TCOutputMode0=0
unit.0.0.coretype=VIO
unit.0.0.eventCount0=1
unit.0.0.eventCount1=1
unit.0.0.port.-1.buscount=0
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unit.0.0.port.-1.s.0.alias=
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unit.0.0.port.-1.s.0.visible=1
unit.0.0.port.-1.s.1.alias=
unit.0.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.1.name=DataPort[1]
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unit.0.0.port.-1.s.1.visible=1
unit.0.0.port.-1.s.10.alias=
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unit.0.0.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.2.s.4.value=0100000000000000
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unit.0.0.port.2.s.5.value=0100000000000000
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unit.0.1.port.2.s.2.visible=1
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unit.0.2.browser_tree_state<Data\ Port>=0
unit.0.2.browser_tree_state<Trigger\ Ports>=0
unit.0.2.browser_tree_state<TriggerPort0>=1
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unit.0.2.plotBusY=
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unit.0.2.port.-1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.2.port.-1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.2.port.-1.s.7.orderindex=-1
unit.0.2.port.-1.s.7.visible=1
unit.0.2.port.-1.s.8.alias=P[8]
unit.0.2.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.-1.s.8.name=DataPort[8]
unit.0.2.port.-1.s.8.orderindex=-1
unit.0.2.port.-1.s.8.visible=1
unit.0.2.port.-1.s.9.alias=P[9]
unit.0.2.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.-1.s.9.name=DataPort[9]
unit.0.2.port.-1.s.9.orderindex=-1
unit.0.2.port.-1.s.9.visible=1
unit.0.2.port.0.b.0.alias=
unit.0.2.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
unit.0.2.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.b.0.name=TriggerPort0
unit.0.2.port.0.b.0.orderindex=-1
unit.0.2.port.0.b.0.radix=Hex
unit.0.2.port.0.b.0.signedOffset=0.0
unit.0.2.port.0.b.0.signedPrecision=0
unit.0.2.port.0.b.0.signedScaleFactor=1.0
unit.0.2.port.0.b.0.unsignedOffset=0.0
unit.0.2.port.0.b.0.unsignedPrecision=0
unit.0.2.port.0.b.0.unsignedScaleFactor=1.0
unit.0.2.port.0.b.0.visible=1
unit.0.2.port.0.buscount=1
unit.0.2.port.0.channelcount=24
unit.0.2.port.0.s.0.alias=P[0]
unit.0.2.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.0.name=TriggerPort0[0]
unit.0.2.port.0.s.0.orderindex=-1
unit.0.2.port.0.s.0.visible=1
unit.0.2.port.0.s.1.alias=P[1]
unit.0.2.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.1.name=TriggerPort0[1]
unit.0.2.port.0.s.1.orderindex=-1
unit.0.2.port.0.s.1.visible=1
unit.0.2.port.0.s.10.alias=P[10]
unit.0.2.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.10.name=TriggerPort0[10]
unit.0.2.port.0.s.10.orderindex=-1
unit.0.2.port.0.s.10.visible=1
unit.0.2.port.0.s.11.alias=P[11]
unit.0.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.11.name=TriggerPort0[11]
unit.0.2.port.0.s.11.orderindex=-1
unit.0.2.port.0.s.11.visible=1
unit.0.2.port.0.s.12.alias=P[12]
unit.0.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.12.name=TriggerPort0[12]
unit.0.2.port.0.s.12.orderindex=-1
unit.0.2.port.0.s.12.visible=1
unit.0.2.port.0.s.13.alias=P[13]
unit.0.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.13.name=TriggerPort0[13]
unit.0.2.port.0.s.13.orderindex=-1
unit.0.2.port.0.s.13.visible=1
unit.0.2.port.0.s.14.alias=P[14]
unit.0.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.14.name=TriggerPort0[14]
unit.0.2.port.0.s.14.orderindex=-1
unit.0.2.port.0.s.14.visible=1
unit.0.2.port.0.s.15.alias=P[15]
unit.0.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.15.name=TriggerPort0[15]
unit.0.2.port.0.s.15.orderindex=-1
unit.0.2.port.0.s.15.visible=1
unit.0.2.port.0.s.16.alias=P[16]
unit.0.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.16.name=TriggerPort0[16]
unit.0.2.port.0.s.16.orderindex=-1
unit.0.2.port.0.s.16.visible=1
unit.0.2.port.0.s.17.alias=P[17]
unit.0.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.17.name=TriggerPort0[17]
unit.0.2.port.0.s.17.orderindex=-1
unit.0.2.port.0.s.17.visible=1
unit.0.2.port.0.s.18.alias=P[18]
unit.0.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.18.name=TriggerPort0[18]
unit.0.2.port.0.s.18.orderindex=-1
unit.0.2.port.0.s.18.visible=1
unit.0.2.port.0.s.19.alias=P[19]
unit.0.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.19.name=TriggerPort0[19]
unit.0.2.port.0.s.19.orderindex=-1
unit.0.2.port.0.s.19.visible=1
unit.0.2.port.0.s.2.alias=P[2]
unit.0.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.2.name=TriggerPort0[2]
unit.0.2.port.0.s.2.orderindex=-1
unit.0.2.port.0.s.2.visible=1
unit.0.2.port.0.s.20.alias=P[20]
unit.0.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.20.name=TriggerPort0[20]
unit.0.2.port.0.s.20.orderindex=-1
unit.0.2.port.0.s.20.visible=1
unit.0.2.port.0.s.21.alias=P[21]
unit.0.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.21.name=TriggerPort0[21]
unit.0.2.port.0.s.21.orderindex=-1
unit.0.2.port.0.s.21.visible=1
unit.0.2.port.0.s.22.alias=P[22]
unit.0.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.22.name=TriggerPort0[22]
unit.0.2.port.0.s.22.orderindex=-1
unit.0.2.port.0.s.22.visible=1
unit.0.2.port.0.s.23.alias=P[23]
unit.0.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.23.name=TriggerPort0[23]
unit.0.2.port.0.s.23.orderindex=-1
unit.0.2.port.0.s.23.visible=1
unit.0.2.port.0.s.3.alias=P[3]
unit.0.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.3.name=TriggerPort0[3]
unit.0.2.port.0.s.3.orderindex=-1
unit.0.2.port.0.s.3.visible=1
unit.0.2.port.0.s.4.alias=P[4]
unit.0.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.4.name=TriggerPort0[4]
unit.0.2.port.0.s.4.orderindex=-1
unit.0.2.port.0.s.4.visible=1
unit.0.2.port.0.s.5.alias=P[5]
unit.0.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.5.name=TriggerPort0[5]
unit.0.2.port.0.s.5.orderindex=-1
unit.0.2.port.0.s.5.visible=1
unit.0.2.port.0.s.6.alias=P[6]
unit.0.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.6.name=TriggerPort0[6]
unit.0.2.port.0.s.6.orderindex=-1
unit.0.2.port.0.s.6.visible=1
unit.0.2.port.0.s.7.alias=P[7]
unit.0.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.7.name=TriggerPort0[7]
unit.0.2.port.0.s.7.orderindex=-1
unit.0.2.port.0.s.7.visible=1
unit.0.2.port.0.s.8.alias=P[8]
unit.0.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.8.name=TriggerPort0[8]
unit.0.2.port.0.s.8.orderindex=-1
unit.0.2.port.0.s.8.visible=1
unit.0.2.port.0.s.9.alias=P[9]
unit.0.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.2.port.0.s.9.name=TriggerPort0[9]
unit.0.2.port.0.s.9.orderindex=-1
unit.0.2.port.0.s.9.visible=1
unit.0.2.portcount=1
unit.0.2.rep_trigger.clobber=1
unit.0.2.rep_trigger.dir=D\:\\MLAB\\Modules\\CPLD_FPGA\\XILINX_ChipScope\\MAKE\\BIN\\13.3
unit.0.2.rep_trigger.filename=waveform
unit.0.2.rep_trigger.format=ASCII
unit.0.2.rep_trigger.loggingEnabled=0
unit.0.2.rep_trigger.signals=All Signals/Buses
unit.0.2.samplesPerTrigger=1
unit.0.2.triggerCapture=1
unit.0.2.triggerNSamplesTS=0
unit.0.2.triggerPosition=0
unit.0.2.triggerWindowCount=1
unit.0.2.triggerWindowDepth=1024
unit.0.2.triggerWindowTS=0
unit.0.2.username=Analyser
unit.0.2.waveform.count=9
unit.0.2.waveform.posn.0.channel=0
unit.0.2.waveform.posn.0.name=P[0]
unit.0.2.waveform.posn.0.type=signal
unit.0.2.waveform.posn.1.channel=1
unit.0.2.waveform.posn.1.name=P[1]
unit.0.2.waveform.posn.1.type=signal
unit.0.2.waveform.posn.10.channel=10
unit.0.2.waveform.posn.10.name=P[10]
unit.0.2.waveform.posn.10.type=signal
unit.0.2.waveform.posn.11.channel=11
unit.0.2.waveform.posn.11.name=P[11]
unit.0.2.waveform.posn.11.type=signal
unit.0.2.waveform.posn.12.channel=12
unit.0.2.waveform.posn.12.name=P[12]
unit.0.2.waveform.posn.12.type=signal
unit.0.2.waveform.posn.13.channel=13
unit.0.2.waveform.posn.13.name=P[13]
unit.0.2.waveform.posn.13.type=signal
unit.0.2.waveform.posn.14.channel=14
unit.0.2.waveform.posn.14.name=P[14]
unit.0.2.waveform.posn.14.type=signal
unit.0.2.waveform.posn.15.channel=15
unit.0.2.waveform.posn.15.name=P[15]
unit.0.2.waveform.posn.15.type=signal
unit.0.2.waveform.posn.16.channel=16
unit.0.2.waveform.posn.16.name=P[16]
unit.0.2.waveform.posn.16.type=signal
unit.0.2.waveform.posn.17.channel=17
unit.0.2.waveform.posn.17.name=P[17]
unit.0.2.waveform.posn.17.type=signal
unit.0.2.waveform.posn.2.channel=2
unit.0.2.waveform.posn.2.name=P[2]
unit.0.2.waveform.posn.2.type=signal
unit.0.2.waveform.posn.3.channel=3
unit.0.2.waveform.posn.3.name=P[3]
unit.0.2.waveform.posn.3.type=signal
unit.0.2.waveform.posn.4.channel=4
unit.0.2.waveform.posn.4.name=P[4]
unit.0.2.waveform.posn.4.type=signal
unit.0.2.waveform.posn.5.channel=5
unit.0.2.waveform.posn.5.name=P[5]
unit.0.2.waveform.posn.5.type=signal
unit.0.2.waveform.posn.6.channel=6
unit.0.2.waveform.posn.6.name=P[6]
unit.0.2.waveform.posn.6.type=signal
unit.0.2.waveform.posn.7.channel=7
unit.0.2.waveform.posn.7.name=P[7]
unit.0.2.waveform.posn.7.type=signal
unit.0.2.waveform.posn.8.channel=8
unit.0.2.waveform.posn.8.name=P[8]
unit.0.2.waveform.posn.8.type=signal
unit.0.2.waveform.posn.9.channel=9
unit.0.2.waveform.posn.9.name=P[9]
unit.0.2.waveform.posn.9.type=signal

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/S3AN01_ChipScope_18x1024.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/S3AN01_ChipScope_9x2048.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/Version
0,0 → 1,4
TimeStamp: 2013_06_25__09_41
ComputerName: MIHOMSI
ISE Version: 13.3
ReleaseInfo: None

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/S3AN01_ChipScope_18x1024.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/S3AN01_ChipScope_9x2048.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/Version
0,0 → 1,4
TimeStamp: 2013_06_25__17_31
ComputerName: MIHO-W7
ISE Version: 14.5
ReleaseInfo: None

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/!____!.txt
0,0 → 1,20
CoreGenerator Project Files
---------------------------
Software: ISE 14.5 (WebPack)
Device: Spartan3AN XC3S50AN-4TQG144C
Input (source) Files
--------------------
S3AN01_ChipScopeILA.cgp - Core Generator Project File (used by GUI CoreGen)
ChipScope_ICON.xco - ChipScope Config Block Configuration File
ChipScope_ILA_18_1024.xco - ChipScope Integrated Logic Analyser Configuration File 18 bits 1024 smaples
ChipScope_ILA_9_2048.xco - ChipScope Integrated Logic Analyser Configuration File 9 bits 2048 smaples
ChipScope_VIO_FreqSel.xco - ChipScope Virtul IO Configuration File (used for Frequency Selection)
ChipScope_VIO_UserOut.xco - ChipScope Virtul IO Configuration File (used for User Output)
All other files may be deleted. Open .cgp file in CoreGenerator and let it regenerate
all cores.

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ICON.xco
0,0 → 1,56
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 12:54:35 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
CSET component_name=ChipScope_ICON
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=3
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:10Z
# END Extra information
GENERATE
# CRC: 1a9afcd1

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_18_1024.xco
0,0 → 1,141
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 12:43:44 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET check_bramcount=false
CSET component_name=ChipScope_ILA_18_1024
CSET constraint_type=external
CSET counter_width_1=4
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=18
CSET data_same_as_trigger=false
CSET disable_save_keep=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=true
CSET example_design=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic_with_edges
CSET match_type_11=basic_with_edges
CSET match_type_12=basic_with_edges
CSET match_type_13=basic_with_edges
CSET match_type_14=basic_with_edges
CSET match_type_15=basic_with_edges
CSET match_type_16=basic_with_edges
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic_with_edges
CSET match_type_5=basic_with_edges
CSET match_type_6=basic_with_edges
CSET match_type_7=basic_with_edges
CSET match_type_8=basic_with_edges
CSET match_type_9=basic_with_edges
CSET match_units_1=3
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=16
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=24
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=true
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:34Z
# END Extra information
GENERATE
# CRC: ab76e1ca

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_9_2048.xco
0,0 → 1,141
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 13:35:12 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET check_bramcount=false
CSET component_name=ChipScope_ILA_9_2048
CSET constraint_type=external
CSET counter_width_1=4
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=9
CSET data_same_as_trigger=false
CSET disable_save_keep=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=true
CSET example_design=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic_with_edges
CSET match_type_11=basic_with_edges
CSET match_type_12=basic_with_edges
CSET match_type_13=basic_with_edges
CSET match_type_14=basic_with_edges
CSET match_type_15=basic_with_edges
CSET match_type_16=basic_with_edges
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic_with_edges
CSET match_type_5=basic_with_edges
CSET match_type_6=basic_with_edges
CSET match_type_7=basic_with_edges
CSET match_type_8=basic_with_edges
CSET match_type_9=basic_with_edges
CSET match_units_1=3
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=16
CSET number_of_trigger_ports=1
CSET sample_data_depth=2048
CSET sample_on=Rising
CSET trigger_port_width_1=24
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=true
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:34Z
# END Extra information
GENERATE
# CRC: 100acb04

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_FreqSel.xco
0,0 → 1,59
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 12:56:15 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=8
CSET component_name=ChipScope_VIO_FreqSel
CSET constraint_type=external
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=false
CSET enable_synchronous_input_port=true
CSET enable_synchronous_output_port=true
CSET example_design=false
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:59Z
# END Extra information
GENERATE
# CRC: c6d481e1

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_UserOut.xco
0,0 → 1,59
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Thu Jun 20 12:55:33 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=8
CSET component_name=ChipScope_VIO_UserOut
CSET constraint_type=external
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=false
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=true
CSET example_design=false
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=3
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-26T22:44:59Z
# END Extra information
GENERATE
# CRC: 738ddf25

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/coregen.cgp
0,0 → 1,9
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET package = tqg144
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/DirInfo.txt
0,0 → 1,33
//
// Toto je popisný soubor pro popis obsahu adresáře
//
[InfoShortDescription.en]
Xilinx ChipScope Demo
[InfoShortDescription.cs]
Xilinx ChipScope Demo
[InfoLongDescription.en]
ChipScope IP Core from Xilinx company enable us to add pretty
powerful logic analyser into our own FPGA design. It is necessary
to have a valid license for generation of bitfile but not for
usage and debugging. The text here shows a realisation of
an universal logic analyser in Spartan device on MLAB
board S3AN01. It shows the use of Xilinx Virtual Cable technology
as well.
The maximum achieved sampling rate is 170 MS/s with 9 or 18 input channels.
[InfoLongDescription.cs]
IP jádro ChipScope firmy Xilinx umožňuje vložit do vlastního návrhu
FPGA obvodu docela výkonný logický analyzátor. K překladu takového
obvodu potřebujeme příslušnou licenci, ale pro použití (ladění)
už ne. Uvedený článek ukazuje realizaci univerzálního logického
analyzátoru v obvodu Spartan na desce S3AN01 ze stavebnice MLAB
a to současně s použitím technologie Xilinx Virtual Cable
s přenosem JTAG příkazů po síti.
Maximální dosažená rychlost vzorkování je 170 MS/s na 9 nebo 18 kanálech.
[SortPreferences]
[End]

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/FindXilinxTools.cmd
0,0 → 1,40
@echo off
rem Finds installation of Xilinx tools and makes necessary env settings
rem ----- Set 32/64 bit
if Defined PROCESSOR_ARCHITEW6432 (
Set ProcArch=%PROCESSOR_ARCHITEW6432%
) else (
Set ProcArch=%PROCESSOR_ARCHITECTURE%
)
if "%ProcArch%" == "AMD64" Set ProcArch=x64
rem echo %ProcArch%
if "%ProcArch%" == "x64" (
set fileXilinxSet=settings64.bat
) else (
set fileXilinxSet=settings32.bat
)
rem ----- Find Xilinx directory
echo Find Xilinx Tools
for %%i in (C:\SW32\Xilinx C:\Xilinx) do (
rem Take the last directory
for /F %%j in ('dir %%i\*.* /AD /B /O-N') do (
for %%k in (%%i\%%j\ISE_DS) do (
rem echo %%j\%fileXilinxSet%
if exist %%k\%fileXilinxSet% (
echo Found at %%k\%fileXilinxSet%
call %%k\%fileXilinxSet%
set XILINX_VERSION=%%j
if not "%1"=="" (
rem Call script
call %1
) else (
rem Just set env
goto Label1
)
)
)
)
)
:Label1

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_CoreGen.cmd
0,0 → 1,81
@echo off
rem Batch to (re)generate IP cores (ChipScope components)
rem Run once, takes several minutes to finish.
rem
rem Do not modify source files directory structure
rem
rem Tested with Xilinx ISE WebPack 13.3 and 14.5
rem This step does not require ChipScope License
rem
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
rem ----- Run Coregen in paralel (we all have multicore cpu don't we?)
rem Unfortunately CoreGen can't be run in parallel.
rem There is some conflict (You cenrtainly know what all that cores are good for...)
rem start "CoreGen ICON" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r
rem start "CoreGen ILA 18x1024" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r
rem start "CoreGen ILA 9x2048" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r
rem start "CoreGen VIO FreqSel" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r
rem start "CoreGen VIO UserOut" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r
rem ----- Run CoreGen one after one for all components
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_ICON
echo ===============================
pause
exit 1
)
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_ILA_18_1024
echo ======================================
pause
exit 1
)
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_ILA_9_2048
echo =====================================
pause
exit 1
)
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_VIO_FreqSel
echo ======================================
pause
exit 1
)
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in coregen ChipScope_VIO_UserOut
echo ======================================
pause
exit 1
)
rem ----- Finished
rm coregen.log
echo.
echo CoreGen Finished with no Errors

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_S3AN01_ChipScope.cmd
0,0 → 1,179
@echo off
rem Batch generates bitfile for Logic Analyser Demo
rem
rem Parameters:
rem
rem 18x1024|9x2048 ... select analyser size (width and depth)
rem
rem Do not modify srouce files directory structure
rem
rem Tested with Xilinx ISE WebPack 14.5 with ChipScope License
rem
rem ----- first parameter
set product=%1%
if "%product%"=="18x1024" (
echo 18x1024
) else if "%product%" == "9x2048" (
echo 9x2048
) else (
echo Missing parameter %product%
echo usage: %0% 18x1024^|9x2048
pause
exit 1
)
echo.
echo Product: %product%
echo.
rem ----- Set core (top VHDL entity) name
set core=S3AN01_ChipScope
rem ----- Set FPGA part
set fpgaPart=xc3s50an-tqg144-4
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
rem ----- Set WORK dir
if exist WORK_%core%_%product% rmdir /S /Q WORK_%core%_%product%
mkdir WORK_%core%_%product%
cd WORK_%core%_%product%
rem ----- Set TEMP dir (relative to WORK dir)
mkdir TMP
set TMP=TMP
rem ----- INPUT UCF and VHDL files (linux format c:/.../... )
set srcPath=../..
set ucfFile=VHDL/S3AN01_ChipScope.ucf
echo vhdl work "%srcPath%/COREGEN/ChipScope_ICON.vhd" > srcFiles.prj
echo vhdl work "%srcPath%/COREGEN/ChipScope_VIO_FreqSel.vhd" >>srcFiles.prj
echo vhdl work "%srcPath%/COREGEN/ChipScope_ILA_9_2048.vhd" >>srcFiles.prj
echo vhdl work "%srcPath%/VHDL/S3AN01_ChipScope.vhd" >>srcFiles.prj
rem ----- SET XST setting
echo set -xsthdpdir "xst" > setXst.xst
echo run >>setXst.xst
echo -ifn "srcFiles.prj" >>setXst.xst
echo -ofn %core% >>setXst.xst
echo -ofmt NGC >>setXst.xst
echo -top %core% >>setXst.xst
echo -iob True >>setXst.xst
echo -p %fpgaPart% >>setXst.xst
if "%product%"=="18x1024" (
echo -generics { ILA_WIDE=TRUE } >>setXst.xst
) else (
echo -generics { ILA_WIDE=FALSE } >>setXst.xst
)
rem ----- SET BITGEN setting
echo -w > setBitGen.ut
echo -g ConfigRate:25 >>setBitGen.ut
echo -g UnusedPin:PullUp >>setBitGen.ut
echo -g DriveDone:Yes >>setBitGen.ut
call xst -ifn "setXst.xst" -ofn "%core%.log"
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in xst
echo ============
pause
exit 1
)
call ngdbuild -intstyle ise -dd _ngo -sd ../../COREGEN -nt timestamp -uc "%srcPath%/%ucfFile%" -p %fpgaPart% %core%.ngc %core%.ngd
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in ngdbuild
echo =================
pause
exit 1
)
call map -intstyle ise -p %fpgaPart% -cm area -ir off -pr off -c 100 -o %core%.ncd %core%.ngd %core%.pcf
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in map
echo ============
pause
exit 1
)
call par -w -intstyle ise -ol high -t 1 %core%.ncd %core%.ncd %core%.pcf
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in par
echo ============
pause
exit 1
)
call trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml %core%.twx %core%.ncd -o %core%.twr %core%.pcf
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in trace
echo ==============
pause
exit 1
)
call bitgen -f "setBitGen.ut" %core%.ncd
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in bidgen
echo ===============
pause
exit 1
)
rem ----- Verify Timing
findstr /B /C:"All constraints were met." %core%.par
if %errorlevel% NEQ 0 (
echo.
echo.
echo ERROR in Timing
echo ===============
pause
exit 1
)
if exist ..\BIN\%XILINX_VERSION% (
rem ----- Copy result to BIN\{ISE_VER} directory
copy /Y %core%.bit ..\BIN\%XILINX_VERSION%\%core%_%product%.bit
rem copy /Y %core%.par ..\BIN\%XILINX_VERSION%\%core%_%product%.par
rem ----- Remove WORK dir
rem (bitgen starts wbtc.exe as a secondary process)
cd ..
rem Wait for xwebtalk has finished its work (sending stat data to Xilinx)
echo | set /p=Waiting for WebTalk...
:StartLoop
tasklist | findstr /i /c:"wbtc.exe" > nul
if %errorlevel% NEQ 0 (
goto ExitLoop
)
sleep 1
echo | set /p=*
goto StartLoop
)
:ExitLoop
rem Tohle nefunguje, protože výstup wmic je UTF-16 a to finstr neumí
rem wmic process | findstr /c:"%core%_%product%"
rem wmic process > ..\"%core%_%product%".wmic
rmdir /S /Q WORK_%core%_%product%
exit 0
)
exit 1

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_all.cmd
0,0 → 1,53
@echo off
rem Batch to generate bitstream
rem
rem S3AN01_ChipScope_18x1024.bit
rem S3AN01_ChipScope_9x2048.bit
rem
rem Do not modify srouce files directory structure
rem
rem Tested with Xilinx ISE WebPack 14.5 with ChipScope License
rem
rem ----- Check if ChipScope IP Cores are ready
if not exist ..\COREGEN\ChipScope_ICON.vhd goto coregen
if not exist ..\COREGEN\ChipScope_ILA_18_1024.vhd goto coregen
if not exist ..\COREGEN\ChipScope_ILA_9_2048.vhd goto coregen
if not exist ..\COREGEN\ChipScope_VIO_FreqSel.vhd goto coregen
if not exist ..\COREGEN\ChipScope_VIO_UserOut.vhd goto coregen
goto next
:coregen
rem ----- Regenerate ChipScope IP Cores
echo.
echo Missing ChipScope IP Core output files
echo Regenerating will take a long time (5 minutes on i5-3770)
echo.
pause
call make_CoreGen.cmd
:next
rem ----- Clear target directory
rmdir /S /Q BIN 2> nul
mkdir BIN
rem ----- Get Current date and time
for /F "Tokens=2-4 Delims=. " %%A in ("%DATE%") do (
set CurDate=%%C_%%B_%%A
)
for /F "Tokens=1-2 Delims=:,. " %%D in ("%TIME: =0%") do (
set CurTime=%%D_%%E
)
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
mkdir BIN\%XILINX_VERSION%
rem ----- Create Version metafile
echo TimeStamp: %CurDate%__%CurTime%> BIN\%XILINX_VERSION%\Version
echo ComputerName: %COMPUTERNAME%>> BIN\%XILINX_VERSION%\Version
echo ISE Version: %XILINX_VERSION%>> BIN\%XILINX_VERSION%\Version
echo ReleaseInfo: None>> BIN\%XILINX_VERSION%\Version
rem ----- Compile variants (paralel run)
start "compile S3AN01_ChipScope_18x1024" make_S3AN01_ChipScope.cmd 18x1024
start "compile S3AN01_ChipScope_9x2048" make_S3AN01_ChipScope.cmd 9x2048

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_18_1024.cmd
0,0 → 1,24
@echo off
rem
rem Script for starting Analyser.exe with predefined settings.
rem The script starts mlab_xvcd.exe deamon for users who use
rem Xilinx Virtual Cable and FTDI JTAG cable. Those users
rem should select in ChipScope Analyser setting
rem JTAG Chain / Open Plug-in.
rem
rem ----- Run Xilinx Virtual Cable Daemon (as separate process)
rem Run it if you use XVC cable connected to the local computer
rem To start the daemon if already runnig does no harm
if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe (
start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe
)
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
rem ----- Run ChipScope Analyser
analyzer.exe -project ..\ANALYSER\Analyser_18_1024.cpj -init ..\ANALYSER\Analyser.ini

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_9_2048.cmd
0,0 → 1,24
@echo off
rem
rem Script for starting Analyser.exe with predefined settings.
rem The script starts mlab_xvcd.exe deamon for users who use
rem Xilinx Virtual Cable and FTDI JTAG cable. Those users
rem should select in ChipScope Analyser setting
rem JTAG Chain / Open Plug-in.
rem
rem ----- Run Xilinx Virtual Cable Daemon (as separate process)
rem Run it if you use XVC cable connected to the local computer
rem To start the daemon if already runnig does no harm
if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe (
start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe
)
rem ----- Find and Set Xilinx Tools
call FindXilinxTools.cmd
rem ----- Run ChipScope Analyser
analyzer.exe -project ..\ANALYSER\Analyser_9_2048.cpj -init ..\ANALYSER\Analyser.ini

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL/S3AN01_ChipScope.ucf
0,0 → 1,112
# Board: www.mlab.cz S3AN01A
# Device: XC3S50AN-4TQG144C
# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes
# Main Clock (Embedded 100MHz board oscillator)
NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33;
NET "CLK100MHz" TNM_NET = CLK100MHz;
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;
# Enable suboptimal routing of CLK100MHz to DCM input
# (the CLK100MHz pin is across the whole chip realtive to DCM)
# PIN "DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
# Place BUFGMUX at the appropriate position
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;
# SPI Flash Vendor Mode Select (for external SPI boot Flash)
NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# DIP Switches (positive signals with pull-down)
NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# LED String (positive output signals)
NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33;
NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33;
NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33;
NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33;
NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33;
NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33;
NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33;
NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33;
# LED Display Output Signals (negative, multiplexed) - Segments
NET "LD_SEG_n[0]" LOC = P15 |IOSTANDARD = LVCMOS33; # Segment A A
NET "LD_SEG_n[1]" LOC = P30 |IOSTANDARD = LVCMOS33; # Segment B -----
NET "LD_SEG_n[2]" LOC = P21 |IOSTANDARD = LVCMOS33; # Segment C F | | B
NET "LD_SEG_n[3]" LOC = P19 |IOSTANDARD = LVCMOS33; # Segment D | G |
NET "LD_SEG_n[4]" LOC = P18 |IOSTANDARD = LVCMOS33; # Segment E -----
NET "LD_SEG_n[5]" LOC = P16 |IOSTANDARD = LVCMOS33; # Segment F E | | C
NET "LD_SEG_n[6]" LOC = P24 |IOSTANDARD = LVCMOS33; # Segment G | D |
NET "LD_SEG_n[7]" LOC = P20 |IOSTANDARD = LVCMOS33; # Segment DP ----- DP
# LED Display Output Signals (negative, multiplexed) - Common Anodas
NET "LD_CA_n[0]" LOC = P25 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[1]" LOC = P31 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[2]" LOC = P32 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[3]" LOC = P13 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.13 with U1.33
NET "LD_CA_n[4]" LOC = P27 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[5]" LOC = P29 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[6]" LOC = P28 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[7]" LOC = P12 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.12 with U1.35
# Bank 1 Port (input for tests, pull-up)
NET "P[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# Diferencial Signals on 4 pin header (J7)
NET "DIF1P" LOC = P110 |IOSTANDARD = LVDS_33;
NET "DIF1N" LOC = P111 |IOSTANDARD = LVDS_33;
NET "DIF2P" LOC = P112 |IOSTANDARD = LVDS_33;
NET "DIF2N" LOC = P113 |IOSTANDARD = LVDS_33;
# Timing Constraint for Crossing Time Domain
# Source is ChipScope_VIO_FreqSel output in CLK_FAST time domain
# Destination is SW_SYNC register in CLK100MHz time domain
INST "SW_SYNC_?" TNM = "TNM_SW_SYNC";
TIMESPEC "TS_SW_SYNC" = TO "TNM_SW_SYNC" TIG;
# Timing Constraint for Crossing Time Domain
# Source is SET_CLK_xxx register (FSM) in CLK100MHz time domain
# Destination is ChipScope_VIO_FreqSel inputs in CLK_FAST time domain
INST "SYNC_IN_?" TNM = "TNM_SET_CLK";
TIMESPEC "TS_SET_CLK" = TO "TNM_SET_CLK" TIG;
# Timing Constraint for Clock Switch
# Block BUFGMUX is used as Assynchronous switcher
PIN "BUFGMUX_CLK_FAST.S" TIG;

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL/S3AN01_ChipScope.vhd
0,0 → 1,612
-- ========================================================================
--
-- S3AN01_ChipScope
--
-- Logic Analyser based on Xilinx ChipScope IP Core for S3AN01 Board
--
-- (c) miho 2013 / http://www.mlab.cz/PermaLink/XILINX_ChipScope
--
-- Demo application contains some Clock Logic (DCM block and
-- clock switch to be able to set different sample clocks).
-- The main function is ChipScope Logic Analyser with 16 data inputs
-- (with 24 bit trigger) and storage for 1024 Data Samples.
--
-- Sampling clock is selectable to 170/100/50/20/10/5/2/1MHz
--
-- To implement the design the ChipScope license is required.
--
-- To use (the logic analyser) no speceial license is needed,
-- WebPack ISE or Lab Tools is enough). Requires some compatible
-- JTAG cable. Compatible with MLAB Xilinx Virtual Cable as well
-- http://www.mlab.cz/PermaLink/XILINX_XVC
--
-- Device: Spartan3AN XC3S50AN-4TQG144C
--
-- Software: ISE WebPack 14.5
--
-- ========================================================================
-- Standard Library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Xilinx Library (necessary for DMC and other Xilinx blocks)
library UNISIM;
use UNISIM.VComponents.all;
-- Interface
entity S3AN01_ChipScope is
generic(
ILA_WIDE: boolean := TRUE; -- TRUE/FALSE -> 18bit x 1024 / 9bit x 2048 logic analyser
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
);
port(
-- Main Clock
CLK100MHz: in std_logic; -- 100MHz external xtal clock source
-- Mode Signals (usualy not used)
VS: out std_logic_vector(2 downto 0); -- SPI Flash Vendor Mode Select
-- Dipswitch Inputs
DIPSW: in std_logic_vector(7 downto 0);
-- LED Bar Outputs
LED: out std_logic_vector(7 downto 0);
-- LED Display (8 digits with 7 segments and decimal point)
LD_CA_n: out std_logic_vector(7 downto 0);
LD_SEG_n: out std_logic_vector(7 downto 0);
-- Bank 1 Pins Inputs
P: in std_logic_vector(24 downto 0);
-- Diferencial Signals on 4 pin header (J7)
DIF1P: inout std_logic;
DIF1N: inout std_logic;
DIF2P: inout std_logic;
DIF2N: inout std_logic
);
end S3AN01_ChipScope;
-- Implementation
architecture S3AN01_ChipScope_a of S3AN01_ChipScope is
-- Clock Signals
-- =============
-- DCM Signals
signal DCM_CLK0: std_logic; -- DCM output for feedback
signal DCM_CLKFX: std_logic; -- DCM output of the fastest clock
signal CLK_FAST: std_logic; -- Main clock for ILA
signal CLK_FAST_Q: std_logic; -- Auxiliary signal (for CLK_FAST sent to pin)
-- 100MHz Clock Switch
-- CLK100MHz Clock Domain
signal CLK100MHz_CE: std_logic; -- Gate Signal for slow dwn of the 100MHz clock
signal CLK100MHz_Gated: std_logic; -- Gated Clocks
signal CLK100MHz_CE_Cnt: unsigned(6 downto 0) := (others => '0'); -- Gate Signal Counter (min frequency is 1/100 of CLK100MHz
-- 1 Hot Clock Select Signals
-- CLK100MHz Clock Domain
signal SET_CLK_MAX: std_logic := '0'; -- Clock Select Signal - Maximim (150-170Mhz)
signal SET_CLK_100MHz: std_logic := '1'; -- Clock Select Signal - 100MHz
signal SET_CLK_50MHz: std_logic := '0'; -- Clock Select Signal - 50MHz
signal SET_CLK_20Mhz: std_logic := '0'; -- Clock Select Signal - 20MHz
signal SET_CLK_10Mhz: std_logic := '0'; -- Clock Select Signal - 10MHz
signal SET_CLK_5Mhz: std_logic := '0'; -- Clock Select Signal - 5MHz
signal SET_CLK_2Mhz: std_logic := '0'; -- Clock Select Signal - 2MHz
signal SET_CLK_1Mhz: std_logic := '0'; -- Clock Select Signal - 1MHz
-- Signals from and to ChipScope Virtual IO (set and display frequency)
-- CLK_FAST and CLK100MHz time domain
signal SYNC_IN: std_logic_vector(7 downto 0); -- Input to ChipScope VIO
signal SYNC_OUT: std_logic_vector(7 downto 0); -- Output from ChipScope VIO
signal SW_SYNC: std_logic_vector(7 downto 0) := (others => '0'); -- Asyn inputs synced
-- LED Ouput with time multiplex
-- =============================
signal WideBCD: std_logic_vector(2*5-1 downto 0); -- Constant width of ILA in BCD (2 char wide)
signal FrequencyBCD: std_logic_vector(3*5-1 downto 0); -- Selected frequency in BCD (3 char wide)
signal Code: std_logic_vector(4 downto 0); -- BCD to 7 Segment Decoder Output
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
-- Time Multiplex
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
signal LedEnable: std_logic; -- LED Display Brightness
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
-- Test Generator signals
-- ======================
signal Counter: std_logic_vector(7 downto 0); -- Counter
-- ChipScope Signals
-- =================
-- Input data
-- CLK_FAST Clock Domain
signal DataReg: std_logic_vector(P'range); -- Data and Trigger input
-- Trigger Output
signal TriggerOut: std_logic; -- Trigegr output from ChipScope ILA to pin
-- User Outputs from ChipScope Virtual IO
signal SYNC_OUT_USER: std_logic_vector(2 downto 0); -- Output from ChipScope VIO
-- ChipScope Control Signals
signal Control0: std_logic_vector(35 downto 0);
signal Control1: std_logic_vector(35 downto 0);
signal Control2: std_logic_vector(35 downto 0);
-- ChipScope Control Block
component ChipScope_ICON
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0)
);
end component;
-- ChipScope Virtual I/O Block
component ChipScope_VIO_FreqSel
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
SYNC_IN: in std_logic_vector(7 downto 0);
SYNC_OUT: out std_logic_vector(7 downto 0)
);
end component;
-- ChipScope Virtual I/O Block
component ChipScope_VIO_UserOut
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
SYNC_OUT: out std_logic_vector(2 downto 0)
);
end component;
-- ChipScope Integrated Logic Analyser
component ChipScope_ILA_18_1024
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(17 downto 0); -- 18 bits wide data
TRIG0: in std_logic_vector(23 downto 0);
TRIG_OUT: out std_logic
);
end component;
-- ChipScope Integrated Logic Analyser
component ChipScope_ILA_9_2048
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(8 downto 0); -- 9 bits wide data
TRIG0: in std_logic_vector(23 downto 0);
TRIG_OUT: out std_logic
);
end component;
begin
-- ===================================================
-- Clock Network and Clock Switching
-- ===================================================
--
-- The fastest clock signal is generated from 100MHz by DCM.
-- The design maximim is 170MHz for selected device.
--
-- For lower frequency the 100MHz clocks are gated in BUFGCE
-- acording to SET_CLK_xxx signals.
--
-- For Logic Analyser we use 170MHz from DCM or gated 100MHz
-- switchd by BUFGMUX block.
-- DCM_SP: Digital Clock Manager Circuit
-- Spartan-3A
-- Xilinx HDL Language Template, version 14.5
--
-- CLKFB without BUFG (we do not need phase relation to the original clock)
--
-- Design Limits (XC3S50AN-4):
--
-- 5/3 -> 166MHz - o.k. (best 5.9ns - 169.5MHz)
-- 17/10 -> 170MHz - o.k. (best 5.748ns - 174MHz) <------ Used Here
-- 12/7 -> 171MHz - Timing Error
-- 7/4 -> 175MHz - Timing Error
-- 18/10 -> 180MHz - Timing Error
--
DCM_SP_inst: DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 17, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 10.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15
DLL_FREQUENCY_MODE => "HIGH", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
)
port map (
CLK0 => DCM_CLK0, -- 0 degree DCM CLK ouptput
-- CLK180 => CLK180, -- 180 degree DCM CLK output
-- CLK270 => CLK270, -- 270 degree DCM CLK output
-- CLK2X => CLK2X, -- 2X DCM CLK output
-- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
-- CLK90 => CLK90, -- 90 degree DCM CLK output
-- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => DCM_CLKFX, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
-- LOCKED => LOCKED, -- DCM LOCK status output
-- PSDONE => PSDONE, -- Dynamic phase adjust done output
-- STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => DCM_CLK0, -- DCM clock feedback
CLKIN => CLK100MHz, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => PSCLK, -- Dynamic phase adjust clock input
-- PSEN => PSEN, -- Dynamic phase adjust enable input
-- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
-- Generate Clock Gate signal for 100MHz Clock
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if CLK100MHz_CE_Cnt=0 then
CLK100MHz_CE <= '1';
if SET_CLK_100MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(1-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_50MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(2-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_20MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(5-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_10MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(10-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_5MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(20-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_2MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(50-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_1MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(100-1, CLK100MHz_CE_Cnt'length);
end if;
else
CLK100MHz_CE <= '0';
CLK100MHz_CE_Cnt <= CLK100MHz_CE_Cnt-1;
end if;
end if;
end process;
-- Gate 100MHz Clocks (to produce 100/50/20/10/5/2/1 MHz)
-- Generates 5ns pulses with 10/20/50/100/200/500/1000ns period
BUFGCE_CLK100MHz: BUFGCE
port map (
I => CLK100MHz, -- Clock buffer input
CE => CLK100MHz_CE, -- Clock enable input
O => CLK100MHz_Gated -- Clock buffer ouptput
);
-- Switch (gated) 100MHz and the fastest Clock signal from DCM
BUFGMUX_CLK_FAST: BUFGMUX
port map (
I0 => CLK100MHz_Gated, -- Clock0 input -- 100/50/20/10/50/20/1MHz
I1 => DCM_CLKFX, -- Clock1 input -- 170MHz
S => SET_CLK_MAX, -- Clock select input
O => CLK_FAST -- Clock MUX output
);
-- Assynchrnous inputs and inputs from CLK_FAST clock domain must be synchronised
-- SYNC_OUT - CLK_FAST clock domain
-- DIPSW - External (off-chip) async inputs
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
SW_SYNC <= SYNC_OUT or DIPSW;
end if;
end process;
-- Ferquency Selector
-- FSM - 1 hot
process (CLK100MHz)
variable TMP: std_logic_vector(SYNC_OUT'range);
variable NEW_DATA: std_logic;
begin
if rising_edge(CLK100MHz) then
TMP := (others => '0');
NEW_DATA := '1';
if SW_SYNC(7)='1' then
TMP(7) := '1';
elsif SW_SYNC(6)='1' then
TMP(6) := '1';
elsif SW_SYNC(5)='1' then
TMP(5) := '1';
elsif SW_SYNC(4)='1' then
TMP(4) := '1';
elsif SW_SYNC(3)='1' then
TMP(3) := '1';
elsif SW_SYNC(2)='1' then
TMP(2) := '1';
elsif SW_SYNC(1)='1' then
TMP(1) := '1';
elsif SW_SYNC(0)='1' then
TMP(0) := '1';
else
NEW_DATA := '0';
end if;
if NEW_DATA='1' then
SET_CLK_MAX <= TMP(7);
SET_CLK_100MHz <= TMP(6);
SET_CLK_50MHz <= TMP(5);
SET_CLK_20MHz <= TMP(4);
SET_CLK_10MHz <= TMP(3);
SET_CLK_5MHz <= TMP(2);
SET_CLK_2MHz <= TMP(1);
SET_CLK_1MHz <= TMP(0);
end if;
end if;
end process;
-- Send selected frequency to ChipScope Virtual IO
-- Sync it to the CLK_FAST timing domain
SET_CLK_proc: process (CLK_FAST)
begin
if rising_edge(CLK_FAST) then
SYNC_IN(7) <= SET_CLK_MAX;
SYNC_IN(6) <= SET_CLK_100MHz;
SYNC_IN(5) <= SET_CLK_50MHz;
SYNC_IN(4) <= SET_CLK_20Mhz;
SYNC_IN(3) <= SET_CLK_10Mhz;
SYNC_IN(2) <= SET_CLK_5Mhz;
SYNC_IN(1) <= SET_CLK_2Mhz;
SYNC_IN(0) <= SET_CLK_1Mhz;
end if;
end process;
-- ===================================================
-- ChipScope Instance - Control / Virtual IO / ILA
-- ===================================================
-- ChipScope Instance - Control Block
MyChipScopeICON: ChipScope_ICON
port map (
CONTROL0 => Control0,
CONTROL1 => Control1,
CONTROL2 => Control2
);
-- ChipScope Instance - Virtual I/O Block
MyChipScopeVIO_FreqSel: ChipScope_VIO_FreqSel
port map (
CONTROL => Control0,
CLK => CLK_FAST,
SYNC_IN => SYNC_IN,
SYNC_OUT => SYNC_OUT
);
-- ChipScope Instance - Virtual I/O Block
MyChipScopeVIO_UserOut: ChipScope_VIO_UserOut
port map (
CONTROL => Control1,
CLK => CLK_FAST,
SYNC_OUT => SYNC_OUT_USER
);
-- ChipScope Instance - Integrated Logic Analyser
ILA_18_1024: if ILA_WIDE generate
begin
MyChipScopeILA: ChipScope_ILA_18_1024
port map (
CONTROL => Control2,
CLK => CLK_FAST,
DATA => DataReg(17 downto 0),
TRIG0 => DataReg(23 downto 0),
TRIG_OUT => TriggerOut
);
end generate;
ILA_9_2048: if not ILA_WIDE generate
begin
MyChipScopeILA: ChipScope_ILA_9_2048
port map (
CONTROL => Control2,
CLK => CLK_FAST,
DATA => DataReg(8 downto 0),
TRIG0 => DataReg(23 downto 0),
TRIG_OUT => TriggerOut
);
end generate;
-- Data inputs (ILA does not like to have data inputs connected to io pins)
process(CLK_FAST)
begin
if rising_edge(CLK_FAST) then
DataReg <= P(DataReg'range);
end if;
end process;
-- VIO User Outputs
VS <= SYNC_OUT_USER;
-- Trigger Output (Diferencial signal)
OBUFDS_TriggerOut: OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
I => TriggerOut, -- Buffer input
O => DIF1P, -- Diff_p output (connect directly to top-level port)
OB => DIF1N -- Diff_n output (connect directly to top-level port)
);
-- ===================================================
-- LED Display (multiplexed)
-- ===================================================
-- Frequency in BCD
FrequencyBCD <= "00001"&"00111"&"00000" when SET_CLK_MAX='1' else -- 170 MHz
"00001"&"00000"&"00000" when SET_CLK_100MHz='1' else -- 100 MHz
"11111"&"00101"&"00000" when SET_CLK_50MHz='1' else -- 50 MHz
"11111"&"00010"&"00000" when SET_CLK_20MHz='1' else -- 20 MHz
"11111"&"00001"&"00000" when SET_CLK_10MHz='1' else -- 10 MHz
"11111"&"11111"&"00101" when SET_CLK_5MHz='1' else -- 5 MHz
"11111"&"11111"&"00010" when SET_CLK_2MHz='1' else -- 2 MHz
"11111"&"11111"&"00001" when SET_CLK_1MHz='1' else -- 1 MHz
"11111"&"11111"&"11111";
-- ILA width in BCD
ILA_DCD_18_1024: if ILA_WIDE generate
begin
WideBCD <= "00001"&"01000";
end generate;
ILA_DCD_9_2048: if not ILA_WIDE generate
begin
WideBCD <= "11111"&"01001";
end generate;
-- Input data selector ( WIDE / ILA / FREQ )
Code <= FrequencyBCD( 4 downto 0) when Digits="00000001" else
FrequencyBCD( 9 downto 5) when Digits="00000010" else
FrequencyBCD(14 downto 10) when Digits="00000100" else
"10010" when Digits="00001000" else -- A
"10001" when Digits="00010000" else -- L
"10000" when Digits="00100000" else -- I
WideBCD( 4 downto 0) when Digits="01000000" else
WideBCD( 9 downto 5) when Digits="10000000" else
"11111";
-- Time Multiplex
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if MuxCounter < MUXCOUNT-1 then
MuxCounter <= MuxCounter + 1;
else
MuxCounter <= (others => '0');
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left (1 hot encoded)
end if;
-- Display brightness (1/2)
if MuxCounter > (MUXCOUNT-MUXCOUNT/2) then
LedEnable <= '1';
else
LedEnable <= '0';
end if;
end if;
end process;
-- BCD to 7 Segmet Decoder
-- -- A
-- | | F B
-- -- G
-- | | E C
-- -- D H
-- HGFEDCBA
Segments <= "00111111" when Code="00000" else -- Digit 0 -- Hex Didits
"00000110" when Code="00001" else -- Digit 1
"01011011" when Code="00010" else -- Digit 2
"01001111" when Code="00011" else -- Digit 3
"01100110" when Code="00100" else -- Digit 4
"01101101" when Code="00101" else -- Digit 5
"01111101" when Code="00110" else -- Digit 6
"00000111" when Code="00111" else -- Digit 7
"01111111" when Code="01000" else -- Digit 8
"01101111" when Code="01001" else -- Digit 9
"01110111" when Code="01010" else -- Digit A
"01111100" when Code="01011" else -- Digit b
"00111001" when Code="01100" else -- Digit C
"01011110" when Code="01101" else -- Digit d
"01111001" when Code="01110" else -- Digit E
"00110001" when Code="01111" else -- Digit F
"00000110" when Code="10000" else -- Digit I -- User Digits
"00111000" when Code="10001" else -- Digit L
"01110111" when Code="10010" else -- Digit A
"00000000"; -- none
-- Connect LED Display Output Ports (negative outputs)
LD_CA_n <= not Digits;
LD_SEG_n <= not Segments when LedEnable='1' else "11111111";
-- ===================================================
-- Test generator (counter)
-- ===================================================
-- Test counter
process(CLK100MHz)
begin
if rising_edge(CLK100MHz) then
Counter <= std_logic_vector(unsigned(Counter) + 1);
end if;
end process;
-- Test outputs
LED <= Counter;
-- CLK_FAST Output - DDR register
ODDR2_FastClk: ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset
)
port map (
C0 => CLK_FAST, -- 1-bit clock input
C1 => not CLK_FAST, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0', -- 1-bit set input
Q => CLK_FAST_Q -- 1-bit output data
);
-- CLK_FAST Output - differncial pin buffer
OBUFDS_FastClkOut: OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
I => CLK_FAST_Q, -- Buffer input
O => DIF2P, -- Diff_p output (connect directly to top-level port)
OB => DIF2N -- Diff_n output (connect directly to top-level port)
);
end S3AN01_ChipScope_a;