/Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER-cache.lib
135,8 → 135,8
P 2 0 1 0 65 -50 100 -50 N
P 2 0 1 0 65 50 100 50 N
X ~ 1 -250 50 150 R 50 50 1 1 I
X ~ 2 250 50 150 L 50 50 1 1 I
X ~ 3 -250 -50 150 R 50 50 1 1 I
X ~ 2 -250 -50 150 R 50 50 1 1 I
X ~ 3 250 50 150 L 50 50 1 1 I
X ~ 4 250 -50 150 L 50 50 1 1 I
ENDDRAW
ENDDEF
163,11 → 163,11
P 2 0 1 0 -35 0 35 0 N
P 2 0 1 0 -35 100 35 100 N
X ~ 1 -250 100 150 R 50 50 1 1 I
X ~ 2 -250 100 150 R 50 50 1 1 I N
X ~ 3 -250 0 150 R 50 50 1 1 I
X ~ 4 -250 0 150 R 50 50 1 1 I N
X ~ 5 -250 -100 150 R 50 50 1 1 I
X ~ 6 -250 -100 150 R 50 50 1 1 I N
X ~ 2 -250 0 150 R 50 50 1 1 I
X ~ 3 -250 -100 150 R 50 50 1 1 I
X ~ 4 -250 -100 150 R 50 50 1 1 I N
X ~ 5 -250 0 150 R 50 50 1 1 I N
X ~ 6 -250 100 150 R 50 50 1 1 I N
ENDDRAW
ENDDEF
#
196,14 → 196,14
P 2 0 1 0 65 -50 100 -50 N
P 2 0 1 0 65 50 100 50 N
P 2 0 1 0 65 150 100 150 N
X ~ 1 -250 150 150 R 50 50 1 1 I
X ~ 2 250 150 150 L 50 50 1 1 I
X ~ 3 -250 50 150 R 50 50 1 1 I
X ~ 4 250 50 150 L 50 50 1 1 I
X ~ 5 -250 -50 150 R 50 50 1 1 I
X ~ 6 250 -50 150 L 50 50 1 1 I
X ~ 7 -250 -150 150 R 50 50 1 1 I
X ~ 8 250 -150 150 L 50 50 1 1 I
X ~ 1 250 150 150 L 50 50 1 1 I
X ~ 2 -250 150 150 R 50 50 1 1 I
X ~ 3 250 50 150 L 50 50 1 1 I
X ~ 4 -250 50 150 R 50 50 1 1 I
X ~ 5 250 -50 150 L 50 50 1 1 I
X ~ 6 -250 -50 150 R 50 50 1 1 I
X ~ 7 250 -150 150 L 50 50 1 1 I
X ~ 8 -250 -150 150 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
/Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.bak
30,7 → 30,7
LIBS:contrib
LIBS:valves
LIBS:U3_MLAB_ADAPTER-cache
EELAYER 25 0
EELAYER 24 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
283,23 → 283,23
$Comp
L HEADER_2x01_PARALLEL J10
U 1 1 54860825
P 6750 3500
F 0 "J10" H 6750 3400 60 0000 C CNN
F 1 "MOSI" H 7000 3500 60 0000 C CNN
F 2 "" H 6750 3500 60 0000 C CNN
F 3 "" H 6750 3500 60 0000 C CNN
1 6750 3500
P 6650 3500
F 0 "J10" H 6650 3400 60 0000 C CNN
F 1 "MOSI" H 6900 3500 60 0000 C CNN
F 2 "" H 6650 3500 60 0000 C CNN
F 3 "" H 6650 3500 60 0000 C CNN
1 6650 3500
-1 0 0 1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J9
U 1 1 5486082B
P 6750 3150
F 0 "J9" H 6750 3050 60 0000 C CNN
F 1 "SCLK" H 7000 3150 60 0000 C CNN
F 2 "" H 6750 3150 60 0000 C CNN
F 3 "" H 6750 3150 60 0000 C CNN
1 6750 3150
P 6650 3150
F 0 "J9" H 6650 3050 60 0000 C CNN
F 1 "SCLK" H 6900 3150 60 0000 C CNN
F 2 "" H 6650 3150 60 0000 C CNN
F 3 "" H 6650 3150 60 0000 C CNN
1 6650 3150
-1 0 0 1
$EndComp
Wire Wire Line
319,9 → 319,9
Wire Wire Line
7150 3250 7150 3150
Wire Wire Line
7150 3150 7000 3150
7150 3150 6900 3150
Wire Wire Line
7000 3500 7150 3500
6900 3500 7150 3500
Wire Wire Line
7150 3500 7150 3350
Wire Wire Line
548,4 → 548,22
MECHANICAL HOLES \n3,2mm diameter
Wire Wire Line
8100 4500 8100 5250
Text Label 6900 3150 0 60 ~ 0
SCLK
Text Label 6900 3500 0 60 ~ 0
MOSI
Text Label 7800 3250 0 60 ~ 0
#SS
Text Label 7800 3350 0 60 ~ 0
MISO
Text Label 4350 3300 0 60 ~ 0
UART_RX
Text Label 4350 3500 0 60 ~ 0
UART_TX
Text Label 2950 3250 0 60 ~ 0
GPIO199
Text Label 2950 3350 0 60 ~ 0
GPIO200
Text Label 2950 3450 0 60 ~ 0
GPIO204
$EndSCHEMATC
/Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.kicad_pcb
1,12 → 1,12
(kicad_pcb (version 4) (host pcbnew "(2014-10-14 BZR 5188)-product")
(kicad_pcb (version 4) (host pcbnew "(2014-08-29 BZR 5106)-product")
 
(general
(links 43)
(no_connects 43)
(area 150.865115 78.8162 159.014886 84.328001)
(area 0 0 0 0)
(thickness 1.6)
(drawings 0)
(tracks 0)
(tracks 40)
(zones 0)
(modules 22)
(nets 13)
37,7 → 37,10
)
 
(setup
(last_trace_width 0.254)
(last_trace_width 0.4)
(user_trace_width 0.3)
(user_trace_width 0.4)
(user_trace_width 0.5)
(trace_clearance 0.254)
(zone_clearance 0.508)
(zone_45_only no)
62,7 → 65,7
(pad_drill 0.7)
(pad_to_mask_clearance 0)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(visible_elements 7FFFFF7F)
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions false)
94,15 → 97,15
(net 1 GND)
(net 2 +5V)
(net 3 +1.8V)
(net 4 "Net-(J2-Pad1)")
(net 5 "Net-(J3-Pad1)")
(net 6 "Net-(J4-Pad1)")
(net 7 "Net-(J6-Pad4)")
(net 8 "Net-(J6-Pad6)")
(net 9 "Net-(J11-Pad1)")
(net 10 "Net-(J10-Pad1)")
(net 11 "Net-(J11-Pad2)")
(net 12 "Net-(J11-Pad4)")
(net 4 /GPIO199)
(net 5 /GPIO200)
(net 6 /GPIO204)
(net 7 /UART_TX)
(net 8 /UART_RX)
(net 9 /SCLK)
(net 10 /MOSI)
(net 11 /#SS)
(net 12 /MISO)
 
(net_class Default "Toto je výchozí třída sítě."
(clearance 0.254)
113,16 → 116,16
(uvia_drill 0.127)
(add_net +1.8V)
(add_net +5V)
(add_net /#SS)
(add_net /GPIO199)
(add_net /GPIO200)
(add_net /GPIO204)
(add_net /MISO)
(add_net /MOSI)
(add_net /SCLK)
(add_net /UART_RX)
(add_net /UART_TX)
(add_net GND)
(add_net "Net-(J10-Pad1)")
(add_net "Net-(J11-Pad1)")
(add_net "Net-(J11-Pad2)")
(add_net "Net-(J11-Pad4)")
(add_net "Net-(J2-Pad1)")
(add_net "Net-(J3-Pad1)")
(add_net "Net-(J4-Pad1)")
(add_net "Net-(J6-Pad4)")
(add_net "Net-(J6-Pad6)")
)
 
(module MLAB_C:TantalC_SizeC_Reflow (layer B.Cu) (tedit 54799D04) (tstamp 548711C6)
132,19 → 135,19
(path /5485FFA7)
(attr smd)
(fp_text reference C1 (at 0 3) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_text value CP2 (at 0 -3) (layer B.SilkS) hide
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start -4 1) (end -4 -1) (layer B.SilkS))
(fp_line (start 2 -1) (end -2 -1) (layer B.SilkS))
(fp_line (start 2 1) (end -2 1) (layer B.SilkS))
(fp_line (start -4 1) (end -4 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2 -1) (end -2 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2 1) (end -2 1) (layer B.SilkS) (width 0.15))
(fp_text user + (at -4 2) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start -5 3) (end -5 1) (layer B.SilkS))
(fp_line (start -5 2) (end -4 2) (layer B.SilkS))
(fp_line (start -5 3) (end -5 1) (layer B.SilkS) (width 0.15))
(fp_line (start -5 2) (end -4 2) (layer B.SilkS) (width 0.15))
(pad 2 smd rect (at 2 0) (size 2 2) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 1 smd rect (at -2 0) (size 2 2) (layers B.Cu B.Paste B.Mask)
163,19 → 166,19
(path /548601CE)
(attr smd)
(fp_text reference C2 (at 0 3) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_text value CP2 (at 0 -3) (layer B.SilkS) hide
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start -4 1) (end -4 -1) (layer B.SilkS))
(fp_line (start 2 -1) (end -2 -1) (layer B.SilkS))
(fp_line (start 2 1) (end -2 1) (layer B.SilkS))
(fp_line (start -4 1) (end -4 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2 -1) (end -2 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2 1) (end -2 1) (layer B.SilkS) (width 0.15))
(fp_text user + (at -4 2) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start -5 3) (end -5 1) (layer B.SilkS))
(fp_line (start -5 2) (end -4 2) (layer B.SilkS))
(fp_line (start -5 3) (end -5 1) (layer B.SilkS) (width 0.15))
(fp_line (start -5 2) (end -4 2) (layer B.SilkS) (width 0.15))
(pad 2 smd rect (at 2 0) (size 2 2) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 1 smd rect (at -2 0) (size 2 2) (layers B.Cu B.Paste B.Mask)
194,23 → 197,23
(path /5485FEF7)
(attr smd)
(fp_text reference D1 (at 0 2) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_text value DIODESCH (at 0 -3) (layer B.SilkS) hide
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 0) (end 0 1) (layer B.SilkS))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS))
(fp_line (start 0 -1) (end 0 0) (layer B.SilkS))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS))
(fp_line (start 0 0) (end 0 1) (layer B.SilkS) (width 0.15))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 0 -1) (end 0 0) (layer B.SilkS) (width 0.15))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS) (width 0.15))
(fp_text user A (at -1 -1) (layer B.SilkS)
(effects (font (size 0 0)) (justify mirror))
(effects (font (size 0 0) (thickness 0.15)) (justify mirror))
)
(fp_text user K (at 1 -1) (layer B.SilkS)
(effects (font (size 0 0)) (justify mirror))
(effects (font (size 0 0) (thickness 0.15)) (justify mirror))
)
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes) (width 0.15))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes) (width 0.15))
(pad 1 smd rect (at -1 0) (size 1 1) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 2 smd rect (at 1 0) (size 1 1) (layers B.Cu B.Paste B.Mask)
229,23 → 232,23
(path /548601BC)
(attr smd)
(fp_text reference D2 (at 0 2) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_text value DIODESCH (at 0 -3) (layer B.SilkS) hide
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 0) (end 0 1) (layer B.SilkS))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS))
(fp_line (start 0 -1) (end 0 0) (layer B.SilkS))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS))
(fp_line (start 0 0) (end 0 1) (layer B.SilkS) (width 0.15))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 0 -1) (end 0 0) (layer B.SilkS) (width 0.15))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS) (width 0.15))
(fp_text user A (at -1 -1) (layer B.SilkS)
(effects (font (size 0 0)) (justify mirror))
(effects (font (size 0 0) (thickness 0.15)) (justify mirror))
)
(fp_text user K (at 1 -1) (layer B.SilkS)
(effects (font (size 0 0)) (justify mirror))
(effects (font (size 0 0) (thickness 0.15)) (justify mirror))
)
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes) (width 0.15))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes) (width 0.15))
(pad 1 smd rect (at -1 0) (size 1 1) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 2 smd rect (at 1 0) (size 1 1) (layers B.Cu B.Paste B.Mask)
258,14 → 261,14
)
 
(module MLAB_hreb:Pin_Header_Straight_2x03 placed (layer F.Cu) (tedit 54870C46) (tstamp 548711E8)
(at 30.48 -46.99)
(at 15.494 -7.874 90)
(descr "1 pin")
(tags "CONN DEV")
(path /5485F9FC)
(fp_text reference J1 (at 0 -3.81) (layer F.SilkS)
(fp_text reference J1 (at 0 -3.81 90) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.2032)))
)
(fp_text value "5V POWER" (at 0 0) (layer F.SilkS) hide
(fp_text value "5V POWER" (at 0 0 90) (layer F.SilkS) hide
(effects (font (size 1.27 1.27) (thickness 0.2032)))
)
(fp_line (start -3.81 2.54) (end 3.81 2.54) (layer F.SilkS) (width 0.254))
274,18 → 277,18
(fp_line (start -3.81 2.54) (end -3.81 0) (layer F.SilkS) (width 0.254))
(fp_line (start -3.81 -2.54) (end -3.81 0) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 -2.54) (end -3.81 -2.54) (layer F.SilkS) (width 0.254))
(pad 1 thru_hole rect (at -2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(pad 1 thru_hole rect (at -2.54 1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(pad 2 thru_hole rect (at 0 1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(pad 3 thru_hole rect (at 2.54 1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 3 thru_hole rect (at 2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(pad 4 thru_hole rect (at 2.54 -1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 5 thru_hole rect (at 0 -1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(pad 4 thru_hole rect (at 2.54 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(pad 5 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(pad 6 thru_hole rect (at -2.54 -1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 6 thru_hole rect (at -2.54 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(model Pin_Headers/Pin_Header_Straight_2x03.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
294,7 → 297,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 548711F2)
(at 31.75 -40.64)
(at 0.508 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /5486108C)
309,9 → 312,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 4 "Net-(J2-Pad1)"))
(net 4 /GPIO199))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 4 "Net-(J2-Pad1)"))
(net 4 /GPIO199))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
320,7 → 323,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 548711FC)
(at 39.37 -48.26)
(at 3.048 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54861113)
335,9 → 338,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 5 "Net-(J3-Pad1)"))
(net 5 /GPIO200))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 5 "Net-(J3-Pad1)"))
(net 5 /GPIO200))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
346,7 → 349,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871206)
(at 38.1 -40.64)
(at 5.588 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54861163)
361,9 → 364,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 6 "Net-(J4-Pad1)"))
(net 6 /GPIO204))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 6 "Net-(J4-Pad1)"))
(net 6 /GPIO204))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
372,7 → 375,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x03 placed (layer F.Cu) (tedit 54870C46) (tstamp 54871216)
(at -10.16 -19.05)
(at 12.192 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /548601AA)
391,13 → 394,13
(pad 1 thru_hole rect (at -2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 3 +1.8V))
(pad 3 thru_hole rect (at 2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 3 thru_hole rect (at 2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 3 +1.8V))
(pad 4 thru_hole rect (at 2.54 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 5 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 3 +1.8V))
(pad 5 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 6 thru_hole rect (at -2.54 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(model Pin_Headers/Pin_Header_Straight_2x03.wrl
425,21 → 428,21
(fp_line (start -2 4) (end -2 -4) (layer F.SilkS) (width 0.254))
(fp_line (start -2 4) (end 0 4) (layer F.SilkS) (width 0.254))
(pad 1 thru_hole rect (at -1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 4 "Net-(J2-Pad1)"))
(net 3 +1.8V))
(pad 2 thru_hole rect (at 1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 3 +1.8V))
(net 4 /GPIO199))
(pad 3 thru_hole rect (at -1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 5 "Net-(J3-Pad1)"))
(net 8 /UART_RX))
(pad 4 thru_hole rect (at 1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 7 "Net-(J6-Pad4)"))
(net 5 /GPIO200))
(pad 5 thru_hole rect (at -1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 6 "Net-(J4-Pad1)"))
(net 7 /UART_TX))
(pad 6 thru_hole rect (at 1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 8 "Net-(J6-Pad6)"))
(net 6 /GPIO204))
(pad 7 thru_hole rect (at -1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(pad 8 thru_hole rect (at 1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 8 thru_hole rect (at 1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(model Pin_Headers/Pin_Header_Straight_2x04.wrl
(at (xyz 0 0 0))
(scale (xyz 0.7874 0.7874 0.7874))
448,7 → 451,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871232)
(at 6.35 -35.56)
(at -2.032 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54861315)
463,9 → 466,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 7 "Net-(J6-Pad4)"))
(net 8 /UART_RX))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 7 "Net-(J6-Pad4)"))
(net 8 /UART_RX))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
473,8 → 476,8
)
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 5487123C)
(at 27.94 -54.61)
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54874B71)
(at -4.572 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /5486130F)
489,9 → 492,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 8 "Net-(J6-Pad6)"))
(net 7 /UART_TX))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 8 "Net-(J6-Pad6)"))
(net 7 /UART_TX))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
499,8 → 502,8
)
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871246)
(at 20.32 -59.69)
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54874ADA)
(at -14.732 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /5486082B)
515,9 → 518,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 9 "Net-(J11-Pad1)"))
(net 9 /SCLK))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 9 "Net-(J11-Pad1)"))
(net 9 /SCLK))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
526,7 → 529,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871250)
(at 41.91 -55.88)
(at -12.192 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54860825)
541,9 → 544,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 10 "Net-(J10-Pad1)"))
(net 10 /MOSI))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 10 "Net-(J10-Pad1)"))
(net 10 /MOSI))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
569,13 → 572,13
(fp_line (start -2 2) (end -2 -2) (layer F.SilkS) (width 0.254))
(fp_line (start -2 2) (end 0 2) (layer F.SilkS) (width 0.254))
(pad 1 thru_hole rect (at -1 -1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 9 "Net-(J11-Pad1)"))
(net 9 /SCLK))
(pad 2 thru_hole rect (at 1 -1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 11 "Net-(J11-Pad2)"))
(net 10 /MOSI))
(pad 3 thru_hole rect (at -1 1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 10 "Net-(J10-Pad1)"))
(net 11 /#SS))
(pad 4 thru_hole rect (at 1 1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 12 "Net-(J11-Pad4)"))
(net 12 /MISO))
(model Pin_Headers/Pin_Header_Straight_2x02.wrl
(at (xyz 0 0 0))
(scale (xyz 0.7874 0.7874 0.7874))
584,7 → 587,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871268)
(at 22.86 -53.34)
(at -7.112 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54860610)
599,9 → 602,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 11 "Net-(J11-Pad2)"))
(net 11 /#SS))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 11 "Net-(J11-Pad2)"))
(net 11 /#SS))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
610,7 → 613,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871272)
(at 15.24 -54.61)
(at -9.652 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54860710)
625,9 → 628,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 12 "Net-(J11-Pad4)"))
(net 12 /MISO))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 12 "Net-(J11-Pad4)"))
(net 12 /MISO))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
641,10 → 644,12
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862BF8)
(fp_text reference J14 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
655,10 → 660,12
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862A8F)
(fp_text reference J15 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
669,10 → 676,12
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862E35)
(fp_text reference J16 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
683,10 → 692,12
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862E8B)
(fp_text reference J17 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
697,12 → 708,55
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862E2F)
(fp_text reference J18 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
 
(segment (start 10.5 -1.6) (end 10.5 -4.232) (width 0.4) (layer B.Cu) (net 4))
(segment (start 10.5 -4.232) (end 0.508 -14.224) (width 0.4) (layer B.Cu) (net 4))
(segment (start 12.5 -1.6) (end 12.5 -2.65) (width 0.4) (layer B.Cu) (net 5))
(segment (start 12.5 -2.65) (end 11.15401 -3.99599) (width 0.4) (layer B.Cu) (net 5))
(segment (start 11.15401 -3.99599) (end 11.15401 -4.502898) (width 0.4) (layer B.Cu) (net 5))
(segment (start 11.15401 -4.502898) (end 3.048 -12.608908) (width 0.4) (layer B.Cu) (net 5))
(segment (start 3.048 -12.608908) (end 3.048 -14.224) (width 0.4) (layer B.Cu) (net 5))
(segment (start 14.5 -1.6) (end 14.5 -1.756) (width 0.4) (layer B.Cu) (net 6))
(segment (start 14.5 -1.756) (end 11.80802 -4.44798) (width 0.4) (layer B.Cu) (net 6))
(segment (start 11.80802 -4.44798) (end 11.80802 -6.77848) (width 0.4) (layer B.Cu) (net 6))
(segment (start 11.80802 -6.77848) (end 5.588 -12.9985) (width 0.4) (layer B.Cu) (net 6))
(segment (start 5.588 -12.9985) (end 5.588 -14.224) (width 0.4) (layer B.Cu) (net 6))
(segment (start 14.5 0.4) (end 14.5 1.45) (width 0.4) (layer B.Cu) (net 7))
(segment (start 14.5 1.45) (end 13.791989 2.158011) (width 0.4) (layer B.Cu) (net 7))
(segment (start 13.791989 2.158011) (end 1.222009 2.158011) (width 0.4) (layer B.Cu) (net 7))
(segment (start 1.222009 2.158011) (end -4.572 -3.635998) (width 0.4) (layer B.Cu) (net 7))
(segment (start -4.572 -3.635998) (end -4.572 -12.9985) (width 0.4) (layer B.Cu) (net 7))
(segment (start -4.572 -12.9985) (end -4.572 -14.224) (width 0.4) (layer B.Cu) (net 7))
(segment (start 12.5 0.4) (end 12.5 1.45) (width 0.4) (layer B.Cu) (net 8))
(segment (start 12.5 1.45) (end 12.445999 1.504001) (width 0.4) (layer B.Cu) (net 8))
(segment (start 12.445999 1.504001) (end 9.486799 1.504001) (width 0.4) (layer B.Cu) (net 8))
(segment (start 9.486799 1.504001) (end 4.200001 -3.782797) (width 0.4) (layer B.Cu) (net 8))
(segment (start 4.200001 -3.782797) (end 4.200001 -7.991999) (width 0.4) (layer B.Cu) (net 8))
(segment (start 4.200001 -7.991999) (end -2.032 -14.224) (width 0.4) (layer B.Cu) (net 8))
(segment (start -14.732 -14.224) (end -14.732 -16.764) (width 0.4) (layer B.Cu) (net 9))
(segment (start -14.732 -14.224) (end -14.732 -2.868) (width 0.4) (layer B.Cu) (net 9))
(segment (start -14.732 -2.868) (end -16 -1.6) (width 0.4) (layer B.Cu) (net 9))
(segment (start -12.192 -14.224) (end -12.192 -16.764) (width 0.4) (layer B.Cu) (net 10))
(segment (start -14 -1.6) (end -14 -12.416) (width 0.4) (layer B.Cu) (net 10))
(segment (start -14 -12.416) (end -12.192 -14.224) (width 0.4) (layer B.Cu) (net 10))
(segment (start -16 0.4) (end -16 1.45) (width 0.4) (layer B.Cu) (net 11))
(segment (start -16 1.45) (end -15.945999 1.504001) (width 0.4) (layer B.Cu) (net 11))
(segment (start -15.945999 1.504001) (end -12.986799 1.504001) (width 0.4) (layer B.Cu) (net 11))
(segment (start -12.986799 1.504001) (end -7.112 -4.370798) (width 0.4) (layer B.Cu) (net 11))
(segment (start -7.112 -4.370798) (end -7.112 -14.224) (width 0.4) (layer B.Cu) (net 11))
(segment (start -9.652 -14.224) (end -9.652 -16.764) (width 0.4) (layer B.Cu) (net 12))
(segment (start -14 0.4) (end -12.95 0.4) (width 0.4) (layer B.Cu) (net 12))
(segment (start -12.95 0.4) (end -9.652 -2.898) (width 0.4) (layer B.Cu) (net 12))
(segment (start -9.652 -2.898) (end -9.652 -12.9985) (width 0.4) (layer B.Cu) (net 12))
(segment (start -9.652 -12.9985) (end -9.652 -14.224) (width 0.4) (layer B.Cu) (net 12))
 
)
/Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.kicad_pcb-bak
1,9 → 1,9
(kicad_pcb (version 4) (host pcbnew "(2014-10-14 BZR 5188)-product")
(kicad_pcb (version 4) (host pcbnew "(2014-08-29 BZR 5106)-product")
 
(general
(links 43)
(no_connects 43)
(area 150.865115 78.8162 159.014886 84.328001)
(area 0 0 0 0)
(thickness 1.6)
(drawings 0)
(tracks 0)
94,15 → 94,15
(net 1 GND)
(net 2 +5V)
(net 3 +1.8V)
(net 4 "Net-(J2-Pad1)")
(net 5 "Net-(J3-Pad1)")
(net 6 "Net-(J4-Pad1)")
(net 7 "Net-(J6-Pad4)")
(net 8 "Net-(J6-Pad6)")
(net 9 "Net-(J11-Pad1)")
(net 10 "Net-(J10-Pad1)")
(net 11 "Net-(J11-Pad2)")
(net 12 "Net-(J11-Pad4)")
(net 4 /GPIO199)
(net 5 /GPIO200)
(net 6 /GPIO204)
(net 7 /UART_TX)
(net 8 /UART_RX)
(net 9 /SCLK)
(net 10 /MOSI)
(net 11 /#SS)
(net 12 /MISO)
 
(net_class Default "Toto je výchozí třída sítě."
(clearance 0.254)
113,38 → 113,38
(uvia_drill 0.127)
(add_net +1.8V)
(add_net +5V)
(add_net /#SS)
(add_net /GPIO199)
(add_net /GPIO200)
(add_net /GPIO204)
(add_net /MISO)
(add_net /MOSI)
(add_net /SCLK)
(add_net /UART_RX)
(add_net /UART_TX)
(add_net GND)
(add_net "Net-(J10-Pad1)")
(add_net "Net-(J11-Pad1)")
(add_net "Net-(J11-Pad2)")
(add_net "Net-(J11-Pad4)")
(add_net "Net-(J2-Pad1)")
(add_net "Net-(J3-Pad1)")
(add_net "Net-(J4-Pad1)")
(add_net "Net-(J6-Pad4)")
(add_net "Net-(J6-Pad6)")
)
 
(module MLAB_C:TantalC_SizeC_Reflow (layer B.Cu) (tedit 54799D04) (tstamp 548711C6)
(at 160.02 118.11)
(at 69.85 1.27)
(descr "Tantal Cap. , Size C, EIA-6032, Reflow,")
(tags "Tantal Cap. , Size C, EIA-6032, Reflow,")
(path /5485FFA7)
(attr smd)
(fp_text reference C1 (at 0 3) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_text value CP2 (at 0 -3) (layer B.SilkS) hide
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start -4 1) (end -4 -1) (layer B.SilkS))
(fp_line (start 2 -1) (end -2 -1) (layer B.SilkS))
(fp_line (start 2 1) (end -2 1) (layer B.SilkS))
(fp_line (start -4 1) (end -4 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2 -1) (end -2 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2 1) (end -2 1) (layer B.SilkS) (width 0.15))
(fp_text user + (at -4 2) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start -5 3) (end -5 1) (layer B.SilkS))
(fp_line (start -5 2) (end -4 2) (layer B.SilkS))
(fp_line (start -5 3) (end -5 1) (layer B.SilkS) (width 0.15))
(fp_line (start -5 2) (end -4 2) (layer B.SilkS) (width 0.15))
(pad 2 smd rect (at 2 0) (size 2 2) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 1 smd rect (at -2 0) (size 2 2) (layers B.Cu B.Paste B.Mask)
157,25 → 157,25
)
 
(module MLAB_C:TantalC_SizeC_Reflow (layer B.Cu) (tedit 54799D04) (tstamp 548711CC)
(at 163.83 106.68)
(at 73.66 -10.16)
(descr "Tantal Cap. , Size C, EIA-6032, Reflow,")
(tags "Tantal Cap. , Size C, EIA-6032, Reflow,")
(path /548601CE)
(attr smd)
(fp_text reference C2 (at 0 3) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_text value CP2 (at 0 -3) (layer B.SilkS) hide
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start -4 1) (end -4 -1) (layer B.SilkS))
(fp_line (start 2 -1) (end -2 -1) (layer B.SilkS))
(fp_line (start 2 1) (end -2 1) (layer B.SilkS))
(fp_line (start -4 1) (end -4 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2 -1) (end -2 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2 1) (end -2 1) (layer B.SilkS) (width 0.15))
(fp_text user + (at -4 2) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start -5 3) (end -5 1) (layer B.SilkS))
(fp_line (start -5 2) (end -4 2) (layer B.SilkS))
(fp_line (start -5 3) (end -5 1) (layer B.SilkS) (width 0.15))
(fp_line (start -5 2) (end -4 2) (layer B.SilkS) (width 0.15))
(pad 2 smd rect (at 2 0) (size 2 2) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 1 smd rect (at -2 0) (size 2 2) (layers B.Cu B.Paste B.Mask)
188,29 → 188,29
)
 
(module MLAB_D:Diode-MiniMELF_Standard (layer B.Cu) (tedit 547999ED) (tstamp 548711D2)
(at 165.1 101.6)
(at 74.93 -15.24)
(descr "Diode Mini-MELF Standard")
(tags "Diode Mini-MELF Standard")
(path /5485FEF7)
(attr smd)
(fp_text reference D1 (at 0 2) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_text value DIODESCH (at 0 -3) (layer B.SilkS) hide
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 0) (end 0 1) (layer B.SilkS))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS))
(fp_line (start 0 -1) (end 0 0) (layer B.SilkS))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS))
(fp_line (start 0 0) (end 0 1) (layer B.SilkS) (width 0.15))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 0 -1) (end 0 0) (layer B.SilkS) (width 0.15))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS) (width 0.15))
(fp_text user A (at -1 -1) (layer B.SilkS)
(effects (font (size 0 0)) (justify mirror))
(effects (font (size 0 0) (thickness 0.15)) (justify mirror))
)
(fp_text user K (at 1 -1) (layer B.SilkS)
(effects (font (size 0 0)) (justify mirror))
(effects (font (size 0 0) (thickness 0.15)) (justify mirror))
)
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes) (width 0.15))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes) (width 0.15))
(pad 1 smd rect (at -1 0) (size 1 1) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 2 smd rect (at 1 0) (size 1 1) (layers B.Cu B.Paste B.Mask)
223,29 → 223,29
)
 
(module MLAB_D:Diode-MiniMELF_Standard (layer B.Cu) (tedit 547999ED) (tstamp 548711D8)
(at 162.56 113.03)
(at 72.39 -3.81)
(descr "Diode Mini-MELF Standard")
(tags "Diode Mini-MELF Standard")
(path /548601BC)
(attr smd)
(fp_text reference D2 (at 0 2) (layer B.SilkS)
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_text value DIODESCH (at 0 -3) (layer B.SilkS) hide
(effects (justify mirror))
(effects (font (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 0) (end 0 1) (layer B.SilkS))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS))
(fp_line (start 0 -1) (end 0 0) (layer B.SilkS))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS))
(fp_line (start 0 0) (end 0 1) (layer B.SilkS) (width 0.15))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 0 -1) (end 0 0) (layer B.SilkS) (width 0.15))
(fp_line (start 0 1) (end 0 -1) (layer B.SilkS) (width 0.15))
(fp_text user A (at -1 -1) (layer B.SilkS)
(effects (font (size 0 0)) (justify mirror))
(effects (font (size 0 0) (thickness 0.15)) (justify mirror))
)
(fp_text user K (at 1 -1) (layer B.SilkS)
(effects (font (size 0 0)) (justify mirror))
(effects (font (size 0 0) (thickness 0.15)) (justify mirror))
)
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes) (width 0.15))
(fp_circle (center 0 0) (end 0 0) (layer B.Adhes) (width 0.15))
(pad 1 smd rect (at -1 0) (size 1 1) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 2 smd rect (at 1 0) (size 1 1) (layers B.Cu B.Paste B.Mask)
258,14 → 258,14
)
 
(module MLAB_hreb:Pin_Header_Straight_2x03 placed (layer F.Cu) (tedit 54870C46) (tstamp 548711E8)
(at 130.81 100.33)
(at 15.494 -7.874 90)
(descr "1 pin")
(tags "CONN DEV")
(path /5485F9FC)
(fp_text reference J1 (at 0 -3.81) (layer F.SilkS)
(fp_text reference J1 (at 0 -3.81 90) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.2032)))
)
(fp_text value "5V POWER" (at 0 0) (layer F.SilkS) hide
(fp_text value "5V POWER" (at 0 0 90) (layer F.SilkS) hide
(effects (font (size 1.27 1.27) (thickness 0.2032)))
)
(fp_line (start -3.81 2.54) (end 3.81 2.54) (layer F.SilkS) (width 0.254))
274,18 → 274,18
(fp_line (start -3.81 2.54) (end -3.81 0) (layer F.SilkS) (width 0.254))
(fp_line (start -3.81 -2.54) (end -3.81 0) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 -2.54) (end -3.81 -2.54) (layer F.SilkS) (width 0.254))
(pad 1 thru_hole rect (at -2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(pad 1 thru_hole rect (at -2.54 1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(pad 2 thru_hole rect (at 0 1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(pad 3 thru_hole rect (at 2.54 1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 3 thru_hole rect (at 2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(pad 4 thru_hole rect (at 2.54 -1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 5 thru_hole rect (at 0 -1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(pad 4 thru_hole rect (at 2.54 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(pad 5 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(pad 6 thru_hole rect (at -2.54 -1.27 90) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 6 thru_hole rect (at -2.54 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(model Pin_Headers/Pin_Header_Straight_2x03.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
294,7 → 294,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 548711F2)
(at 132.08 106.68)
(at 0.254 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /5486108C)
309,9 → 309,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 4 "Net-(J2-Pad1)"))
(net 4 /GPIO199))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 4 "Net-(J2-Pad1)"))
(net 4 /GPIO199))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
320,7 → 320,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 548711FC)
(at 139.7 99.06)
(at 2.794 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54861113)
335,9 → 335,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 5 "Net-(J3-Pad1)"))
(net 5 /GPIO200))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 5 "Net-(J3-Pad1)"))
(net 5 /GPIO200))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
346,7 → 346,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871206)
(at 138.43 106.68)
(at 5.334 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54861163)
361,9 → 361,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 6 "Net-(J4-Pad1)"))
(net 6 /GPIO204))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 6 "Net-(J4-Pad1)"))
(net 6 /GPIO204))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
372,7 → 372,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x03 placed (layer F.Cu) (tedit 54870C46) (tstamp 54871216)
(at 132.08 87.63)
(at 12.192 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /548601AA)
391,13 → 391,13
(pad 1 thru_hole rect (at -2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 3 +1.8V))
(pad 3 thru_hole rect (at 2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 3 thru_hole rect (at 2.54 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 3 +1.8V))
(pad 4 thru_hole rect (at 2.54 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 5 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 3 +1.8V))
(pad 5 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 6 thru_hole rect (at -2.54 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(model Pin_Headers/Pin_Header_Straight_2x03.wrl
425,21 → 425,21
(fp_line (start -2 4) (end -2 -4) (layer F.SilkS) (width 0.254))
(fp_line (start -2 4) (end 0 4) (layer F.SilkS) (width 0.254))
(pad 1 thru_hole rect (at -1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 4 "Net-(J2-Pad1)"))
(net 3 +1.8V))
(pad 2 thru_hole rect (at 1 -3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 3 +1.8V))
(net 4 /GPIO199))
(pad 3 thru_hole rect (at -1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 5 "Net-(J3-Pad1)"))
(net 8 /UART_RX))
(pad 4 thru_hole rect (at 1 -1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 7 "Net-(J6-Pad4)"))
(net 5 /GPIO200))
(pad 5 thru_hole rect (at -1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 6 "Net-(J4-Pad1)"))
(net 7 /UART_TX))
(pad 6 thru_hole rect (at 1 1 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 8 "Net-(J6-Pad6)"))
(net 6 /GPIO204))
(pad 7 thru_hole rect (at -1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(pad 8 thru_hole rect (at 1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 1 GND))
(pad 8 thru_hole rect (at 1 3 90) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 2 +5V))
(model Pin_Headers/Pin_Header_Straight_2x04.wrl
(at (xyz 0 0 0))
(scale (xyz 0.7874 0.7874 0.7874))
448,7 → 448,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871232)
(at 106.68 111.76)
(at -4.826 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54861315)
463,9 → 463,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 7 "Net-(J6-Pad4)"))
(net 8 /UART_RX))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 7 "Net-(J6-Pad4)"))
(net 8 /UART_RX))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
474,7 → 474,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 5487123C)
(at 128.27 92.71)
(at -2.286 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /5486130F)
489,9 → 489,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 8 "Net-(J6-Pad6)"))
(net 7 /UART_TX))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 8 "Net-(J6-Pad6)"))
(net 7 /UART_TX))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
500,7 → 500,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871246)
(at 120.65 87.63)
(at -12.446 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /5486082B)
515,9 → 515,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 9 "Net-(J11-Pad1)"))
(net 9 /SCLK))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 9 "Net-(J11-Pad1)"))
(net 9 /SCLK))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
526,7 → 526,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871250)
(at 142.24 91.44)
(at -7.366 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54860825)
541,9 → 541,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 10 "Net-(J10-Pad1)"))
(net 10 /MOSI))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 10 "Net-(J10-Pad1)"))
(net 10 /MOSI))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
569,13 → 569,13
(fp_line (start -2 2) (end -2 -2) (layer F.SilkS) (width 0.254))
(fp_line (start -2 2) (end 0 2) (layer F.SilkS) (width 0.254))
(pad 1 thru_hole rect (at -1 -1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 9 "Net-(J11-Pad1)"))
(net 9 /SCLK))
(pad 2 thru_hole rect (at 1 -1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 11 "Net-(J11-Pad2)"))
(net 10 /MOSI))
(pad 3 thru_hole rect (at -1 1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 10 "Net-(J10-Pad1)"))
(net 11 /#SS))
(pad 4 thru_hole rect (at 1 1) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask F.SilkS)
(net 12 "Net-(J11-Pad4)"))
(net 12 /MISO))
(model Pin_Headers/Pin_Header_Straight_2x02.wrl
(at (xyz 0 0 0))
(scale (xyz 0.7874 0.7874 0.7874))
584,7 → 584,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871268)
(at 123.19 93.98)
(at -14.986 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54860610)
599,9 → 599,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 11 "Net-(J11-Pad2)"))
(net 11 /#SS))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 11 "Net-(J11-Pad2)"))
(net 11 /#SS))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
610,7 → 610,7
)
 
(module MLAB_hreb:Pin_Header_Straight_2x01 placed (layer F.Cu) (tedit 5472F1F7) (tstamp 54871272)
(at 115.57 92.71)
(at -9.906 -15.494)
(descr "1 pin")
(tags "CONN DEV")
(path /54860710)
625,9 → 625,9
(fp_line (start 1.27 2.54) (end -1.27 2.54) (layer F.SilkS) (width 0.254))
(fp_line (start -1.27 2.54) (end -1.27 -2.54) (layer F.SilkS) (width 0.254))
(pad 2 thru_hole rect (at 0 1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 12 "Net-(J11-Pad4)"))
(net 12 /MISO))
(pad 1 thru_hole rect (at 0 -1.27) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS)
(net 12 "Net-(J11-Pad4)"))
(net 12 /MISO))
(model Pin_Headers/Pin_Header_Straight_2x01.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
636,29 → 636,33
)
 
(module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 54345FDC) (tstamp 54871277)
(at 116.84 101.6)
(at 20.32 -15.44)
(descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862BF8)
(fp_text reference J14 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
 
(module MLAB_dira:MountingHole_3mm placed (layer F.Cu) (tedit 54345FDC) (tstamp 5487127C)
(at 115.57 113.03)
(at -20.32 -15.44)
(descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862A8F)
(fp_text reference J15 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
669,10 → 673,12
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862E35)
(fp_text reference J16 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
683,10 → 689,12
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862E8B)
(fp_text reference J17 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
697,10 → 705,12
(tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,")
(path /54862E2F)
(fp_text reference J18 (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value M3 (at 1 5) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User))
(fp_circle (center 0 0) (end 2 0) (layer Cmts.User) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Adhes *.Mask)
(net 1 GND) (clearance 1) (zone_connect 2))
)
/Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.net
1,8 → 1,8
(export (version D)
(design
(source C:\Chroust\Zaloha\MLAB\Modules\ARM\ODROID-U3\SCH_PCB\U3_MLAB_ADAPTER.sch)
(date "9.12.2014 12:04:41")
(tool "Eeschema (2014-10-14 BZR 5188)-product"))
(source D:/Honza/MLAB/Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.sch)
(date "9.12.2014 20:10:53")
(tool "Eeschema (2014-08-29 BZR 5106)-product"))
(components
(comp (ref J6)
(value IOS_PORT_#1)
185,74 → 185,74
(pin (num 8) (name ~) (type input)))))
(libraries
(library (logical device)
(uri C:\kicad\kicad\share\library\device.lib))
(uri C:\KiCad\kicad\share\library\device.lib))
(library (logical U3_MLAB_ADAPTER-cache)
(uri C:\Chroust\Zaloha\MLAB\Modules\ARM\ODROID-U3\SCH_PCB\U3_MLAB_ADAPTER-cache.lib)))
(uri D:\Honza\MLAB\Modules\ARM\ODROID-U3\SCH_PCB\U3_MLAB_ADAPTER-cache.lib)))
(nets
(net (code 1) (name "Net-(J2-Pad1)")
(node (ref J2) (pin 2))
(net (code 1) (name +1.8V)
(node (ref C2) (pin 1))
(node (ref D2) (pin 2))
(node (ref J6) (pin 1))
(node (ref J2) (pin 1)))
(net (code 2) (name +5V)
(node (ref D1) (pin 2))
(node (ref C1) (pin 1))
(node (ref J6) (pin 8))
(node (ref J1) (pin 3))
(node (ref J1) (pin 4)))
(net (code 3) (name +1.8V)
(node (ref D2) (pin 2))
(node (ref J5) (pin 4))
(node (ref J5) (pin 3))
(node (ref C2) (pin 1))
(node (ref J6) (pin 2)))
(net (code 4) (name "Net-(J4-Pad1)")
(node (ref J5) (pin 5))
(node (ref J5) (pin 2)))
(net (code 2) (name /GPIO199)
(node (ref J2) (pin 1))
(node (ref J6) (pin 2))
(node (ref J2) (pin 2)))
(net (code 3) (name /GPIO204)
(node (ref J6) (pin 6))
(node (ref J4) (pin 1))
(node (ref J4) (pin 2))
(node (ref J6) (pin 5)))
(net (code 5) (name "Net-(J6-Pad4)")
(node (ref J7) (pin 2))
(node (ref J7) (pin 1))
(node (ref J6) (pin 4)))
(net (code 6) (name "Net-(J11-Pad2)")
(node (ref J4) (pin 2)))
(net (code 4) (name /MISO)
(node (ref J13) (pin 2))
(node (ref J13) (pin 1))
(node (ref J11) (pin 4)))
(net (code 5) (name /#SS)
(node (ref J11) (pin 3))
(node (ref J12) (pin 2))
(node (ref J12) (pin 1)))
(net (code 6) (name /SCLK)
(node (ref J9) (pin 1))
(node (ref J9) (pin 2))
(node (ref J11) (pin 1)))
(net (code 7) (name /MOSI)
(node (ref J11) (pin 2))
(node (ref J12) (pin 1)))
(net (code 7) (name "Net-(J10-Pad1)")
(node (ref J10) (pin 2))
(node (ref J10) (pin 1))
(node (ref J11) (pin 3)))
(net (code 8) (name "Net-(J11-Pad4)")
(node (ref J11) (pin 4))
(node (ref J13) (pin 1))
(node (ref J13) (pin 2)))
(net (code 9) (name "Net-(J6-Pad6)")
(node (ref J10) (pin 2)))
(net (code 8) (name +5V)
(node (ref D1) (pin 2))
(node (ref C1) (pin 1))
(node (ref J6) (pin 7))
(node (ref J1) (pin 2))
(node (ref J1) (pin 5)))
(net (code 9) (name /UART_RX)
(node (ref J7) (pin 1))
(node (ref J7) (pin 2))
(node (ref J6) (pin 3)))
(net (code 10) (name /UART_TX)
(node (ref J8) (pin 1))
(node (ref J8) (pin 2))
(node (ref J6) (pin 6)))
(net (code 10) (name "Net-(J11-Pad1)")
(node (ref J9) (pin 2))
(node (ref J9) (pin 1))
(node (ref J11) (pin 1)))
(net (code 11) (name GND)
(node (ref J1) (pin 6))
(node (ref J1) (pin 5))
(node (ref J5) (pin 5))
(node (ref C2) (pin 2))
(node (ref J6) (pin 5))
(node (ref J8) (pin 2)))
(net (code 11) (name /GPIO200)
(node (ref J3) (pin 2))
(node (ref J3) (pin 1))
(node (ref J6) (pin 4)))
(net (code 12) (name GND)
(node (ref J5) (pin 1))
(node (ref J5) (pin 2))
(node (ref J5) (pin 3))
(node (ref J5) (pin 4))
(node (ref J5) (pin 6))
(node (ref D2) (pin 1))
(node (ref J15) (pin 1))
(node (ref J1) (pin 2))
(node (ref C2) (pin 2))
(node (ref J14) (pin 1))
(node (ref D1) (pin 1))
(node (ref C1) (pin 2))
(node (ref J17) (pin 1))
(node (ref J16) (pin 1))
(node (ref J18) (pin 1))
(node (ref J14) (pin 1))
(node (ref J15) (pin 1))
(node (ref J6) (pin 8))
(node (ref J1) (pin 1))
(node (ref J6) (pin 7))
(node (ref C1) (pin 2))
(node (ref D1) (pin 1)))
(net (code 12) (name "Net-(J3-Pad1)")
(node (ref J3) (pin 2))
(node (ref J3) (pin 1))
(node (ref J6) (pin 3)))))
(node (ref J1) (pin 3))
(node (ref J1) (pin 4))
(node (ref J1) (pin 6)))))
/Modules/ARM/ODROID-U3/SCH_PCB/U3_MLAB_ADAPTER.sch
1,4 → 1,3
<<<<<<< .mine
EESchema Schematic File Version 2
LIBS:power
LIBS:device
31,7 → 30,7
LIBS:contrib
LIBS:valves
LIBS:U3_MLAB_ADAPTER-cache
EELAYER 25 0
EELAYER 24 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
51,7 → 50,7
P 3600 3400
F 0 "J6" H 3600 3150 60 0000 C CNN
F 1 "IOS_PORT_#1" H 3600 3650 60 0000 C CNN
F 2 "MLAB_hreb:2mm_Pin_Header_Straight_2x04" H 3600 3550 60 0001 C CNN
F 2 "" H 3600 3550 60 0000 C CNN
F 3 "" H 3600 3550 60 0000 C CNN
1 3600 3400
1 0 0 -1
62,7 → 61,7
P 7550 3300
F 0 "J11" H 7550 3500 60 0000 C CNN
F 1 "IO_PORT_#2" H 7550 3100 60 0000 C CNN
F 2 "MLAB_hreb:2mm_Pin_Header_Straight_2x02" H 7550 3350 60 0001 C CNN
F 2 "" H 7550 3350 60 0000 C CNN
F 3 "" H 7550 3350 60 0000 C CNN
1 7550 3300
1 0 0 -1
73,7 → 72,7
P 1750 5900
F 0 "J1" H 1750 5700 60 0000 C CNN
F 1 "5V POWER" H 1750 6100 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x03" H 1750 6000 60 0001 C CNN
F 2 "" H 1750 6000 60 0000 C CNN
F 3 "" H 1750 6000 60 0000 C CNN
1 1750 5900
-1 0 0 -1
106,7 → 105,7
P 2400 6150
F 0 "D1" H 2400 6250 40 0000 C CNN
F 1 "DIODESCH" H 2400 6050 40 0000 C CNN
F 2 "MLAB_D:Diode-MiniMELF_Standard" H 2400 6150 60 0001 C CNN
F 2 "" H 2400 6150 60 0000 C CNN
F 3 "" H 2400 6150 60 0000 C CNN
1 2400 6150
0 -1 -1 0
139,7 → 138,7
P 2750 6150
F 0 "C1" H 2750 6250 40 0000 L CNN
F 1 "CP2" H 2756 6065 40 0000 L CNN
F 2 "MLAB_C:TantalC_SizeC_Reflow" H 2788 6000 30 0001 C CNN
F 2 "" H 2788 6000 30 0000 C CNN
F 3 "" H 2750 6150 60 0000 C CNN
1 2750 6150
1 0 0 -1
169,7 → 168,7
P 3550 5900
F 0 "J5" H 3550 5700 60 0000 C CNN
F 1 "1,8V CPU Core" H 3550 6100 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x03" H 3550 6000 60 0001 C CNN
F 2 "" H 3550 6000 60 0000 C CNN
F 3 "" H 3550 6000 60 0000 C CNN
1 3550 5900
-1 0 0 -1
191,7 → 190,7
P 4200 6150
F 0 "D2" H 4200 6250 40 0000 C CNN
F 1 "DIODESCH" H 4200 6050 40 0000 C CNN
F 2 "MLAB_D:Diode-MiniMELF_Standard" H 4200 6150 60 0001 C CNN
F 2 "" H 4200 6150 60 0000 C CNN
F 3 "" H 4200 6150 60 0000 C CNN
1 4200 6150
0 -1 -1 0
224,7 → 223,7
P 4550 6150
F 0 "C2" H 4550 6250 40 0000 L CNN
F 1 "CP2" H 4556 6065 40 0000 L CNN
F 2 "MLAB_C:TantalC_SizeC_Reflow" H 4588 6000 30 0001 C CNN
F 2 "" H 4588 6000 30 0000 C CNN
F 3 "" H 4550 6150 60 0000 C CNN
1 4550 6150
1 0 0 -1
265,7 → 264,7
P 8350 3100
F 0 "J12" H 8350 3200 60 0000 C CNN
F 1 "#SS" H 8600 3100 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 8350 3100 60 0001 C CNN
F 2 "" H 8350 3100 60 0000 C CNN
F 3 "" H 8350 3100 60 0000 C CNN
1 8350 3100
1 0 0 -1
276,7 → 275,7
P 8350 3500
F 0 "J13" H 8350 3600 60 0000 C CNN
F 1 "MISO" H 8600 3500 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 8350 3500 60 0001 C CNN
F 2 "" H 8350 3500 60 0000 C CNN
F 3 "" H 8350 3500 60 0000 C CNN
1 8350 3500
1 0 0 -1
284,23 → 283,23
$Comp
L HEADER_2x01_PARALLEL J10
U 1 1 54860825
P 6750 3500
F 0 "J10" H 6750 3400 60 0000 C CNN
F 1 "MOSI" H 7000 3500 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 6750 3500 60 0001 C CNN
F 3 "" H 6750 3500 60 0000 C CNN
1 6750 3500
P 6650 3500
F 0 "J10" H 6650 3400 60 0000 C CNN
F 1 "MOSI" H 6900 3500 60 0000 C CNN
F 2 "" H 6650 3500 60 0000 C CNN
F 3 "" H 6650 3500 60 0000 C CNN
1 6650 3500
-1 0 0 1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J9
U 1 1 5486082B
P 6750 3150
F 0 "J9" H 6750 3050 60 0000 C CNN
F 1 "SCLK" H 7000 3150 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 6750 3150 60 0001 C CNN
F 3 "" H 6750 3150 60 0000 C CNN
1 6750 3150
P 6650 3150
F 0 "J9" H 6650 3050 60 0000 C CNN
F 1 "SCLK" H 6900 3150 60 0000 C CNN
F 2 "" H 6650 3150 60 0000 C CNN
F 3 "" H 6650 3150 60 0000 C CNN
1 6650 3150
-1 0 0 1
$EndComp
Wire Wire Line
320,9 → 319,9
Wire Wire Line
7150 3250 7150 3150
Wire Wire Line
7150 3150 7000 3150
7150 3150 6900 3150
Wire Wire Line
7000 3500 7150 3500
6900 3500 7150 3500
Wire Wire Line
7150 3500 7150 3350
Wire Wire Line
363,7 → 362,7
P 2550 3100
F 0 "J2" H 2550 3000 60 0000 C CNN
F 1 "GPIO199" H 2900 3100 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 2550 3100 60 0001 C CNN
F 2 "" H 2550 3100 60 0000 C CNN
F 3 "" H 2550 3100 60 0000 C CNN
1 2550 3100
-1 0 0 1
374,7 → 373,7
P 2550 3300
F 0 "J3" H 2550 3200 60 0000 C CNN
F 1 "GPIO200" H 2900 3300 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 2550 3300 60 0001 C CNN
F 2 "" H 2550 3300 60 0000 C CNN
F 3 "" H 2550 3300 60 0000 C CNN
1 2550 3300
-1 0 0 1
385,7 → 384,7
P 2550 3500
F 0 "J4" H 2550 3400 60 0000 C CNN
F 1 "GPIO204" H 2900 3500 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 2550 3500 60 0001 C CNN
F 2 "" H 2550 3500 60 0000 C CNN
F 3 "" H 2550 3500 60 0000 C CNN
1 2550 3500
-1 0 0 1
396,7 → 395,7
P 4950 3500
F 0 "J8" H 4950 3600 60 0000 C CNN
F 1 "UART_TX" H 5300 3500 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 4950 3500 60 0001 C CNN
F 2 "" H 4950 3500 60 0000 C CNN
F 3 "" H 4950 3500 60 0000 C CNN
1 4950 3500
1 0 0 -1
407,7 → 406,7
P 4950 3300
F 0 "J7" H 4950 3400 60 0000 C CNN
F 1 "UART_RX" H 5300 3300 60 0000 C CNN
F 2 "MLAB_hreb:Pin_Header_Straight_2x01" H 4950 3300 60 0001 C CNN
F 2 "" H 4950 3300 60 0000 C CNN
F 3 "" H 4950 3300 60 0000 C CNN
1 4950 3300
1 0 0 -1
463,7 → 462,7
P 8500 4700
F 0 "J15" H 8450 4850 50 0000 C CNN
F 1 "M3" H 8550 4750 40 0000 C CNN
F 2 "MLAB_dira:MountingHole_3mm" H 8550 4650 60 0001 C CNN
F 2 "" H 8550 4650 60 0000 C CNN
F 3 "" H 8550 4650 60 0000 C CNN
1 8500 4700
1 0 0 -1
474,7 → 473,7
P 8500 4550
F 0 "J14" H 8450 4700 50 0000 C CNN
F 1 "M3" H 8550 4600 40 0000 C CNN
F 2 "MLAB_dira:MountingHole_3mm" H 8550 4500 60 0001 C CNN
F 2 "" H 8550 4500 60 0000 C CNN
F 3 "" H 8550 4500 60 0000 C CNN
1 8500 4550
1 0 0 -1
485,7 → 484,7
P 8500 5150
F 0 "J18" H 8450 5300 50 0000 C CNN
F 1 "M3" H 8550 5200 40 0000 C CNN
F 2 "MLAB_dira:MountingHole_3mm" H 8550 5100 60 0001 C CNN
F 2 "" H 8550 5100 60 0000 C CNN
F 3 "" H 8550 5100 60 0000 C CNN
1 8500 5150
1 0 0 -1
496,7 → 495,7
P 8500 4850
F 0 "J16" H 8450 5000 50 0000 C CNN
F 1 "M3" H 8550 4900 40 0000 C CNN
F 2 "MLAB_dira:MountingHole_3mm" H 8550 4800 60 0001 C CNN
F 2 "" H 8550 4800 60 0000 C CNN
F 3 "" H 8550 4800 60 0000 C CNN
1 8500 4850
1 0 0 -1
507,7 → 506,7
P 8500 5000
F 0 "J17" H 8450 5150 50 0000 C CNN
F 1 "M3" H 8550 5050 40 0000 C CNN
F 2 "MLAB_dira:MountingHole_3mm" H 8550 4950 60 0001 C CNN
F 2 "" H 8550 4950 60 0000 C CNN
F 3 "" H 8550 4950 60 0000 C CNN
1 8500 5000
1 0 0 -1
549,560 → 548,22
MECHANICAL HOLES \n3,2mm diameter
Wire Wire Line
8100 4500 8100 5250
Text Label 6900 3150 0 60 ~ 0
SCLK
Text Label 6900 3500 0 60 ~ 0
MOSI
Text Label 7800 3250 0 60 ~ 0
#SS
Text Label 7800 3350 0 60 ~ 0
MISO
Text Label 4350 3300 0 60 ~ 0
UART_RX
Text Label 4350 3500 0 60 ~ 0
UART_TX
Text Label 2950 3250 0 60 ~ 0
GPIO199
Text Label 2950 3350 0 60 ~ 0
GPIO200
Text Label 2950 3450 0 60 ~ 0
GPIO204
$EndSCHEMATC
=======
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:header
LIBS:konektory
LIBS:Jumpers
LIBS:U3_MLAB_ADAPTER-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L HEADER_2x04 J6
U 1 1 5485F8D0
P 3600 3400
F 0 "J6" H 3600 3150 60 0000 C CNN
F 1 "IOS_PORT_#1" H 3600 3650 60 0000 C CNN
F 2 "" H 3600 3550 60 0000 C CNN
F 3 "" H 3600 3550 60 0000 C CNN
1 3600 3400
1 0 0 -1
$EndComp
$Comp
L HEADER_2x02 J11
U 1 1 5485F97F
P 7550 3300
F 0 "J11" H 7550 3500 60 0000 C CNN
F 1 "IO_PORT_#2" H 7550 3100 60 0000 C CNN
F 2 "" H 7550 3350 60 0000 C CNN
F 3 "" H 7550 3350 60 0000 C CNN
1 7550 3300
1 0 0 -1
$EndComp
$Comp
L HEADER_2x03_PARALLEL J1
U 1 1 5485F9FC
P 1750 5900
F 0 "J1" H 1750 5700 60 0000 C CNN
F 1 "5V POWER" H 1750 6100 60 0000 C CNN
F 2 "" H 1750 6000 60 0000 C CNN
F 3 "" H 1750 6000 60 0000 C CNN
1 1750 5900
-1 0 0 -1
$EndComp
$Comp
L GND #PWR1
U 1 1 5485FDDC
P 2100 6150
F 0 "#PWR1" H 2100 6150 30 0001 C CNN
F 1 "GND" H 2100 6080 30 0001 C CNN
F 2 "" H 2100 6150 60 0000 C CNN
F 3 "" H 2100 6150 60 0000 C CNN
1 2100 6150
1 0 0 -1
$EndComp
$Comp
L +5V #PWR3
U 1 1 5485FEBD
P 2750 5750
F 0 "#PWR3" H 2750 5840 20 0001 C CNN
F 1 "+5V" H 2750 5840 30 0000 C CNN
F 2 "" H 2750 5750 60 0000 C CNN
F 3 "" H 2750 5750 60 0000 C CNN
1 2750 5750
1 0 0 -1
$EndComp
$Comp
L DIODESCH D1
U 1 1 5485FEF7
P 2400 6150
F 0 "D1" H 2400 6250 40 0000 C CNN
F 1 "DIODESCH" H 2400 6050 40 0000 C CNN
F 2 "" H 2400 6150 60 0000 C CNN
F 3 "" H 2400 6150 60 0000 C CNN
1 2400 6150
0 -1 -1 0
$EndComp
$Comp
L GND #PWR2
U 1 1 5485FF80
P 2400 6450
F 0 "#PWR2" H 2400 6450 30 0001 C CNN
F 1 "GND" H 2400 6380 30 0001 C CNN
F 2 "" H 2400 6450 60 0000 C CNN
F 3 "" H 2400 6450 60 0000 C CNN
1 2400 6450
1 0 0 -1
$EndComp
$Comp
L GND #PWR4
U 1 1 5485FF9A
P 2750 6450
F 0 "#PWR4" H 2750 6450 30 0001 C CNN
F 1 "GND" H 2750 6380 30 0001 C CNN
F 2 "" H 2750 6450 60 0000 C CNN
F 3 "" H 2750 6450 60 0000 C CNN
1 2750 6450
1 0 0 -1
$EndComp
$Comp
L CP2 C1
U 1 1 5485FFA7
P 2750 6150
F 0 "C1" H 2750 6250 40 0000 L CNN
F 1 "CP2" H 2756 6065 40 0000 L CNN
F 2 "" H 2788 6000 30 0000 C CNN
F 3 "" H 2750 6150 60 0000 C CNN
1 2750 6150
1 0 0 -1
$EndComp
Wire Wire Line
2000 5900 2750 5900
Wire Wire Line
2400 5900 2400 5950
Connection ~ 2400 5900
Connection ~ 2750 5900
Wire Wire Line
2400 6350 2400 6450
Wire Wire Line
2750 6350 2750 6450
Wire Wire Line
2100 5800 2100 6150
Wire Wire Line
2100 5800 2000 5800
Wire Wire Line
2000 6000 2100 6000
Connection ~ 2100 6000
Wire Wire Line
2750 5750 2750 5950
$Comp
L HEADER_2x03_PARALLEL J5
U 1 1 548601AA
P 3550 5900
F 0 "J5" H 3550 5700 60 0000 C CNN
F 1 "1,8V CPU Core" H 3550 6100 60 0000 C CNN
F 2 "" H 3550 6000 60 0000 C CNN
F 3 "" H 3550 6000 60 0000 C CNN
1 3550 5900
-1 0 0 -1
$EndComp
$Comp
L GND #PWR6
U 1 1 548601B0
P 3900 6150
F 0 "#PWR6" H 3900 6150 30 0001 C CNN
F 1 "GND" H 3900 6080 30 0001 C CNN
F 2 "" H 3900 6150 60 0000 C CNN
F 3 "" H 3900 6150 60 0000 C CNN
1 3900 6150
1 0 0 -1
$EndComp
$Comp
L DIODESCH D2
U 1 1 548601BC
P 4200 6150
F 0 "D2" H 4200 6250 40 0000 C CNN
F 1 "DIODESCH" H 4200 6050 40 0000 C CNN
F 2 "" H 4200 6150 60 0000 C CNN
F 3 "" H 4200 6150 60 0000 C CNN
1 4200 6150
0 -1 -1 0
$EndComp
$Comp
L GND #PWR9
U 1 1 548601C2
P 4200 6450
F 0 "#PWR9" H 4200 6450 30 0001 C CNN
F 1 "GND" H 4200 6380 30 0001 C CNN
F 2 "" H 4200 6450 60 0000 C CNN
F 3 "" H 4200 6450 60 0000 C CNN
1 4200 6450
1 0 0 -1
$EndComp
$Comp
L GND #PWR11
U 1 1 548601C8
P 4550 6450
F 0 "#PWR11" H 4550 6450 30 0001 C CNN
F 1 "GND" H 4550 6380 30 0001 C CNN
F 2 "" H 4550 6450 60 0000 C CNN
F 3 "" H 4550 6450 60 0000 C CNN
1 4550 6450
1 0 0 -1
$EndComp
$Comp
L CP2 C2
U 1 1 548601CE
P 4550 6150
F 0 "C2" H 4550 6250 40 0000 L CNN
F 1 "CP2" H 4556 6065 40 0000 L CNN
F 2 "" H 4588 6000 30 0000 C CNN
F 3 "" H 4550 6150 60 0000 C CNN
1 4550 6150
1 0 0 -1
$EndComp
Wire Wire Line
3800 5900 4550 5900
Wire Wire Line
4200 5900 4200 5950
Connection ~ 4200 5900
Connection ~ 4550 5900
Wire Wire Line
4200 6350 4200 6450
Wire Wire Line
4550 6350 4550 6450
Wire Wire Line
3900 5800 3900 6150
Wire Wire Line
3900 5800 3800 5800
Wire Wire Line
3800 6000 3900 6000
Connection ~ 3900 6000
Wire Wire Line
4550 5650 4550 5950
$Comp
L +1.8V #PWR10
U 1 1 5486039E
P 4550 5650
F 0 "#PWR10" H 4550 5790 20 0001 C CNN
F 1 "+1.8V" H 4550 5760 30 0000 C CNN
F 2 "" H 4550 5650 60 0000 C CNN
F 3 "" H 4550 5650 60 0000 C CNN
1 4550 5650
1 0 0 -1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J12
U 1 1 54860610
P 8350 3100
F 0 "J12" H 8350 3200 60 0000 C CNN
F 1 "#SS" H 8600 3100 60 0000 C CNN
F 2 "" H 8350 3100 60 0000 C CNN
F 3 "" H 8350 3100 60 0000 C CNN
1 8350 3100
1 0 0 -1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J13
U 1 1 54860710
P 8350 3500
F 0 "J13" H 8350 3600 60 0000 C CNN
F 1 "MISO" H 8600 3500 60 0000 C CNN
F 2 "" H 8350 3500 60 0000 C CNN
F 3 "" H 8350 3500 60 0000 C CNN
1 8350 3500
1 0 0 -1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J10
U 1 1 54860825
P 6750 3500
F 0 "J10" H 6750 3400 60 0000 C CNN
F 1 "MOSI" H 7000 3500 60 0000 C CNN
F 2 "" H 6750 3500 60 0000 C CNN
F 3 "" H 6750 3500 60 0000 C CNN
1 6750 3500
-1 0 0 1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J9
U 1 1 5486082B
P 6750 3150
F 0 "J9" H 6750 3050 60 0000 C CNN
F 1 "SCLK" H 7000 3150 60 0000 C CNN
F 2 "" H 6750 3150 60 0000 C CNN
F 3 "" H 6750 3150 60 0000 C CNN
1 6750 3150
-1 0 0 1
$EndComp
Wire Wire Line
7800 3350 8000 3350
Wire Wire Line
8000 3350 8000 3500
Wire Wire Line
8000 3500 8100 3500
Wire Wire Line
7800 3250 8000 3250
Wire Wire Line
8000 3250 8000 3100
Wire Wire Line
8000 3100 8100 3100
Wire Wire Line
7300 3250 7150 3250
Wire Wire Line
7150 3250 7150 3150
Wire Wire Line
7150 3150 7000 3150
Wire Wire Line
7000 3500 7150 3500
Wire Wire Line
7150 3500 7150 3350
Wire Wire Line
7150 3350 7300 3350
$Comp
L +5V #PWR8
U 1 1 54860E24
P 4100 2950
F 0 "#PWR8" H 4100 3040 20 0001 C CNN
F 1 "+5V" H 4100 3040 30 0000 C CNN
F 2 "" H 4100 2950 60 0000 C CNN
F 3 "" H 4100 2950 60 0000 C CNN
1 4100 2950
1 0 0 -1
$EndComp
Wire Wire Line
4100 2950 4100 3550
Wire Wire Line
4100 3550 3850 3550
$Comp
L +1.8V #PWR7
U 1 1 54860E81
P 3950 2950
F 0 "#PWR7" H 3950 3090 20 0001 C CNN
F 1 "+1.8V" H 3950 3060 30 0000 C CNN
F 2 "" H 3950 2950 60 0000 C CNN
F 3 "" H 3950 2950 60 0000 C CNN
1 3950 2950
1 0 0 -1
$EndComp
Wire Wire Line
3850 3250 3950 3250
Wire Wire Line
3950 3250 3950 2950
$Comp
L HEADER_2x01_PARALLEL J2
U 1 1 5486108C
P 2550 3100
F 0 "J2" H 2550 3000 60 0000 C CNN
F 1 "GPIO199" H 2900 3100 60 0000 C CNN
F 2 "" H 2550 3100 60 0000 C CNN
F 3 "" H 2550 3100 60 0000 C CNN
1 2550 3100
-1 0 0 1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J3
U 1 1 54861113
P 2550 3300
F 0 "J3" H 2550 3200 60 0000 C CNN
F 1 "GPIO200" H 2900 3300 60 0000 C CNN
F 2 "" H 2550 3300 60 0000 C CNN
F 3 "" H 2550 3300 60 0000 C CNN
1 2550 3300
-1 0 0 1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J4
U 1 1 54861163
P 2550 3500
F 0 "J4" H 2550 3400 60 0000 C CNN
F 1 "GPIO204" H 2900 3500 60 0000 C CNN
F 2 "" H 2550 3500 60 0000 C CNN
F 3 "" H 2550 3500 60 0000 C CNN
1 2550 3500
-1 0 0 1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J8
U 1 1 5486130F
P 4950 3500
F 0 "J8" H 4950 3600 60 0000 C CNN
F 1 "UART_TX" H 5300 3500 60 0000 C CNN
F 2 "" H 4950 3500 60 0000 C CNN
F 3 "" H 4950 3500 60 0000 C CNN
1 4950 3500
1 0 0 -1
$EndComp
$Comp
L HEADER_2x01_PARALLEL J7
U 1 1 54861315
P 4950 3300
F 0 "J7" H 4950 3400 60 0000 C CNN
F 1 "UART_RX" H 5300 3300 60 0000 C CNN
F 2 "" H 4950 3300 60 0000 C CNN
F 3 "" H 4950 3300 60 0000 C CNN
1 4950 3300
1 0 0 -1
$EndComp
Wire Wire Line
3850 3450 4350 3450
Wire Wire Line
2800 3100 2950 3100
Wire Wire Line
2950 3100 2950 3250
Wire Wire Line
2950 3250 3350 3250
Wire Wire Line
3350 3350 2900 3350
Wire Wire Line
2900 3350 2900 3300
Wire Wire Line
2900 3300 2800 3300
Wire Wire Line
2800 3500 2900 3500
Wire Wire Line
2900 3500 2900 3450
Wire Wire Line
2900 3450 3350 3450
Wire Wire Line
4350 3450 4350 3500
Wire Wire Line
4350 3500 4700 3500
Wire Wire Line
4700 3300 4350 3300
Wire Wire Line
4350 3300 4350 3350
Wire Wire Line
4350 3350 3850 3350
$Comp
L GND #PWR5
U 1 1 54861F1A
P 3250 3650
F 0 "#PWR5" H 3250 3650 30 0001 C CNN
F 1 "GND" H 3250 3580 30 0001 C CNN
F 2 "" H 3250 3650 60 0000 C CNN
F 3 "" H 3250 3650 60 0000 C CNN
1 3250 3650
1 0 0 -1
$EndComp
Wire Wire Line
3250 3550 3250 3650
Wire Wire Line
3350 3550 3250 3550
$Comp
L CONN1_1 J15
U 1 1 54862A8F
P 8500 4700
F 0 "J15" H 8450 4850 50 0000 C CNN
F 1 "M3" H 8550 4750 40 0000 C CNN
F 2 "" H 8550 4650 60 0000 C CNN
F 3 "" H 8550 4650 60 0000 C CNN
1 8500 4700
1 0 0 -1
$EndComp
$Comp
L CONN1_1 J14
U 1 1 54862BF8
P 8500 4550
F 0 "J14" H 8450 4700 50 0000 C CNN
F 1 "M3" H 8550 4600 40 0000 C CNN
F 2 "" H 8550 4500 60 0000 C CNN
F 3 "" H 8550 4500 60 0000 C CNN
1 8500 4550
1 0 0 -1
$EndComp
$Comp
L CONN1_1 J18
U 1 1 54862E2F
P 8500 5150
F 0 "J18" H 8450 5300 50 0000 C CNN
F 1 "M3" H 8550 5200 40 0000 C CNN
F 2 "" H 8550 5100 60 0000 C CNN
F 3 "" H 8550 5100 60 0000 C CNN
1 8500 5150
1 0 0 -1
$EndComp
$Comp
L CONN1_1 J16
U 1 1 54862E35
P 8500 4850
F 0 "J16" H 8450 5000 50 0000 C CNN
F 1 "M3" H 8550 4900 40 0000 C CNN
F 2 "" H 8550 4800 60 0000 C CNN
F 3 "" H 8550 4800 60 0000 C CNN
1 8500 4850
1 0 0 -1
$EndComp
$Comp
L CONN1_1 J17
U 1 1 54862E8B
P 8500 5000
F 0 "J17" H 8450 5150 50 0000 C CNN
F 1 "M3" H 8550 5050 40 0000 C CNN
F 2 "" H 8550 4950 60 0000 C CNN
F 3 "" H 8550 4950 60 0000 C CNN
1 8500 5000
1 0 0 -1
$EndComp
$Comp
L GND #PWR12
U 1 1 54863035
P 8100 5250
F 0 "#PWR12" H 8100 5250 30 0001 C CNN
F 1 "GND" H 8100 5180 30 0001 C CNN
F 2 "" H 8100 5250 60 0000 C CNN
F 3 "" H 8100 5250 60 0000 C CNN
1 8100 5250
1 0 0 -1
$EndComp
Wire Wire Line
8100 4500 8200 4500
Wire Wire Line
8200 4650 8100 4650
Connection ~ 8100 4650
Wire Wire Line
8100 4800 8200 4800
Connection ~ 8100 4800
Wire Wire Line
8100 4950 8200 4950
Connection ~ 8100 4950
Wire Wire Line
8100 5100 8200 5100
Connection ~ 8100 5100
Wire Notes Line
7700 4200 9700 4200
Wire Notes Line
9700 4200 9700 5700
Wire Notes Line
9700 5700 7700 5700
Wire Notes Line
7700 5700 7700 4200
Text Notes 8700 4950 0 60 ~ 0
MECHANICAL HOLES \n3,2mm diameter
Wire Wire Line
8100 4500 8100 5250
$EndSCHEMATC
>>>>>>> .r3812
/Modules/Audio/ADCaudio01B/PCB_SCH/ADCaudio01B-B_Adhes.pdf
71,7 → 71,7
10 0 obj
<<
/Producer (KiCAD PDF)
/CreationDate (D:20141130130535)
/CreationDate (D:20141208204332)
/Creator (PCBNEW)
/Title (D:\Honza\MLAB\Modules\Audio\ADCaudio01B\PCB_SCH\ADCaudio01B-B_Adhes.pdf)
/Trapped false
/Modules/Audio/ADCaudio01B/PCB_SCH/ADCaudio01B-F_Adhes.pdf
68,7 → 68,7
10 0 obj
<<
/Producer (KiCAD PDF)
/CreationDate (D:20141130130535)
/CreationDate (D:20141208204332)
/Creator (PCBNEW)
/Title (D:\Honza\MLAB\Modules\Audio\ADCaudio01B\PCB_SCH\ADCaudio01B-F_Adhes.pdf)
/Trapped false