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/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/src/PulseGen.vhd
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----------------------------------------------------------------------------------
-- Company: www.mlab.cz
-- Based on code written by MIHO.
--
-- Design Name: S3AN01A
-- Project Name: PulseGen
-- Target Devices: XC3S50AN-4
-- Tool versions: ISE 13.3
-- Description: Sample of Pulse Generator at S3AN01A MLAB board.
--
-- Dependencies: External PS/2 Keyboard has to be connected.
--
-- Version: $Id$
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use WORK.PS2_pkg.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity PulseGen is
generic (
-- Top Value for 100MHz Clock Counter
MAXCOUNT: integer := 30_000_000;
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
);
port (
-- Main Clock
CLK100MHz: in std_logic;
-- Mode Signals (usualy not used)
M: in std_logic_vector(2 downto 0);
VS: in std_logic_vector(2 downto 0);
-- Dipswitch Inputs
DIPSW: in std_logic_vector(7 downto 0);
-- Push Buttons
PB: in std_logic_vector(3 downto 0);
-- LED Bar Outputs
LED: out std_logic_vector(7 downto 0);
-- LED Display (8 digit with 7 segments and ddecimal point)
LD_A_n: out std_logic;
LD_B_n: out std_logic;
LD_C_n: out std_logic;
LD_D_n: out std_logic;
LD_E_n: out std_logic;
LD_F_n: out std_logic;
LD_G_n: out std_logic;
LD_DP_n: out std_logic;
LD_0_n: out std_logic;
LD_1_n: out std_logic;
LD_2_n: out std_logic;
LD_3_n: out std_logic;
LD_4_n: out std_logic;
LD_5_n: out std_logic;
LD_6_n: out std_logic;
LD_7_n: out std_logic;
-- VGA Video Out Port
VGA_R: out std_logic_vector(1 downto 0);
VGA_G: out std_logic_vector(1 downto 0);
VGA_B: out std_logic_vector(1 downto 0);
VGA_VS: out std_logic;
VGA_HS: out std_logic;
-- Bank 1 Pins - Inputs for this Test
B: inout std_logic_vector(24 downto 0);
-- PS/2 Bidirectional Port (open collector, J31 and J32)
-- PS2_CLK1: inout std_logic;
-- PS2_DATA1: inout std_logic;
PS2_CLK2: inout std_logic;
PS2_DATA2: inout std_logic;
-- Diferencial Signals on 4 pin header (J7)
DIF1P: inout std_logic;
DIF1N: inout std_logic;
DIF2P: inout std_logic;
DIF2N: inout std_logic;
-- I2C Signals (on connector J30)
I2C_SCL: inout std_logic;
I2C_SDA: inout std_logic;
-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
SD1AP: inout std_logic;
SD1AN: inout std_logic;
SD1BP: inout std_logic;
SD1BN: inout std_logic;
SD2AP: inout std_logic;
SD2AN: inout std_logic;
SD2BP: inout std_logic;
SD2BN: inout std_logic;
-- Analog In Out
ANA_OUTD: out std_logic;
ANA_REFD: out std_logic;
ANA_IND: in std_logic;
-- SPI Memory Interface
SPI_CS_n: inout std_logic;
SPI_DO: inout std_logic;
SPI_DI: inout std_logic;
SPI_CLK: inout std_logic;
SPI_WP_n: inout std_logic
);
end entity PulseGen;
architecture PulseGen_a of PulseGen is
function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable mybcd : std_logic_vector(11 downto 0) := (others => '0');
variable bint : std_logic_vector(7 downto 0) := bin;
begin
for i in 0 to 7 loop -- repeating 8 times.
mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits.
mybcd(0) := bint(7);
bint(7 downto 1) := bint(6 downto 0);
bint(0) :='0';
if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
end if;
if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
end if;
if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
end if;
end loop;
return mybcd;
end to_bcd;
-- O1: ____|^^^^^^^|______
-- O2: _________|^^|______
-- t1 t2
-- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz
signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2
signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2
signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer
signal O1: std_logic := '0'; -- Output 1
signal O2: std_logic := '0'; -- Output 2
signal CTburst: unsigned(15 downto 0) := X"0000"; -- Pulse counter
-- LED Demo Signals
-- ----------------
signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary)
signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary)
signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz)
-- LED Display
-- -----------
signal Number: std_logic_vector(32 downto 0); -- LED Display Input
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
signal Enable: std_logic;
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
-- PS/2 Port
-- ---------
-- Interface Signals
signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code
signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code
signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock)
signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code
-- Result
signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory)
-- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese
-- VGA Demo Signals
-- ----------------
signal CLK: std_logic; -- Main Clock - global distribution network
signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG
signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network
signal VGA_Blank: boolean; -- Blank
signal VGA_Hsync: boolean; -- Horisontal Synchronisation
signal VGA_Vsync: boolean; -- Vertical Synchronisation
signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter
signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter
signal PinState: std_logic; -- For IB1 Port Test
signal Red: std_logic_vector(1 downto 0);
signal Green: std_logic_vector(1 downto 0);
signal Blue: std_logic_vector(1 downto 0);
-- ADDA
signal ADDA_DataIn: std_logic_vector(7 downto 0);
begin
-- Basic LED Blinking Test
-- =======================
-- LED Bar Counter
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if Counter < MAXCOUNT-1 then
Counter <= Counter + 1;
else
Counter <= (others => '0');
Bar <= Bar + 1;
end if;
end if;
end process;
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
-- LED Display (multiplexed)
-- =========================
-- Connect LED Display Output Ports (negative outputs)
LD_A_n <= not (Segments(0) and Enable);
LD_B_n <= not (Segments(1) and Enable);
LD_C_n <= not (Segments(2) and Enable);
LD_D_n <= not (Segments(3) and Enable);
LD_E_n <= not (Segments(4) and Enable);
LD_F_n <= not (Segments(5) and Enable);
LD_G_n <= not (Segments(6) and Enable);
LD_DP_n <= not (Segments(7) and Enable);
LD_0_n <= not Digits(0);
LD_1_n <= not Digits(1);
LD_2_n <= not Digits(2);
LD_3_n <= not Digits(3);
LD_4_n <= not Digits(4);
LD_5_n <= not Digits(5);
LD_6_n <= not Digits(6);
LD_7_n <= not Digits(7);
-- Time Multiplex
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if MuxCounter < MUXCOUNT-1 then
MuxCounter <= MuxCounter + 1;
else
MuxCounter <= (others => '0');
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
Enable <= '0';
end if;
if MuxCounter > (MUXCOUNT-4) then
Enable <= '1';
end if;
end if;
end process;
-- BCD to 7 Segmet Decoder
-- -- A
-- | | F B
-- -- G
-- | | E C
-- -- D H
-- ABCDEFGH
Segments <= "11111100" when Code="0000" else -- Digit 0
"01100000" when Code="0001" else -- Digit 1
"11011010" when Code="0010" else -- Digit 2
"11110010" when Code="0011" else -- Digit 3
"01100110" when Code="0100" else -- Digit 4
"10110110" when Code="0101" else -- Digit 5
"10111110" when Code="0110" else -- Digit 6
"11100000" when Code="0111" else -- Digit 7
"11111110" when Code="1000" else -- Digit 8
"11110110" when Code="1001" else -- Digit 9
"11101110" when Code="1010" else -- Digit A
"00111110" when Code="1011" else -- Digit b
"10011100" when Code="1100" else -- Digit C
"01111010" when Code="1101" else -- Digit d
"10011110" when Code="1110" else -- Digit E
"10001110" when Code="1111" else -- Digit F
"00000000";
Code <= Number( 3 downto 0) when Digits="00000001" else
Number( 7 downto 4) when Digits="00000010" else
Number(11 downto 8) when Digits="00000100" else
Number(15 downto 12) when Digits="00001000" else
Number(19 downto 16) when Digits="00010000" else
Number(23 downto 20) when Digits="00100000" else
Number(27 downto 24) when Digits="01000000" else
Number(31 downto 28) when Digits="10000000" else
"0000";
-- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0
-- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1
-- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2
-- "11111111";
-- Number(31 downto 28) <= Key(3 downto 0);
-- Number( 7 downto 0) <= std_logic_vector(BAR);
-- Number(31 downto 24) <= DIPSW;
-- PS/2 Port
-- =========
-- Instantiate PS/2 Keyboard Interface Handler
PS2_Keyboard: PS2 generic map(
CLKFREQ => 100_000_000
)
port map(
-- Main Clock
Clk => CLK100MHz,
-- PS/2 Port
PS2_Clk => PS2_CLK2,
PS2_Data => PS2_DATA2,
-- Result - valid when PS2_Valid
PS2_Code => PS2_Code,
PS2_Attribs => PS2_Attribs,
PS2_Valid => PS2_Valid,
-- Immediate State of Shifts
PS2_Shifts => PS2_Shifts
); -- PS2
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if PS2_Valid and PS2_Attribs(7)='0' then
-- Valid Scan Code with no Break Attribute
PS2_Result( 7 downto 0) <= PS2_Code;
PS2_Result(15 downto 8) <= PS2_Attribs;
end if;
if PS2_Valid and PS2_Attribs(7)='0' then
if PS2_Code = X"74" and T1<2000 then T1<=T1+1; end if;
if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if;
if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if;
if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if;
CT0<=X"0000";
O1<='0';
O2<='0';
CTburst<=X"0000";
end if;
if PB(0)='1' then
T1<=X"0000";
T2<=X"0000";
end if;
if DIPSW(0)='1' then
if CT0>X"F000" then
CT0<=X"0000";
else
CT0<=CT0+1;
end if;
else
if CT0>X"0200" then
CT0<=X"0000";
else
CT0<=CT0+1;
end if;
end if;
if CTburst>2000 then
CTburst<=X"0000";
end if;
if (CTburst<1000) or (DIPSW(1)='0') then
if CT0=X"0000" then
O1<='1';
end if;
if CT0=T1+X"0000" then
O2<='1';
end if;
end if;
if CT0=T2+T1+X"0000" then
O1<='0';
O2<='0';
CTburst<=CTburst+1;
end if;
end if;
end process;
-- Display Result on LED
Number(3 downto 0) <= (others=>'0');
Number(15 downto 4) <= to_bcd(std_logic_vector(T2));
Number(19 downto 16) <= (others=>'0');
Number(31 downto 20) <= to_bcd(std_logic_vector(T1));
-- Test Diferencial In/Outs
-- ========================
-- Output Signal on SATA Connector
SD1AP <= Bar(0);
SD1AN <= Bar(1);
SD1BP <= Bar(2);
SD1BN <= Bar(3);
-- Input Here via SATA Cable
SD2AP <= 'Z';
SD2AN <= 'Z';
SD2BP <= 'Z';
SD2BN <= 'Z';
-- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them
-- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!!
DIF1P <= O1;
B(0) <= O1;
DIF1N <= not O1;
B(1) <= not O1;
DIF2P <= O2;
B(2) <= O2;
DIF2N <= not O2;
B(3) <= not O2;
VGA_R(0) <= O1;
VGA_R(1) <= O2;
-- Unused Signals
-- ==============
-- I2C Signals (on connector J30)
I2C_SCL <= 'Z';
I2C_SDA <= 'Z';
-- SPI Memory Interface
SPI_CS_n <= 'Z';
SPI_DO <= 'Z';
SPI_DI <= 'Z';
SPI_CLK <= 'Z';
SPI_WP_n <= 'Z';
ANA_OUTD <= 'Z';
ANA_REFD <= 'Z';
VGA_R <= "ZZ";
VGA_G <= "ZZ";
VGA_B <= "ZZ";
VGA_VS <= 'Z';
VGA_HS <= 'Z';
end architecture PulseGen_a;
Property changes:
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+Id
\ No newline at end of property

/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/src/LIB/PS2.vhd
0,0 → 1,520
----------------------------------------------------------------------------------
-- Company: www.mlab.cz
-- Engineer: miho
--
-- Create Date: 19:31:10 02/20/2011
-- Design Name: S3AN01A Test Design
-- Module Name: PS2
-- Project Name: S3AN01A Test Design
-- Target Devices: XILINX FPGA (Spartan3A/3AN)
-- Tool versions: ISE 12.4 / 13.1 / 13.3
-- Description: Test design for PCB verification
--
-- Dependencies: None
--
-- Revision: 0.01 File Created
--
----------------------------------------------------------------------------------
--
-- PS/2 Keyboard Driver
-- ====================
--
-- PS2_Code
-- --------
--
-- Standard PS/2 Scan Code
--
--
-- PS2_Attribs
-- -----------
--
-- Bit 0 - Shift
-- Bit 1 - Ctrl
-- Bit 2 - Alt
-- Bit 3 - Ext0 (arrows, ...)
-- Bit 4 - Ext1
-- Bit 5 - Shift Num (arrows with NumLock)
-- Bit 6
-- Bit 7 - Break (key release)
--
--
-- PS2_Shifts
-- ----------
--
-- Bit 0 - Shift Left
-- Bit 1 - Shift Right
-- Bit 2 - Ctrl Left
-- Bit 3 - Ctrl Right
-- Bit 4 - Alt Left
-- Bit 5 - Alt Right
-- Bit 6 - Num Lock
-- Bit 7 - Caps Lock
-- Bit 8 - Scroll Lock
-- Bit 9 - Shift Num (virtual state) - Not to be used
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PS2 is
generic (
-- Top Value for 100MHz Clock Counter
CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000)
);
port (
-- Main Clock
Clk: in std_logic;
-- PS/2 Port
PS2_Clk: inout std_logic;
PS2_Data: inout std_logic;
-- Result - valid when PS2_Valid
PS2_Valid: out boolean; -- Valid Data (synchronous with Clk)
PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code
PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code
-- Immediate State of Shifts
PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc.
);
end entity PS2;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package PS2_pkg is
component PS2
generic (
-- Top Value for 100MHz Clock Counter
CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000)
);
port (
-- Main Clock
Clk: in std_logic;
-- PS/2 Port
PS2_Clk: inout std_logic;
PS2_Data: inout std_logic;
-- Result - valid when PS2_Valid
PS2_Valid: out boolean; -- Valid Data (synchronous with Main Clock)
PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code
PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code
-- Immediate State of Shifts
PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc.
);
end component PS2;
end package;
architecture PS2_a of PS2 is
function to_std_logic(State: boolean) return std_logic is
begin
if State then
return '1';
else
return '0';
end if;
end function to_std_logic;
-- Sampled PS/2 Clock and Data
signal PS2_Clk_d: std_logic := '0'; -- For sync with systerm clock
signal PS2_Clk_dd: std_logic := '0'; -- For falling edge detection
signal PS2_Data_d: std_logic := '0'; -- For sync with systerm clock
-- Level 0 - Read Byte from PS/2 Interface
type ReadByte_t is ( -- Read Byte FSM State Type
Idle, -- Inactive State
D0, D1, D2, D3, D4, D5, D6, D7, -- Receiving Bits
Parity, -- Receiving Parity
Final -- Receiving Stop Bit and Sending ReadByte_rdy
);
signal ReadByteState: ReadByte_t := Idle; -- Read Byte FSM State
signal ReadByte: std_logic_vector(7 downto 0) := (others => '0'); -- Read Byte (Raw Scan Code Byte)
signal ReadByte_rdy: boolean := false; -- Read Byte Ready (synchronous with Clk)
-- Level 1 - Process Raw Scan Codes E0,F1 and F0 - valid only when Level1_rdy
signal FlagE0: boolean := false; -- E0 - Ext0 Key
signal FlagE1: boolean := false; -- E1 - Ext1 Key
signal FlagF0: boolean := false; -- F0 - Break (release) Key
signal Level1_rdy: boolean := false; -- Send Data and Flags to the next level
-- Level 2 - Process Raw Scan Codes and Shift-Like Atributes E0, E1 and F0 - valid only when Level2_rdy
signal FlagBreak: boolean := false; -- F0 - Break (depress) Key
signal FlagAltR: boolean := false; -- E0 11 - State of Right Alt Key
signal FlagAltL: boolean := false; -- 11 - State of Left Alt Key
signal FlagShiftNum: boolean := false; -- E0 12 - State of Ext Left Shift (pseudo key)
signal FlagShiftL: boolean := false; -- 12
signal FlagShiftR: boolean := false; -- 59
signal FlagCtrlR: boolean := false; -- E0 14
signal FlagCtrlL: boolean := false; -- 14
signal FlagExt0: boolean := false; -- E0 Keys (extended keys)
signal FlagExt1: boolean := false; -- E1 Keys (extended keys - Prt_Scr and Pause_Brk)
signal FlagNumLock: boolean := false; -- 77 Num Lock State
signal FlagScrollLock: boolean := false; -- 7E Scroll Lock State
signal FlagCapsLock: boolean := false; -- 58 Caps Lock State
signal Level2_rdy: boolean := false; -- Send Data and Flags to the next level
signal Level2a_rdy: boolean := false; -- Send Read Ack for Write Byte
-- Write Byte
type WriteByteState_t is ( -- Write Byte FSM State Type
Idle, -- Idle State
WriteStart, -- Start (pull PS2_Clk down)
WaitStart, -- Wait
SendBits, -- Send Data Bits
WriteParity, -- Send Parity
WriteStop, -- Send Stop Bit
AckBit, -- Wait for Ack Bit from Keyboard
Final, -- Wait for Idle on PS2_Clk and PS2_Data
WaitAckByte -- Wait for Ack Byte from Keyboard
);
signal WriteByteState: WriteByteState_t := Idle; -- Write Byte FSM State
signal WriteCode: std_logic_vector(7 downto 0) := (others =>'0'); -- What to Write
signal WriteByte: boolean := false; -- Init Write Byte Sequence
signal SendingData: boolean := false; -- Block Receiver when Sending Data
signal WriteByte_ack: boolean := false; -- Ack Writen Byte
signal WriteReg: std_logic_vector(7 downto 0) := (others =>'0'); -- Transmit Shift Register
signal ParityBit: std_logic := '0'; -- Parity Bit
signal StartTime: unsigned(31 downto 0) := (others =>'0'); -- Timer for Start of Write (PS2_Clk low)
signal WriteBits: unsigned(3 downto 0) := (others =>'0'); -- Bit Counter
-- Update LED Indicators
type UpdState_t is ( -- Update Led Indicators FSM State Type
Idle, -- Inactive State
SendReset, -- For Debug - Reset Keyboard
SendLed1, -- Send FD
SendLed2, -- Send New LED State
SendFinal --
);
signal UpdState: UpdState_t := Idle; -- Update Led Indicators FSM State
signal UpdateLed: boolean := false; -- Send new LED State to the Keyboard
signal UpdateLed_ack: boolean := false; -- Ack (1 clock pulse)
begin
-- Sync External Signals with Clock
process (Clk)
begin
if rising_edge(Clk) then
-- Sync
PS2_Clk_d <= PS2_Clk;
PS2_Data_d <= PS2_Data;
-- For Falling Edge Detection
PS2_Clk_dd <= PS2_Clk_d;
end if;
end process;
-- Level 0 - Read Byte from PS/2 Interface
process (Clk)
begin
if rising_edge(Clk) then
ReadByte_rdy <= false;
if PS2_Clk_dd='1' and PS2_Clk_d='0' and not SendingData then
-- Falling Edge of PS2_Clk
case ReadByteState is
when Idle =>
-- Test Start Bit
if PS2_Data='0' then
ReadByteState <= D0;
end if;
when D0 =>
-- Bit 0
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D1;
when D1 =>
-- Bit 1
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D2;
when D2 =>
-- Bit 2
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D3;
when D3 =>
-- Bit 3
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D4;
when D4 =>
-- Bit 4
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D5;
when D5 =>
-- Bit 5
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D6;
when D6 =>
-- Bit 6
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= D7;
when D7 =>
-- Bit 7
ReadByte <= PS2_Data & ReadByte(7 downto 1);
ReadByteState <= Parity;
when Parity =>
-- Check Parity Here...
ReadByteState <= Final;
when Final =>
-- End of Byte
ReadByteState <= Idle;
ReadByte_rdy <= true; -- Scan Code Ready (8 bit word)
end case;
end if;
end if;
end process;
-- Level 1 - Process Raw Scan Codes and ESC Atributes E0, E1 and F0
process (Clk)
begin
if rising_edge(Clk) then
if Level1_rdy then
-- Clean State when Sent Data from Level1 processing
Level1_rdy <= false;
FlagE0 <= false;
FlagE1 <= false;
FlagF0 <= false;
else
if ReadByte_rdy then
-- Process Scan Code Byte from Level 0
if ReadByte=X"E0" then
-- Ext Code
FlagE0 <= true;
elsif ReadByte=X"E1" then
-- Special Ext Code
FlagE1 <= true;
elsif ReadByte=X"F0" then
-- Break Flag
FlagF0 <= true;
else
-- Scan Code
Level1_rdy <= true;
end if;
end if;
end if;
end if;
end process;
-- Level 2 - Process Shift (left and right shift, alt and ctrl) and Num Lock (numeric virtual shift)
process (Clk)
begin
if rising_edge(Clk) then
-- Clear Comands to Higher Level
UpdateLed <= false;
Level2a_rdy <= false;
Level2_rdy <= false;
-- Process Read Byte
if Level1_rdy then
if ReadByte=X"11" then
-- Alt Key
if FlagE0 then
FlagAltR <= not FlagF0;
else
FlagAltL <= not FlagF0;
end if;
elsif ReadByte=X"12" then
-- Left Shift
if FlagE0 then
FlagShiftNum <= not FlagF0;
else
FlagShiftL <= not FlagF0;
end if;
elsif ReadByte=X"59" then
-- Right Shift
FlagShiftR <= not FlagF0;
elsif ReadByte=X"14" then
-- Ctrl
if FlagE0 then
FlagCtrlR <= not FlagF0;
else
FlagCtrlL <= not FlagF0;
end if;
elsif ReadByte=X"77" and not FlagCtrlL and not FlagCtrlR and not FlagAltL and not FlagAltR then
-- Num Lock On/Off
if not FlagF0 then
FlagNumLock <= not FlagNumLock;
UpdateLed <= true; -- Set UpdateLed Request
end if;
elsif ReadByte=X"58" then
-- Caps Lock
if not FlagF0 then
FlagCapsLock <= not FlagCapsLock;
UpdateLed <= true; -- Set UpdateLed Request
end if;
elsif ReadByte=X"7E" then
if not FlagF0 then
FlagScrollLock <= not FlagScrollLock;
UpdateLed <= true; -- Set UpdateLed Request
end if;
else
-- Send Data to the next Level
FlagExt0 <= FlagE0;
FlagExt1 <= FlagE1;
FlagBreak <= FlagF0;
if WriteByteState=WaitAckByte then
-- Send Data (Ack Byte) to WriteByte
Level2a_rdy <= true;
else
-- Send Scan Code to the next Level
Level2_rdy <= true;
end if;
end if;
end if;
end if;
end process;
-- Send Data
PS2_Valid <= Level2_rdy;
-- Scan COde
PS2_Code(7 downto 0) <= ReadByte;
-- Attribs
PS2_Attribs(0) <= '1' when FlagShiftL or FlagShiftR else '0'; -- Bit 0 - Shift
PS2_Attribs(1) <= '1' when FlagCtrlL or FlagCtrlR else '0'; -- Bit 1 - Ctrl
PS2_Attribs(2) <= '1' when FlagAltL or FlagAltR else '0'; -- Bit 2 - Alt
PS2_Attribs(3) <= '1' when FlagExt0 else '0'; -- Bit 3 - Ext Code E0
PS2_Attribs(4) <= '1' when FlagExt1 else '0'; -- Bit 4 - Ext Code E1
PS2_Attribs(5) <= '1' when FlagShiftNum else '0'; -- Bit 5 - Shift Num (Arrows,...) - only if NumLock Led is Off
PS2_Attribs(6) <= '0';
PS2_Attribs(7) <= '1' when FlagBreak else '0'; -- Bit 7 - Break (release) Key
-- Immediate State of Shift Like Keys
PS2_Shifts(0) <= '1' when FlagShiftL else '0'; -- Bit 0 - Shift Left
PS2_Shifts(1) <= '1' when FlagShiftR else '0'; -- Bit 1 - Shift Right
PS2_Shifts(2) <= '1' when FlagCtrlL else '0'; -- Bit 2 - Ctrl Left
PS2_Shifts(3) <= '1' when FlagCtrlR else '0'; -- Bit 3 - Ctrl Right
PS2_Shifts(4) <= '1' when FlagAltL else '0'; -- Bit 4 - Alt Left
PS2_Shifts(5) <= '1' when FlagAltR else '0'; -- Bit 5 - Alt Right
PS2_Shifts(6) <= '1' when FlagNumLock else '0'; -- Bit 7 - Num Lock
PS2_Shifts(7) <= '1' when FlagCapsLock else '0'; -- Bit 8 - Caps Lock
PS2_Shifts(8) <= '1' when FlagScrollLock else '0'; -- Bit 9 - Scroll Lock
PS2_Shifts(9) <= '1' when FlagShiftNum else '0'; -- Bit 6 - Shift Num (virtual state) - Not to be used
-- Write Byte to PS/2 Interface
-- Init By: WriteByte
-- Finish Indication: WriteByte_ack
process (Clk)
begin
if rising_edge(Clk) then
WriteByte_ack <= false;
case WriteByteState is
when Idle =>
PS2_Clk <= 'Z';
PS2_Data <= 'Z';
if WriteByte then
WriteByteState <= WriteStart;
WriteReg <= WriteCode;
end if;
when WriteStart =>
if PS2_Data_d='1' and PS2_Clk_d='1' then
-- PS2 Interface in Idle State
PS2_Clk <= '0'; -- Start of Write (PS2_Clk=L)
StartTime <= to_unsigned(CLKFREQ/16000, StartTime'length); -- cca 60us Start
WriteBits <= to_unsigned(7, WriteBits'length); -- 8 bits
WriteByteState <= WaitStart;
SendingData <= true;
end if;
when WaitStart =>
if StartTime>0 then
StartTime <= StartTime - 1;
else
PS2_Data <= '0'; -- Start Bit
PS2_Clk <= 'Z'; -- Release Clk
ParityBit <= '1'; -- Init Parity Generator (code 1111_1111 has parity 1)
WriteByteState <= SendBits;
end if;
when SendBits =>
if PS2_Clk_dd='1' and PS2_Clk_d='0' then
PS2_Data <= WriteReg(0);
ParityBit <= ParityBit xor WriteReg(0);
WriteReg <= '1' & WriteReg(7 downto 1);
if WriteBits>0 then
WriteBits <= WriteBits - 1;
else
WriteByteState <= WriteParity;
end if;
end if;
when WriteParity =>
if PS2_Clk_dd='1' and PS2_Clk_d='0' then
PS2_Data <= ParityBit;
WriteByteState <= WriteStop;
end if;
when WriteStop =>
if PS2_Clk_dd='1' and PS2_Clk_d='0' then
PS2_Data <= '1';
WriteByteState <= AckBit;
end if;
when AckBit =>
PS2_Data <= 'Z';
if PS2_Clk_dd='1' and PS2_Clk_d='0' then
WriteByteState <= Final;
end if;
when Final =>
if PS2_Clk_d='1' then
WriteByteState <= WaitAckByte;
SendingData <= false;
end if;
when WaitAckByte =>
if Level2a_rdy then
WriteByteState <= Idle;
WriteByte_ack <= true;
end if;
end case;
end if;
end process;
-- Level 3 - Update LED Indicators
-- Init By: UpdateLed or Level2_rdy(with scan code and attrib)
-- Finish Indication: UpdateLed_ack (not used)
process (Clk)
begin
if rising_edge(Clk) then
UpdateLed_ack <= false; -- 1 Clock Pulse
WriteByte <= false;
case UpdState is
when Idle =>
-- Register the request
if Level2_rdy and ReadByte=X"07" and not FlagBreak then
WriteCode <= X"FF";
WriteByte <= true;
elsif UpdateLed then
UpdateLed_ack <= true;
UpdState <= SendLed1;
end if;
when SendReset =>
if WriteByteState=Idle then
-- Send Keyborad Reset
WriteCode <= X"FF";
WriteByte <= true;
UpdState <= SendFinal;
end if;
when SendLed1 =>
if WriteByteState=Idle then
-- Send LED Command
WriteCode <= X"ED";
WriteByte <= true;
UpdState <= SendLed2;
end if;
when SendLed2 =>
if WriteByte_ack then
-- Send LED State
WriteCode <= "00000" & to_std_logic(FlagCapsLock)
& to_std_logic(FlagNumLock)
& to_std_logic(FlagScrollLock);
WriteByte <= true;
UpdState <= SendFinal;
end if;
when SendFinal =>
if WriteByte_ack then ---WriteByteState=Idle then
-- Last Data has been Send
UpdState <= Idle;
end if;
end case;
end if;
end process;
end architecture PS2_a;

/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/src/S3AN01B.ucf
0,0 → 1,152
# Board: www.mlab.cz S3AN01A
# Device: XC3S50AN-4C
# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes
# Main Clock (Embedded 100MHz board oscillator)
NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33;
#NET "CLK100MHz" LOC = P125 | IOSTANDARD = LVCMOS33;
NET "CLK100MHz" TNM_NET = CLK100MHz;
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;
# For DCM connection across the whole chip
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;
NET "PS2_CLK2" CLOCK_DEDICATED_ROUTE = FALSE;
# Mode signals
NET "M[0]" LOC = P38 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "M[1]" LOC = P37 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M1 and M2 for boot from external SPI Flash Memory
NET "M[2]" LOC = P39 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M2 for boot from internal Flash memory
# SPI Flash Vendor Mode Select (for external SPI boot Flash)
NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# DIP Switches (positive signals with pull-down)
NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# Push Buttons (positive signals with pull-down)
NET "PB[0]" LOC = P121 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "PB[1]" LOC = P120 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "PB[2]" LOC = P117 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "PB[3]" LOC = P116 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# LED String (positive output signals)
NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33;
NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33;
NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33;
NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33;
NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33;
NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33;
NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33;
NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33;
# LED Display Output Signals (negative, multiplexed)
NET "LD_A_n" LOC = P15 |IOSTANDARD = LVCMOS33;
NET "LD_B_n" LOC = P30 |IOSTANDARD = LVCMOS33;
NET "LD_C_n" LOC = P21 |IOSTANDARD = LVCMOS33;
NET "LD_D_n" LOC = P19 |IOSTANDARD = LVCMOS33;
NET "LD_E_n" LOC = P18 |IOSTANDARD = LVCMOS33;
NET "LD_F_n" LOC = P16 |IOSTANDARD = LVCMOS33;
NET "LD_G_n" LOC = P24 |IOSTANDARD = LVCMOS33;
NET "LD_DP_n" LOC = P20 |IOSTANDARD = LVCMOS33;
NET "LD_0_n" LOC = P25 |IOSTANDARD = LVCMOS33;
NET "LD_1_n" LOC = P31 |IOSTANDARD = LVCMOS33;
NET "LD_2_n" LOC = P32 |IOSTANDARD = LVCMOS33;
NET "LD_3_n" LOC = P13 |IOSTANDARD = LVCMOS33; # !!! Connect U1.13 with U1.33
NET "LD_4_n" LOC = P27 |IOSTANDARD = LVCMOS33;
NET "LD_5_n" LOC = P29 |IOSTANDARD = LVCMOS33;
NET "LD_6_n" LOC = P28 |IOSTANDARD = LVCMOS33;
NET "LD_7_n" LOC = P12 |IOSTANDARD = LVCMOS33; # !!! Connect U1.12 with U1.35
# VGA Analog Display Connection (outputs)
NET "VGA_R[0]" LOC = P3 |IOSTANDARD = LVCMOS33;
NET "VGA_R[1]" LOC = P4 |IOSTANDARD = LVCMOS33;
NET "VGA_G[0]" LOC = P5 |IOSTANDARD = LVCMOS33;
NET "VGA_G[1]" LOC = P6 |IOSTANDARD = LVCMOS33;
NET "VGA_B[0]" LOC = P7 |IOSTANDARD = LVCMOS33;
NET "VGA_B[1]" LOC = P8 |IOSTANDARD = LVCMOS33;
NET "VGA_VS" LOC = P10 |IOSTANDARD = LVCMOS33;
NET "VGA_HS" LOC = P11 |IOSTANDARD = LVCMOS33;
# Bank 1 Port (input for tests, pull-up)
NET "B[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "B[24]" LOC = P97 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Connected with B[23] on PCB
# PS/2 Bidirectional Port (open collector, J31 and J32)
#NET "PS2_CLK1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # S3AN01A PCB Design has bug so these pins
#NET "PS2_DATA1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # will be assinged after PCB redesign
NET "PS2_CLK2" LOC = P42 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "PS2_DATA2" LOC = P58 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# Diferencial Signals on 4 pin header (J7)
NET "DIF1P" LOC = P110 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIF1N" LOC = P111 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIF2P" LOC = P112 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIF2N" LOC = P113 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# I2C Signals (on connector J30)
NET "I2C_SCL" LOC = P115 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "I2C_SDA" LOC = P114 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
NET "SD1AP" LOC = P54 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD1AN" LOC = P55 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD1BP" LOC = P59 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD1BN" LOC = P57 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD2AP" LOC = P124 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD2AN" LOC = P126 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD2BP" LOC = P131 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SD2BN" LOC = P129 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# SPI Memory Interface
NET "SPI_CS_n" LOC = P41 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "SPI_DO" LOC = P71 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SPI_DI" LOC = P62 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SPI_CLK" LOC = P72 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "SPI_WP_n" LOC = P70 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# Analog In Out
NET "ANA_OUTD" LOC = P67 |IOSTANDARD = LVCMOS33;
NET "ANA_REFD" LOC = P68 |IOSTANDARD = LVCMOS33;
NET "ANA_IND" LOC = P69 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
/*
# Used Signals (test points)
NET "TPS1" LOC = P53 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS2" LOC = P125 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS3" LOC = P127 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS4" LOC = P130 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS5" LOC = P141 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "TPS6" LOC = P123 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
NET "XXX1" LOC = P33 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only
NET "XXX2" LOC = P35 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only
*/

/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/PulseGen.xise
0,0 → 1,350
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<!-- ISE source project file created by Project Navigator. -->
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<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
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<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s50an" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|PulseGen|PulseGen_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="src/PulseGen.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PulseGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="PulseGen" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="PulseGen_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="PulseGen_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="PulseGen_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="PulseGen_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="Pulse Generator from 10ns to 2us." xil_pn:valueState="non-default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="PulseGen" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/13.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="PulseGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-08-28T23:51:54" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AAC6D7E01D414DD992A4DDE7C0B857EB" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/pulsegen.bit
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/Modules/CPLD_FPGA/S3AN01B/HDL/PulseGen/PulseGen.ipf
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/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL/S3AN01_ChipScope.ucf
File deleted

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL/S3AN01_ChipScope.vhd
File deleted

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/HDL/S3AN01_ChipScope.ucf
0,0 → 1,112
# Board: www.mlab.cz S3AN01A
# Device: XC3S50AN-4TQG144C
# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes
# Main Clock (Embedded 100MHz board oscillator)
NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33;
NET "CLK100MHz" TNM_NET = CLK100MHz;
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;
# Enable suboptimal routing of CLK100MHz to DCM input
# (the CLK100MHz pin is across the whole chip realtive to DCM)
# PIN "DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
# Place BUFGMUX at the appropriate position
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;
# SPI Flash Vendor Mode Select (for external SPI boot Flash)
NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# DIP Switches (positive signals with pull-down)
NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
# LED String (positive output signals)
NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33;
NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33;
NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33;
NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33;
NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33;
NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33;
NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33;
NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33;
# LED Display Output Signals (negative, multiplexed) - Segments
NET "LD_SEG_n[0]" LOC = P15 |IOSTANDARD = LVCMOS33; # Segment A A
NET "LD_SEG_n[1]" LOC = P30 |IOSTANDARD = LVCMOS33; # Segment B -----
NET "LD_SEG_n[2]" LOC = P21 |IOSTANDARD = LVCMOS33; # Segment C F | | B
NET "LD_SEG_n[3]" LOC = P19 |IOSTANDARD = LVCMOS33; # Segment D | G |
NET "LD_SEG_n[4]" LOC = P18 |IOSTANDARD = LVCMOS33; # Segment E -----
NET "LD_SEG_n[5]" LOC = P16 |IOSTANDARD = LVCMOS33; # Segment F E | | C
NET "LD_SEG_n[6]" LOC = P24 |IOSTANDARD = LVCMOS33; # Segment G | D |
NET "LD_SEG_n[7]" LOC = P20 |IOSTANDARD = LVCMOS33; # Segment DP ----- DP
# LED Display Output Signals (negative, multiplexed) - Common Anodas
NET "LD_CA_n[0]" LOC = P25 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[1]" LOC = P31 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[2]" LOC = P32 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[3]" LOC = P13 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.13 with U1.33
NET "LD_CA_n[4]" LOC = P27 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[5]" LOC = P29 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[6]" LOC = P28 |IOSTANDARD = LVCMOS33;
NET "LD_CA_n[7]" LOC = P12 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.12 with U1.35
# Bank 1 Port (input for tests, pull-up)
NET "P[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
NET "P[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
# Diferencial Signals on 4 pin header (J7)
NET "DIF1P" LOC = P110 |IOSTANDARD = LVDS_33;
NET "DIF1N" LOC = P111 |IOSTANDARD = LVDS_33;
NET "DIF2P" LOC = P112 |IOSTANDARD = LVDS_33;
NET "DIF2N" LOC = P113 |IOSTANDARD = LVDS_33;
# Timing Constraint for Crossing Time Domain
# Source is ChipScope_VIO_FreqSel output in CLK_FAST time domain
# Destination is SW_SYNC register in CLK100MHz time domain
INST "SW_SYNC_?" TNM = "TNM_SW_SYNC";
TIMESPEC "TS_SW_SYNC" = TO "TNM_SW_SYNC" TIG;
# Timing Constraint for Crossing Time Domain
# Source is SET_CLK_xxx register (FSM) in CLK100MHz time domain
# Destination is ChipScope_VIO_FreqSel inputs in CLK_FAST time domain
INST "SYNC_IN_?" TNM = "TNM_SET_CLK";
TIMESPEC "TS_SET_CLK" = TO "TNM_SET_CLK" TIG;
# Timing Constraint for Clock Switch
# Block BUFGMUX is used as Assynchronous switcher
PIN "BUFGMUX_CLK_FAST.S" TIG;

/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/HDL/S3AN01_ChipScope.vhd
0,0 → 1,612
-- ========================================================================
--
-- S3AN01_ChipScope
--
-- Logic Analyser based on Xilinx ChipScope IP Core for S3AN01 Board
--
-- (c) miho 2013 / http://www.mlab.cz/PermaLink/XILINX_ChipScope
--
-- Demo application contains some Clock Logic (DCM block and
-- clock switch to be able to set different sample clocks).
-- The main function is ChipScope Logic Analyser with 16 data inputs
-- (with 24 bit trigger) and storage for 1024 Data Samples.
--
-- Sampling clock is selectable to 170/100/50/20/10/5/2/1MHz
--
-- To implement the design the ChipScope license is required.
--
-- To use (the logic analyser) no speceial license is needed,
-- WebPack ISE or Lab Tools is enough). Requires some compatible
-- JTAG cable. Compatible with MLAB Xilinx Virtual Cable as well
-- http://www.mlab.cz/PermaLink/XILINX_XVC
--
-- Device: Spartan3AN XC3S50AN-4TQG144C
--
-- Software: ISE WebPack 14.5
--
-- ========================================================================
-- Standard Library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Xilinx Library (necessary for DMC and other Xilinx blocks)
library UNISIM;
use UNISIM.VComponents.all;
-- Interface
entity S3AN01_ChipScope is
generic(
ILA_WIDE: boolean := TRUE; -- TRUE/FALSE -> 18bit x 1024 / 9bit x 2048 logic analyser
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
);
port(
-- Main Clock
CLK100MHz: in std_logic; -- 100MHz external xtal clock source
-- Mode Signals (usualy not used)
VS: out std_logic_vector(2 downto 0); -- SPI Flash Vendor Mode Select
-- Dipswitch Inputs
DIPSW: in std_logic_vector(7 downto 0);
-- LED Bar Outputs
LED: out std_logic_vector(7 downto 0);
-- LED Display (8 digits with 7 segments and decimal point)
LD_CA_n: out std_logic_vector(7 downto 0);
LD_SEG_n: out std_logic_vector(7 downto 0);
-- Bank 1 Pins Inputs
P: in std_logic_vector(24 downto 0);
-- Diferencial Signals on 4 pin header (J7)
DIF1P: inout std_logic;
DIF1N: inout std_logic;
DIF2P: inout std_logic;
DIF2N: inout std_logic
);
end S3AN01_ChipScope;
-- Implementation
architecture S3AN01_ChipScope_a of S3AN01_ChipScope is
-- Clock Signals
-- =============
-- DCM Signals
signal DCM_CLK0: std_logic; -- DCM output for feedback
signal DCM_CLKFX: std_logic; -- DCM output of the fastest clock
signal CLK_FAST: std_logic; -- Main clock for ILA
signal CLK_FAST_Q: std_logic; -- Auxiliary signal (for CLK_FAST sent to pin)
-- 100MHz Clock Switch
-- CLK100MHz Clock Domain
signal CLK100MHz_CE: std_logic; -- Gate Signal for slow dwn of the 100MHz clock
signal CLK100MHz_Gated: std_logic; -- Gated Clocks
signal CLK100MHz_CE_Cnt: unsigned(6 downto 0) := (others => '0'); -- Gate Signal Counter (min frequency is 1/100 of CLK100MHz
-- 1 Hot Clock Select Signals
-- CLK100MHz Clock Domain
signal SET_CLK_MAX: std_logic := '0'; -- Clock Select Signal - Maximim (150-170Mhz)
signal SET_CLK_100MHz: std_logic := '1'; -- Clock Select Signal - 100MHz
signal SET_CLK_50MHz: std_logic := '0'; -- Clock Select Signal - 50MHz
signal SET_CLK_20Mhz: std_logic := '0'; -- Clock Select Signal - 20MHz
signal SET_CLK_10Mhz: std_logic := '0'; -- Clock Select Signal - 10MHz
signal SET_CLK_5Mhz: std_logic := '0'; -- Clock Select Signal - 5MHz
signal SET_CLK_2Mhz: std_logic := '0'; -- Clock Select Signal - 2MHz
signal SET_CLK_1Mhz: std_logic := '0'; -- Clock Select Signal - 1MHz
-- Signals from and to ChipScope Virtual IO (set and display frequency)
-- CLK_FAST and CLK100MHz time domain
signal SYNC_IN: std_logic_vector(7 downto 0); -- Input to ChipScope VIO
signal SYNC_OUT: std_logic_vector(7 downto 0); -- Output from ChipScope VIO
signal SW_SYNC: std_logic_vector(7 downto 0) := (others => '0'); -- Asyn inputs synced
-- LED Ouput with time multiplex
-- =============================
signal WideBCD: std_logic_vector(2*5-1 downto 0); -- Constant width of ILA in BCD (2 char wide)
signal FrequencyBCD: std_logic_vector(3*5-1 downto 0); -- Selected frequency in BCD (3 char wide)
signal Code: std_logic_vector(4 downto 0); -- BCD to 7 Segment Decoder Output
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
-- Time Multiplex
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
signal LedEnable: std_logic; -- LED Display Brightness
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
-- Test Generator signals
-- ======================
signal Counter: std_logic_vector(7 downto 0); -- Counter
-- ChipScope Signals
-- =================
-- Input data
-- CLK_FAST Clock Domain
signal DataReg: std_logic_vector(P'range); -- Data and Trigger input
-- Trigger Output
signal TriggerOut: std_logic; -- Trigegr output from ChipScope ILA to pin
-- User Outputs from ChipScope Virtual IO
signal SYNC_OUT_USER: std_logic_vector(2 downto 0); -- Output from ChipScope VIO
-- ChipScope Control Signals
signal Control0: std_logic_vector(35 downto 0);
signal Control1: std_logic_vector(35 downto 0);
signal Control2: std_logic_vector(35 downto 0);
-- ChipScope Control Block
component ChipScope_ICON
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0)
);
end component;
-- ChipScope Virtual I/O Block
component ChipScope_VIO_FreqSel
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
SYNC_IN: in std_logic_vector(7 downto 0);
SYNC_OUT: out std_logic_vector(7 downto 0)
);
end component;
-- ChipScope Virtual I/O Block
component ChipScope_VIO_UserOut
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
SYNC_OUT: out std_logic_vector(2 downto 0)
);
end component;
-- ChipScope Integrated Logic Analyser
component ChipScope_ILA_18_1024
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(17 downto 0); -- 18 bits wide data
TRIG0: in std_logic_vector(23 downto 0);
TRIG_OUT: out std_logic
);
end component;
-- ChipScope Integrated Logic Analyser
component ChipScope_ILA_9_2048
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(8 downto 0); -- 9 bits wide data
TRIG0: in std_logic_vector(23 downto 0);
TRIG_OUT: out std_logic
);
end component;
begin
-- ===================================================
-- Clock Network and Clock Switching
-- ===================================================
--
-- The fastest clock signal is generated from 100MHz by DCM.
-- The design maximim is 170MHz for selected device.
--
-- For lower frequency the 100MHz clocks are gated in BUFGCE
-- acording to SET_CLK_xxx signals.
--
-- For Logic Analyser we use 170MHz from DCM or gated 100MHz
-- switchd by BUFGMUX block.
-- DCM_SP: Digital Clock Manager Circuit
-- Spartan-3A
-- Xilinx HDL Language Template, version 14.5
--
-- CLKFB without BUFG (we do not need phase relation to the original clock)
--
-- Design Limits (XC3S50AN-4):
--
-- 5/3 -> 166MHz - o.k. (best 5.9ns - 169.5MHz)
-- 17/10 -> 170MHz - o.k. (best 5.748ns - 174MHz) <------ Used Here
-- 12/7 -> 171MHz - Timing Error
-- 7/4 -> 175MHz - Timing Error
-- 18/10 -> 180MHz - Timing Error
--
DCM_SP_inst: DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 17, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 10.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15
DLL_FREQUENCY_MODE => "HIGH", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
)
port map (
CLK0 => DCM_CLK0, -- 0 degree DCM CLK ouptput
-- CLK180 => CLK180, -- 180 degree DCM CLK output
-- CLK270 => CLK270, -- 270 degree DCM CLK output
-- CLK2X => CLK2X, -- 2X DCM CLK output
-- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
-- CLK90 => CLK90, -- 90 degree DCM CLK output
-- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => DCM_CLKFX, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
-- LOCKED => LOCKED, -- DCM LOCK status output
-- PSDONE => PSDONE, -- Dynamic phase adjust done output
-- STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => DCM_CLK0, -- DCM clock feedback
CLKIN => CLK100MHz, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => PSCLK, -- Dynamic phase adjust clock input
-- PSEN => PSEN, -- Dynamic phase adjust enable input
-- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
-- Generate Clock Gate signal for 100MHz Clock
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if CLK100MHz_CE_Cnt=0 then
CLK100MHz_CE <= '1';
if SET_CLK_100MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(1-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_50MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(2-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_20MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(5-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_10MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(10-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_5MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(20-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_2MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(50-1, CLK100MHz_CE_Cnt'length);
elsif SET_CLK_1MHz='1' then
CLK100MHz_CE_Cnt <= to_unsigned(100-1, CLK100MHz_CE_Cnt'length);
end if;
else
CLK100MHz_CE <= '0';
CLK100MHz_CE_Cnt <= CLK100MHz_CE_Cnt-1;
end if;
end if;
end process;
-- Gate 100MHz Clocks (to produce 100/50/20/10/5/2/1 MHz)
-- Generates 5ns pulses with 10/20/50/100/200/500/1000ns period
BUFGCE_CLK100MHz: BUFGCE
port map (
I => CLK100MHz, -- Clock buffer input
CE => CLK100MHz_CE, -- Clock enable input
O => CLK100MHz_Gated -- Clock buffer ouptput
);
-- Switch (gated) 100MHz and the fastest Clock signal from DCM
BUFGMUX_CLK_FAST: BUFGMUX
port map (
I0 => CLK100MHz_Gated, -- Clock0 input -- 100/50/20/10/50/20/1MHz
I1 => DCM_CLKFX, -- Clock1 input -- 170MHz
S => SET_CLK_MAX, -- Clock select input
O => CLK_FAST -- Clock MUX output
);
-- Assynchrnous inputs and inputs from CLK_FAST clock domain must be synchronised
-- SYNC_OUT - CLK_FAST clock domain
-- DIPSW - External (off-chip) async inputs
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
SW_SYNC <= SYNC_OUT or DIPSW;
end if;
end process;
-- Ferquency Selector
-- FSM - 1 hot
process (CLK100MHz)
variable TMP: std_logic_vector(SYNC_OUT'range);
variable NEW_DATA: std_logic;
begin
if rising_edge(CLK100MHz) then
TMP := (others => '0');
NEW_DATA := '1';
if SW_SYNC(7)='1' then
TMP(7) := '1';
elsif SW_SYNC(6)='1' then
TMP(6) := '1';
elsif SW_SYNC(5)='1' then
TMP(5) := '1';
elsif SW_SYNC(4)='1' then
TMP(4) := '1';
elsif SW_SYNC(3)='1' then
TMP(3) := '1';
elsif SW_SYNC(2)='1' then
TMP(2) := '1';
elsif SW_SYNC(1)='1' then
TMP(1) := '1';
elsif SW_SYNC(0)='1' then
TMP(0) := '1';
else
NEW_DATA := '0';
end if;
if NEW_DATA='1' then
SET_CLK_MAX <= TMP(7);
SET_CLK_100MHz <= TMP(6);
SET_CLK_50MHz <= TMP(5);
SET_CLK_20MHz <= TMP(4);
SET_CLK_10MHz <= TMP(3);
SET_CLK_5MHz <= TMP(2);
SET_CLK_2MHz <= TMP(1);
SET_CLK_1MHz <= TMP(0);
end if;
end if;
end process;
-- Send selected frequency to ChipScope Virtual IO
-- Sync it to the CLK_FAST timing domain
SET_CLK_proc: process (CLK_FAST)
begin
if rising_edge(CLK_FAST) then
SYNC_IN(7) <= SET_CLK_MAX;
SYNC_IN(6) <= SET_CLK_100MHz;
SYNC_IN(5) <= SET_CLK_50MHz;
SYNC_IN(4) <= SET_CLK_20Mhz;
SYNC_IN(3) <= SET_CLK_10Mhz;
SYNC_IN(2) <= SET_CLK_5Mhz;
SYNC_IN(1) <= SET_CLK_2Mhz;
SYNC_IN(0) <= SET_CLK_1Mhz;
end if;
end process;
-- ===================================================
-- ChipScope Instance - Control / Virtual IO / ILA
-- ===================================================
-- ChipScope Instance - Control Block
MyChipScopeICON: ChipScope_ICON
port map (
CONTROL0 => Control0,
CONTROL1 => Control1,
CONTROL2 => Control2
);
-- ChipScope Instance - Virtual I/O Block
MyChipScopeVIO_FreqSel: ChipScope_VIO_FreqSel
port map (
CONTROL => Control0,
CLK => CLK_FAST,
SYNC_IN => SYNC_IN,
SYNC_OUT => SYNC_OUT
);
-- ChipScope Instance - Virtual I/O Block
MyChipScopeVIO_UserOut: ChipScope_VIO_UserOut
port map (
CONTROL => Control1,
CLK => CLK_FAST,
SYNC_OUT => SYNC_OUT_USER
);
-- ChipScope Instance - Integrated Logic Analyser
ILA_18_1024: if ILA_WIDE generate
begin
MyChipScopeILA: ChipScope_ILA_18_1024
port map (
CONTROL => Control2,
CLK => CLK_FAST,
DATA => DataReg(17 downto 0),
TRIG0 => DataReg(23 downto 0),
TRIG_OUT => TriggerOut
);
end generate;
ILA_9_2048: if not ILA_WIDE generate
begin
MyChipScopeILA: ChipScope_ILA_9_2048
port map (
CONTROL => Control2,
CLK => CLK_FAST,
DATA => DataReg(8 downto 0),
TRIG0 => DataReg(23 downto 0),
TRIG_OUT => TriggerOut
);
end generate;
-- Data inputs (ILA does not like to have data inputs connected to io pins)
process(CLK_FAST)
begin
if rising_edge(CLK_FAST) then
DataReg <= P(DataReg'range);
end if;
end process;
-- VIO User Outputs
VS <= SYNC_OUT_USER;
-- Trigger Output (Diferencial signal)
OBUFDS_TriggerOut: OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
I => TriggerOut, -- Buffer input
O => DIF1P, -- Diff_p output (connect directly to top-level port)
OB => DIF1N -- Diff_n output (connect directly to top-level port)
);
-- ===================================================
-- LED Display (multiplexed)
-- ===================================================
-- Frequency in BCD
FrequencyBCD <= "00001"&"00111"&"00000" when SET_CLK_MAX='1' else -- 170 MHz
"00001"&"00000"&"00000" when SET_CLK_100MHz='1' else -- 100 MHz
"11111"&"00101"&"00000" when SET_CLK_50MHz='1' else -- 50 MHz
"11111"&"00010"&"00000" when SET_CLK_20MHz='1' else -- 20 MHz
"11111"&"00001"&"00000" when SET_CLK_10MHz='1' else -- 10 MHz
"11111"&"11111"&"00101" when SET_CLK_5MHz='1' else -- 5 MHz
"11111"&"11111"&"00010" when SET_CLK_2MHz='1' else -- 2 MHz
"11111"&"11111"&"00001" when SET_CLK_1MHz='1' else -- 1 MHz
"11111"&"11111"&"11111";
-- ILA width in BCD
ILA_DCD_18_1024: if ILA_WIDE generate
begin
WideBCD <= "00001"&"01000";
end generate;
ILA_DCD_9_2048: if not ILA_WIDE generate
begin
WideBCD <= "11111"&"01001";
end generate;
-- Input data selector ( WIDE / ILA / FREQ )
Code <= FrequencyBCD( 4 downto 0) when Digits="00000001" else
FrequencyBCD( 9 downto 5) when Digits="00000010" else
FrequencyBCD(14 downto 10) when Digits="00000100" else
"10010" when Digits="00001000" else -- A
"10001" when Digits="00010000" else -- L
"10000" when Digits="00100000" else -- I
WideBCD( 4 downto 0) when Digits="01000000" else
WideBCD( 9 downto 5) when Digits="10000000" else
"11111";
-- Time Multiplex
process (CLK100MHz)
begin
if rising_edge(CLK100MHz) then
if MuxCounter < MUXCOUNT-1 then
MuxCounter <= MuxCounter + 1;
else
MuxCounter <= (others => '0');
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left (1 hot encoded)
end if;
-- Display brightness (1/2)
if MuxCounter > (MUXCOUNT-MUXCOUNT/2) then
LedEnable <= '1';
else
LedEnable <= '0';
end if;
end if;
end process;
-- BCD to 7 Segmet Decoder
-- -- A
-- | | F B
-- -- G
-- | | E C
-- -- D H
-- HGFEDCBA
Segments <= "00111111" when Code="00000" else -- Digit 0 -- Hex Didits
"00000110" when Code="00001" else -- Digit 1
"01011011" when Code="00010" else -- Digit 2
"01001111" when Code="00011" else -- Digit 3
"01100110" when Code="00100" else -- Digit 4
"01101101" when Code="00101" else -- Digit 5
"01111101" when Code="00110" else -- Digit 6
"00000111" when Code="00111" else -- Digit 7
"01111111" when Code="01000" else -- Digit 8
"01101111" when Code="01001" else -- Digit 9
"01110111" when Code="01010" else -- Digit A
"01111100" when Code="01011" else -- Digit b
"00111001" when Code="01100" else -- Digit C
"01011110" when Code="01101" else -- Digit d
"01111001" when Code="01110" else -- Digit E
"00110001" when Code="01111" else -- Digit F
"00000110" when Code="10000" else -- Digit I -- User Digits
"00111000" when Code="10001" else -- Digit L
"01110111" when Code="10010" else -- Digit A
"00000000"; -- none
-- Connect LED Display Output Ports (negative outputs)
LD_CA_n <= not Digits;
LD_SEG_n <= not Segments when LedEnable='1' else "11111111";
-- ===================================================
-- Test generator (counter)
-- ===================================================
-- Test counter
process(CLK100MHz)
begin
if rising_edge(CLK100MHz) then
Counter <= std_logic_vector(unsigned(Counter) + 1);
end if;
end process;
-- Test outputs
LED <= Counter;
-- CLK_FAST Output - DDR register
ODDR2_FastClk: ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset
)
port map (
C0 => CLK_FAST, -- 1-bit clock input
C1 => not CLK_FAST, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0', -- 1-bit set input
Q => CLK_FAST_Q -- 1-bit output data
);
-- CLK_FAST Output - differncial pin buffer
OBUFDS_FastClkOut: OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
I => CLK_FAST_Q, -- Buffer input
O => DIF2P, -- Diff_p output (connect directly to top-level port)
OB => DIF2N -- Diff_n output (connect directly to top-level port)
);
end S3AN01_ChipScope_a;