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library ieee; |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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use ieee.numeric_std.all; |
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|
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|
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library UNISIM; |
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library UNISIM; |
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use UNISIM.vcomponents.all; |
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use UNISIM.vcomponents.all; |
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|
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|
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entity clock_divider is |
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entity clock_divider is |
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generic ( |
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generic ( |
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G_DIVISOR : positive := 2 |
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G_DIVISOR : positive := 2 |
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); |
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); |
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port ( |
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port ( |
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|
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|
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i_clk : in std_logic; |
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i_clk : in std_logic; |
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i_rst : in std_logic; |
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i_rst : in std_logic; |
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|
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|
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o_clk : out std_logic |
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o_clk : out std_logic |
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|
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|
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); |
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); |
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end entity clock_divider; |
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end entity clock_divider; |
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|
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|
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architecture behavioral of clock_divider is |
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architecture behavioral of clock_divider is |
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|
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|
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subtype t_counter is natural range 0 to ( G_DIVISOR - 1 ); |
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subtype t_counter is natural range 0 to ( G_DIVISOR - 1 ); |
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signal s_counter : t_counter := 0; |
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signal s_counter : t_counter := 0; |
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|
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|
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constant C_COUNTER : t_counter := G_DIVISOR / 2 - 1; |
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constant C_COUNTER : t_counter := G_DIVISOR / 2 - 1; |
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|
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|
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signal s_clk_divided : std_logic; |
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signal s_clk_divided : std_logic; |
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attribute clock_signal : string; |
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attribute clock_signal : string; |
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attribute clock_signal of s_clk_divided : signal is "yes"; |
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attribute clock_signal of s_clk_divided : signal is "yes"; |
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|
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|
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begin |
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begin |
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|
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|
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assert ( G_DIVISOR > 1 ) report "The divisor should be greater than 1" severity failure; |
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assert ( G_DIVISOR > 1 ) report "The divisor should be greater than 1" severity failure; |
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|
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|
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counting : process( i_clk ) |
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counting : process( i_clk ) |
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begin |
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begin |
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if( rising_edge(i_clk) ) then |
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if( rising_edge(i_clk) ) then |
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if( i_rst = '1' ) then |
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if( i_rst = '1' ) then |
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s_counter <= 0; |
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s_counter <= 0; |
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s_clk_divided <= '0'; |
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s_clk_divided <= '0'; |
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else |
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else |
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if( s_counter = t_counter'high ) then |
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if( s_counter = t_counter'high ) then |
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s_counter <= 0; |
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s_counter <= 0; |
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s_clk_divided <= '0'; |
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s_clk_divided <= '0'; |
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else |
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else |
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s_counter <= s_counter + 1; |
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s_counter <= s_counter + 1; |
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if( s_counter = C_COUNTER ) then |
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if( s_counter = C_COUNTER ) then |
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s_clk_divided <= '1'; |
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s_clk_divided <= '1'; |
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end if; |
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end if; |
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end if; |
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end if; |
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end if; |
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end if; |
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end if; |
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end if; |
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end process counting; |
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end process counting; |
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|
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|
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BUFR_inst : BUFR |
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BUFR_inst : BUFR |
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generic map ( |
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generic map ( |
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BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" |
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BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" |
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SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6" |
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SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6" |
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port map ( |
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port map ( |
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O => o_clk, -- Clock buffer output |
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O => o_clk, -- Clock buffer output |
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CE => '1', -- Clock enable input |
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CE => '1', -- Clock enable input |
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CLR => '0', -- Clock buffer reset input |
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CLR => '0', -- Clock buffer reset input |
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I => s_clk_divided -- Clock buffer input |
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I => s_clk_divided -- Clock buffer input |
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); |
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); |
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|
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|
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end architecture; |
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end architecture; |