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-- wrapper for the local oscillator division logic |
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-- wrapper for the local oscillator division logic |
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-- |
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-- |
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library ieee; |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.std_logic_1164.all; |
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|
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|
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library UNISIM; |
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library UNISIM; |
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use UNISIM.vcomponents.all; |
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use UNISIM.vcomponents.all; |
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|
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|
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library sychro1; |
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library sychro1; |
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|
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|
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entity lo_divider_wrapper is |
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entity lo_divider_wrapper is |
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generic ( |
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generic ( |
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G_DIVISOR : integer |
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G_DIVISOR : integer |
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); |
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); |
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port ( |
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port ( |
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|
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|
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-- input clock: |
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-- input clock: |
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IN_CLK_LO_N : IN std_logic; |
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IN_CLK_LO_N : IN std_logic; |
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IN_CLK_LO_P : IN std_logic; |
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IN_CLK_LO_P : IN std_logic; |
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|
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|
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in_clk_enable : in std_logic; |
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in_clk_enable : in std_logic; |
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|
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|
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-- divided clock |
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-- divided clock |
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OUT_CLK_LO_DIVIDED_N : OUT std_logic; |
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OUT_CLK_LO_DIVIDED_N : OUT std_logic; |
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OUT_CLK_LO_DIVIDED_P : OUT std_logic |
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OUT_CLK_LO_DIVIDED_P : OUT std_logic |
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|
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|
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); |
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); |
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|
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|
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end lo_divider_wrapper; |
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end lo_divider_wrapper; |
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|
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|
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architecture behavioral of lo_divider_wrapper is |
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architecture behavioral of lo_divider_wrapper is |
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|
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|
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-- clock signals for in->divide->out clock: |
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-- clock signals for in->divide->out clock: |
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signal s_in_clk_lo : std_logic; |
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signal s_in_clk_lo : std_logic; |
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signal s_in_clk_lo_bufred : std_logic; |
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signal s_in_clk_lo_bufred : std_logic; |
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signal s_divided_lo : std_logic; |
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signal s_divided_lo : std_logic; |
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attribute clock_signal : string; |
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attribute clock_signal : string; |
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attribute clock_signal of s_divided_lo : signal is "yes"; |
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attribute clock_signal of s_divided_lo : signal is "yes"; |
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|
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|
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begin |
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begin |
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|
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|
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IBUFGDS_inst : IBUFGDS |
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IBUFGDS_inst : IBUFGDS |
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generic map ( |
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generic map ( |
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DIFF_TERM => TRUE |
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DIFF_TERM => TRUE |
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--IBUF_LOW_PWR => TRUE -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards |
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--IBUF_LOW_PWR => TRUE -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards |
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) |
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) |
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port map ( |
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port map ( |
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O => s_in_clk_lo, -- Clock buffer output |
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O => s_in_clk_lo, -- Clock buffer output |
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I => IN_CLK_LO_P, -- Diff_p clock buffer input (connect directly to top-level port) |
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I => IN_CLK_LO_P, -- Diff_p clock buffer input (connect directly to top-level port) |
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IB => IN_CLK_LO_N -- Diff_n clock buffer input (connect directly to top-level port) |
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IB => IN_CLK_LO_N -- Diff_n clock buffer input (connect directly to top-level port) |
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); |
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); |
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|
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|
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-- TEST2: misto counteru pouziju deleni v BUFR |
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-- TEST2: misto counteru pouziju deleni v BUFR |
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BUFR_inst : BUFR |
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BUFR_inst : BUFR |
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generic map ( |
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generic map ( |
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BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" |
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BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" |
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SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6" |
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SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6" |
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port map ( |
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port map ( |
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O => s_in_clk_lo_bufred, -- Clock buffer output |
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O => s_in_clk_lo_bufred, -- Clock buffer output |
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CE => in_clk_enable, -- Clock enable input |
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CE => in_clk_enable, -- Clock enable input |
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CLR => '0', -- Clock buffer reset input |
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CLR => '0', -- Clock buffer reset input |
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I => s_in_clk_lo -- Clock buffer input |
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I => s_in_clk_lo -- Clock buffer input |
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); |
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); |
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|
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|
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-- TEST3: opravil jsem clock_divider, zkusim ho sem dat zpatky |
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-- TEST3: opravil jsem clock_divider, zkusim ho sem dat zpatky |
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-- -> BUFR -> BYPASS |
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-- -> BUFR -> BYPASS |
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-- zpatky clock_divider |
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-- zpatky clock_divider |
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|
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|
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-- TEMP1: vyhozeni counteru |
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-- TEMP1: vyhozeni counteru |
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divider_inst : entity sychro1.clock_divider |
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divider_inst : entity sychro1.clock_divider |
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generic map( G_DIVISOR => G_DIVISOR ) |
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generic map( G_DIVISOR => G_DIVISOR ) |
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port map( i_clk => s_in_clk_lo_bufred, i_rst => '0', o_clk => s_divided_lo ); |
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port map( i_clk => s_in_clk_lo_bufred, i_rst => '0', o_clk => s_divided_lo ); |
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--s_divided_lo <= s_in_clk_lo_bufred; |
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--s_divided_lo <= s_in_clk_lo_bufred; |
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|
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|
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OBUFDS_inst : OBUFDS |
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OBUFDS_inst : OBUFDS |
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generic map ( |
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generic map ( |
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IOSTANDARD => "DEFAULT" ) |
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IOSTANDARD => "DEFAULT" ) |
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port map ( |
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port map ( |
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O => OUT_CLK_LO_DIVIDED_P, -- Diff_p output (connect directly to top-level port) |
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O => OUT_CLK_LO_DIVIDED_P, -- Diff_p output (connect directly to top-level port) |
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OB => OUT_CLK_LO_DIVIDED_N, -- Diff_n output (connect directly to top-level port) |
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OB => OUT_CLK_LO_DIVIDED_N, -- Diff_n output (connect directly to top-level port) |
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I => s_divided_lo -- Buffer input |
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I => s_divided_lo -- Buffer input |
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); |
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); |
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|
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end architecture; |
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end architecture; |
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